Memory, memory preparation method, chip and equipment

Abstract

The invention discloses a memory, a preparation method of the memory, a chip and equipment, and belongs to the technical field of semiconductors. The memory comprises multiple layers of memory cell arrays, multiple common bit lines and multiple connecting lines, the common bit lines, the connecting lines and the memory cell arrays are in one-to-one correspondence, and the multiple common bit lines and the multiple connecting lines are located on the same side of the multiple layers of memory cell arrays; the multiple layers of memory cell arrays are stacked on the substrate along a first direction perpendicular to the substrate; the plurality of common bit lines are stacked in the first direction and are arranged at intervals, and the first side of each common bit line is connected with the local bit line of the corresponding storage unit array; the second side of each common bit line is connected with the corresponding connecting line, and each connecting line extends along the first direction. One side of the memory cell array is connected with the common bit line, the other side does not need to be connected with the common bit line, electric leakage caused by floating of the common bit line on the other side is avoided, the number of the common bit lines is small, stray capacitance caused by the common bit lines is low, and the coupling problem in the memory is reduced.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and in particular to a memory, a method for preparing a memory, a chip, and a device. Background Art

[0002] With the development of semiconductor technology, more and more types of memories are manufactured using semiconductor technology, and the memory includes a memory cell array for storing data. In one possible case, the memory includes a 3D stacked structure memory, and the data capacity that can be stored in the memory is increased by stacking multiple memory cell arrays for storing data. Summary of the invention

[0003] The present application provides a memory, a method for manufacturing a memory, a chip and a device, which can stack multiple memory cell arrays. The technical solution is as follows:

[0004] In a first aspect, a memory is provided, the memory comprising a multi-layer memory cell array, a plurality of common bit lines and a plurality of connection lines, each of the common bit lines, each of the connection lines and each layer of the memory cell array corresponds to each other, and the plurality of common bit lines and the plurality of connection lines are all located on the same side of the multi-layer memory cell array;

[0005] The multi-layer memory cell array is stacked on the substrate along a first direction perpendicular to the substrate;

[0006] The plurality of common bit lines are stacked and spaced apart along the first direction, and the first side of each common bit line is respectively connected to a local bit line of the corresponding memory cell array in each layer;

[0007] The second side of each of the common bit lines is connected to a corresponding one of the connection lines, and each of the connection lines extends along the first direction.

[0008] In a possible implementation, the memory further includes a plurality of filling modules, the filling modules and the common bit lines correspond one to one, and the plurality of filling modules and the plurality of common bit lines are located on the same side of the multi-layer memory cell array;

[0009] The second side of each of the common bit lines is connected to a filling module corresponding to each of the common bit lines, and each of the filling modules is also connected to a connecting line corresponding to each of the common bit lines.

[0010] In a possible implementation manner, the filling modules have different lengths along a second direction parallel to the substrate.

[0011] In a possible implementation manner, each of the filling modules forms a step along the first direction, and a length of any of the filling modules along the second direction is shorter than a length of an adjacent filling module below.

[0012] In a possible implementation, the steps formed by the filling module include two groups of steps spaced apart along the first direction, namely, a first step and a second step;

[0013] The common bit line of the first step connection is located above the common bit line of the second step connection, and the distance between the connection line of the first step connection and the corresponding common bit line is shorter than the distance between the connection line of the second step connection and the corresponding common bit line.

[0014] In a possible implementation manner, the steps are symmetrical odd-even steps.

[0015] In a possible implementation, the filling module includes a metal stack, the metal stack is connected to the second side of the corresponding common bit line, and the metal stack is further connected to the corresponding connection line.

[0016] In a second aspect, a method for preparing a memory is provided, the method comprising:

[0017] Along a first direction perpendicular to the substrate, stacking a multi-layer memory cell array and a plurality of common bit lines on the substrate, wherein the local bit lines of the multi-layer memory cell array are respectively connected to the first side of the corresponding common bit lines, and the plurality of common bit lines are arranged at intervals along the first direction;

[0018] A plurality of connection lines respectively connected to each of the common bit lines are formed on the second side of each of the common bit lines, so as to obtain a memory including the multi-layer memory cell array, the plurality of common bit lines and the plurality of connection lines, wherein each of the connection lines extends along the first direction, and the plurality of common bit lines and the plurality of connection lines are all located on the same side of the multi-layer memory cell array.

[0019] In a possible implementation, the method further includes:

[0020] Forming a plurality of stacked filling modules on the substrate, the second side of each of the common bit lines is connected to a filling module corresponding to each of the common bit lines, the filling modules and the common bit lines correspond one to one, and the plurality of filling modules and the plurality of common bit lines are all located on the same side of the multi-layer memory cell array;

[0021] The forming of a plurality of connection lines respectively connected to each of the common bit lines on the second side of each of the common bit lines comprises:

[0022] A connection line corresponding to each of the common bit lines is formed on a filling module corresponding to each of the common bit lines.

[0023] In a possible implementation, the plurality of filling modules stacked on the substrate include:

[0024] forming a plurality of stacked initial modules on the substrate, wherein the plurality of initial modules have the same length along a second direction parallel to the substrate;

[0025] The multiple initial modules are etched to obtain the multiple filling modules, and the filling modules corresponding to the multiple common bit lines have different lengths along the second direction.

[0026] In a possible implementation, etching the multiple initial modules to obtain the multiple filling modules includes:

[0027] forming a shielding material on the stacked plurality of initial modules, wherein the shielding material is used to determine an area that needs to be etched;

[0028] Performing a first etching on the stacked multiple initial modules according to the shielding material, wherein the first etching is used to change the length of each of the initial modules along the second direction;

[0029] Performing a second etching on the plurality of initial modules after the first etching to obtain a plurality of first modules having gaps, wherein the gaps are used for depositing metal materials;

[0030] A metal material is deposited in the gap of the first module to obtain a filling module including a metal stack, wherein the metal stack is connected to the second side of the common bit line.

[0031] In one possible implementation, the first etching of the stacked multiple initial modules according to the shielding material includes: changing the shielding area of ​​the shielding material, etching the multiple initial modules multiple times, so that the multiple initial modules form a plurality of filling modules arranged in a stepped manner; wherein the length of any filling module along the second direction is shorter than the length of the adjacent filling module below.

[0032] In a possible implementation, the step of changing the shielding area of ​​the shielding material and etching the multiple initial modules multiple times so that the multiple initial modules form multiple filling modules arranged in a stepped manner includes:

[0033] Performing a first etching on the stacked multiple initial modules according to the shielding material to obtain an intermediate step structure;

[0034] A shielding material covering a portion of the step structure is formed on the intermediate step structure, and the intermediate step structure is further subjected to first etching according to the shielding material to obtain two groups of steps spaced apart along the first direction, namely, a first step and a second step.

[0035] In a possible implementation, before performing the second etching on the plurality of initial modules after the first etching, the method further includes:

[0036] A protection wall is formed between the first step and the second step, and the protection wall is used to protect the first step during the second etching process.

[0037] In a possible implementation manner, before etching the multiple initial modules to obtain the multiple filling modules, the method further includes:

[0038] A first etching is performed on one side of the plurality of initial modules to obtain the plurality of initial modules with step differences, wherein the step differences are used to form symmetrical odd and even steps during the etching process.

[0039] In a possible implementation, forming a connection line corresponding to each common bit line on a filling module corresponding to each common bit line includes:

[0040] An insulating layer is formed on each of the filling modules, and connection holes corresponding to the metal stacks of each of the filling modules are formed in the insulating layer. Metal material is deposited in each of the connection holes, and the deposited metal material is ground to obtain the connection wires connected to the metal stacks.

[0041] In a third aspect, a chip is provided, comprising the memory in the first aspect or any possible implementation manner of the first aspect.

[0042] According to a fourth aspect, an electronic device is provided, comprising the memory according to the first aspect or any possible implementation of the first aspect.

[0043] In a possible implementation, the electronic device further includes a processor, which is coupled to the memory, and the processor is used to load and execute at least one instruction stored in the memory to enable the electronic device to operate.

[0044] The technical solution provided by this application brings at least the following beneficial effects:

[0045] One side of the memory cell array needs to be connected to a common bit line, while the other side does not need to be connected to a common bit line. The number of memory cell arrays and common bit lines is the same, which reduces the number of common bit lines included in the memory, reduces the proportion of common bit lines in the memory, reduces the parasitic capacitance caused by the common bit lines, and effectively reduces the coupling problem in the memory. In addition, when applying voltage to the common bit line, since there is no common bit line on the other side of the memory cell array, the floating problem of the common bit line on the other side will not occur, thus avoiding leakage caused by the floating of the common bit line. The number of common bit lines required is small, the preparation process of the memory is simple, and the preparation efficiency is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0048] Figure 2 A schematic diagram of the structure of a common bit line provided in an embodiment of the present application;

[0049] Figure 3 A top view of a memory provided in an embodiment of the present application;

[0050] Figure 4 A schematic diagram of connecting a common bit line and a connecting line provided in an embodiment of the present application;

[0051] Figure 5 A schematic diagram of the structure of another memory provided in an embodiment of the present application;

[0052] Figure 6 A top view of another memory provided in an embodiment of the present application;

[0053] Figure 7 A schematic diagram of the structure of another memory provided in an embodiment of the present application;

[0054] Figure 8 A flowchart of a method for preparing a memory provided in an embodiment of the present application;

[0055] Fig. 9 A schematic diagram of stacking an initial module provided in an embodiment of the present application;

[0056] Fig.10 A schematic diagram of deposition of a protective mask provided in an embodiment of the present application;

[0057] Fig.11 A schematic diagram of etching a protective mask provided in an embodiment of the present application;

[0058] Fig.12 A schematic diagram of a preparation process of a memory provided in an embodiment of the present application;

[0059] Fig.13 A schematic diagram of a covering material provided in an embodiment of the present application;

[0060] Fig.14 A schematic diagram of a structure of a step difference formed by etching provided in an embodiment of the present application;

[0061] Fig.15 A schematic diagram of another covering material provided in an embodiment of the present application;

[0062] Fig.16 A schematic diagram of a step etching process provided in an embodiment of the present application;

[0063] Fig.17 A schematic diagram of another step etching process provided in an embodiment of the present application;

[0064] Fig.18 A schematic diagram of another step etching process provided in an embodiment of the present application;

[0065] Fig.19 A schematic diagram of the structure of an intermediate step structure provided in an embodiment of the present application;

[0066] Fig. 20 A schematic diagram of covering another shielding material provided in an embodiment of the present application;

[0067] Fig.21 A schematic diagram of another step etching process provided in an embodiment of the present application;

[0068] Fig. 22 A schematic diagram of the structure of a first step and a second step provided in an embodiment of the present application;

[0069] Fig.23 A schematic diagram of a process of initial material deposition for a protective wall provided in an embodiment of the present application;

[0070] Fig.24 A schematic diagram showing the comparison of a protective wall before and after etching provided in an embodiment of the present application;

[0071] Fig.25 A schematic diagram of a protective wall etching process provided in an embodiment of the present application;

[0072] Fig.26A schematic diagram of the structure of a protective wall provided in an embodiment of the present application;

[0073] Fig. 27 A schematic diagram of the structure of a first module provided in an embodiment of the present application;

[0074] Fig.28 A schematic diagram of metal material deposition provided in an embodiment of the present application;

[0075] Fig.29 A structural schematic diagram of a filling module provided in an embodiment of the present application;

[0076] Fig.30 A schematic diagram of the structure of an oxidation wall provided in an embodiment of the present application;

[0077] Fig.31 A schematic diagram of a covering material provided in an embodiment of the present application;

[0078] Fig.32 A schematic diagram of etching an oxide wall provided in an embodiment of the present application;

[0079] Fig.33 A schematic diagram of forming a connection line provided in an embodiment of the present application;

[0080] Fig.34 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0081] In order to make the purpose, technical solution and advantages of this application clearer, the following will further describe the implementation mode of this application in detail with reference to the accompanying drawings. The terms used in the implementation mode of this application are only used to explain the specific embodiments of this application, and are not intended to limit this application.

[0082] Figure 1 A schematic diagram of a memory structure provided in an embodiment of the present application is shown in FIG. Figure 1 The memory includes a multi-layer memory cell array 11, a plurality of common bit lines 12 and a plurality of connection lines 13. Figure 1 The left figure in FIG. 1 shows a side view of the memory in the x direction. Figure 1 The right figure in shows a side view of the memory in the y direction.

[0083] Figure 1 The black rectangle is used to indicate the memory cell array 11, the gray rectangle in the y direction is used to indicate the common bit line 12, the gray rectangle in the z direction is used to indicate the connection line 13, and the substrate is indicated by oblique line shading.

[0084] See also Figure 1The connection relationship among the memory cell array 11, the common bit line 12 and the connection line 13 includes but is not limited to: the multi-layer memory cell array 11 is stacked on the substrate along a first direction perpendicular to the substrate; the multiple common bit lines 12 are stacked and spaced along the first direction, and the first sides of the common bit lines 12 are respectively connected to the local bit lines of the corresponding memory cell arrays 11 of each layer; the second sides of the common bit lines 12 are respectively connected to the corresponding connection lines 13, and the connection lines 13 extend along the first direction.

[0085] Exemplarily, the memory cell array 11 includes a plurality of memory cells, each of which includes a transistor and a capacitor, wherein the capacitor is used to store charge, and the transistor is used to control the charge to flow into or out of the capacitor. When the transistor is turned on, the charge flows into the capacitor, and when the transistor is turned off, the charge is fixed in the capacitor. When the charge is stored in the capacitor, the data stored in the capacitor is 1, and when the charge is not stored in the capacitor, the data stored in the capacitor is 0. Therefore, the principle of storing data in the memory cell is to store data in the memory cell by controlling whether the capacitor included in the memory cell stores charge.

[0086] The storage unit also includes a local bit line (local BL), which is used to read and write the capacitor. A voltage is applied to the local bit line to read or change the charge stored in the capacitor, thereby completing the read and write operations on the capacitor.

[0087] In some cases, a plurality of local bit lines included in the memory cell array 11 are connected to a common bit line 12 corresponding to the memory cell array 11, and a voltage is applied to any local bit line included in the memory cell array 11 by applying a voltage to the common bit line 12, thereby reading and writing a capacitor connected to any local bit line. The common bit line 12 may also be referred to as a common bit line (common BL).

[0088] See also Figure 1 The first side of the common bit line 12 is arranged on the side wall of the memory cell array 11 to be connected to the local bit line included in the memory cell array 11. The side wall of the memory cell array 11 is parallel to the first direction. Figure 2 A schematic diagram of the structure of a common bit line provided in an embodiment of the present application is shown in FIG. Figure 2 In Figure (1), the plane marked in gray corresponds to Figure 1 The view of the common bit line 12 in the left figure, Figure 2 In FIG. 2 , the plane marked in gray is the first side of the common bit line 12 .

[0089] For example, the first side of the common bit line 12 connected to the local bit line included in the memory cell array 11 may have no gap with the side wall of the memory cell array 11, that is, Figure 1 The first side of the common bit line 12 shown in the left figure is in contact with the side wall of the memory cell array 11. The first side of the common bit line 12 connected to the local bit line included in the memory cell array 11 may also have a gap with the side wall of the memory cell array 11, for example Figure 3 There is a gap between the common bit line 12 and the sidewall of the memory cell array 11 , and the line segments drawn in the memory cell array 11 indicate the local bit lines included in the memory cell array 11 . Figure 3 A top view of a memory device corresponding to a first direction provided in an embodiment of the present application, Figure 3 The cross-sectional view of the cc' orientation corresponds to Figure 1 The left image shows a side view of the memory.

[0090] In some cases, the multi-layer memory cell array 11 and the multi-layer isolation layer are alternately stacked on the substrate along a first direction, and the first direction is, for example, Figure 1 The upper and lower memory cell arrays 11 are isolated by inserting an isolation layer between the memory cell arrays 11. The inserted isolation layer is, for example, Figure 1 The memory cell array 11 is shown as a white rectangle in the middle.

[0091] In the case where the first side of the common bit line 12 is connected to the local bit line of the memory cell array 11, when the memory cell arrays 11 and the isolation layer are alternately stacked, there will be gaps between the common bit lines 12 connected to different memory cell arrays 11, that is, multiple common bit lines 12 are arranged at intervals. Therefore, the common bit line 12 also needs to be connected to the isolation layer, and the isolation layer is used to fill the gaps between the common bit lines 12.

[0092] Since the multi-layer memory cell arrays 11 are stacked together in the first direction, the common bit lines 12 connected to the multi-layer memory cell arrays 11 shield each other in the first direction, for example Figure 3 In the memory shown, multiple common bit lines 12 block each other, and only one common bit line 12 can be seen from the first direction. Therefore, the second side of the common bit line 12 needs to be connected to the connection line to realize leading out each common bit line 12 in the first direction.

[0093] The second side of the common bit line 12 refers to a side surface different from the first side, and the second side may refer to a top surface of the common bit line 12, for example Figure 2 The connection relationship between the common bit line 12 and the connection line 13 can be seen in Figure 4 The second side may also refer to the side opposite to the first side, for example Figure 2The connection relationship between the common bit line 12 and the connection line 13 can be seen from the side marked in gray in FIG. Figure 1 In addition, Figure 2 (2) and (3) are intended to illustrate possible situations where the first side and the second side are relative to each other. The embodiment of the present application does not limit the shape of the common bit line 12 and the positions of the first side and the second side of the common bit line 12.

[0094] In a possible case, the second side of the common bit line 12 may be directly connected to the connection line 13, for example Figure 1 As shown. Exemplarily, the lengths of the multiple common bit lines 12 along the x direction may be different, and the lengths of the multiple common bit lines 12 along the x direction may be completely different, that is, the lengths of any two common bit lines 12 along the x direction may be different, or may be partially different. Figure 4 A schematic diagram of a connection between a common bit line 12 and a connection line 13 provided in an embodiment of the present application is shown in FIG. Figure 4 The white rectangle in the middle indicates the common bit line 12, and the black rectangle indicates the connection line 13. Figure 4 , the lengths of the plurality of common bit lines 12 are completely different, and the length of any common bit line 12 is shorter than the length of the common bit line 12 below any common bit line 12 , so as to form a step.

[0095] In this step structure, the common bit line 12 of the upper layer will not block the common bit line 12 of the lower layer in the first direction. Figure 4 The first layer of common bit lines 12 from top to bottom will not block the second layer of common bit lines 12, and each connection line 13 can be smoothly connected to the corresponding common bit line 12 without connecting to other common bit lines 12. In a possible case, multiple common bit lines 12 can also form Figure 1 The ladder from top to bottom shown in the right figure is used to successfully connect the connection line 13 corresponding to the common bit line 12. The ladder formed can be Figure 1 or Figure 4 The steps shown may also be symmetrical odd-even steps.

[0096] Exemplarily, the common bit line 12 and the connection line 13 may be indirectly connected, and the memory further includes a plurality of filling modules 14 . Figure 5 A schematic diagram of the structure of another memory provided in an embodiment of the present application, Figure 5 In FIG. 1 , a rectangle connected to the common bit line 12 indicates a filling module 14. Figure 5 The filling module 14 includes a white rectangle and a light gray rectangle. Different colors are used to distinguish different materials. For the various materials included in the filling module 14, please refer to the following Figure 8 The process of preparing the memory in the illustrated embodiment will not be described in detail here.

[0097] See also Figure 5The filling modules 14 and the common bit lines 12 correspond to each other one by one, and the plurality of filling modules 14 and the plurality of common bit lines 12 are all located on the same side of the multi-layer memory cell array 11, and the same side may be Figure 5 The right side shown may also be the left side of the memory cell array 11. The second side of each common bit line 12 is connected to a filling module 14 corresponding to each common bit line 12, and the filling module 14 corresponding to each common bit line 12 is also connected to a connection line 13 corresponding to each common bit line 12. Figure 5 A top view of the memory shown can be seen in Figure 6 , Figure 6 The width of the filling modules 14 is different, so two rows appear in the top view, where the width of the filling module 14 refers to Figure 5 Since the connection lines and the filling modules 14 overlap in the first direction, the filling modules 14 in the top view form a plurality of blocks due to the shielding of the connection lines.

[0098] In a possible implementation, each filling module 14 has a different length along a second direction parallel to the substrate. Figure 1 In the x direction, the filling modules 14 of different lengths form a gap in the first direction, and the gap can be used to connect the connecting line 13. For example, the lengths of the multiple filling modules 14 can be completely different or partially different. The principle and Figure 4 The principle of different lengths of the plurality of common bit lines 12 is similar, and reference may be made to the relevant description of different lengths of the plurality of common bit lines 12, which will not be repeated for the time being. Exemplarily, each filling module 14 forms a step along the first direction, and the length of any filling module 14 along the second direction (referring to the length in the second direction, i.e., the x direction) is shorter than the length of the adjacent filling module 14 below.

[0099] Figure 7 A schematic diagram of the structure of a memory provided in an embodiment of the present application, Figure 7 (1) corresponds to Figure 6 The cross-sectional view at the aa' position in Figure 7 (2) corresponds to Figure 6 The cross-sectional view of the bb' position in Figure 7 (3) corresponds to Figure 6 Cross-sectional view at the cc' position. Figure 7 In the embodiment, since the number of stacked memory cell arrays 11 is relatively large, the connection lines 13 corresponding to the multi-layer memory cell arrays 11 need to form multiple columns to avoid the connection lines 13 from overlapping and interfering with each other.

[0100] Figure 7 The connection lines 13 are shown to form two columns. Figure 7In the embodiment, the steps formed by the plurality of filling modules 14 include two groups of step structures arranged at intervals along the first direction, i.e., the z direction, namely, the first step and the second step, wherein the common bit line 12 connected to the first step is located above the common bit line 12 connected to the second step, and the distance between the connecting line 13 connected to the first step and the corresponding common bit line 12 is shorter than the distance between the connecting line 13 connected to the second step and the corresponding common bit line 12. That is, when the connecting lines 13 form two rows, the connecting lines 13 connected to the first step are as follows: Figure 7 As shown in (3), the connecting line 13 of the second step connection is located on the inner side. Figure 7 (3) is shown on the outside.

[0101] The length of the filling module 14 included in the first step is shown in Figure 7 The first figure, the length of the filling module 14 included in the second step is shown in Figure 7 The second picture, by Figure 7 It can be seen that the lengths of the filling modules 14 included in the first step are different. Therefore, the upper filling module 14 will not block the lower filling module 14 in the first direction. The connecting line 13 corresponding to the lower filling module 14 can successfully connect to the lower filling module 14 and will not connect to the upper filling module 14. Figure 7 The materials of each module included in the memory are also shown. For a description of the materials, see Figure 8 The description of the related embodiments in will not be repeated here.

[0102] In a possible implementation, the steps formed by the multiple filling modules 14 may be Figure 7 The symmetrical odd-even ladder shown can also be Figure 1 The asymmetric steps shown. Exemplarily, the filling module 14 comprises a metal stack, such as Figure 7 The gray part of the filling module in the figure shows that the connection relationship between the filling module 14 and the common bit line 12 and the connecting line 13 includes: the metal stack is connected to the second side of the corresponding common bit line 12, and the metal stack is also connected to the corresponding connecting line 13.

[0103] For example, the metal stack of the plurality of filling modules 14 may be as follows: Figure 7 Symmetrical V-shaped steps are formed in the first direction, and the metal stacks of different filling modules 14 do not overlap, thereby reducing parasitic capacitance caused by the overlap.

[0104] The above examples are intended to illustrate the structure of the memory, rather than to limit the memory cell array 11, common bit line 12, connection line 13 and filling module 14 included in the memory. The thickness of the memory cell array 11 can be the same or different, the thickness of the common bit line 12 can be the same or different, the thickness of the connection line 13 can be the same or different, and the thickness of the filling module 14 can be the same or different. Exemplarily, the memory is, for example, a dynamic random access memory (DRAM), or other memories including a memory cell array, a common bit line and a connection line, which is not limited in the embodiments of the present application.

[0105] In summary, in the memory provided by the embodiment of the present application, one side of the memory cell array needs to be connected to the common bit line, while the other side does not need to be connected to the common bit line. The number of memory cell arrays is the same as the number of common bit lines, which reduces the number of common bit lines that need to be included in the memory. The small number of common bit lines brings low parasitic capacitance, which effectively reduces the coupling problem caused by parasitic capacitance in the memory. In addition, multiple common bit lines are connected to the same side of the memory cell array. When voltage is applied to the common bit lines, there are no common bit lines on the other side of the memory cell array, and the floating problem of the common bit lines on the other side will not occur, thus avoiding leakage caused by the floating of the common bit lines. The gap under the connecting line is filled by the filling module to make the connection between the common bit lines and the connecting lines more reliable.

[0106] The present invention provides a method for preparing a memory device. Figure 1 , Figure 3 , Figure 5-Figure 7 Any memory shown, the flowchart of the method is as follows Figure 8 As shown, it includes step 801-step 802.

[0107] In step 801, a multi-layer memory cell array and a plurality of common bit lines are stacked on a substrate along a first direction perpendicular to the substrate, the local bit lines of the multi-layer memory cell array are respectively connected to the first sides of the corresponding common bit lines, and the plurality of common bit lines are spaced apart along the first direction.

[0108] In a possible implementation, a preparation device can stack multiple layers of memory cell arrays and multiple common bit lines on a substrate by thin film stacking technology. The substrate may be made of silicon (Si) or other materials. The common bit lines may be contact line connection layers stacked and arranged in intervals in a direction perpendicular to the substrate. In addition, the process of stacking memory cell arrays and common bit lines may be performed synchronously. For example, the preparation device connects the local bit lines of the memory cell array and the first side of the common bit lines, and stacks the connected memory cell arrays and common bit lines on the substrate. The process of stacking memory cell arrays and common bit lines may also be performed asynchronously. For example, the preparation device first stacks multiple layers of memory cell arrays, and then connects the local bit lines of the memory cell array and the first side of the common bit lines to achieve stacking of common bit lines.

[0109] Optionally, the preparation device alternately stacks the multi-layer memory cell array and the isolation layer during the stacking process. The composition of the isolation layer may be oxide or other composition with heat dissipation function. In this case, the stacked common bit lines are also alternately stacked with the isolation layer in the first direction to achieve the spacing of the common bit lines. The embodiment of the present application does not limit the number of memory cell arrays to be stacked, which may be 64 layers or other numbers. In the subsequent preparation process illustrated by example in conjunction with the accompanying drawings, 16 layers are temporarily used as an example for illustration.

[0110] In step 802, a plurality of connection lines respectively connected to each common bit line are formed on the second side of each common bit line, thereby obtaining a memory including a multi-layer memory cell array, a plurality of common bit lines and a plurality of connection lines, wherein each connection line extends along a first direction, and the plurality of common bit lines and the plurality of connection lines are all located on the same side of the multi-layer memory cell array.

[0111] In the case where the second side of the common bit line is directly connected to the connecting line, the manufacturing equipment can etch the common bit line to change the length of the common bit line so that a gap is formed between the plurality of common bit lines, and then a connecting line is formed according to the gap. For the process of forming the connecting line, please refer to the process of depositing a metal material to form the connecting line in the embodiment below, which will not be repeated here.

[0112] In the case where the second side of the common bit line is indirectly connected to the connection line, for example, the second side of the common bit line is connected to the connection line through a filling module, the manufacturing equipment also needs to form a plurality of stacked filling modules on the substrate, the second side of each common bit line is connected to the filling module corresponding to each common bit line, the filling module and the common bit line correspond one to one, and the plurality of filling modules and the plurality of common bit lines are all located on the same side of the multi-layer storage unit. Afterwards, the connection lines corresponding to each common bit line are formed on the filling modules corresponding to each common bit line to realize the indirect connection between the common bit line and the connection line.

[0113] The embodiments of the present application do not limit the timing of preparing the stacked filling module of the device. It can be stacked synchronously with the memory cell array and the common bit line, or asynchronously with the memory cell array and the common bit line. In one possible case, the process of preparing the stacked filling module of the device includes: forming a plurality of stacked initial modules on a substrate, and the plurality of initial modules have the same length along a second direction parallel to the substrate; etching the plurality of initial modules to obtain a plurality of filling modules, and the filling modules corresponding to the plurality of common bit lines have different lengths along the second direction. The second direction can be referred to in Figure 5 In the x direction, it should be understood that when introducing the length of the filling module or the initial module below, it refers to the length in the second direction.

[0114] Fig. 9 A schematic diagram of the effect of a thin film stack provided in an embodiment of the present application, Fig. 9 The (1) graph corresponds to Figure 6 The cross-sectional view at the aa' position, Fig. 9 The corresponding graph of (2) Figure 6 The cross-sectional view of the bb' position, Fig. 9 The (3) graph corresponds to Figure 6 The perspective and the perspective of the three drawings provided in the subsequent embodiments of the present application in conjunction with the drawings to introduce the preparation process of the memory Fig. 9 Similarly, no further explanation will be given later.

[0115] See also Fig. 9 The stacked initial modules have the same length along the second direction and correspond one-to-one to the common bit lines. Fig. 9 The material used in the film stacking process is also shown in the figure, where the component of the common bit line is, for example, tungsten (W), or other conductive materials. The initial module is made of insulating materials, such as silicon nitride (SiN). SiN is a good insulator material at high temperatures, and its chemical substances are stable. It is not corroded by all inorganic acids except hydrofluoric acid, and can also exist stably in some alkalis. The initial module can also be made of other insulating materials.

[0116] Fig. 9 In the stacking process, since the memory cell array is stacked alternately with the isolation layer, the common bit line and the initial module are also stacked alternately with the isolation layer to ensure that the common bit line and the initial module correspond to the height of the corresponding memory cell array. The composition of the isolation layer can be Fig. 9 Oxides shown.

[0117] After stacking to obtain multiple initial modules of the same length, the preparation equipment further etches the multiple initial modules to obtain multiple filling modules of different lengths. Etching refers to removing and stripping materials. The embodiment of the present application does not limit the etching method adopted, which can be dry etching, wet etching, or other etching operations. Dry etching is the use of plasma to etch the initial module, and dry etching includes but is not limited to sputtering and ion beam milling, plasma etching, high-pressure plasma etching, etc. Wet etching refers to the use of a chemical reaction between a solution and the initial module to remove part of the material of the initial module.

[0118] In a possible implementation, during the etching process, the manufacturing device will first form a protective mask on the surface of the memory cell array to prevent the memory cell array from being damaged during the etching process. Fig.10 As shown, it includes a first protective layer and a second protective layer. The first protective layer is obtained by hard mask (HM) deposition (deposition, DEP), the material used in the deposition process is amorphous carbon (amorphous carbon layer, ACl), and the second protective layer is obtained by depositing silicon oxynitride (SiON).

[0119] Since the formed protection mask also blocks the initial module, it is necessary to open the protection mask covering the initial module. Fig.10 For example, the process of opening the protective mask covering the initial module includes: depositing a shielding material on the protective mask, the shielding material is, for example, photoresist (PR); etching the protective mask according to the covering shielding material, and the etched protective mask is as shown in FIG. Fig.11 As shown, the protective mask covering the initial module has been removed.

[0120] Fig.11 In the process of etching, the shielding material covered on the protective mask is also removed after the etching is completed. The process of removing the shielding material includes but is not limited to ashing (ASH) and cleaning (CLN). Among them, ashing is used to remove the shielding material, and cleaning is used to remove polymers, such as dust particles and metal pollutants generated during the etching process.

[0121] See also Fig.11 , the initial module is covered with an isolation layer, which also needs to be removed. In addition, the first layer of the initial module as a dummy tier (DT) also needs to be removed. Figure 7Since the first layer initial module needs to be filled with metal tungsten later, the DT of the initial module needs to be removed in order to deposit metal tungsten later. Optionally, the preparation equipment can remove the oxide material and DT as the isolation layer by the first etching. The prefix "first" in the first etching is intended to distinguish the direction of etching, rather than to limit the etching method used. The first etching refers to the etching direction being longitudinal etching from top to bottom parallel to the first direction. The preparation equipment performs CLN after the first etching to obtain the following Fig.12 The structure shown, Fig.12 In the example, the DT and the first isolation layer in several initial modules have been removed.

[0122] After removing the DT and the first isolation layer, the preparation equipment can start the first etching of the initial module. The process of the first etching is, for example, forming a shielding material on the stacked multiple initial modules, the shielding material is used to determine the area to be etched; performing the first etching on the stacked multiple initial modules according to the shielding material, the first etching is used to change the length of each initial module along the second direction; performing the second etching on the multiple initial modules after the first etching to obtain multiple first modules with gaps, the gaps are used to deposit metal materials; depositing metal materials in the gaps of the first modules to obtain a filling module including a metal stack, and the metal stack is connected to the second side of the common bit line.

[0123] Exemplarily, the process of preparing equipment performing a first etching on multiple stacked initial modules according to the shielding material includes: changing the shielding area of ​​the shielding material, etching the multiple initial modules multiple times, so that the multiple initial modules form a plurality of filling modules arranged in a stepped manner; wherein the length of any filling module along the second direction is shorter than the length of the adjacent filling module below.

[0124] Since the difference in the preparation process of forming the filling modules of different structures lies in the different coverage areas of the shielding materials, the preparation principles are similar. Figure 7 As shown, taking the formation of steps by filling modules corresponding to adjacent common bit lines among multiple common bit lines as an example, various steps of etching the initial module to obtain the filling module are introduced. For filling modules of other structures, reference can be made to the relevant description, which will not be repeated in this article.

[0125] In one possible case, the steps formed by the multiple initial modules after the first etching include two groups of steps spaced apart along the first direction, namely the first step and the second step, the common bit line connected to the first step is located above the common bit line connected to the second step, and the distance between the connecting line connected to the first step and the corresponding common bit line is shorter than the distance between the connecting line connected to the second step and the corresponding common bit line, then the shielding area of ​​the shielding material is changed, and the multiple initial modules are etched multiple times, including: performing a first etching on the stacked multiple initial modules according to the shielding material to obtain an intermediate step structure; forming a shielding material covering part of the step structure on the intermediate step structure, and continuing to perform a first etching on the intermediate step structure according to the shielding material to obtain two groups of steps spaced apart along the first direction, namely the first step and the second step.

[0126] See also Figure 7 , because the steps formed by multiple filling modules are symmetrical odd-even steps, that is, the first layer is on the left, the second layer is on the right, the third layer is on the left, etc., therefore, it is necessary to ensure that the initial module on the right is lower than the initial module on the left. Before etching the initial model, the preparation equipment will perform a first etching on one side of the multiple initial modules to obtain multiple initial modules with step differences, which are used to form odd-even steps during the etching process. See Fig.13 , the preparation equipment will perform photolithography (PH) on the initial module to cover the initial module with a geometric structure of the masking material. Exemplarily, the preparation equipment covers the left side of the initial module, such as Fig.13 The shielding material shown in the figure is used to perform a first etching on the stacked initial module according to the shielding material, and after the etching is completed, ashing and cleaning operations are performed to remove the shielding material used in the etching process, so as to obtain the following Fig.14 The step difference shown.

[0127] After the left and right step differences are formed by the first etching, the manufacturing equipment starts etching the step. For example, the manufacturing equipment forms a shielding material according to the step difference, for example Fig.15 As shown, after that, according to Fig.15 The shielding material shown in the figure is first etched. In the first etching process, oxygen / nitrogen (O / N) etching is used, that is, etching of oxide and nitride, thereby etching the isolation layer belonging to oxide and the initial module of nitride. The shapes of the multiple initial modules obtained by etching can be seen in Fig.16 .

[0128] After etching the initial module according to the shielding material, the preparation device can adjust the shape of the shielding material to continue the first etching according to the shielding material after the shape adjustment to achieve the deepening of the step. Fig.17 . Fig.17 In one possible case, the etching frequency of the first etching is O / N etching twice per cycle, wherein the cycle is a time length set according to experience, and O / N etching twice means etching two layers of oxide and two layers of nitride each time, therefore, Fig.17 In the embodiment, two isolation layers and two initial modules are etched according to the trimmed shielding material. The etching frequency may also be other cases, which are not limited in the embodiment of the present application.

[0129] See also Fig.18 After deepening the step, the preparation equipment can repeat the above adjustment of the shielding material, and continue the first etching process according to the adjusted shielding material to obtain an intermediate step structure. Fig.18 In the embodiment, the intermediate step structure includes a first region and a second region, wherein the first region is as follows Fig.18 As shown in the first figure, the second area is Fig.18 As shown in the second figure in the figure, the first area and the second area can be understood as Figure 6 The row of steps corresponding to aa' and the row of steps corresponding to bb' in the figure are shown in FIG. The width of the first region is consistent with the width of the first step, and the height of the first region is consistent with the height of the first step. Therefore, the first etching needs to be continued on the second region to obtain the first step and the second step.

[0130] Illustratively, the preparation device is as follows Fig.19 As shown, the shielding material originally covering the intermediate step structure is removed, and the removal process can be achieved by ashing and cleaning. Then, a new shielding material is formed on the first area. By forming the new shielding material, the module included in the first area is avoided from being etched during the etching process. The new shielding material formed is as shown in FIG. Fig. 20 As shown, the formed shielding material not only covers the first area, but also covers the memory cell array to avoid damaging the memory cell array during etching. Fig.21 The third area shown, see Fig.21 , the steps in the third region are transferred to the bottom. And, after the etching is completed, ashing and cleaning are continued to remove the blocking material.

[0131] Fig. 22 A side view of a first step and a second step provided in an embodiment of the present application, corresponding to Figure 6 View from the side in the bb' direction, see Fig. 22 , the modules corresponding to the heights of the third area and the first area are spliced ​​to obtain the second step, and the unspliced ​​modules in the first area form the first step.

[0132] After the first step and the second step are formed by the first etching, the multiple initial modules after the first etching may be further subjected to the second etching. The second etching refers to the lateral etching in which the etching direction is perpendicular to the first direction. In one possible case, before the multiple initial modules after the first etching are subjected to the second etching, a protective wall needs to be formed between the first step and the second step, and the protective wall is used to protect the first step during the second etching.

[0133] See also Fig.23 Before forming the protection wall, a stop layer is first deposited, and the stop layer is used as the removal end point of the protection wall to determine the boundary of the protection wall. For example, the composition of the stop layer can be as follows: Fig.23 The figure shows polysilicon (poly), which can also be any silicide such as silicon nitride (SiN). After the cut-off layer is deposited, the initial material of the protective wall can be formed according to the cut-off layer. The initial material can be any oxide, including but not limited to tetraethoxysilane (TEOS). Optionally, the process of preparing the equipment to form the initial material includes but is not limited to: depositing oxide; chemical mechanical polishing (CMP) of the deposited oxide, and through the synergistic effect of chemical corrosion and mechanical polishing, the excess material on the oxide surface is efficiently removed and nano-scale flattened to obtain Fig.23 Starting materials for the structures shown.

[0134] Fig.24 A top view of an initial module after the first etching provided in an embodiment of the present application, Fig.24 In the left figure, the surface of the first step and the second step is covered with a layer of initial material. The preparation equipment needs to adjust the shape of the initial material through photolithography to retain the protective wall between the first step and the second step. Fig.24 The protective wall shown in the right picture.

[0135] In one possible case, the process of obtaining the protection wall by photolithography includes: depositing to form a protection mask, and forming a blocking material on the protection mask, such as Fig.25 As shown; the initial material and polysilicon are first etched according to the blocking material, and the blocking material and the protective mask are removed by ashing and cleaning after the first etching, to obtain Fig.26 The protective wall shown. The function and composition of the protective mask are similar to those of the protective mask in the above embodiment, and the relevant description can be referred to, and will not be repeated here.

[0136] After forming the protective wall, Fig.26The first step and the second step shown in the figure are subjected to a second etching to obtain a plurality of first modules, wherein the first module includes a gap for depositing a metal material, wherein the metal material is used to connect the common bit line and the connection line. The first module obtained after the second etching is, for example, Fig. 27 The second etching is similar in principle to the first etching and can also be implemented by wet etching or dry etching, the difference being that the etching directions are different.

[0137] After obtaining a plurality of first modules including gaps, metal materials may be deposited in the gaps to obtain a metal stack for connecting connecting wires. Exemplarily, the process of depositing metal materials in the gaps of the first modules includes depositing W, grinding W, and cleaning W. Fig.28 The structure shown in FIG. 1 is then removed by etching, grinding, cleaning, and other processes outside the first step and the second step to form a structure as shown in FIG. Fig.29 The metal stack is obtained by depositing metal materials in the gaps, ensuring that the metal stacks included in different filling modules have no overlap, thereby reducing the parasitic capacitance caused by the overlap.

[0138] In a possible implementation, the process of forming a connection line in a filling module of a preparation device includes: forming an insulating layer on each filling module, forming a connection hole corresponding to the metal stack of each filling module in the insulating layer, depositing a metal material in each connection hole, grinding the deposited metal material, and obtaining a connection line connected to the metal stack. The insulating layer may be an oxide, and a connection hole is formed in the insulating layer as a partition, so that the shape of the connection line is determined according to the connection hole. Exemplarily, the preparation device performs oxide deposition and grinding operations on the filling module to obtain Fig.30 The oxide wall shown in FIG. 1 is used as an insulating layer. After the oxide wall is formed, the preparation equipment etches a gap in the oxide wall for depositing the connection line, that is, the connection hole. The etching process is similar to the etching process illustrated in the above embodiment, including the deposition of the protective mask, the scrubber (SCR) cleaning of the SiON in the protective mask, and the deposition of the shielding material. Among them, the SCR cleaning is a step in the process flow. Fig.31 A schematic diagram of deposition of a protective mask is shown. Fig.31 The protective mask shown in FIG. 1 includes a hard mask formed of ACl and a thin film formed of SiON. Fig.31 There are gaps between the photoresists formed in the first and second figures, and the gaps are used to determine the gaps between the oxide walls. The positions of the gaps are determined according to the positions of the metal stacks.

[0139] After forming the shielding material, the preparation device performs a first etching on the area not covered by the shielding material, and performs ashing and cleaning after the first etching to remove the shielding material, so as to obtain Fig.32 Then, a connecting line is formed in the gap of the oxide wall, and the forming process includes but is not limited to: depositing titanium nitride (TiN) and W, grinding the deposited TiN and W, and cleaning the ground TiN and W to obtain a connecting line. The formed connecting line is as shown in FIG. Fig.33 shown.

[0140] In summary, in the method for preparing the memory provided by the embodiment of the present application, one side of the memory cell array needs to be connected to a common bit line, and the number of common bit lines and the memory cell array is the same, which reduces the number of common bit lines, and the parasitic capacitance caused by the common bit line is small, which reduces the coupling problem caused by the parasitic capacitance. In addition, since one side of the memory cell array is connected to the common bit line, when a voltage is applied to the common bit line, there is no common bit line on the other side, and leakage problems caused by floating common bit lines will not occur. The connection method between the common bit line and the connecting line is not limited, and the flexibility is high. The gap under the connecting line can be filled by a filling module to make the reliability of the connection between the common bit line and the connecting line higher.

[0141] An embodiment of the present application provides a chip, which includes any possible memory described above.

[0142] An embodiment of the present application provides an electronic device, which includes any possible memory described above. Exemplarily, the electronic device also includes a processor, which is coupled to the memory, and the processor is used to load and execute instructions stored in the memory to enable the electronic device to operate.

[0143] In some implementation scenarios, the electronic device may be a server. Fig.34 3401 and 3402. The server may have relatively large differences due to different configurations or performances, and may include one or more processors 3401 and one or more memories 3402, wherein at least one computer program is stored in the one or more memories 3402, and the at least one computer program is loaded and executed by the one or more processors 3401 to enable the server to run. Of course, the server may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output, and the server may also include other components for realizing device functions, which will not be described in detail here.

[0144] In a possible implementation, the electronic device including the memory may be a terminal, such as a smart phone, a tablet computer, a player, a notebook computer or a desktop computer. The terminal may also be called a user equipment, a portable terminal, a laptop terminal, a desktop terminal or other names.

[0145] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions. For example, the storage unit arrays involved in this application are all obtained with full authorization.

[0146] It should be understood that the "plurality" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0147] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A memory, characterized in that: The memory comprises a multi-layer memory cell array (11), a plurality of common bit lines (12) and a plurality of connection lines (13), each of the common bit lines (12), each of the connection lines (13) and each layer of the memory cell array (11) corresponds one to one, and the plurality of common bit lines (12) and the plurality of connection lines (13) are all located on the same side of the multi-layer memory cell array (11); The multi-layer memory cell array (11) is stacked on the substrate along a first direction perpendicular to the substrate; A plurality of common bit lines (12) are stacked and spaced apart along the first direction, and a first side of each common bit line (12) is respectively connected to a local bit line of a corresponding layer of the memory cell array (11); The second side of each of the common bit lines (12) is respectively connected to a corresponding one of the connection lines (13), and each of the connection lines (13) extends along the first direction.

2. The memory according to claim 1, characterized in that: The memory further comprises a plurality of filling modules (14), the filling modules (14) and the common bit lines (12) corresponding one to one, and the plurality of filling modules (14) and the plurality of common bit lines (12) are all located on the same side of the multi-layer memory cell array (11); The second side of each of the common bit lines (12) is connected to a corresponding filling module (14), and each of the filling modules (14) is also connected to a connecting line (13) corresponding to each of the common bit lines (12).

3. The memory according to claim 2, characterized in that: The lengths of the filling modules (14) along a second direction parallel to the substrate are different.

4. The memory according to claim 3, characterized in that: Each of the filling modules (14) forms a step along the first direction, and the length of any of the filling modules (14) along the second direction is shorter than the length of the adjacent filling module (14) below.

5. The memory according to claim 4, characterized in that: The steps formed by the filling module (14) include two groups of steps spaced apart along the first direction, namely, a first step and a second step; The common bit line (12) of the first step connection is located above the common bit line (12) of the second step connection, and the distance between the connection line (13) of the first step connection and the corresponding common bit line (12) is shorter than the distance between the connection line (13) of the second step connection and the corresponding common bit line (12).

6. The memory according to claim 4 or 5, characterized in that: The steps are symmetrical odd-even steps.

7. The memory according to any one of claims 2 to 5, characterized in that: The filling module (14) comprises a metal stack, the metal stack is connected to the second side of the corresponding common bit line (12), and the metal stack is also connected to the corresponding connection line (13).

8. A method for preparing a memory, characterized in that: The method comprises: Along a first direction perpendicular to the substrate, stacking a multi-layer memory cell array and a plurality of common bit lines on the substrate, wherein the local bit lines of the multi-layer memory cell array are respectively connected to the first side of the corresponding common bit lines, and the plurality of common bit lines are arranged at intervals along the first direction; A plurality of connection lines respectively connected to each of the common bit lines are formed on the second side of each of the common bit lines, so as to obtain a memory including the multi-layer memory cell array, the plurality of common bit lines and the plurality of connection lines, wherein each of the connection lines extends along the first direction, and the plurality of common bit lines and the plurality of connection lines are all located on the same side of the multi-layer memory cell array.

9. The method according to claim 8, characterized in that The method further comprises: Forming a plurality of stacked filling modules on the substrate, the second side of each of the common bit lines is connected to a filling module corresponding to each of the common bit lines, the filling modules and the common bit lines correspond one to one, and the plurality of filling modules and the plurality of common bit lines are all located on the same side of the multi-layer memory cell array; The forming of a plurality of connection lines respectively connected to each of the common bit lines on the second side of each of the common bit lines comprises: A connection line corresponding to each of the common bit lines is formed on a filling module corresponding to each of the common bit lines.

10. The method according to claim 9, characterized in that The plurality of filling modules stacked on the substrate include: forming a plurality of stacked initial modules on the substrate, wherein the plurality of initial modules have the same length along a second direction parallel to the substrate; The multiple initial modules are etched to obtain the multiple filling modules, and the filling modules corresponding to the multiple common bit lines have different lengths along the second direction.

11. The method according to claim 10, characterized in that The etching of the plurality of initial modules to obtain the plurality of filling modules comprises: forming a shielding material on the stacked plurality of initial modules, wherein the shielding material is used to determine an area that needs to be etched; Performing a first etching on the stacked multiple initial modules according to the shielding material, wherein the first etching is used to change the length of each of the initial modules along the second direction; Performing a second etching on the plurality of initial modules after the first etching to obtain a plurality of first modules having gaps, wherein the gaps are used for depositing metal materials; A metal material is deposited in the gap of the first module to obtain a filling module including a metal stack, wherein the metal stack is connected to the second side of the common bit line.

12. The method according to claim 11, characterized in that The first etching of the stacked multiple initial modules according to the shielding material includes: The shielding area of ​​the shielding material is changed, and the multiple initial modules are etched multiple times, so that the multiple initial modules form a plurality of filling modules arranged in a stepped manner; wherein the length of any of the filling modules along the second direction is shorter than the length of the adjacent filling module below.

13. The method according to claim 12, characterized in that The step of changing the shielding area of ​​the shielding material and etching the plurality of initial modules multiple times so that the plurality of initial modules form a plurality of filling modules arranged in a stepped manner includes: Performing a first etching on the stacked multiple initial modules according to the shielding material to obtain an intermediate step structure; A shielding material covering a portion of the step structure is formed on the intermediate step structure, and the intermediate step structure is further subjected to first etching according to the shielding material to obtain two groups of steps spaced apart along the first direction, namely, a first step and a second step.

14. The method according to claim 13, characterized in that Before performing a second etching on the plurality of initial modules after the first etching, the method further comprises: A protection wall is formed between the first step and the second step, and the protection wall is used to protect the first step during the second etching process.

15. The method according to claim 12, characterized in that Before etching the plurality of initial modules to obtain the plurality of filling modules, the method further includes: A first etching is performed on one side of the plurality of initial modules to obtain the plurality of initial modules with step differences, wherein the step differences are used to form symmetrical odd and even steps during the etching process.

16. The method according to any one of claims 11 to 15, characterized in that: The forming of connection lines corresponding to the common bit lines on the filling modules corresponding to the common bit lines comprises: An insulating layer is formed on each of the filling modules, and connection holes corresponding to the metal stacks of each of the filling modules are formed in the insulating layer. Metal material is deposited in each of the connection holes, and the deposited metal material is ground to obtain the connection wires connected to the metal stacks.

17. A chip, characterized in that: The chip comprises the memory as claimed in any one of claims 1-7.

18. An electronic device, characterized in that: The electronic device comprises the memory as claimed in any one of claims 1-7.

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