Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. A semiconductor device may include: a gate structure including a stacked local line and a multi-step structure defining a pad of the local line; channel patterns respectively disposed over the pads; a block word line disposed over the channel pattern and extending along a contour of the multi-step structure; and first contact plugs passing through the channel pattern and connecting the channel pattern and the local lines, respectively.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly, to semiconductor devices and methods of manufacturing semiconductor devices. Background Art

[0002] The integration degree of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, as the improvement of the integration degree of a semiconductor device in which a memory cell is formed as a single layer on a substrate has reached a limit, a three-dimensional semiconductor device in which a memory cell is stacked on a substrate is being proposed. In addition, in order to improve the operational reliability of the semiconductor device, various structures and manufacturing methods are being developed. Summary of the invention

[0003] According to an embodiment disclosed in the present invention, a semiconductor device may include: a gate structure including a stacked local line and a multi-step structure, wherein the multi-step structure defines a pad for the local line; a channel pattern, which is respectively arranged above the pad; a block word line, which is arranged above the channel pattern and extends along a profile of the multi-step structure; and a first contact plug, which passes through the channel pattern and connects the channel pattern with the local line, respectively.

[0004] According to an embodiment disclosed in the present invention, a semiconductor device may include: a gate structure including stacked local lines; first contact plugs extending through the gate structure and respectively connected to the local lines; a channel pattern disposed above the gate structure and respectively connected to the first contact plugs; and a block word line disposed above the channel pattern.

[0005] According to an embodiment disclosed in the present invention, a method for manufacturing a semiconductor device may include: forming a stack including first material layers and second material layers alternately stacked; forming a multi-step structure in the stack so that each first material layer is exposed; forming a channel pattern on the multi-step structure; forming a block word line extending along the contour of the multi-step structure; and forming a first contact plug passing through the channel pattern and extending into the stack.

[0006] According to an embodiment disclosed in the present invention, a method for manufacturing a semiconductor device may include: forming a gate structure including local lines and insulating layers alternately stacked; forming first contact plugs extending through the gate structure and respectively connected to the local lines; forming channel patterns on the gate structure respectively connected to the first contact plugs; and forming block word lines that intersect the channel patterns and extend on the gate structure.

[0007] These and other features and advantages of the present disclosure will be better understood from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram illustrating a structure of a semiconductor device according to an embodiment disclosed in the present invention.

[0009] FIG. 2A to FIG. 2D is a diagram illustrating a structure of a semiconductor device according to an embodiment disclosed in the present invention.

[0010] FIG. 3A to FIG. 3D is a diagram illustrating a structure of a semiconductor device according to an embodiment disclosed in the present invention.

[0011] 4A to 4D is a diagram illustrating a structure of a semiconductor device according to an embodiment disclosed in the present invention.

[0012] Figure 5A and Figure 5B is a diagram illustrating a structure of a semiconductor device according to an embodiment disclosed in the present invention.

[0013] Figure 6 is a diagram illustrating a structure of a semiconductor device according to an embodiment disclosed in the present invention.

[0014] Figure 7 is a diagram illustrating a structure of a semiconductor device according to an embodiment disclosed in the present invention.

[0015] Figure 8 , Fig. 9A , Fig. 9B , FIG. 10A to FIG. 10C , FIG. 11A to FIG. 11C , FIG. 12A to FIG. 12C , FIG. 13A to FIG. 13D as well as FIG. 14A to FIG. 14D is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment disclosed in the present invention.

[0016] FIG. 15A to FIG. 15C is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment disclosed in the present invention.

[0017] Fig.16 , 17A to 17C as well as 18A to 18D 2 is a diagram illustrating a manufacturing method according to an embodiment of the present disclosure.

[0018] 19A to 19D 2 is a diagram illustrating a manufacturing method according to an embodiment of the present disclosure.

[0019] Fig. 20 is a diagram showing the structure of a semiconductor device according to an embodiment disclosed in the present invention.

[0020] Fig.21 is a diagram showing the structure of a semiconductor device according to an embodiment disclosed in the present invention. DETAILED DESCRIPTION

[0021] Embodiments disclosed herein provide a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

[0022] The integration degree of a semiconductor device can be improved by three-dimensionally stacking memory cells. In addition, a semiconductor device having a stable structure and improved reliability can be provided.

[0023] Hereinafter, embodiments of the technical concept disclosed in the present invention are described with reference to the accompanying drawings.

[0024] Figure 1 is a diagram illustrating a structure of a semiconductor device according to an embodiment disclosed in the present invention.

[0025] Reference Figure 1 The semiconductor device may include a gate structure GST, a channel pattern CP, a block word line BLKWL, and a first contact plug CT1. The semiconductor device may also include at least one of a global line GL, a second contact plug CT2, a buffer layer 13, and a gate insulating layer GI.

[0026] The gate structure GST may include alternately stacked local lines LL and insulating layers 12. The local line LL may include a local source selection line, a local drain selection line, or a local word line. The local line LL may be made of or include a conductive material such as, for example, polysilicon, tungsten, or molybdenum. "Polysilicon" used as this term in the present disclosure refers to polycrystalline silicon (poly-Si). The gate structure GST may include a multi-step structure. The multi-step structure may extend in a first direction I. Each local line LL may be exposed by the multi-step structure, and the exposed portion of each local line may be defined as a pad PD.

[0027] The buffer layer 13 may be disposed over the gate structure GST. The buffer layer 13 may be formed along the contour of the multi-step structure and may cover the pad PD. The buffer layer 13 may be made of or include an insulating material such as oxide.

[0028] The channel pattern CP may be disposed above the gate structure GST, and more specifically, may be disposed above the buffer layer 13. Therefore, the channel pattern CP may be in direct contact with the buffer layer 13. The channel pattern CP may be made of or include a semiconductor material, such as at least one of single crystal silicon, polycrystalline silicon, germanium Ge, silicon germanium SiGe, and gallium arsenide GaAs. The channel pattern CP may include a junction disposed on both sides of the block word line BLKWL. The junction may include a source region and a drain region. The channel pattern CP may be disposed above the pad PD, respectively. The channel pattern CP may be arranged to be spaced apart in a first direction I and may extend in a second direction II. The second direction II may be a direction intersecting the first direction I. In an embodiment, the first direction I and the second direction II may be orthogonal to each other.

[0029] The block word line BLKWL may be disposed over the channel pattern CP and may extend along the profile of the multi-step structure in the first direction I. The block word line BLKWL may be made of or include a conductive material such as, for example, polysilicon, tungsten, or molybdenum.

[0030] The gate insulating layer GI may be disposed between the channel pattern CP and the block word line BLKWL. The gate insulating layer GI may surround the channel pattern CP and may extend in the first direction I along the profile of the multi-step structure. The gate insulating layer GI may include a protrusion P protruding between the multi-step structure and the channel pattern CP. A top surface of the gate insulating layer GI may have a multi-step profile.

[0031] The first contact plugs CT1 may each pass through the channel pattern CP and may be connected to the corresponding local line LL. The first contact plugs CT1 may each pass through the gate insulating layer GI, the channel pattern CP, and the buffer layer 13, and may be electrically connected to the local line LL corresponding thereto. Therefore, each of the first contact plugs CT1 may extend to a different depth in the gate structure GST and may be respectively connected to different local lines LL. Therefore, the channel pattern CP and the local line LL may be connected through the first contact plugs CT1.

[0032] The second contact plug CT2 may be connected to the channel pattern CP on the opposite side of the first contact plug CT1. A pair of the first contact plug CT1 and the second contact plug CT2 may be disposed to face each other with the block word line BLKWL interposed therebetween, and may be connected to the same channel pattern CP. The second contact plug CT2 may be connected to the channel pattern CP and the global line GL, respectively.

[0033] According to the above structure, the transfer transistor can be set in the area where the channel pattern CP and the block word line BLKWL intersect. Each transfer transistor can be a switch that controls the connection between the global line GL and the corresponding local line LL. The transfer transistor can be turned on or off according to the block selection signal applied to the block word line BLKWL. When the transfer transistor is turned on, the corresponding pair of global lines GL and local lines LL can be connected through the corresponding first contact plug CT1 and second contact plug CT2.

[0034] The transfer transistor may be disposed above the multi-step structure. Since the transfer transistor is disposed above the multi-step structure, a separate region for forming the transfer transistor above or below the gate structure GST may not be required, and thus the memory integration (also referred to as integration density or element density) of the semiconductor device may be significantly increased.

[0035] FIG. 2A to FIG. 2D is a diagram illustrating a structure of a semiconductor device according to an embodiment disclosed in the present invention. Figure 2D It is a floor plan. Figure 2A It is along Figure 2D A cross-sectional view taken along line AA′, Figure 2B It is along Figure 2D A cross-sectional view taken along line BB′, and Figure 2C It is along Figure 2D Hereinafter, description of contents overlapping with those already described may be omitted.

[0036] Reference FIG. 2A to FIG. 2D , the semiconductor device may include at least one of a gate structure GST, a channel pattern CP, a buffer layer 23, a gate insulating layer GI, a block word line BLKWL, an etch stop layer 24, an interlayer insulating layer 25, a first contact plug CT1, and a second contact plug CT2.

[0037] The gate structure GST may include a local line LL and an insulating layer 22 that are alternately stacked. A buffer layer 23 may be disposed over the gate structure GST. A channel pattern CP may be disposed over the gate structure GST, and more specifically, the channel pattern CP may be disposed over the buffer layer 23. A block word line BLKWL may be disposed over the channel pattern CP, may intersect the channel pattern CP, and may extend in a first direction I. A gate insulating layer GI may be disposed between the channel pattern CP and the block word line BLKWL. An etch stop layer 24 may be disposed over the block word line BLKWL and the gate insulating layer GI.

[0038] The buffer layer 23 may include a plurality of grooves G on the top surface thereof. The grooves G may be respectively disposed between the channel patterns CP. A sidewall of the channel pattern CP may include a curved surface, and the curved surface may be connected to the grooves G. The gate insulating layer GI may be filled in the grooves G.

[0039] The top surface of the gate insulating layer GI may have a multi-step profile. The multi-step profile of the gate insulating layer GI may be transferred from the multi-step structure of the gate structure GST. The block word line BLKWL may have a multi-step profile on at least one of the top surface and the lower surface. The multi-step profile of the block word line BLKWL may be transferred from the gate insulating layer GI.

[0040] The first contact plug CT1 may pass through the channel pattern CP and may be connected to the corresponding local line LL. The first contact plug CT1 may pass through the interlayer insulating layer 25, the etch stop layer 24, the gate insulating layer GI, the channel pattern CP, and the buffer layer 23, and may be electrically connected to the corresponding local line LL. In an embodiment, the first contact plug CT1 may be directly connected to the channel pattern CP and the corresponding local line LL.

[0041] The second contact plug CT2 may be connected to the channel pattern CP. The second contact plug CT2 may pass through the interlayer insulating layer 25, the etch stop layer 24, and the gate insulating layer GI and may be connected to the channel pattern CP. In an embodiment, the second contact plug CT2 may be connected to the top surface of the channel pattern CP.

[0042] According to the above structure, the transfer transistor PT can be formed in the multi-step structure of the gate structure GST. The transfer transistor PT can be disposed at each step, and the transfer transistor PT can be arranged to be spaced apart along the first direction I. Therefore, the transfer transistor PT can be disposed at different heights.

[0043] In each pass transistor PT, the second contact plug CT2 may be connected to the source region of the channel pattern CP, and the first contact plug CT1 may be connected to the drain region of the channel pattern CP. Therefore, when the pass transistor is turned on, the bias of the global line may be transferred to the local line LL.

[0044] FIG. 3A to FIG. 3D is a diagram illustrating a structure of a semiconductor device according to an embodiment disclosed in the present invention. Figure 3D It is a floor plan. Figure 3A It is along Figure 3D A cross-sectional view taken along line AA′, Figure 3B It is along Figure 3D A cross-sectional view taken along line BB′, and Figure 3C It is along Figure 3DHereinafter, description of any contents overlapping with those already described may be omitted.

[0045] Reference FIG. 3A to FIG. 3D , the semiconductor device may include at least one of a gate structure GST, a channel pattern CP, a buffer layer 33, a gate insulating layer GI, a block word line BLKWL, an etch stop layer 34, an interlayer insulating layer 35, a first contact plug CT1, and a second contact plug CT2.

[0046] The gate structure GST may include alternately stacked local lines LL and insulating layers 32. A channel pattern CP may be disposed over the gate structure GST. A block word line BLKWL may be disposed over the channel pattern CP, may intersect the channel pattern CP, and may extend in a first direction I. An etch stop layer 34 may be disposed over the block word line BLKWL, the gate insulating layer GI, and the buffer layer 33.

[0047] The buffer layer 33 may be disposed above the gate structure GST. The buffer layer 33 may be disposed between the gate structure GST and the channel pattern CP. The buffer layer 33 may extend in the first direction I along the profile of the multi-step structure. Because the channel patterns CP are spaced apart from each other, the buffer layer 33 may also contact the block word line BLKWL filling the space between the continuous channel patterns CP. The buffer layer 33 may also have a multi-step structure profile, wherein each step of the buffer layer 33 is disposed under the corresponding channel pattern CP. Each step of the buffer layer 33 may only partially overlap with the corresponding channel pattern CP and may have an edge area that is not covered by the channel pattern CP.

[0048] The gate insulating layers GI may each surround a corresponding one of the channel patterns CP. More specifically, the gate insulating layer GI may be formed along the sidewalls and top surfaces of the corresponding channel patterns CP. The space between the adjacent channel patterns CP in the first direction I may not be filled with the gate insulating layer GI. In this case, the buffer layer 33 may be exposed between the gate insulating layers GI.

[0049] The block word line BLKWL may extend in the first direction I while surrounding the channel pattern CP. The block word line BLKWL may surround the top surface TS and the sidewall SW of the channel pattern CP. The block word line BLKWL may extend in the first direction I while surrounding at least three surfaces of the channel pattern CP with the gate insulating layer GI interposed therebetween. The block word line BLKWL may include a protrusion PP that protrudes between the channel patterns CP and contacts the buffer layer 33.

[0050] Each of the first contact plugs CT1 may pass through the etch stop layer 34, the gate insulating layer GI, and the corresponding channel pattern CP to be connected to the corresponding local line LL. The second contact plugs CT2 may pass through the etch stop layer 34 and the gate insulating layer GI to be connected to the corresponding channel pattern CP. Therefore, the bottom end of each second contact plug may contact the corresponding channel pattern CP.

[0051] According to the above structure, the transfer transistor PT can be arranged above the multi-step structure of the gate structure GST. The block word line BLKWL can protrude between the channel patterns CP, so the area where the block word line BLKWL and the channel pattern CP overlap can be increased. Therefore, the operating characteristics of the transfer transistor PT can be improved.

[0052] 4A to 4D is a diagram illustrating a structure of a semiconductor device according to an embodiment disclosed in the present invention. Figure 4D It is a floor plan. Figure 4A It is along Figure 4D A cross-sectional view taken along line AA′, Figure 4B It is along Figure 4D A cross-sectional view taken along line BB′, and Figure 4C It is along Figure 4D Hereinafter, description of the contents that have been previously described may be omitted.

[0053] Reference 4A to 4D The semiconductor device may include at least one of a gate structure GST, a channel pattern CP, a gate insulating layer GI, a block word line BLKWL, a capping layer 44, an interlayer insulating layer 45, a protective layer 48, a first contact plug CT1, a second contact plug CT2, and a third contact plug CT3.

[0054] The gate structure GST may include alternately stacked local lines LL and insulating layers 42. The gate structure GST may not include a multi-step structure, and a top surface of the gate structure GST may be flat.

[0055] The first contact plugs CT1 may extend through the gate structure GST and may be connected to the local lines LL, respectively. The first contact plugs CT1 may extend to different depths in the gate structure GST. Insulating spacers SPC may surround sidewalls of the first contact plugs CT1, respectively. The first contact plugs CT1 may be connected to the lower surface of the channel pattern CP.

[0056] The channel patterns CP may be disposed over the gate structure GST. On the top surface of the gate structure GST, the channel patterns CP may be disposed to correspond to the first contact plugs CT1, respectively. The channel patterns CP may be connected to the first contact plugs CT1, respectively. The channel patterns CP may be disposed at substantially the same height.

[0057] The gate insulating layer GI may surround the channel patterns CP, respectively. The gate insulating layer GI may be formed along the sidewalls and top surfaces of the channel patterns CP. Spaces between adjacent channel patterns CP in the first direction I may be filled with the gate insulating layer GI or may not be filled with the gate insulating layer GI. Figure 4B In the illustrated embodiment, the gate insulating layer GI does not completely fill the space between the channel patterns adjacent to each other in the first direction I.

[0058] The block word line BLKWL may be disposed above the channel pattern CP. The block word line BLKWL may include at least one of a first conductive layer 47A, a barrier layer 47B, and a second conductive layer 47C. The second conductive layer 47C may include a material having a lower specific resistance than the material of the first conductive layer 47A. In an embodiment, the first conductive layer 47A may be made of or include polysilicon, and the second conductive layer 47C may be made of or include a metal such as tungsten or molybdenum. The barrier layer 47B may be made of or include a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride.

[0059] The block word line BLKWL may surround the top surface and the sidewall of the channel pattern CP. The block word line BLKWL may protrude between the channel patterns CP. The block word line BLKWL may include a protrusion PP protruding between the channel patterns CP, such as Figure 4A The protrusion PP may contact the insulating layer 42. The block word line BLKWL may extend in the first direction I while surrounding the channel pattern CP.

[0060] A protective layer 48 may be disposed over the block word line BLKWL. The protective layer 48 may be used to protect the block word line BLKWL in a manufacturing process. In an embodiment, the protective layer 48 may be made of or include an oxide, and may reduce oxidation of the second conductive layer 47C including tungsten in a manufacturing process.

[0061] The capping layer 44 may be formed to at least partially surround the top surface and sidewalls of the block word line BLKWL. In an implementation, the capping layer 44 may reduce oxidation of the first conductive layer 47A and the second conductive layer 47C exposed through the sidewalls.

[0062] The second contact plug CT2 may pass through the interlayer insulating layer 45, the capping layer 44, and the gate insulating layer GI, and may be connected to the channel pattern CP, respectively. The second contact plug CT2 may be connected to the upper region of the channel pattern CP. Figure 4CAs shown, the bottom edge of the second contact plug CT2 may be slightly inserted into the upper region of the corresponding channel pattern CP.

[0063] At least one third contact plug CT3 may pass through the interlayer insulating layer 45 , the capping layer 44 , and the protection layer 48 , and may be connected to the block word line BLKWL.

[0064] According to the above structure, the pass transistor PT may be disposed above the gate structure GST. The pass transistor PT may be disposed at substantially the same height. The block word line BLKWL may protrude between the channel patterns CP, and the operation characteristics of the pass transistor PT may be improved.

[0065] Figure 5A and Figure 5B is a diagram illustrating a structure of a semiconductor device according to an embodiment disclosed in the present invention. Figure 5B is a plan view, and Figure 5A It is along Figure 5B Hereinafter, description of contents overlapping with the above contents may be omitted.

[0066] Reference Figure 5A and Figure 5B The semiconductor device may include at least one of a gate structure GST, a channel pattern CP, a gate insulating layer GI, a block word line BLKWL, a capping layer 54, an interlayer insulating layer 55, a protective layer 58, an insulating layer 59, a first contact plug CT1, a second contact plug CT2, and a third contact plug CT3.

[0067] The gate structure GST may include alternately stacked local lines LL and insulating layers 52. The gate structure GST may have a flat top surface and may not include a multi-step structure.

[0068] The semiconductor device may include a plurality of first contact plugs CT1. The first contact plugs CT1 may extend through the gate structure GST and may be respectively connected to the local lines LL. The first contact plugs CT1 may extend to different depths in the gate structure GST. Insulating spacers SPC may respectively surround sidewalls of the first contact plugs CT1.

[0069] The channel pattern CP may be disposed above the gate structure GST. The channel pattern CP may be disposed above the top surface of the gate structure GST to correspond to the first contact plugs CT1, respectively. The channel patterns CP may be connected to the first contact plugs CT1, respectively. The lower surface of the channel pattern CP may be in contact with the top surface of the first contact plug CT1. The channel pattern CP may include a junction. In an embodiment, the channel pattern CP may include a source region SR and a drain region DR disposed on both sides of the block word line BLKWL. The source region SR and the drain region DR may be regions doped with N-type or P-type impurities at a high concentration.

[0070] The block word line BLKWL may be disposed above the channel pattern CP, may intersect the channel pattern CP, and may extend in the first direction I. The gate insulating layer GI may be disposed between the channel pattern CP and the block word line BLKWL, respectively. The block word line BLKWL may include at least one of a first conductive layer 57A, a barrier layer 57B, and a second conductive layer 57C. The second conductive layer 57C may include a material having a lower specific resistance than that of the material of the first conductive layer 57A. The barrier layer 57B may be made of or include a metal nitride.

[0071] A protection layer 58 may be disposed over the block word line BLKWL. The protection layer 58 may be used to protect the block word line BLKWL in a manufacturing process, and may be made of or include oxide.

[0072] The capping layer 54 may be formed to at least partially surround the top surface and sidewalls of the block word line BLKWL. The capping layer 54 may be formed along the contours of the insulating layer 59, the channel pattern CP, the block word line BLKWL, and the protective layer 58. The capping layer 54 may reduce oxidation of the first conductive layer 57A and the second conductive layer 57C exposed through the sidewalls.

[0073] The second contact plug CT2 may pass through the interlayer insulating layer 55 and the capping layer 54 and may be connected to the channel pattern CP. The third contact plug CT3 may pass through the interlayer insulating layer 55, the capping layer 54, and the protective layer 58 and may be connected to the block word line BLKWL.

[0074] According to the above structure, the transfer transistor PT may be disposed above the gate structure GST. A plurality of transfer transistors PT may be formed and the plurality of transfer transistors PT may be disposed at substantially the same height. The transfer transistor PT may have a planar shape.

[0075] Figure 6 is a diagram illustrating a structure of a semiconductor device according to an embodiment disclosed in the present invention.

[0076] Reference Figure 6, the semiconductor device may include a gate structure GST, a transfer transistor PT, and a second contact plug CT2. The semiconductor device may also include a substrate 60, a peripheral circuit PC, a channel structure CH, a buffer layer 63, a source structure 67, a first interlayer insulating layer IL1, a second interlayer insulating layer IL2, a third interlayer insulating layer IL3, a first interconnection structure IC1, a second interconnection structure IC2, a first bonding pad BP1, and a second bonding pad BP2.

[0077] The gate structure GST may include a local line LL and an insulating layer 62 alternately stacked. The gate structure GST may include a multi-step structure, and the pad PD of the local line LL may be exposed through the multi-step structure. The transfer transistor PT may be arranged above the multi-step structure. The transfer transistor PT may be arranged above the pad PD, respectively. The transfer transistor PT may include a channel pattern CP, a block word line, and a gate insulating layer. The buffer layer 63 may be arranged between the gate structure GST and the channel pattern CP. The second contact plug CT2 may connect the channel pattern CP and the global line, respectively. Here, the global line may be arranged in the first interlayer insulating layer IL1 or may be arranged in the second interlayer insulating layer IL2.

[0078] The channel structure CH may pass through the gate structure GST. The channel structure CH may include at least one of a channel layer 64, a memory layer 65, and an insulating core 66. A source structure 67 may be disposed over the gate structure GST, and the channel structure CH may extend into the source structure 67. A third interlayer insulating layer IL3 may be disposed over the source structure 67 and the uppermost insulating layer 62.

[0079] The peripheral circuit PC may be disposed over the substrate 60. The peripheral circuit PC may include a row decoder, a page buffer, a logic circuit, etc. In an embodiment, an active region may be defined in the substrate 60 by an element isolation layer 4, and the transistor TR may be disposed in the active region. The transistor TR may include a gate insulating layer 1, a gate electrode 2, and a junction 3.

[0080] The first interconnect structure IC1 and the first bonding pad BP1 may be disposed in the first interlayer insulating layer IL1. The first interconnect structure IC1 may include a through hole, a line, etc. The first interconnect structure IC1 may be electrically connected to the channel structure CH, the transfer transistor PT, etc. The second interconnect structure IC2 and the second bonding pad BP2 may be disposed in the second interlayer insulating layer IL2. The second interconnect structure IC2 may include a through hole, a line, etc. The second interconnect structure IC2 may be electrically connected to the peripheral circuit PC.

[0081] According to the above structure, the cell array and the peripheral circuit PC can be electrically connected through the first bonding pad BP1 and the second bonding pad BP2. Since the transfer transistor PT is disposed above the multi-step structure rather than on the substrate 60, the area on the substrate 60 where the peripheral circuit PC is to be formed can be sufficiently ensured.

[0082] In addition, in this figure, the gate structure GST is shown to include an inverted multi-step structure, but the gate structure GST may include a multi-step structure in a forward direction. In this case, the peripheral circuit PC and the gate structure GST may be sequentially stacked on the substrate, and the bonding pad may be omitted.

[0083] Figure 7 is a diagram illustrating a structure of a semiconductor device according to an embodiment disclosed in the present invention.

[0084] Reference Figure 7 The semiconductor device may include a gate structure GST, a transfer transistor PT, a first contact plug CT1, and an insulating spacer SPC. The semiconductor device may also include a substrate 70, a peripheral circuit PC, a channel structure CH, a source structure 77, a first interlayer insulating layer IL1, a second interlayer insulating layer IL2, a third interlayer insulating layer IL3, a first interconnection structure IC1, a second interconnection structure IC2, a first bonding pad BP1, and a second bonding pad BP2.

[0085] The gate structure GST may include alternately stacked local lines LL and insulating layers 72. The first contact plugs CT1 may extend toward the rear surface RS through the front surface FS of the gate structure GST and may be electrically connected to the local lines LL, respectively. Insulating spacers SPC may surround sidewalls of the first contact plugs CT1, respectively.

[0086] The transfer transistors PT may be disposed over the front surface FS of the gate structure GST to correspond to the first contact plugs CT1. The transfer transistors PT may each include a channel pattern CP, a block word line, and a gate insulating layer. The first contact plugs CT1 may connect the channel pattern CP and the local line LL, respectively.

[0087] The channel structure CH may pass through the gate structure GST. The channel structure CH may include at least one of a channel layer 74, a memory layer 75, and an insulating core 76. A source structure 77 may be disposed over the gate structure GST, and the channel structure CH may extend into the source structure 77. A third interlayer insulating layer IL3 may be disposed over the source structure 77 and the uppermost insulating layer 72.

[0088] The peripheral circuit PC may be disposed above the substrate 70. The peripheral circuit PC may include a row decoder, a page buffer, a logic circuit, etc. In an embodiment, an active region may be defined in the substrate 70 by an element isolation layer 4, and the transistor TR may be disposed in the active region. The transistor TR may include a gate insulating layer 1, a gate electrode 2, and a junction 3.

[0089] The first interconnect structure IC1 and the first bonding pad BP1 may be disposed in the first interlayer insulating layer IL1. The first interconnect structure IC1 may include a through hole, a line, etc. The first interconnect structure IC1 may be electrically connected to the channel structure CH, the transfer transistor PT, etc. The second interconnect structure IC2 and the second bonding pad BP2 may be disposed in the second interlayer insulating layer IL2. The second interconnect structure IC2 may include a through hole, a line, etc. The second interconnect structure IC2 may be electrically connected to the peripheral circuit PC.

[0090] According to the above structure, the cell array and the peripheral circuit PC can be electrically connected through the first bonding pad BP1 and the second bonding pad BP2. Since the transfer transistor PT is disposed above the front surface FS of the gate structure GST instead of on the substrate 70, the area on the substrate 70 where the peripheral circuit PC is to be formed can be sufficiently ensured.

[0091] Figure 8 , Fig. 9A , Fig. 9B , FIG. 10A to FIG. 10C , FIG. 11A to FIG. 11C , FIG. 12A to FIG. 12C , FIG. 13A to FIG. 13D as well as FIG. 14A to FIG. 14D 1 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment disclosed in the present invention. Each diagram may be a plan view or a cross-sectional view. Hereinafter, descriptions of contents overlapping with the above contents may be omitted.

[0092] Reference Figure 8 , a stack including alternately stacked first material layers 81 and second material layers 82 can be formed. The first material layer 81 can be used to form a local line. The second material layer 82 can be used to insulate the stacked local lines from each other. The first material layer 81 can be made of a material having a high etching selectivity relative to the second material layer 82 or include a material having a high etching selectivity relative to the second material layer 82. The first material layer 81 can be made of a sacrificial material such as a nitride or include a sacrificial material such as a nitride, or can be made of a conductive material such as, for example, polysilicon, tungsten, or molybdenum or include a conductive material such as, for example, polysilicon, tungsten, or molybdenum. The second material layer 82 can be made of an insulating material such as an oxide, a nitride, or a void or include an insulating material such as an oxide, a nitride, or a void.

[0093] The stack ST may include a cell region and a contact region. The cell region CR may be a region where memory cells are to be stacked, and the contact region CTR may be a region where an interconnection structure for transmitting a driving voltage to the stacked memory cells is to be disposed.

[0094] Subsequently, a channel structure CH may be formed in the stack ST. The channel structure CH may pass through the cell region CR of the stack ST. Subsequently, a multi-step structure may be formed in the stack ST. The multi-step structure may be formed in the contact region CTR of the stack ST. Each first material layer 81 may be exposed by the multi-step structure. The portion of the first material layer 81 exposed by the multi-step structure may be defined as a pad PD.

[0095] Subsequently, a buffer layer 83 may be formed on the stack ST. The buffer layer 83 may be formed in the cell region CR and the contact region CTR. The buffer layer 83 may be formed along the contour of the multi-step structure. The buffer layer 83 may be made of or include an insulating material such as an oxide or a nitride.

[0096] Subsequently, a channel layer 84 may be formed on the buffer layer 83. The channel layer 84 may be formed along the contour of the multi-step structure. The channel layer 84 may be made of or include a semiconductor material such as, for example, polysilicon, silicon germanium, germanium, or gallium arsenide.

[0097] Subsequently, a pad layer P may be formed on the channel layer 84. The pad layer P may be formed along the contour of the multi-step structure and may be formed in a method with poor step coverage. The uniformity of the thickness of the pad layer P may be lower than the uniformity of the thickness of the buffer layer 83. The pad layer P may include a horizontal portion extending in a horizontal direction and a vertical portion extending in a vertical direction, and may be formed to have a smaller thickness in the vertical portion than in the horizontal portion.

[0098] Reference Fig. 9A and Fig. 9B , a channel pattern 84A may be formed. In an embodiment, the pad layer P and the channel layer 84 may be etched by a wet etching method. Because the pad layer P has a relatively small thickness in the vertical portion, the vertical portion is first etched to expose the channel layer 84. Therefore, the vertical portion of the channel layer 84 may be etched first and the horizontal portion may be retained. Thus, a channel pattern 84A arranged to be spaced apart from each other on a multi-step structure may be formed. The channel pattern 84A may be arranged above each step and may be adjacent to each other in the first direction I. In the process of forming the channel pattern 84A, the buffer layer 83 may be partially etched. A groove G arranged between the channel patterns 84A and extending in the second direction II may be formed on the top surface of the buffer layer 83.

[0099] Subsequently, a well region may be formed in the channel pattern 84A. In an embodiment, the well region may be formed by doping P-type impurities. The process of forming the well region may be omitted.

[0100] Reference FIG. 10A to FIG. 10C , a gate insulating layer 85 may be formed on the channel pattern 84A. In an embodiment, the gate insulating layer 85 may be formed in an oxidation process. Through the oxidation process, a surface of the channel pattern 84A may be oxidized to form the gate insulating layer 85.

[0101] Subsequently, a block word line 86 may be formed on the gate insulating layer 85. First, a conductive layer may be formed on the gate insulating layer 85, and the conductive layer may be etched to form the block word line 86. The block word line 86 may be disposed in the contact region and may extend in the first direction I along a multi-step profile. In an embodiment, the block word line 86 may include polysilicon and a metal. The metal may include titanium, tungsten, molybdenum, tungsten nitride, tungsten silicon nitride, and the like.

[0102] Subsequently, a junction may be formed in the channel pattern 84A by doping N-type or P-type impurities. The junction may be disposed on both sides of the block word line 86. In an embodiment, the process of forming the junction may be omitted.

[0103] Subsequently, an etch stop layer 87 may be formed on the block word line 86. The etch stop layer 87 may be used to control the depth of forming a contact plug in a subsequent process, and may include silicon carbon nitride (SiCN).

[0104] Reference FIG. 11A to FIG. 11C , a mask pattern 88 may be formed on the etch stop layer 87. The mask pattern 88 may cover the contact region CTR and expose the cell region CR. Subsequently, the etch stop layer 87, the gate insulating layer 85, and the channel pattern 84A may be etched using the mask pattern 88 as an etch barrier. Subsequently, the mask pattern 88 may be removed, and a cleaning process may be performed.

[0105] Reference FIG. 12A to FIG. 12C , an interlayer insulating layer 89 may be formed. Subsequently, the first material layer 81 may be replaced with a local line 81L. In an embodiment, after forming a slit SL extending through the stack ST in the first direction I, the first material layer 81 may be removed through the slit SL. Subsequently, a local line 81L may be formed in a region where the first material layer 81 is removed. The local line 81L may include a metal such as tungsten and molybdenum. Thus, a gate structure GST including the local line 81L and the second material layer 82 alternately stacked may be formed. Subsequently, a slit structure SLS may be formed in the slit SL. The slit structure SLS may include at least one of an insulating material, a semiconductor material, and a conductive material.

[0106] For reference, when the first material layer 81 includes a conductive material, the replacement process may be omitted. In this case, the first material layer 81 may be used as a local line 81L, and the stack ST may be formed into a gate structure GST.

[0107] Reference FIG. 13A to FIG. 13D , a first opening OP1 may be formed. The first opening OP1 may be disposed on one side of the block word line 86. The first opening OP1 may pass through the interlayer insulating layer 89, the etch stop layer 87, and the gate insulating layer 85, and may expose the channel pattern 84A. In an embodiment, a preliminary first opening may be formed to expose the surface of the etch stop layer 87. The etch stop layer 87 may include a material having a high etch selectivity relative to the interlayer insulating layer 89, and the depth of the first preliminary opening may be adjusted using the etch selectivity. Subsequently, the first opening OP1 exposing the channel pattern 84A may be formed by extending the preliminary first opening downward.

[0108] A second opening OP2 may be formed. The second opening OP2 may be disposed on the other side of the block word line 86. The first opening OP1 and the second opening OP2 may be adjacent to each other in the second direction II, with the block word line 86 interposed therebetween. The second opening OP2 may pass through the interlayer insulating layer 89, the etch stop layer 87, and the gate insulating layer 85, and may expose the channel pattern 84A. In an embodiment, after forming a second preliminary opening to expose the surface of the etch stop layer 87, the second opening OP2 may be formed by extending the second preliminary opening downward. When forming the preliminary first opening, a preliminary second opening may be formed. In addition, when forming the first opening OP1, the second opening OP2 may be formed.

[0109] Reference FIG. 14A to FIG. 14D , the first opening OP1 may extend downward. In an embodiment, a mask pattern covering the second opening OP2 and exposing the first opening OP1 may be formed on the interlayer insulating layer 89. Subsequently, the channel pattern 84A may be etched using the mask pattern as an etching barrier to extend the first opening OP1 downward. Thus, the first opening OP1 may be selectively extended to a depth that exposes the pads PD of the local lines 81L, respectively. Subsequently, the mask pattern may be removed.

[0110] Subsequently, a first contact plug CT1 may be formed in the first opening OP1. The first contact plug CT1 may pass through the channel pattern 84A and may be connected to the corresponding pad PD of the local line 81L. The first contact plug CT1 may pass through the channel pattern 84A and may connect the channel pattern 84A and the local line 81L. In an embodiment, a barrier metal layer may be formed, and a gap-filling metal layer may be formed in the barrier metal layer. The barrier metal layer may be made of or include a metal nitride, and the gap-filling metal layer may include tungsten or molybdenum, etc.

[0111] A second contact plug CT2 may be formed in the second opening OP2. The second contact plug CT2 may be connected to the channel pattern 84A, respectively. The second contact plug CT2 may connect the channel pattern 84A and the global line. In an embodiment, a barrier metal layer may be formed, and a gap-filling metal layer may be formed in the barrier metal layer. The barrier metal layer may be made of or include a metal nitride, and the gap-filling metal layer may include tungsten or molybdenum, etc. When the first contact plug CT1 is formed, the second contact plug CT2 may be formed.

[0112] According to the above-mentioned manufacturing method, a transfer transistor disposed in the region where the channel pattern 84A and the block word line 86 intersect can be formed. The transfer transistor can be disposed above the multi-step structure and can be disposed at different heights. The junction of the transfer transistor and the local line 81L can be connected through the first contact plug CT1, and the junction of the transfer transistor and the global line can be connected through the second contact plug CT2.

[0113] In addition, although not shown in this figure, a wafer bonding process may be additionally performed. After forming a first wafer including a cell array and a transfer transistor and a second wafer including a peripheral circuit, the first wafer and the second wafer may be bonded. Since the transfer transistor is formed on the multi-step structure of the first wafer, the area on the second wafer where the peripheral circuit is to be formed may be sufficiently ensured.

[0114] FIG. 15A to FIG. 15C 2 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0115] Reference Fig.15A , a stack including first material layers 91 and second material layers 92 alternately stacked may be formed. Subsequently, a multi-step structure may be formed in the stack ST. Each first material layer 91 may be exposed by the multi-step structure. Subsequently, a buffer layer 93 may be formed on the stack ST, and a channel layer 94 may be formed on the buffer layer 93. Subsequently, a mask pattern M may be formed on the channel layer 94.

[0116] Reference Fig. 15B , a channel pattern 94A may be formed by etching the channel layer 94 using the mask pattern M as an etching barrier. The channel pattern 94A may be disposed above each step. Subsequently, a gate insulating layer 95 may be formed on the channel pattern 94A. In an embodiment, the gate insulating layer 95 may be formed in an oxidation process. Through the oxidation process, the top surface and the sidewalls of the channel pattern 94A may be oxidized, and gate insulating layers 95 respectively surrounding the channel patterns 94A may be formed.

[0117] Subsequently, a block word line 96 may be formed. A conductive layer may be formed on the gate insulating layer 95, and the block word line 96 may be formed by etching the conductive layer. The block word line 96 may include a protrusion PP protruding between the channel patterns 94A, and may surround the top surface and sidewalls of the channel pattern 94A.

[0118] Then, as mentioned above FIG. 10A to FIG. 10C , FIG. 11A to FIG. 11C , FIG. 12A to FIG. 12C , FIG. 13A to FIG. 13D as well as FIG. 14A to FIG. 14D As described, an etch stop layer may be formed on the block word line 96 , and a first contact plug and a second contact plug may be formed.

[0119] According to the above manufacturing method, a pass transistor disposed in a region where the channel pattern 94A and the block word line 96 intersect may be formed. The block word line 96 may be formed to surround the top surface and sidewalls of the channel pattern 94A, and the pass transistor may have a Fin type structure.

[0120] Fig.16 , 17A to 17C as well as 18A to 18D 2 is a diagram illustrating a manufacturing method according to an embodiment of the present disclosure. Hereinafter, descriptions of contents overlapping with the above contents may be omitted.

[0121] Reference Fig.16 , a gate structure GST including local lines 101L and insulating layers 102 alternately stacked may be formed. Subsequently, first contact plugs CT1 extending through the gate structure GST and respectively connected to the local lines 101L may be formed. Insulating spacers 103 may respectively surround sidewalls of the first contact plugs CT1. For reference, in this figure, for ease of description, only a portion of the first contact plugs CT1 is shown.

[0122] Subsequently, a channel layer 104 may be formed on the gate structure GST. The channel layer 104 may be made of or include silicon germanium, germanium, polysilicon, gallium arsenide, or the like.

[0123] Reference 17A to 17C, the channel layer 104 may be etched to form a channel pattern 104A. In an embodiment, the channel layer 104 may be etched using a mask pattern as an etching barrier. The channel patterns 104A may be respectively disposed on the first contact plugs CT1, and the channel patterns 104A and the first contact plugs CT1 may be respectively connected to each other. The channel pattern 104A and the local line 101L may be connected through the first contact plugs CT1.

[0124] Subsequently, the channel pattern 104A may be oxidized to form a gate insulating layer 105. Subsequently, a well region may be formed by doping P-type impurities in the channel pattern 104A.

[0125] Subsequently, a block word line 106 extending to cross the channel pattern 104A may be formed on the gate structure GST. In an embodiment, after forming the polysilicon layer 106A, the barrier layer 106B, and the metal layer 106C, a protective layer 109 may be formed on the metal layer 106C. Subsequently, the protective layer 109, the metal layer 106C, the barrier layer 106B, and the polysilicon layer 106A may be etched to form the block word line 106. The barrier layer 106B may be made of or include a metal nitride, and the metal layer 106C may be made of or include tungsten or molybdenum, etc. The protective layer 109 may be used to reduce oxidation of the metal layer 106C in a manufacturing process. In an embodiment, the protective layer 109 may include tetraethyl orthosilicate (TEOS).

[0126] Reference 18A to 18D , a capping layer 107 may be formed. The capping layer 107 may surround the sidewalls of the block word line 106. Here, the sidewalls may be etching surfaces ES, and the polysilicon layer 106A, the barrier layer 106B, and the metal layer 106C may be exposed through the etching surfaces ES. The capping layer 107 may reduce oxidation of the exposed polysilicon layer 106A and the metal layer 106C. In an embodiment, the capping layer 107 may include nitride.

[0127] Subsequently, an interlayer insulating layer 108 may be formed, and a second contact plug CT2 extending through the interlayer insulating layer 108 may be formed. The second contact plug CT2 may pass through the capping layer 107 and the gate insulating layer 105, and may be connected to the channel pattern 104A. The channel pattern 104A and the global line may be connected through the second contact plug CT2.

[0128] A third contact plug CT3 extending through the interlayer insulating layer 108 may be formed. The third contact plug CT3 may pass through the capping layer 107 and the protective layer 109 and may be connected to the block word line 106. In an embodiment, the third contact plug CT3 may pass through the protective layer 109 to be connected to the metal layer 106C. The third contact plug CT3 may include a barrier metal layer and a gap-filling metal layer. For reference, when forming the third contact plug CT3, a contact plug connected to the channel structure may be formed.

[0129] According to the above-described manufacturing method, a pass transistor disposed in a region where the channel pattern 104A and the block word line 106 intersect may be formed. The pass transistor may be disposed over the gate structure GST and may be disposed at substantially the same height.

[0130] 19A to 19D 2 is a diagram illustrating a manufacturing method according to an embodiment of the present disclosure. Hereinafter, descriptions of contents overlapping with the above contents may be omitted.

[0131] Reference Fig.19A , a gate structure GST including alternately stacked local lines 111L and insulating layers 112 may be formed. Subsequently, first contact plugs CT1 extending through the gate structure GST and respectively connected to the local lines 111L may be formed. Insulating spacers 113 may respectively surround sidewalls of the first contact plugs CT1. For reference, in this figure, one first contact plug CT1 is enlarged for ease of description.

[0132] Subsequently, a channel layer 114 may be formed on the gate structure GST, and a gate insulating layer 115 may be formed on the channel layer 114. Subsequently, a conductive layer for forming a block word line may be formed on the gate insulating layer 115. In an embodiment, a polysilicon layer 116A may be formed on the gate insulating layer 115. The polysilicon layer 116A may be doped with N-type or P-type impurities.

[0133] Reference Fig.19B , the polysilicon layer 116A, the gate insulating layer 115, and the channel layer 114 may be etched. Thus, the channel pattern 114A may be formed. Subsequently, the insulating layer 120 may be formed in the region where the polysilicon layer 116A, the gate insulating layer 115, and the channel layer 114 are etched away.

[0134] Reference Fig.19C, a barrier layer 116B, a metal layer 116C, and a protective layer 119 may be formed. Subsequently, after etching the protective layer 119, the metal layer 116C, the barrier layer 116B, and the polysilicon layer 116A may be etched to form a block word line 116. For reference, the block word line 116 may be formed by sequentially forming a polysilicon layer 116A, a barrier layer 116B, a metal layer 116C, and a protective layer 119, and then etching the polysilicon layer 116A, the barrier layer 116B, the metal layer 116C, and the protective layer 119 at once.

[0135] Subsequently, a capping layer 117 may be formed on the block word line 116 and the channel pattern 114A. Subsequently, the channel pattern 114A may be doped with N-type or P-type impurities to form junctions JN1 and JN2. The first junction JN1 and the second junction JN2 may be formed on both sides of the block word line 116, and the first junction JN1 may be connected to the first contact plug CT1.

[0136] Subsequently, an interlayer insulating layer 118 may be formed, and a second contact plug CT2 extending through the interlayer insulating layer 118 may be formed. The second contact plug CT2 may pass through the capping layer 117 and may be connected to the channel pattern 114A. The second junction JN2 of the channel pattern 114A and the global line may be connected through the second contact plug CT2.

[0137] A third contact plug CT3 may be formed extending through the interlayer insulating layer 118. The third contact plug CT3 may pass through the capping layer 117 and the protection layer 119 and may be connected to the block word line 116. In an implementation, the third contact plug CT3 may be connected to the metal layer 116C.

[0138] When the second contact plug CT2 is formed, the third contact plug CT3 may be formed. When the second opening OP2 exposing the second junction JN2 is formed, the third opening OP3 exposing the block word line 116 may be formed. The third opening OP3 may expose the metal layer 116C. When the second contact plug CT2 is formed in the second opening OP2, the third contact plug CT3 may be formed in the third opening OP3.

[0139] According to the above-described manufacturing method, a pass transistor disposed in a region where the channel pattern 114A and the block word line 116 intersect may be formed. The pass transistor may be disposed over the gate structure GST and may be disposed at substantially the same height.

[0140] The structures and manufacturing methods according to the above-described embodiments can be applied to semiconductor devices of various structures. Fig. 20 and Fig.21 A schematic configuration of a semiconductor device to which the above-described embodiments are applicable is illustrated.

[0141] Fig. 20 is a diagram showing the structure of a semiconductor device according to an embodiment disclosed in the present invention.

[0142] Reference Fig. 20 , the semiconductor device may include a substrate SUB, a peripheral circuit PC, and a memory cell array CA. Here, the peripheral circuit PC and the memory cell array CA may be formed on the same substrate.

[0143] The substrate SUB may be made of or include a semiconductor material. In an embodiment, the semiconductor material may include at least one of a group IV semiconductor, a group III-V compound semiconductor, and a group II-VI compound semiconductor. Here, the group IV semiconductor may include single crystal silicon Si, polycrystalline silicon, germanium Ge, or silicon germanium SiGe. The group III-V compound semiconductor may include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. The group II-VI compound semiconductor may include ZnS, ZnO, or CdS.

[0144] The substrate SUB may include a dielectric layer. The substrate SUB may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate SUB may include an organic material. In an embodiment, the substrate SUB may include graphene.

[0145] The substrate SUB may be a bulk wafer or an epitaxial layer grown by a selective epitaxial growth (SEG) method. The substrate SUB may be a layer formed by a metal induced lateral crystallization (MILC) method and may partially include a metal. The substrate SUB may have a single crystalline state, a polycrystalline state, or an amorphous state. The substrate SUB may include impurities of group II, group III, group IV, group V, or group VI. In an embodiment, the substrate SUB may include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0146] The peripheral circuit PC may be disposed between the substrate SUB and the memory cell array CA. The peripheral circuit PC may include a row decoder, a column decoder, a page buffer, a logic circuit, a control circuit, a sense amplifier, an input / output circuit, etc. In an embodiment, the peripheral circuit PC may include an NMOS transistor, a PMOS transistor, a resistor, a capacitor, etc. The peripheral circuit PC may also include an interconnect structure. The interconnect structure may be used as a path for transmitting an operating voltage, and may include a contact plug, a line, etc.

[0147] The memory cell array CA may include memory cells. In an embodiment, the memory cell array CA may include a memory string connected between a source line and a bit line, and each memory string may include stacked memory cells. In an embodiment, the memory cell array CA may include a memory cell connected between a word line and a bit line. The memory cell array CA may also include an interconnect structure.

[0148] Fig.21 is a diagram showing the structure of a semiconductor device according to an embodiment disclosed in the present invention.

[0149] Reference Fig.21 , the semiconductor device may include a substrate SUB, a peripheral circuit PC, a bonding structure BS and a memory cell array CA. Here, the peripheral circuit PC and the memory cell array CA may be formed on separate substrates and then bonded. The semiconductor device may further include a supporting base SP_B.

[0150] The substrate SUB may be used as a support member in the process of forming the peripheral circuit PC. The support base SP_B may be used as a support member in the process of forming the memory cell array CA. In an embodiment, after separately manufacturing a first wafer including the memory cell array CA and a second wafer including the peripheral circuit PC, the first wafer and the second wafer may be electrically connected through a bonding structure BS. After bonding, at least a portion of the support base SP_B of the first wafer may be removed. The support base SP_B may be completely removed or may be partially retained on the memory cell array CA.

[0151] The support substrate SP_B may be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The support substrate SP_B may be a bulk wafer, an epitaxial layer grown by a selective epitaxial growth (SEG) method, or a layer formed by a metal induced lateral crystallization (MILC) method. The support substrate SP_B may have a single crystal state, a polycrystalline state, or an amorphous state. The support substrate SP_B may include impurities of group II, group III, group IV, group V, or group VI.

[0152] The bonding structure BS can be used to connect the memory cell array CA and the peripheral circuit PC. In an embodiment, the memory cell array CA and the peripheral circuit PC can be bonded by a wafer-to-wafer bonding method, a chip-to-wafer bonding method, a chip-to-chip bonding method, etc. The bonding structure BS may include a bonding pad, a bonding layer, a bonding interface, etc. The bonding pad may include a metal such as copper and aluminum, and / or an alloy. The bonding interface may include a non-metal-non-metal interface, a metal-metal interface, etc. The memory cell array CA and the peripheral circuit PC may be electrically connected via the bonding structure BS.

[0153] For reference, the interconnection structure included in the memory cell array CA and / or the peripheral circuit PC can be directly connected without a bonding pad. In an embodiment, a bonding layer included in the memory cell array CA and a bonding layer included in the peripheral circuit PC can be bonded to form a bonding interface, and the interconnection structure included in the memory cell array CA and the interconnection structure included in the peripheral circuit PC can be directly connected. Thus, contact plugs, wires, etc. formed on different wafers can be electrically connected without separate bonding pads.

[0154] Other structures can be referred to above Fig. 20 The structures described are the same or similar.

[0155] In addition, the semiconductor device may have a Fig. 20 and Fig.21 The described embodiments may be combined into a structure, or may have a partially modified structure. Fig. 20 and Fig.21 In the described embodiments, the positions of the memory cell array CA and the peripheral circuit PC may be changed. At least one memory cell array CA and / or at least one peripheral circuit PC may be additionally incorporated into the reference Fig. 20 In an embodiment, a portion of the peripheral circuit PC may be provided in the memory cell array CA.

[0156] Although the embodiments of the technical concept disclosed in the present invention have been described with reference to the accompanying drawings, this is only used to describe the embodiments of the concept disclosed in the present invention, and the present invention is not limited to the above-mentioned embodiments. Within the scope of the technical concept disclosed in the present invention described in the claims, technicians in the field to which the present invention belongs will be able to make various forms of replacement, modification and variation to the embodiments, and these also belong to the scope of the present invention.

[0157] CROSS-REFERENCE TO RELATED APPLICATIONS

[0158] This application claims priority to Korean Patent Application No. 10-2023-0128779 filed on September 26, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: A gate structure, the gate structure comprising a stacked local line and a multi-step structure, wherein the multi-step structure defines a pad of the local line; Channel patterns, the channel patterns are respectively arranged above the pads; a block word line disposed above the channel pattern and extending along an outline of the multi-step structure; and First contact plugs pass through the channel patterns and connect the channel patterns and the local lines, respectively.

2. The semiconductor device according to claim 1, further comprising: a global line disposed above the gate structure; as well as Second contact plugs are provided to connect the channel patterns and the global lines, respectively.

3. The semiconductor device according to claim 1, wherein The multi-step structure extends in a first direction, and the channel patterns are arranged in the first direction.

4. The semiconductor device according to claim 1, wherein The block word line extends in a first direction, and the channel pattern extends in a second direction crossing the first direction.

5. The semiconductor device according to claim 1, further comprising: A gate insulating layer is disposed between the channel pattern and the block word line.

6. The semiconductor device according to claim 1, further comprising: An etch stop layer is disposed above the block word line.

7. The semiconductor device according to claim 6, wherein: The first contact plug passes through the etch stop layer.

8. The semiconductor device according to claim 1, wherein The block word line includes a plurality of protrusions spaced apart from each other and protruding between the channel patterns.

9. The semiconductor device according to claim 8, wherein: The block word line surrounds a top surface and sidewalls of the channel pattern.

10. A semiconductor device, comprising: a gate structure comprising stacked local lines; first contact plugs extending through the gate structure and connected to the local lines, respectively; channel patterns, the channel patterns being disposed above the gate structures and respectively connected to the first contact plugs; as well as A block word line is disposed above the channel pattern.

11. The semiconductor device according to claim 10, further comprising: a global line disposed above the gate structure; as well as The second contact plugs are respectively connected to the channel patterns and the global lines.

12. The semiconductor device according to claim 11, wherein The first contact plug is connected to a lower surface of the channel pattern, and the second contact plug is connected to a top surface of the channel pattern.

13. The semiconductor device according to claim 10, further comprising: A gate insulating layer surrounds the channel patterns respectively.

14. The semiconductor device according to claim 10, further comprising: A capping layer is disposed above the block word line and surrounds a sidewall of the block word line.

15. The semiconductor device according to claim 14, further comprising: a global line disposed above the gate structure; as well as Second contact plugs pass through the capping layer and connect the channel patterns and the global lines, respectively.

16. The semiconductor device according to claim 10, wherein: The block word line includes a protrusion protruding between the channel patterns.

17. The semiconductor device according to claim 16, wherein: The block word line surrounds a top surface and sidewalls of the channel pattern.

18. The semiconductor device according to claim 10, further comprising: A third contact plug is connected to the block word line.

19. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a laminate including alternately stacked first material layers and second material layers; forming a multi-step structure in the stack such that each of the first material layers is exposed; forming a channel pattern on the multi-step structure; forming a block word line extending along an outline of the multi-step structure; as well as A first contact plug is formed passing through the channel pattern and extending into the stack.

20. The method according to claim 19, further comprising the steps of: forming second contact plugs respectively connected to the channel patterns; and Global lines respectively connected to the second contact plugs are formed.

21. The method according to claim 19, wherein: The step of forming the channel pattern comprises the following steps: forming a buffer layer on the stack; forming a channel layer on the buffer layer; and A pad layer is formed on the channel layer.

22. The method according to claim 21, wherein: The step of forming the channel pattern further includes the following steps: The channel pattern is formed by etching the pad layer and the channel layer in a wet etching method.

23. The method according to claim 19, further comprising the steps of: A gate insulating layer is formed by oxidizing the channel pattern.

24. The method according to claim 19, wherein: The step of forming the block word line comprises the following steps: The block word line is formed to surround a top surface and a sidewall of the channel pattern.

25. The method according to claim 19, further comprising the steps of: An etch stop layer is formed on the block word line.

26. The method according to claim 25, wherein: The step of forming the first contact plug comprises the following steps: forming a preliminary first opening exposing the etch stop layer; forming a first opening by extending the preliminary first opening to expose the channel pattern; extending the first openings to expose the first material layers respectively; and The first contact plug is formed in the extended first opening.

27. The method according to claim 25, wherein: The step of forming the first contact plug comprises the following steps: forming a first opening exposing the channel pattern; forming a second opening exposing the channel pattern; selectively extending the first opening among the first opening and the second opening to expose the first material layer respectively; forming the first contact plug in the extended first opening; and A second contact plug is formed in the second opening.

28. The method according to claim 27, wherein: The first opening and the second opening are formed simultaneously, and Wherein, the first contact plug and the second contact plug are formed simultaneously.

29. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a gate structure including alternately stacked local lines and insulating layers; forming first contact plugs extending through the gate structure and connected to the local lines, respectively; forming channel patterns respectively connected to the first contact plugs on the gate structure; as well as A block word line is formed to cross the channel pattern and extend over the gate structure.

30. The method according to claim 29, further comprising the steps of: forming second contact plugs respectively connected to the channel patterns; and Global lines respectively connected to the second contact plugs are formed.

31. The method according to claim 29, further comprising the steps of: Gate insulating layers respectively surrounding the channel patterns are formed by oxidizing the channel patterns.

32. The method of claim 29, wherein: The step of forming the block word line comprises the following steps: The block word line is formed to surround a top surface and a sidewall of the channel pattern.

33. The method according to claim 29, further comprising the steps of: A capping layer is formed on the block word line surrounding a sidewall of the block word line.

34. The method of claim 29, wherein: The step of forming the second contact plug comprises the following steps: forming second openings respectively exposing the channel patterns; and The second contact plug is formed in the second opening.

35. The method according to claim 34, further comprising the steps of: When forming the second opening, forming a third opening to expose the block word line; as well as When forming the second contact plug, a third contact plug is formed in the third opening.

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