A method for fabricating a self-selecting memory integrated with CMOS

Abstract

The application discloses a preparation method of a self-selecting memory integrated with CMOS, and belongs to the technical field of semiconductor and CMOS hybrid integrated circuits. The application forms the electrical connection of a selector and a novel memory unit in a CMOS post-process, and constitutes a self-selecting memory structure. Compared with a traditional 1T1R structure, the application significantly improves the array density and reduces the process cost under the condition of meeting the same driving capacity.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor and CMOS hybrid integrated circuit technology, specifically relating to a back-end integration scheme based on a novel emerging memory integrated with CMOS. Background Technology

[0002] With the rapid development of emerging technologies such as smart cities and autonomous driving, the demands for data storage are increasing. Modern memory needs to have faster read / write speeds, lower power consumption, and larger storage capacity. However, existing memory technologies face many challenges. First, the read / write speeds of traditional memory often struggle to keep up with the data processing speeds of processors. Second, especially for Dynamic Random Access Memory (DRAM), its power consumption is difficult to further reduce. Finally, as manufacturing process nodes continue to shrink, the manufacturing cost and complexity of memory also increase, making it difficult to achieve higher storage densities. Therefore, there is an urgent need to research and develop new memory technologies, such as Resistive Random Access Memory (RRAM), Phase-Change Memory (PCRAM), Magnetoresistive Memory (MRAM), and Ferroelectric Memory (FeRAM).

[0003] However, the crosstalk current problem in the integrated arrays of new memory technologies poses a risk of errors and increases power consumption, limiting array density and scale. To address the crosstalk current issue in these integrated arrays, a common solution is to use a series transistor (transisitor) to implement the gating function. However, the 6F three-terminal transistor in a 1T1R array... 2 The feature size reduces the integration potential of novel memories, and three-dimensional integration is difficult. Summary of the Invention

[0004] To overcome the shortcomings of existing technologies, this invention proposes a method for fabricating a self-selecting memory integrated with CMOS, which forms a selector and a novel memory cell in the CMOS back-end to constitute a self-selecting memory structure.

[0005] The technical solution adopted in this invention is as follows:

[0006] A method for fabricating a self-selective memory integrated with CMOS, comprising the following steps:

[0007] 1) Grow a dielectric layer two after the CMOS front-end metal layer;

[0008] 2) A photoresist with a first photolithographic pattern is formed after the second dielectric layer; and a bottom via structure is formed by dry etching;

[0009] 3) After depositing the through-hole material in the through-hole structure, CMP is performed to smooth it out, and the second dielectric layer is used as the CMP stop layer;

[0010] 4) After CMP, functional layer 1, functional layer 2, functional layer 3, and passivation layer are deposited sequentially.

[0011] 5) A photoresist with a second photolithographic pattern is formed after the passivation layer; and a gated unit structure is formed by dry etching;

[0012] 6) Clean the above structure and perform passivation treatment; deposit a passivation layer;

[0013] 7) A photoresist with a third photolithographic pattern is formed after the passivation layer; and the sidewalls of the passivation layer are formed by dry etching;

[0014] 8) Deposit a third medium layer after the above structure to encapsulate the gated unit structure and the passivation layer;

[0015] 9) After depositing the first dielectric layer after the third dielectric layer, CMP grinding is performed;

[0016] 10) After the above-mentioned smoothed substrate layer 1, a photoresist with a fourth photolithographic pattern is formed; and a first intermediate via is formed by dry etching; then the via is deposited and a metal layer is prepared to form the rear metal layer of the gate unit;

[0017] 11) Grow a dielectric layer two after the metal layer behind the gated unit;

[0018] 12) A photoresist with a first photolithographic pattern is formed after the second dielectric layer; and a second intermediate via structure is formed by dry etching;

[0019] 13) After depositing the through-hole material after the through-hole structure, CMP is performed to smooth it out, and the second dielectric layer is used as the CMP stop layer;

[0020] 14) Deposit the storage cell functional layers sequentially after the CMP structure;

[0021] 15) A photoresist with a second photolithographic pattern is formed after the passivation layer; and a memory cell is formed by dry etching;

[0022] 16) Clean the above-mentioned memory cell structure and perform passivation treatment; deposit a passivation layer;

[0023] 17) A photoresist with a third photolithographic pattern is formed after the passivation layer; and the sidewalls of the passivation layer are formed by dry etching;

[0024] 18) Deposit a third dielectric layer after the above structure to encapsulate the device and the passivation layer;

[0025] 19) After depositing the first dielectric layer after the third dielectric layer, CMP grinding is performed;

[0026] 20) After smoothing the above dielectric layer, a photoresist with a fourth photolithographic pattern is formed; a top via is formed by dry etching; then the top via is deposited and a metal layer is prepared to finally complete the self-selection storage device.

[0027] A method for fabricating a self-selective memory integrated with CMOS, comprising the following steps:

[0028] 1) Grow a dielectric layer two after the CMOS front-end metal layer;

[0029] 2) A photoresist with a first photolithographic pattern is formed after the second dielectric layer; and a bottom via structure is formed by dry etching;

[0030] 3) After depositing the through-hole material in the through-hole structure, CMP is performed to smooth it out, and the second dielectric layer is used as the CMP stop layer;

[0031] 4) Deposit the storage unit functional layers sequentially after the CMP structure;

[0032] 5) A photoresist with a second photolithographic pattern is formed after the passivation layer; and a memory cell structure is formed by dry etching;

[0033] 6) Clean the above-mentioned storage cell structure and perform passivation treatment; deposit a passivation layer;

[0034] 7) A photoresist with a third photolithographic pattern is formed after the passivation layer; and the sidewalls of the passivation layer are formed by dry etching;

[0035] 8) Deposit a third medium layer after the above structure to encapsulate the storage cell structure and the passivation layer;

[0036] 9) After depositing the first dielectric layer after the third dielectric layer, CMP grinding is performed;

[0037] 10) After the above-mentioned smoothed substrate layer, a photoresist with a fourth photolithographic pattern is formed; and a first intermediate via is formed by dry etching; then the via is deposited and a metal layer is prepared to form the rear metal layer of the memory cell;

[0038] 11) A dielectric layer 2 is grown after the rear metal layer of the memory cell;

[0039] 12) A photoresist with a first photolithographic pattern is formed after the second dielectric layer; and a second intermediate via structure is formed by dry etching;

[0040] 13) After depositing the through-hole material after the through-hole structure, CMP is performed to smooth it out, and the second dielectric layer is used as the CMP stop layer;

[0041] 14) After CMP, functional layer 1, functional layer 2, functional layer 3, and passivation layer are deposited sequentially.

[0042] 15) A photoresist with a second photolithographic pattern is formed after the passivation layer; and a gate unit is formed by dry etching;

[0043] 16) Clean the above structure and perform passivation treatment; deposit a passivation layer;

[0044] 17) A photoresist with a third photolithographic pattern is formed after the passivation layer; and the sidewalls of the passivation layer are formed by dry etching;

[0045] 18) Deposit a third medium layer after the above structure to encapsulate the gated unit and the passivation layer;

[0046] 19) After depositing the first dielectric layer after the third dielectric layer, CMP grinding is performed;

[0047] 20) After CMP smoothing, a photoresist with a fourth photolithography pattern is formed; and a top via is formed by dry etching; then the top via is deposited and a metal layer is prepared to finally complete the self-selection storage device.

[0048] Using this invention, the gating unit integrated in the back-end of CMOS is electrically connected to the memory unit to perform the function of storing information. The memory unit of this invention can be resistive random access memory (RRAM), phase-change memory (PCRAM), magnetoresistive memory (MRAM), or ferroelectric memory (FeRAM). The memory unit (resistive / phase-change / magnetoresistive / ferroelectric material) prepared using this invention and the gating unit form a 1S1R unit self-selection memory.

[0049] The self-select memory prepared by this invention is integrated in the back-end of CMOS, and the front-end metal layer of CMOS can be Metal 1 layer or other metal layers.

[0050] In the above steps, dielectric layers one, two, and three are preferably silicon dioxide (SiO2) or low-dielectric-constant materials (Low-K dielectrics), such as porous SiO2, porous SiCOH, USG, BPSG, and SiCN, or one or more combinations thereof. The preferred fabrication process is chemical vapor deposition (CVD), such as APCVD, PECVD, or LPCVD, or thermal oxidation. The thickness of the dielectric layers is 200 nm to 1000 nm, which can be set according to the actual usage conditions of the device. Each dielectric layer can be a single-layer or multi-layer structure.

[0051] The preferred material for the through-holes in the above steps is at least one of vanadium (V), niobium (Nb), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), aluminum (Al), titanium aluminum tungsten (TiAlW), ruthenium (Ru), ruthenium oxide (RuO), iridium (Ir), iridium oxide (IrO2), indium tin oxide (ITO), titanium aluminum nitride (TiAlN), aluminum nitride (AlNx), titanium aluminum nitride (TiAlN) or (AlTiN), hafnium (Hf), yttrium (Y), manganese (Mn), zinc (Zn), palladium (Pd), and copper (Cu). The preferred preparation process is physical vapor deposition (PVD), magnetron sputtering, ion beam sputtering, electroplating, electron beam evaporation, thermal evaporation, atomic layer deposition (ALD), or chemical vapor deposition (CVD), with a thickness of 10-100 nm.

[0052] In the above steps, the material of the functional layer is preferably at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, or germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride; and one or more alloys thereof, including multilayer structures or mixtures of multilayer materials. The preferred preparation process is physical vapor deposition (PVD), magnetron sputtering, ion beam sputtering, electron beam evaporation, thermal evaporation, atomic layer deposition (ALD), or chemical vapor deposition (CVD), with a thickness of 5-100 nm. Alternatively, the material may be doped, with the doping element preferably being one or more of Al, Cu, Au, and Ti. The preferred doping processes are ion implantation (IMP) and co-sputtering.

[0053] The material for the second functional layer is preferably at least one of ZnOx, NiOx, TiOx, CrOx, MoOx, WOx, BiOx, SbOx, BaTiOx, InOx, VOx, SrTiOx, AlTiOx, MnOx, or GaNx; or at least one of titanium, tantalum, niobium, titanium nitride, tantalum nitride, titanium aluminum nitride, amorphous carbon, silicon carbide, graphene, carbon nanotubes, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide, and one or more alloys thereof, including multilayer structures or mixtures of multilayer materials. The preferred preparation process is physical vapor deposition (PVD), magnetron sputtering, ion beam sputtering, electron beam evaporation, thermal evaporation, atomic layer deposition (ALD), or chemical vapor deposition (CVD), with a thickness of 1-100 nm.

[0054] The preferred material for the functional layer three is at least one of the following: tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony tellurium, scandium antimony tellurium, indium silver antimony tellurium, germanium antimony, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide. Alternatively, at least one of NdOx, SrOx, GeOx, LaOx, HfOx, GaOx, AlOx, ZrOx, SiOx, YbOx, and MgO. Alternatively, aluminum borate (AlBO), strontium titanate (SrTiOx), zirconium titanate (ZrTiOx), barium titanate (BaTiOx), hafnium zirconium oxide (HfZrO), and hafnium aluminum oxide (HfAlO), etc. The preferred preparation process is physical vapor deposition (PVD), magnetron sputtering, ion beam sputtering, electron beam evaporation, thermal evaporation, atomic layer deposition (ALD), or chemical vapor deposition (CVD), with a thickness of 10-100 nm.

[0055] The functional layer material of the memory cell is preferably at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony tellurium, scandium antimony tellurium, indium silver antimony tellurium, germanium antimony, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide. Or at least one of NdOx, SrOx, GeOx, LaOx, HfOx, GaOx, AlOx, ZrOx, SiOx, YbOx, and MgO. Or aluminum borate (AlBO), strontium titanate (SrTiOx), zirconium titanate (ZrTiOx), barium titanate (BaTiOx), hafnium zirconium oxide (HfZrO), hafnium aluminum oxide (HfAlO), etc. The preferred preparation process is physical vapor deposition (PVD), magnetron sputtering, ion beam sputtering, electron beam evaporation, thermal evaporation, atomic layer deposition (ALD), or chemical vapor deposition (CVD), with a thickness of 10-100 nm.

[0056] Each of the above functional layers can be a single-layer structure or a multi-layer structure.

[0057] In the above steps, the passivation layer is preferably one or more of TEOS, Si3N4, NDC, SiC, AlOx, TaOx, and their alloys, including multilayer structures or mixtures of multilayer materials. The preferred preparation process is physical vapor deposition (PVD), magnetron sputtering, ion beam sputtering, electron beam evaporation, thermal evaporation, atomic layer deposition (ALD), or chemical vapor deposition (CVD), with a thickness of 0.5-100 nm.

[0058] The above-mentioned imaging process includes photolithography and etching techniques, among which the preferred etching processes are dry etching processes such as RIE (Reactive Ion Etching) and ICP (Inductively Coupled Plasma).

[0059] The beneficial effects of this invention are:

[0060] Compared with the traditional 1T1R structure, this invention constructs a self-selection memory structure by forming a selector and a novel memory cell electrical connection in the CMOS back-end, which significantly improves the array density and reduces the process cost while maintaining the same driving capability. Attached Figure Description

[0061] Figure 1 A cross-sectional view of the self-selection memory structure prepared by the present invention, wherein (a) shows the selection unit forming an electrical connection behind the memory unit; and (b) shows the selection unit forming an electrical connection in front of the memory unit.

[0062] Figures 2-21 This is a diagram illustrating the specific process steps of an embodiment of the present invention.

[0063] Figure 22 The above figures are for illustration purposes. Detailed Implementation

[0064] The present invention will be further described below with reference to specific embodiments and accompanying drawings.

[0065] Figure 1 This is a cross-sectional view of the self-selection memory structure prepared according to the present invention, as shown below. Figure 1 As shown, the present invention includes two schemes: one in which the gating unit forms an electrical connection behind the storage unit; and the other in which the gating unit forms an electrical connection in front of the storage unit.

[0066] The following embodiments use a self-selection memory in which the gating unit prepared according to the present invention forms an electrical connection in front of the storage unit as an example.

[0067] S1: As Figure 2 As shown, based on CMOS technology, after the CMOS front-end metal layer W base, a 20nm NDC (doped silicon carbide) dielectric layer is deposited using APCVD technology.

[0068] S2: As Figure 3 As shown, a photoresist with a first photolithographic pattern is formed; a bottom via structure is formed using reactive ion etching (RIE);

[0069] S3: As Figure 4As shown, 30nm TiN was deposited as the through-hole material after the through-hole structure using PVD magnetron sputtering, and then CMP (Chemical Mechanical Polishing) was performed to remove the excess TiN. The dielectric layer II NDC was used as the CMP stop layer.

[0070] S4: As Figure 5 As shown, after CMP, functional layers 45nm NbOx, 10nm TiOx, 5nm AlOx and 5nm AlOx passivation layers are deposited sequentially using ALD process.

[0071] S5: As Figure 6 As shown, a photoresist with a second photolithographic pattern is formed after the passivation layer; and a gated unit structure is formed by reactive ion etching (RIE).

[0072] S6: As Figure 7 As shown, wet cleaning was used to ensure surface cleanliness, followed by 400℃ annealing and passivation to improve interface defects between functional layers and between the sidewalls of functional layers and the passivation layer; then, an ALD process was used to deposit a 5nm AlOx passivation layer.

[0073] S7: As Figure 8 As shown, a photoresist with a third photolithographic pattern is formed after the passivation layer; and the sidewalls of the passivation layer are formed by reactive ion etching (RIE).

[0074] S8: As Figure 9 As shown, an LPCVD-deposited medium layer of 20nm SiNx is used after the above structure to encapsulate the gated unit structure and the passivation layer.

[0075] S9: such as Figure 10 As shown, after the above-mentioned dielectric layer three, a 150nm USG dielectric layer is deposited using APCVD process, and then CMP is performed to smooth it.

[0076] S10: As Figure 11 As shown, a photoresist with a fourth photolithographic pattern is formed after the above-mentioned smoothed substrate layer; a stepped hole is formed by Damascus process; then a 30nm TiN first intermediate via is deposited by PVD, and a 50nm Cu metal layer is prepared by electroplating to form the rear metal layer of the gate unit, and excess Cu is removed by CMP.

[0077] S11: As Figure 12 As shown, after the Cu metal layer, a 20nm NDC (doped silicon carbide) dielectric layer is deposited using APCVD process.

[0078] S12: As Figure 13As shown, a photoresist with a first photolithographic pattern is formed; a second intermediate via structure is formed using reactive ion etching (RIE);

[0079] S13: As Figure 14 As shown, after the second intermediate through-hole structure, 30nm TiN material is deposited by PVD magnetron sputtering process, and then CMP (Chemical Mechanical Polishing) is performed to remove excess TiN. The dielectric layer II NDC is used as the CMP stop layer.

[0080] S14: As Figure 15 As shown, after CMP, a 60nm TaOx storage functional layer is deposited using the ALD process;

[0081] S15: As Figure 16 As shown, a photoresist with a second photolithographic pattern is formed after the passivation layer; and a memory cell structure is formed by reactive ion etching (RIE).

[0082] S16: As Figure 17 As shown, wet cleaning was used to ensure surface cleanliness, followed by 400℃ annealing and passivation to improve interface defects in the functional layer and the interface defects between the functional layer sidewall and the passivation layer; then, a 5nm AlOx passivation layer was deposited using the ALD process.

[0083] S17: As Figure 18 As shown, a photoresist with a third photolithographic pattern is formed after the passivation layer; and the sidewalls of the passivation layer are formed by reactive ion etching (RIE).

[0084] S18: As Figure 19 As shown, an LPCVD-deposited dielectric layer of 20nm SiNx is used after the above structure to encapsulate the memory cell structure and the passivation layer.

[0085] S19: As Figure 20 As shown, after the above-mentioned dielectric layer three, a 100nm USG dielectric layer is deposited using APCVD process, and then CMP is performed to smooth it.

[0086] S20: As Figure 21 As shown, a photoresist with a fourth photolithographic pattern is formed after the above-mentioned smoothed substrate layer; top vias and metal grooves are formed by reactive ion etching (RIE) using a damascus process; then, 30nm TiN is deposited for the top vias, and 50nm Cu metal lines are prepared by electroplating to complete the fabrication of the self-selected memory cell.

[0087] Similar to the self-selection memory with an electrical connection formed in front of the storage unit provided in the above specific embodiments, the self-selection memory with an electrical connection formed behind the storage unit is further described by the following steps:

[0088] S1: Based on CMOS technology, after the CMOS front-end metal layer W base, a 20nm NDC (doped silicon carbide) dielectric layer is deposited using APCVD process.

[0089] S2: Form a photoresist with the first photolithographic pattern; use reactive ion etching (RIE) to form a bottom via structure;

[0090] S3: After the through-hole structure, 30nm TiN material is deposited by PVD magnetron sputtering process, and then CMP (Chemical Mechanical Polishing) is performed to remove the excess TiN. The dielectric layer II NDC is used as the CMP stop layer.

[0091] S4: After CMP, a 60nm TaOx storage functional layer and a 5nm AlOx passivation layer are deposited sequentially using ALD process;

[0092] S5: A photoresist with a second photolithographic pattern is formed after the passivation layer; and a memory cell structure is formed by reactive ion etching (RIE);

[0093] S6: Wet cleaning is used to ensure surface cleanliness, followed by 400℃ annealing and passivation to improve interface defects in the functional layer and the interface defects between the functional layer sidewalls and the passivation layer; then, a 5nm AlOx passivation layer is deposited using the ALD process.

[0094] S7: A photoresist with a third photolithographic pattern is formed after the passivation layer; and the sidewalls of the passivation layer are formed by reactive ion etching (RIE);

[0095] S8: After the above structure, a 20nm SiNx dielectric layer is deposited by LPCVD to encapsulate the memory cell structure and passivation layer.

[0096] S9: After the above dielectric layer three, a 100nm USG dielectric layer is deposited using APCVD process, and then CMP is performed to smooth it.

[0097] S10: After the above-mentioned smoothed substrate layer 1, a photoresist with a fourth photolithographic pattern is formed; and a first intermediate via is formed by reactive ion etching (RIE); then a 30nm TiN via is deposited; and a 50nm Cu metal layer is prepared by electroplating to form the rear metal layer of the memory cell, and excess Cu is removed by CMP.

[0098] S11: After the Cu metal layer, a 20nm NDC (doped silicon carbide) dielectric layer is deposited using APCVD process.

[0099] S12: Form a photoresist with a first photolithographic pattern; form a second intermediate via structure using reactive ion etching (RIE);

[0100] S13: After the second intermediate through-hole structure, 30nm TiN through-hole material is deposited by PVD magnetron sputtering process, and then CMP (Chemical Mechanical Polishing) is performed to remove excess TiN. The dielectric layer II NDC is used as the CMP stop layer.

[0101] S14: After CMP, functional layer 1 (45nm NbOx), functional layer 2 (10nm TiOx), functional layer 3 (5nm AlOx) and passivation layer 5nm AlOx are deposited sequentially using ALD process.

[0102] S15: A photoresist with a second photolithographic pattern is formed after the passivation layer; and the device structure is formed by reactive ion etching (RIE);

[0103] S16: Wet cleaning is used to ensure surface cleanliness, followed by 400℃ annealing and passivation to improve interface defects between functional layers and between the sidewalls of functional layers and the passivation layer; then, a 5nm AlOx passivation layer is deposited using ALD process.

[0104] S17: A photoresist with a third photolithographic pattern is formed after the passivation layer; and the sidewalls of the passivation layer are formed by reactive ion etching (RIE);

[0105] S18: After the above structure, a 20nm SiNx dielectric layer is deposited by LPCVD to encapsulate the device and the passivation layer.

[0106] S19: After the above dielectric layer three, a 150nm USG dielectric layer is deposited using APCVD process, and then CMP is performed to smooth it.

[0107] S20: After the above-mentioned smoothed substrate layer 1, a photoresist with a fourth photolithographic pattern is formed; and a stepped hole is formed by the damascus process; then a 30nm TiN top via is deposited by PVD, and a 50nm Cu is prepared by electroplating, finally completing the self-selection memory device.

[0108] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Those skilled in the art can modify or make equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be determined by the claims.

Claims

1. A method for manufacturing self-selecting memory integrated with CMOS, comprising the steps of: 1) growing a second dielectric layer after the CMOS front metal layer; 2) forming a photoresist with a first lithographic pattern after the second dielectric layer; and forming a bottom via structure by dry etching; 3) depositing a via material after the via structure, and then performing CMP planarization, with the second dielectric layer as the CMP stop layer; 4) sequentially depositing a first functional layer, a second functional layer, a third functional layer, and a passivation layer after the structure after CMP; 5) forming a photoresist with a second lithographic pattern after the passivation layer; and forming a gating unit structure by dry etching; 6) cleaning the above structure, and performing passivation treatment; depositing a passivation layer; 7) forming a photoresist with a third lithographic pattern after the passivation layer; and forming a passivation layer sidewall by dry etching; 8) depositing a third dielectric layer after the above structure, so as to wrap the gating unit structure and the passivation layer; 9) depositing a first dielectric layer after the above third dielectric layer, and then performing CMP planarization; 10) forming a photoresist with a fourth lithographic pattern after the planarized first dielectric layer; and forming a first intermediate via by dry etching; then depositing a via, and preparing a metal layer to form a rear metal layer of the gating unit; 11) growing a second dielectric layer after the rear metal layer of the gating unit; 12) forming a photoresist with a first lithographic pattern after the second dielectric layer; and forming a second intermediate via structure by dry etching; 13) depositing a via material after the via structure, and then performing CMP planarization, with the second dielectric layer as the CMP stop layer; 14) sequentially depositing a storage unit functional layer after the structure after CMP; 15) forming a photoresist with a second lithographic pattern after the passivation layer; and forming a storage unit by dry etching; 16) cleaning the above storage unit structure, and performing passivation treatment; depositing a passivation layer; 17) forming a photoresist with a third lithographic pattern after the passivation layer; and forming a passivation layer sidewall by dry etching; 18) depositing a third dielectric layer after the above structure, so as to wrap the device and the passivation layer; 19) depositing a first dielectric layer after the above third dielectric layer, and then performing CMP planarization; 20) forming a photoresist with a fourth lithographic pattern after the planarized first dielectric layer; and forming a top via by dry etching; then depositing a top via, and preparing a metal layer, to finally complete the self-selecting memory device.

2. A method for manufacturing self-selecting memory integrated with CMOS, comprising the steps of: 1) growing a second dielectric layer after the CMOS front metal layer; 2) forming a photoresist with a first lithographic pattern after the second dielectric layer; and forming a bottom via structure by dry etching; 3) depositing a via material after the via structure, and then performing CMP planarization, with the second dielectric layer as the CMP stop layer; 4) sequentially depositing a storage unit functional layer after the structure after CMP; 5) forming a photoresist with a second lithographic pattern after the passivation layer; and forming a storage unit structure by dry etching; 6) cleaning the above storage unit structure, and performing passivation treatment; depositing a passivation layer; ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 7) after the passivation layer, form a photoresist with a third photoetching pattern, and form a passivation layer side wall by dry etching; 8) after the above structure, deposit a dielectric layer three to wrap the memory cell structure and the passivation layer; 9) after the above dielectric layer three, deposit a dielectric layer one, and then perform CMP polishing; 10) after the above polished dielectric layer one, form a photoresist with a fourth photoetching pattern, and form a first intermediate via hole by dry etching; then deposit a via hole, and prepare a metal layer to form a back metal layer of the memory cell; 11) after the back metal layer of the memory cell, grow a dielectric layer two; 12) after the dielectric layer two, form a photoresist with a first photoetching pattern, and form a second intermediate via hole structure by dry etching; 13) after the via hole structure, deposit a via hole material, and then perform CMP polishing, with the dielectric layer two as a CMP stop layer; 14) after the CMP, sequentially deposit a functional layer one, a functional layer two, a functional layer three, and a passivation layer; 15) after the passivation layer, form a photoresist with a second photoetching pattern, and form a selection unit by dry etching; 16) clean the above structure, and perform passivation treatment; deposit a passivation layer; 17) after the passivation layer, form a photoresist with a third photoetching pattern, and form a passivation layer side wall by dry etching; 18) after the above structure, deposit a dielectric layer three to wrap the selection unit and the passivation layer; 19) after the above dielectric layer three, deposit a dielectric layer one, and then perform CMP polishing; 20) after the CMP polishing, form a photoresist with a fourth photoetching pattern, and form a top via hole by dry etching; then deposit a top via hole, and prepare a metal layer to finally complete the self-selecting memory device.

3. The production method according to claim 1 or 2, characterized by, The memory cell is a resistive random access memory, a phase change memory, a magnetoresistive memory, or a ferroelectric memory, wherein the functional layer material of the memory cell is selected from at least one of a group consisting of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony tellurium, scandium antimony tellurium, indium silver antimony tellurium, germanium antimony, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, hafnium aluminum oxide; or at least one of a group consisting of NdOx, SrOx, GeOx, LaOx, HfOx, GaOx, AlOx, ZrOx, SiOx, YbOx, MgO; or aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, hafnium aluminum oxide, and the preparation process is physical vapor deposition (PVD) or magnetron sputtering, ion beam sputtering, electron beam evaporation or thermal evaporation, atomic layer deposition, or a chemical vapor deposition process, and the thickness is 10-100 nm.

4. The production method according to claim 1 or 2, wherein The functional layer one is selected from at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, antimony telluride and alloys thereof, and one or more of the preparation processes are physical vapor deposition (PVD) or magnetron sputtering, ion beam sputtering, electron beam evaporation or thermal evaporation, atomic layer deposition, or chemical vapor deposition, and the thickness is 5-100 nm; or the above-mentioned materials are doped, the doping elements are selected from one or more of Al, Cu, Au and Ti, and the doping process is ion implantation (IMP) and co-sputtering.

5. The production method according to claim 1 or 2, wherein The functional layer two is selected from at least one of ZnOx, NiOx, TiOx, CrOx, MoOx, WOx, BiOx, SbOx, BaTiOx, InOx, VOx, SrTiOx, AlTiOx, MnOx, GaNx, metal titanium, metal tantalum, metal niobium, titanium nitride, tantalum nitride, aluminum titanium nitride, amorphous carbon, silicon carbide, graphene, carbon nanotube, carbon telluride, carbon tellurium sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, zinc-doped indium oxide and alloys thereof, and one or more of the preparation processes are physical vapor deposition (PVD) or magnetron sputtering, ion beam sputtering, electron beam evaporation or thermal evaporation, atomic layer deposition, or chemical vapor deposition, and the thickness is 1-100 nm.

6. The production method according to claim 1 or 2, wherein The functional layer three is selected from at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony telluride, scandium antimony telluride, indium silver antimony telluride, germanium antimony, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, hafnium aluminum oxide; or at least one of NdOx, SrOx, GeOx, LaOx, HfOx, GaOx, AlOx, ZrOx, SiOx, YbOx, MgO; or aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, hafnium aluminum oxide; The preparation process is physical vapor deposition (PVD) or magnetron sputtering, ion beam sputtering, electron beam evaporation or thermal evaporation, atomic layer deposition, or chemical vapor deposition, and the thickness is 10-100 nm.

7. The production method according to claim 1 or 2, wherein The medium layer one, medium layer two or medium layer three adopts silicon oxide (SiO2), or one or more of porous SiO2, porous SiCOH, USG, BPSG and SiCN low dielectric constant materials and combinations thereof, and the preparation process is chemical vapor deposition (CVD) or thermal oxidation process, and the thickness of the above-mentioned medium layer is 200-1000 nm.

8. The production method according to claim 1 or 2, wherein The through-hole material is selected from at least one of vanadium, niobium, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, titanium tungsten, aluminum, titanium aluminum tungsten, ruthenium, ruthenium oxide, iridium, iridium oxide, indium tin oxide, aluminum titanium nitride, aluminum nitride, aluminum titanium nitride or hafnium, yttrium, manganese, zinc, palladium, copper; a preparation process thereof is physical vapor deposition (PVD) or magnetron sputtering, ion beam sputtering, electroplating, electron beam evaporation or thermal evaporation, atomic layer deposition, or a chemical vapor deposition process, and the thickness is 10-100 nm.

9. The production method according to claim 1 or 2, wherein The passivation layer is selected from one or more of TEOS, Si3N4, NDC, SiC, AlOx, TaOx and alloys thereof; a preparation process thereof is physical vapor deposition (PVD) or magnetron sputtering, ion beam sputtering, electron beam evaporation or thermal evaporation, atomic layer deposition, or a chemical vapor deposition process, and the thickness is 0.5-100 nm.

10. The production method according to claim 1 or 2, wherein The dry etching process is reactive ion etching (RIE) or inductively coupled plasma etching (ICP).

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