Semiconductor structure, manufacturing method thereof and memory system

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a storage system. The method for manufacturing the semiconductor structure comprises the steps that an initial semiconductor structure is obtained, the initial semiconductor structure comprises a semiconductor layer, the semiconductor layer comprises a plurality of semiconductor columns, the semiconductor columns extend in the second direction and are distributed in an array mode in the first direction and the third direction, the first direction and the third direction intersect, and the second direction is perpendicular to the first direction and the third direction; the gate structure is located on the side wall of the semiconductor column and extends in the third direction; removing part of the semiconductor layer from one side far away from the semiconductor column until the first end of the semiconductor column is exposed; and forming a bit line connected with the first end of the semiconductor column and extending along the first direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a method for manufacturing the semiconductor structure, and a storage system. Background Art

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices and cloud storage, the storage density requirements for semiconductor structures such as three-dimensional semiconductor memory devices are becoming higher and higher. However, as the storage density of semiconductor structures increases, the number of storage units increases, the size decreases, and the spatial density increases, which makes the coupling phenomenon between adjacent components more and more serious. Summary of the invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies proposed in the above background technology section or other deficiencies in the prior art.

[0004] The present application provides a method for manufacturing a semiconductor structure. The method comprises: obtaining an initial semiconductor structure, wherein the initial semiconductor structure comprises: a semiconductor layer, comprising a plurality of semiconductor pillars, wherein the semiconductor pillars extend along a second direction and are arrayed along a first direction and a third direction, wherein the first direction and the third direction intersect, and the second direction is perpendicular to the first direction and the third direction; and a gate structure, which is located on a sidewall of the semiconductor pillar and extends along the third direction; removing a portion of the semiconductor layer from a side away from the semiconductor pillar until a first end of the semiconductor pillar is exposed; and forming a bit line connected to the first end of the semiconductor pillar and extending along the first direction.

[0005] In one embodiment, forming a bit line connected to the first end of the semiconductor pillar and extending along the first direction includes: forming a conductive layer at the first end of the semiconductor pillar; and forming the bit line on the conductive layer.

[0006] In one embodiment, obtaining an initial semiconductor structure includes: forming a plurality of initial semiconductor pillars extending along the first direction and the second direction within the semiconductor layer; and forming a plurality of gate structures passing through the initial semiconductor pillars and extending along the third direction and arranged along the first direction, wherein the plurality of gate structures divide the initial semiconductor pillars into a plurality of semiconductor pillars extending along the second direction.

[0007] In one embodiment, a plurality of gate structures are formed that pass through the initial semiconductor column, extend along the third direction, and are arranged along the first direction, including: forming the gate structure and the isolation structure that pass through the initial semiconductor column, extend along the third direction, and are arranged along the first direction, wherein the gate structure and the isolation structure divide the initial semiconductor column into a plurality of semiconductor columns extending along the second direction.

[0008] In one embodiment, the gate structure and the isolation structure are formed through the initial semiconductor column, extending along the third direction, and arranged along the first direction, including: forming a first trench and a second trench that pass through the initial semiconductor column, extend along the third direction, and are alternately arranged along the first direction; and forming the gate structure and the isolation structure in the first trench and the second trench, respectively.

[0009] In one embodiment, a plurality of initial semiconductor columns extending along the first direction and the second direction are formed in the semiconductor layer, including: a plurality of isolation columns extending along the first direction and the second direction are formed in the semiconductor layer, wherein the plurality of isolation columns divide a portion of the semiconductor layer into the plurality of initial semiconductor columns, and the initial semiconductor columns and the isolation columns are alternately arranged along the third direction.

[0010] In one embodiment, the semiconductor column and the isolation column have the same height in the second direction, and removing a portion of the semiconductor layer from a side away from the semiconductor column to expose the semiconductor column includes: removing a portion of the semiconductor layer along the second direction from a side away from the semiconductor column to expose the isolation column.

[0011] In one embodiment, a first trench and a second trench are formed that pass through the initial semiconductor column and extend along the third direction and are alternately arranged along the first direction, including: forming an initial first trench and a second trench in the semiconductor layer that pass through the initial semiconductor column and extend along the third direction and are alternately arranged along the first direction; forming a first sacrificial layer and a second sacrificial layer in the initial first trench and the second trench, respectively; removing a portion of the second sacrificial layer along the second direction and forming a protective layer in the removed space; and removing the first sacrificial layer and increasing the width and depth of the initial first trench to form the first trench.

[0012] In one embodiment, the gate structure and the isolation structure are formed in the first trench and the second trench, respectively, including: forming a first dielectric layer in the first trench; removing a portion of the first dielectric layer along the second direction to form a first gap; forming a gate dielectric layer on the sidewall of the first gap; forming a gate layer on the surface of the gate dielectric layer; removing a portion of the gate layer along the second direction to form a second gap; forming a third gap along the second direction through the gate layer to expose the first dielectric layer; forming a second dielectric layer in the second gap and the third gap, wherein the gate structure includes the first dielectric layer, the second dielectric layer, the gate dielectric layer and the gate layer that has not been removed; removing the protective layer and the remaining second sacrificial layer to form a fourth gap; and forming the isolation structure in the fourth gap.

[0013] In one embodiment, the method further includes forming a capacitor connected to a second end of the semiconductor pillar opposite to the first end along the second direction.

[0014] In one embodiment, forming a conductive layer at the first end of the semiconductor column includes: forming a transition conductive layer at the first end of the semiconductor column, wherein the first end of the semiconductor column reacts with the transition conductive layer and changes into the conductive layer.

[0015] On the other hand, the present application provides a semiconductor structure. The semiconductor structure includes: a plurality of semiconductor pillars extending along a second direction and arranged in an array along a first direction and a third direction, wherein the first direction and the third direction intersect, and the second direction is perpendicular to the first direction and the third direction; a gate structure located at a first side wall of the semiconductor pillar and extending along the third direction, wherein the first ends of the semiconductor pillars adjacent to each other along the first direction are isolated by the gate structure; and a bit line directly contacting the first end of the semiconductor pillar and extending along the first direction.

[0016] In one embodiment, the gate structure includes: a dielectric layer, close to the first end of the semiconductor column; a gate dielectric layer, located on the dielectric layer and on the first sidewall of the semiconductor column; and a gate layer, located on the dielectric layer and on the surface of the gate dielectric layer.

[0017] In one embodiment, the first end of the semiconductor pillar includes a conductive layer, and the conductive layer is in direct contact with the bit line.

[0018] In one embodiment, an end surface of the gate structure close to the bit line is coplanar with an end surface of the conductive layer close to the bit line.

[0019] In one embodiment, the semiconductor structure further includes: an isolation structure located at a second sidewall of the semiconductor column opposite to the first sidewall and extending along the third direction, wherein adjacent semiconductor columns along the first direction are spaced apart by the gate structure or the isolation structure.

[0020] In one embodiment, the isolation structure includes: an isolation conductive layer; and an isolation dielectric layer surrounding the isolation conductive layer.

[0021] In one embodiment, the semiconductor structure further includes: a capacitor connected to a second end of the semiconductor pillar opposite to the first end along the second direction.

[0022] On the other hand, the present application provides a storage system, which includes at least one three-dimensional memory, each three-dimensional memory including the semiconductor structure as described above; and a controller coupled to the semiconductor structure for controlling the three-dimensional memory to store data.

[0023] In one or more embodiments of the present application, by removing a portion of the semiconductor layer from the side away from the semiconductor column to expose the first end of the semiconductor column, a plurality of semiconductor columns can be formed into an independent structure, that is, the plurality of semiconductor columns are separated from each other, which is beneficial to reduce the coupling phenomenon between adjacent semiconductor columns in subsequent process manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Other features, purposes and advantages of the present application will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0025] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0026] Figure 2 and Figure 3 They are partial structural schematic diagrams of a semiconductor layer provided according to an exemplary embodiment of the present application on a plane formed by a first direction and a third direction and on a plane formed by a third direction and a second direction;

[0027] Figure 4 and Figure 5 are schematic diagrams of structures for forming an initial semiconductor column and an isolation column according to an exemplary embodiment of the present application, wherein: Figure 5 for Figure 4 Schematic diagram of a partial cross section along the AA direction;

[0028] Figure 6 and Figure 7are schematic diagrams of structures for forming an initial first trench and a second trench according to an exemplary embodiment of the present application, wherein: Figure 7 for Figure 6 Schematic diagram of a partial cross section along the BB direction;

[0029] Figure 8 and Fig. 9 is a schematic diagram of a structure for forming a first sacrificial layer and a second sacrificial layer according to an exemplary embodiment of the present application, wherein: Fig. 9 for Figure 8 Schematic diagram of a partial cross section along the BB direction;

[0030] Fig.10 and Fig.11 is a schematic diagram of a structure for forming a protective layer according to an exemplary embodiment of the present application, wherein: Fig.11 for Fig.10 Schematic diagram of a partial cross section along the BB direction;

[0031] Fig.12 and Fig.13 is a schematic diagram of a structure for forming a first groove according to an exemplary embodiment of the present application, wherein: Fig.13 for Fig.12 Schematic diagram of a partial cross section along the BB direction;

[0032] Fig.14 and Fig.15 is a schematic diagram of a structure for forming a dielectric layer according to an exemplary embodiment of the present application, wherein: Fig.15 for Fig.14 Schematic diagram of a partial cross section along the BB direction;

[0033] Fig.16 and Fig.17 is a schematic diagram of a structure for forming a gate dielectric layer and a gate layer according to an exemplary embodiment of the present application, wherein: Fig.17 for Fig.16 Schematic diagram of a partial cross section along the BB direction;

[0034] Fig.18 and Fig.19A is a schematic diagram of a structure for forming a second dielectric layer and a through hole according to an exemplary embodiment of the present application, wherein: Fig.19A for Fig.18 Schematic diagram of a partial cross section along the BB direction;

[0035] Fig.19B is a partial structural schematic diagram of a gate structure provided according to an exemplary embodiment of the present application;

[0036] Fig. 20 and Fig.21is a schematic diagram of a structure for forming an isolation structure according to an exemplary embodiment of the present application, wherein: Fig.21 for Fig. 20 Schematic diagram of a partial cross section along the BB direction;

[0037] Fig. 22 For the general Fig.21 Schematic diagram of the structure after the structure is flipped 180° and thinned;

[0038] Fig.23 is a schematic diagram of a structure for forming a conductive layer and a bit line according to an exemplary embodiment of the present application;

[0039] Fig.24 is a schematic diagram of a structure for forming a capacitor according to an exemplary embodiment of the present application;

[0040] Fig.25 is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of the present application; and

[0041] Fig.26A and Fig.26B is a schematic diagram of a storage system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and do not limit the scope of the present application in any way.

[0043] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first groove discussed in this application may also be referred to as the second groove, the first direction may also be referred to as the second direction, the third direction, and vice versa.

[0044] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0045] In addition, in this document, when describing that one part is located "on" another part, for example, the meaning of "on", "above" and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" does not absolutely mean being above based on the direction of gravity, nor does it only mean the meaning of "on something" or "above something", but also includes the meaning of "on something" or "over something" with no intervening features or layers in between (i.e., directly on something).

[0046] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0047] This document is described with reference to schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and sizes shown, but include various equivalent structures that can achieve the same functions and shape and size deviations caused by, for example, manufacturing. The positions shown in the drawings are schematic in nature and are not intended to limit the positions of the components.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0049] As used in this article, the term "layer" refers to a material portion including an area with a height. A layer can be an area of ​​a uniform or non-uniform continuous structure, whose height is less than the height of the continuous structure. For example, a layer can be located between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above it and / or below it. A layer can include multiple layers.

[0050] In addition, in the present application, when “connected” or “coupled” is used, it may indicate that the corresponding components are in direct contact or indirect contact, unless otherwise clearly defined or can be inferred from the context.

[0051] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0052] Figure 1 is a flow chart of a method 1000 of fabricating a semiconductor structure according to an exemplary embodiment of the present application.

[0053] like Figure 1 As shown, the method 1000 for manufacturing a semiconductor structure may include: S1100, obtaining an initial semiconductor structure, wherein the initial semiconductor structure includes: a semiconductor layer, including a plurality of semiconductor pillars, the semiconductor pillars extending along a second direction Z and arranged in an array along a first direction X and a third direction Y, wherein the first direction X and the third direction Y intersect, and the second direction Z is perpendicular to the first direction X and the third direction Y; and a gate structure, located on a sidewall of the semiconductor pillar and extending along the third direction Y; S1200, removing a portion of the semiconductor layer from a side away from the semiconductor pillar to expose a first end of the semiconductor pillar; and S1300, forming a bit line connected to the first end of the semiconductor pillar and extending along the first direction X. Steps S1100 to S1300 will be described in detail below.

[0054] In the exemplary embodiment of the present application, Fig. 20 and Fig.21 As shown, an initial semiconductor structure 1100 may be obtained. The initial semiconductor structure 1100 may include: a semiconductor layer 1110 (including a plurality of semiconductor pillars 1140 ) and a gate structure 1130 .

[0055] The material of the semiconductor layer 1110 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0056] The semiconductor layer 1110 may include a plurality of semiconductor pillars 1140. The plurality of semiconductor pillars 1140 may extend along the second direction Z and may be distributed in an array along the first direction X and the third direction Y, wherein the first direction X and the third direction Y intersect, and the second direction Z may be perpendicular to the first direction X and the third direction Y. Exemplarily, the plurality of semiconductor pillars 1140 may be formed by removing a portion of the semiconductor layer 1110. In other words, the portion of the semiconductor layer 1110 that is not removed may include the plurality of semiconductor pillars 1140. Therefore, the semiconductor pillars 1140 may have the same material as the portion of the semiconductor layer 1110 that is not removed, such as single crystal silicon, etc.

[0057] Exemplarily, a plurality of semiconductor pillars 1140 are spaced apart from each other to expose one or more sidewalls of the semiconductor pillars 1140. For example, the semiconductor pillars 1140 may have a cubic shape to expose four sidewalls thereof. It should be understood that the semiconductor pillars 1140 may have any suitable three-dimensional shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor pillars 1140 in a plan view (e.g., in an XY plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape), or any other suitable shape.

[0058] The gate structure 1130 may be located on the sidewall of the semiconductor pillar 1140 and may extend along the third direction Y. The gate structure 1130 may include a dielectric layer (including a first dielectric layer 1132), a gate dielectric layer 1133, and a gate layer 1134. The gate dielectric layer 1133 may be located on the dielectric layer and may be located on the first sidewall of the semiconductor pillar 1140. The gate layer 1134 may be located on the dielectric layer and may be located on the surface of the gate dielectric layer 1133. Exemplarily, the gate structure 1130 may also include a second dielectric layer 1135, wherein the second dielectric layer 1135 may be located on the first dielectric layer 1132 and may be located on the surface of the gate layer 1134. Exemplarily, the dielectric layer may also include a third dielectric layer 1131 surrounding a portion of the first dielectric layer 1132. That is, the dielectric layer may include the first dielectric layer 1132 and the third dielectric layer 1131.

[0059] For example, two adjacent gate structures 1130 may be mirror-symmetrical along the second direction Z. The first dielectric layer 1132, the second dielectric layer 1135, and the third dielectric layer 1131 in the two partially mirror-symmetrical gate structures 1130 are continuous. In other words, the first dielectric layer 1132 in the two partially mirror-symmetrical gate structures 1130 may be connected to form an integral structure, the second dielectric layer 1135 in the two gate structures 1130 may be connected to form an integral structure, and the third dielectric layer 1131 in the two gate structures 1130 may be connected to form an integral structure. Fig.19B As shown, a partial structural diagram of a gate structure 1130 is shown.

[0060] By way of example, the semiconductor pillar 1140 and the gate structure 1130 may be used together to form a vertical transistor, wherein the semiconductor pillar 1140 may be used to form an active region of multiple channels in the vertical transistor. By way of example, the gate structure 1130 may be located on at least one sidewall of the semiconductor pillar 1140, i.e., the semiconductor pillar 1140 may be at least partially surrounded by the gate structure 1130. For example, the semiconductor pillar 1140, the gate dielectric layer 1133, and the gate layer 1134 may be radially arranged in this order from the center of the vertical transistor. By way of example, the gate dielectric layer 1133 may surround and contact the semiconductor pillar 1140. The gate layer 1134 may surround and contact the gate dielectric layer 1133.

[0061] It should be understood that Fig. 20 and Fig.21 The situation in which the gate structure 1130 is located on one sidewall of the semiconductor pillar 1140 is only an example and is not specifically limited.

[0062] In one embodiment of the present application, the gate structure 1130 may be located on multiple sidewalls of the semiconductor column 1140, in which case the semiconductor column 1140 and the gate structure 1130 may be used together to form a multi-gate transistor (e.g., a gate-all-around (GAA) transistor, a tri-gate transistor, or a dual-gate transistor). The multi-gate transistor may have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the cut-off state, the leakage current of the multi-gate transistor may also be significantly reduced due to the complete depletion of the channel. Therefore, better speed (saturated drain current) / leakage current performance may be achieved using a multi-gate transistor.

[0063] In another embodiment of the present application, the gate structure 1130 may be located on a side wall of the semiconductor column 1140, in which case the semiconductor column 1140 and the gate structure 1130 may be used together to form a single-gate transistor. For example, the single-gate transistors adjacent to each other along the first direction may be arranged in a mirror-symmetrical manner. By providing a single-gate transistor, the present application can significantly increase the density of the semiconductor column 1140 in the first direction and reduce the difficulty of the manufacturing process. In addition, the mirror-symmetrical single-gate transistor may have a larger process window, which is beneficial to reduce the spacing between the bit lines, word lines, and transistors formed subsequently.

[0064] like Figures 2 to 21As shown, the present application provides a process step diagram for forming an initial semiconductor structure 1100. It should be understood that although the present application provides a process for forming an initial semiconductor structure 1100, the process is not a necessary step for implementing the present application, and the present application can manufacture a semiconductor structure based on the existing initial semiconductor structure 1100. In addition, the process for forming the initial semiconductor structure 1100 provided in the present application is only used as an example and is not specifically limited. In the actual process, the process for forming the initial semiconductor structure 1100 can be reasonably set according to actual needs.

[0065] In the exemplary embodiment of the present application, Figures 2 to 21 As shown, obtaining the initial semiconductor structure 1100 may include: forming a plurality of initial semiconductor pillars 1120 extending along a first direction X and a second direction Z in the semiconductor layer 1110 ( Figure 4 and Figure 5 ); and forming a plurality of gate structures 1130 ( Fig. 20 and Fig.21 ), wherein the plurality of gate structures 1130 can divide the initial semiconductor column 1120 into a plurality of semiconductor columns 1140 extending along the second direction Z.

[0066] For example, Figure 2 and Figure 3 1 and 2 are partial structural schematic diagrams of the semiconductor layer 1110 provided according to an exemplary embodiment of the present application on a plane formed by the first direction X and the third direction Y and on a plane formed by the third direction Y and the second direction Z. Figure 3 As shown, a first dielectric layer 1111 and a second dielectric layer 1112 stacked in sequence may be formed on the surface of the semiconductor layer 1110. For example, the first dielectric layer 1111 and the second dielectric layer 1112 may be etched to form a patterned mask.

[0067] The material of the first dielectric layer 1111 may include an oxide such as silicon oxide. The material of the second dielectric layer 1112 may include a nitride such as silicon nitride. In an exemplary embodiment, the first dielectric layer 1111 and the second dielectric layer 1112 may be deposited by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In another exemplary embodiment, the first dielectric layer 1111 may be formed by oxidizing the surface of the semiconductor layer 1110 by, for example, an oxidation process.

[0068] Figure 4 and Figure 5 are schematic diagrams of structures for forming an initial semiconductor column 1120 and an isolation column 1160 according to an exemplary embodiment of the present application, wherein: Figure 5 for Figure 4 A partial cross-sectional view along the AA direction. For example, Figure 4 and Figure 5 As shown, a plurality of initial semiconductor pillars 1120 extending along a first direction X and a second direction Z may be formed in the semiconductor layer 1110 .

[0069] For example, a plurality of isolation columns 1160 extending along the first direction X and the second direction Z may be formed in the semiconductor layer 1110, wherein the plurality of isolation columns 1160 may divide a portion of the semiconductor layer 1110 into a plurality of initial semiconductor columns 1120. The initial semiconductor columns 1120 and the isolation columns 1160 may be alternately arranged along the third direction Y. For example, a plurality of grooves (not shown) extending along the first direction X and the second direction Z may be formed in the semiconductor layer 1110; and the isolation columns 1160 may be formed in the grooves, wherein the semiconductor layer 1110 that is not removed forms the initial semiconductor columns 1120.

[0070] Exemplarily, the second dielectric layer 1112, the first dielectric layer 1111, and the semiconductor layer 1110 may be etched by an etching process to form a groove and an initial semiconductor pillar 1120. For example, the second dielectric layer 1112 and the first dielectric layer 1111 may be etched by a photolithography process to form a patterned mask, wherein the second dielectric layer 1112 may be used as a bottom anti-reflection layer for photolithography, and the first dielectric layer 1111 may be used as a hard mask; then, the semiconductor layer 1110 is etched by one or more dry etching and / or wet etching processes using the patterned mask as a mask to form a groove in the semiconductor layer 1110, wherein the semiconductor layer 1110 that is not removed may form the initial semiconductor pillar 1120.

[0071] By way of example, the material of the isolation column 1160 may include, but is not limited to, an insulating material such as oxide. By way of example, the isolation column 1160 may be formed by depositing an insulating material in the groove by, for example, a thin film deposition process, so that adjacent initial semiconductor columns 1120 are isolated by the isolation column 1160. In addition, a planarization process such as a mechanical grinding process may be performed to remove the insulating material on the surface of the second dielectric layer 1112.

[0072] In the exemplary embodiment of the present application, Fig. 20 and Fig.21As shown, forming a plurality of gate structures 1130 that pass through the initial semiconductor column 1120 and extend along the third direction Y and are arranged along the first direction X may include: forming a gate structure 1130 and an isolation structure 1150 that pass through the initial semiconductor column 1120 and extend along the third direction Y and are arranged along the first direction X, wherein the gate structure 1130 and the isolation structure 1150 may divide the initial semiconductor column 1120 into a plurality of semiconductor columns 1140 that extend along the second direction Z. In other words, the isolation structure 1150 may also be formed during the process of forming the gate structure 1130, and the gate structure 1130 and the isolation structure 1150 may divide the initial semiconductor column 1120 into a plurality of semiconductor columns 1140 together.

[0073] Exemplarily, forming the gate structure 1130 and the isolation structure 1150 that pass through the initial semiconductor pillar 1120 and extend along the third direction Y and are arranged along the first direction X may include: forming first trenches 100 ( Fig.12 and Fig.13 ) and the second groove 200 ( Figure 6 and Figure 7 ); and forming a gate structure 1130 in the first trench 100 and the second trench 200 respectively ( Fig.18 and Fig.19A ) and isolation structure 1150 ( Fig. 20 and Fig.21 ).

[0074] Figure 6 and Fig.21 It is a process step diagram for forming a gate structure 1130 and an isolation structure 1150 provided in the present application.

[0075] Figure 6 and Figure 7 are schematic diagrams of structures for forming an initial first trench 110 and a second trench 220 according to an exemplary embodiment of the present application, wherein: Figure 7 for Figure 6 A partial cross-sectional schematic diagram along the BB direction. For example, Figure 6 and Figure 7 As shown, initial first trenches 110 and second trenches 200 that pass through the initial semiconductor pillars 1120 and extend along the third direction Y and are alternately arranged along the first direction X may be formed.

[0076] For example, one or more dry etching and / or wet etching processes may be used to etch and form the initial first trench 110 and the second trench 200. The initial first trench 110 and the second trench 200 may divide the initial semiconductor column 1120 into a plurality of semiconductor columns 1140. The present application forms the semiconductor column 1140 by etching the semiconductor layer 1110, so the semiconductor column 1140 may have the same material as the semiconductor layer 1110 and may extend along the second direction Z in the semiconductor layer 1110.

[0077] Figure 8 and Fig. 9 is a schematic diagram of a structure for forming a first sacrificial layer 310 and a second sacrificial layer 320 according to an exemplary embodiment of the present application, wherein: Fig. 9 for Figure 8 A partial cross-sectional schematic diagram along the BB direction. For example, Figure 8 and Fig. 9 As shown, a first sacrificial layer 310 and a second sacrificial layer 320 may be formed in the initial first trench 110 and the second trench 200, respectively. For example, the first sacrificial layer 310 and the second sacrificial layer 320 may be formed by depositing dielectric materials such as silicon oxide, carbon materials, etc., by one or more thin film deposition processes.

[0078] Fig.10 and Fig.11 is a schematic diagram of a structure for forming a protective layer 330 according to an exemplary embodiment of the present application, wherein: Fig.11 for Fig.10 A partial cross-sectional schematic diagram along the BB direction. For example, Fig.10 and Fig.11 As shown, part of the second sacrificial layer 320 may be removed along the second direction Z, and a protective layer 330 may be formed in the removed space. For example, a photolithography process, one or more dry etching and / or wet etching processes may be used to remove part of the second sacrificial layer 320; then one or more thin film deposition processes may be used to form the protective layer 330 in the removed space to cover and protect the remaining second sacrificial layer 320. The material of the protective layer 330 may include, but is not limited to, dielectric materials such as silicon nitride.

[0079] Fig.12 and Fig.13 is a schematic diagram of a structure for forming a first trench 100 according to an exemplary embodiment of the present application, wherein: Fig.13 for Fig.12 A partial cross-sectional schematic diagram along the BB direction. For example, Fig.12 and Fig.13As shown, the first sacrificial layer 310 may be removed, and the width and depth of the initial first trench 110 may be increased to form the first trench 100. For example, the first sacrificial layer 310 may be removed by using a photolithography process, one or more dry etching and / or wet etching processes, etc. Exemplarily, during the process of removing the first sacrificial layer 310, the initial first trench 110 may be enlarged and deepened to form the first trench 100 having a width and a depth greater than the initial first trench 110.

[0080] For example, Figures 14 to 21 As shown, a gate structure 1130 may be formed in the first trench 100, and an isolation structure 1150 may be formed in the second trench 200. For example, two mirror-symmetrical gate structures 1130 may be formed in the first trench 100, wherein Fig.19B A partial structural schematic diagram of a gate structure 1130 is shown.

[0081] Fig.14 and Fig.15 1 is a schematic diagram of a structure for forming a dielectric layer (such as a third dielectric layer 1131 and a first dielectric layer 1132) according to an exemplary embodiment of the present application, wherein: Fig.15 for Fig.14 A partial cross-sectional schematic diagram along the BB direction. For example, Fig.14 and Fig.15 As shown, a first dielectric layer 1132 may be formed in the first trench 100; a portion of the first dielectric layer 1132 may be removed along the second direction Z to form a first gap 400. For example, one or more thin film deposition processes may be used, including but not limited to CVD, PVD, ALD, or any combination thereof to deposit and form the first dielectric layer 1132. The material of the first dielectric layer 1132 includes but is not limited to silicon oxide. Exemplarily, before forming the first dielectric layer 1132, a third dielectric layer 1131 may be deposited on the sidewall of the first trench 100 to partially fill the first trench 100. Exemplarily, a portion of the first dielectric layer 1132 may be removed along the second direction Z so that the remaining first dielectric layer 1132 covers the bottom surface of the first trench 100.

[0082] Fig.16 and Fig.17 1 is a schematic diagram of a structure for forming a gate dielectric layer 1133 and a gate layer 1134 according to an exemplary embodiment of the present application, wherein: Fig.17 for Fig.16 A partial cross-sectional schematic diagram along the BB direction. For example, Fig.16 and Fig.17 As shown, a gate dielectric layer 1133 may be formed on the sidewall of the first gap 400 ; and a gate layer 1134 may be formed inside the gate dielectric layer 1133 .

[0083] Exemplarily, the gate dielectric layer 1133 may be a portion of a continuous third dielectric layer 1131 formed on the sidewalls of the semiconductor pillars 1140 extending along the second direction Z. The gate dielectric layer 1133 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 1133 may include silicon oxide, i.e., a gate oxide. Exemplarily, a wet oxidation and / or dry oxidation process, such as an in-situ steam oxidation process, may be performed to form the gate dielectric layer 1133 on the sidewalls of the first trench 100.

[0084] Then, a gate layer 1134 may be formed inside the gate dielectric layer 1133 in the first trench 100. Exemplarily, the gate layer 1134 may be formed by depositing one or more conductive materials such as metals and / or metal compounds such as metal tungsten W and titanium nitride TiN inside the gate dielectric layer 1133 through one or more thin film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof to form the gate layer 1134. For example, TiN and W may be deposited sequentially to form the gate layer 1134. Exemplarily, a planarization process such as a chemical mechanical polishing process may be performed to remove excess conductive material on the surface of the second dielectric layer 1112.

[0085] Fig.18 and Fig.19A is a schematic diagram of a structure for forming a second dielectric layer 1135 and a through hole 500 according to an exemplary embodiment of the present application, wherein: Fig.19A for Fig.18 A partial cross-sectional schematic diagram along the BB direction. For example, Fig.19A As shown, a portion of the gate layer 1134 may be removed along the second direction Z to form a second gap (not shown); a third gap (not shown) may be formed along the second direction Z through the gate layer 1134 to expose the first dielectric layer 1132; and a second dielectric layer 1135 may be formed in the second gap and the third gap. Exemplarily, the third dielectric layer 1131, the first dielectric layer 1132, the second dielectric layer 1135, the gate dielectric layer 1133, and the gate layer 1134 that has not been removed may be used to form the gate structure 1130. Specifically, Fig.19B A partial structural schematic diagram of a gate structure 1130 is shown, in which the third dielectric layer 1131, the first dielectric layer 1132, the second dielectric layer 1135, the gate dielectric layer 1133 and the gate layer 1134 that has not been removed in the first trench 100 can be used to form at least two mirror-symmetrical gate structures 1130.

[0086] Exemplarily, an etch-back process may be used to remove part of the gate layer 1134 along the second direction Z, so that the upper end of the gate layer 1134 is below the top surface of the semiconductor pillar 1140. In addition, since the gate dielectric layer 1133 is not etched back, the upper end of the gate layer 1134 is below the upper end of the gate dielectric layer 1133. In this way, the etched-back gate layer 1134 may extend along the third direction Y, and its portion corresponding to the semiconductor pillar 1140 may be used as a gate electrode; and its remaining portion may be used as a word line for connecting the gate electrode to a peripheral circuit, so as to transmit electrical signals between the gate electrode and the peripheral circuit.

[0087] For example, the third gap may be formed by an etching process such as punch-down etching, dry etching and / or wet etching to form two disconnected gate structures 1130 in the first trench 100. For example, a bottom punch-down etching process may be used to disconnect the gate structure 1130 at the bottom of the first trench 100 until the first dielectric layer 1132 is exposed.

[0088] For example, one or more thin film deposition processes may be used to deposit and form the second dielectric layer 1135 in the second gap and the third gap. In other words, the second dielectric layer 1135 may be deposited and formed in the remaining space of the first trench 100. The material of the second dielectric layer 1135 includes, but is not limited to, silicon oxide. In addition, a planarization process such as a mechanical grinding process may be performed to remove the second dielectric layer 1135, the second dielectric layer 1112, and the first dielectric layer 1111.

[0089] For example, Fig.18 As shown, a through hole 500 penetrating the gate dielectric layer 1133 and the gate layer 1134 along the second direction Z may be formed to separate the annular gate structure 1130 in the first trench 100 into at least two parts. For example, two through holes 500 with a certain interval may be formed in each annular gate structure 1130 to separate the annular gate structure 1130 into two parts. In other words, the two through holes 500 separate the annular gate dielectric layer 1133 into two parts, and separate the gate layer 1134 into two parts.

[0090] It should be understood that the present application does not specifically limit the size and / or position of the through hole 500 , and the size and / or position of the through hole 500 may be arbitrarily set according to the actual process to separate the gate structure 1130 in the first trench 100 into two parts.

[0091] Fig. 20 and Fig.21 is a schematic diagram of a structure for forming an isolation structure 1150 according to an exemplary embodiment of the present application, wherein: Fig.21 for Fig. 20 Schematic diagram of a partial cross section along direction BB.

[0092] For example, Fig. 20 and Fig.21 As shown, the protective layer 330 and the remaining second sacrificial layer 320 can be removed to form a fourth gap (not shown); and an isolation structure 1150 is formed in the fourth gap. For example, the fourth gap can be formed by using a photolithography process, one or more dry etching and / or wet etching processes, and the isolation structure 1150 can be formed by using one or more thin film deposition processes. Exemplarily, the isolation structure 1150 may include an isolation conductive layer 1152 and an isolation dielectric layer 1151 surrounding the isolation conductive layer 1152. The material of the isolation conductive layer 1152 may include, but is not limited to, metal materials such as tungsten and copper. The material of the isolation dielectric layer 1151 includes, but is not limited to, silicon oxide.

[0093] For example, a lead-out structure (not shown) connected to the isolation structure 1150 may be formed. In the present application, the lead-out structure may be grounded or a certain fixed potential may be applied to the lead-out structure, so that the isolation structure 1150 can electrically insulate adjacent semiconductor pillars 1140 and reduce coupling between adjacent semiconductor pillars 1140.

[0094] Fig. 22 For the general Fig.21 A schematic diagram of a structure in which the structure is flipped 180° and then thinned. In an exemplary embodiment of the present application, Fig. 22 As shown, a portion of the semiconductor layer 1110 may be removed from a side away from the semiconductor pillar 1140 until the first end 1141 of the semiconductor pillar 1140 is exposed.

[0095] For example, the semiconductor pillar 1140 and the isolation pillar 1160 ( Figure 5 ) may have the same height in the second direction Z. Removing a portion of the semiconductor layer 1110 from a side away from the semiconductor pillar 1140 to expose the first end 1141 of the semiconductor pillar 1140 may include: removing a portion of the semiconductor layer 1110 from a side away from the semiconductor pillar 1140 along the second direction Z to expose the isolation pillar 1160. For example, a mechanical grinding process may be used to remove a portion of the semiconductor layer 1110 to expose the isolation pillar 1160, that is, to expose the first end 1141 of the semiconductor pillar 1140.

[0096] In the present application, by removing part of the semiconductor layer 1110 to expose the first end 1141 of the semiconductor column 1140, multiple semiconductor columns 1140 can be formed into an independent structure, that is, the multiple semiconductor columns 1140 are separated from each other, which is beneficial to reduce the coupling phenomenon between adjacent semiconductor columns 1140 in subsequent process manufacturing.

[0097] In the exemplary embodiment of the present application, Fig.23As shown, a bit line 1170 connected to the first end 1141 of the semiconductor pillar 1140 and extending along the first direction X may be formed. For example, a conductive layer 1180 may be formed at the first end of the semiconductor pillar 1140 ; ​​and the bit line 1170 may be formed on the conductive layer 1180 .

[0098] Exemplarily, a transition conductive layer (not shown) may be formed at the first end 1141 of the semiconductor pillar 1140, wherein the first end 1141 of the semiconductor pillar 1140 may react with the transition conductive layer and change into a conductive layer 1180. Exemplarily, the transition conductive layer may include a metal material. Specifically, a metal material may be deposited at the first end 1141 of the semiconductor pillar 1140 to form a transition conductive layer, so that the first end 1141 of the semiconductor pillar 1140 (including silicon) reacts with the directly contacted transition conductive layer (including metal material) and changes into a conductive layer 1180 (including metal silicide). The present application can reduce the resistance of the first end 1141 of the semiconductor pillar 1140 by changing the first end 1141 of the semiconductor pillar 1140 into the conductive layer 1180. It should be understood that the material of the conductive layer 1180 may include, for example, metal silicide, etc.

[0099] For example, Fig.24 As shown, a first doped region 1143 may be formed at a first end 1141 of the semiconductor column 1140 and a second doped region 1144 may be formed at a second end 1142 of the semiconductor column 1140, wherein a bit line 1170 may be connected to the first doped region 1143. The first doped region 1143 and the second doped region 1144 may be the source and drain of the semiconductor column 1140, respectively. The source and the drain may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). The source and the drain may be separated by a gate structure 1130 in the second direction. That is, the gate structure 1130 is vertically formed between the source and the drain. When a gate voltage applied to the gate layer 1134 of the gate structure 1130 is higher than a threshold voltage of the vertical transistor (including the gate structure 1130 and the semiconductor pillar 1140 ), one or more channels of the vertical transistor may be vertically formed in the semiconductor body 1140 between the source and the drain.

[0100] In the exemplary embodiment of the present application, Fig.24As shown, a capacitor 1190 connected to the second end 1142 of the semiconductor pillar 1140 opposite to the first end 1141 along the second direction Z may be formed. The capacitor 1190 may include a first electrode (not shown) connected to the second doped region 1144, a capacitor dielectric (not shown) in contact with the first electrode, and a second electrode (not shown) in contact with the capacitor dielectric. The capacitor 1190 may include, but is not limited to, planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate-plate capacitors. Exemplarily, the capacitor 1190 may be a vertical capacitor in which the first electrode, the capacitor dielectric, and the second electrode are stacked along the second direction, and the capacitor dielectric may be sandwiched between the first electrode and the second electrode.

[0101] Fig.24 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment of the present application.

[0102] The semiconductor structure may include a plurality of semiconductor pillars 1140 , a gate structure 1130 , and a bit line 1170 .

[0103] The plurality of semiconductor pillars 1140 may extend along the second direction Z and be distributed in an array along the first direction X and the third direction Y, wherein the first direction X and the third direction Y intersect, and the second direction Z may be perpendicular to the first direction X and the third direction Y.

[0104] Exemplarily, a plurality of semiconductor pillars 1140 are spaced apart from each other to expose one or more sidewalls of the semiconductor pillars 1140. For example, the semiconductor pillars 1140 may have a cubic shape to expose four sidewalls thereof. It should be understood that the semiconductor pillars 1140 may have any suitable three-dimensional shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor pillars 1140 in a plan view (e.g., in an XY plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape), or any other suitable shape.

[0105] The material of the semiconductor pillar 1140 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0106] The gate structure 1130 may be located on the sidewalls of the semiconductor pillars 1140 and may extend along the third direction Y. For example, the first ends 1141 of the semiconductor pillars 1140 adjacent to each other along the first direction X may be isolated by the gate structure 1130. In other words, the first ends 1141 of the plurality of semiconductor pillars 1140 are not connected.

[0107] The gate structure 1130 may include a dielectric layer (including a first dielectric layer 1132), a gate dielectric layer 1133, and a gate layer 1134. The gate dielectric layer 1133 may be located on the dielectric layer and may be located on the first sidewall of the semiconductor pillar 1140. The gate layer 1134 may be located on the dielectric layer and may be located on the surface of the gate dielectric layer 1133. Exemplarily, the gate structure 1130 may also include a second dielectric layer 1135, wherein the second dielectric layer 1135 may be located on the dielectric layer and may be located on the surface of the gate layer 1134. Exemplarily, the dielectric layer may also include a third dielectric layer 1131 surrounding a portion of the first dielectric layer 1132. That is, the dielectric layer may include the first dielectric layer 1132 and the third dielectric layer 1131.

[0108] For example, two adjacent gate structures 1130 may be mirror-symmetrical along the second direction Z. The first dielectric layer 1132, the second dielectric layer 1135, and the third dielectric layer 1131 in the two partially mirror-symmetrical gate structures 1130 are continuous. In other words, the first dielectric layer 1132 in the two partially mirror-symmetrical gate structures 1130 may be connected to form an integral structure, the second dielectric layer 1135 in the two gate structures 1130 may be connected to form an integral structure, and the third dielectric layer 1131 in the two gate structures 1130 may be connected to form an integral structure. Fig.19B As shown, a partial structural diagram of a gate structure 1130 is shown.

[0109] For example, the semiconductor column 1140 and the gate structure 1130 may be used together to form a vertical transistor, wherein the semiconductor column 1140 may be used to form an active region of multiple channels in the vertical transistor. For example, the gate structure 1130 may be located on at least one sidewall of the semiconductor column 1140, that is, the semiconductor column 1140 may be at least partially surrounded by the gate structure 1130. It should be understood that Fig.24 The situation in which the gate structure 1130 is located on one sidewall of the semiconductor pillar 1140 is only an example and is not specifically limited.

[0110] In one embodiment of the present application, the gate structure 1130 may be located on multiple sidewalls of the semiconductor column 1140, that is, adjacent semiconductor columns 1140 along the first direction X may be spaced apart by the gate structure 1130. At this time, the semiconductor column 1140 and the gate structure 1130 may be used together to form a multi-gate transistor (for example, a gate-all-around (GAA) transistor, a tri-gate transistor, or a dual-gate transistor). The multi-gate transistor may have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the cut-off state, the leakage current of the multi-gate transistor may also be significantly reduced due to the complete depletion of the channel. Therefore, better speed (saturated drain current) / leakage current performance may be achieved using a multi-gate transistor.

[0111] In another embodiment of the present application, the semiconductor structure may further include an isolation structure 1150. The isolation structure 1150 may be located at the second sidewall of the semiconductor column 1140, which is opposite to the first sidewall, and extends along the third direction Y. In other words, the gate structure 1130 and the isolation structure 1150 may be located on two opposite sidewalls of the semiconductor column 1140, respectively, that is, the adjacent semiconductor columns 1140 along the first direction X may be spaced apart by the gate structure 1130 or the isolation structure 1150. At this time, the semiconductor column 1140 and the gate structure 1130 may be used together to form a single-gate transistor. Exemplarily, the single-gate transistors adjacent to each other along the first direction may be arranged in a mirror-symmetrical manner. By providing a single-gate transistor, the present application can significantly increase the density of the semiconductor column 1140 in the first direction and reduce the difficulty of the manufacturing process. In addition, the mirror-symmetrical single-gate transistor may have a larger process window, which is conducive to reducing the spacing between the bit lines, word lines and transistors formed subsequently.

[0112] Exemplarily, the first dielectric layer 1132, the second dielectric layer 1135, the third dielectric layer 1131 and the gate dielectric layer 1133 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or a high-k dielectric. For example, the gate dielectric layer 1133 may include silicon oxide, i.e., gate oxide. The gate layer 1134 may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.) or a silicide. For example, the gate layer 1134 may include doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate layer 1134 includes multiple conductive layers, such as a W layer on a TiN layer.

[0113] By way of example, the isolation structure 1150 may include an isolation conductive layer 1152 and an isolation dielectric layer 1151 surrounding the isolation conductive layer 1152. The material of the isolation conductive layer 1152 may include, but is not limited to, metal materials such as tungsten and copper. The material of the isolation dielectric layer 1151 may include, but is not limited to, silicon oxide.

[0114] Exemplarily, the semiconductor structure may further include a lead structure (not shown) connected to the isolation structure 1150. In the present application, the lead structure may be grounded or a certain fixed potential may be applied to the lead structure, so that the isolation structure 1150 can electrically insulate adjacent semiconductor pillars 1140 and reduce coupling between adjacent semiconductor pillars 1140.

[0115] In an exemplary embodiment of the present application, the plurality of semiconductor pillars 1140 are separated from each other. The bit line 1170 may be in direct contact with the first end 1141 of the semiconductor pillar 1140 and extend along the first direction X. For example, the first end 1141 of the semiconductor pillar 1140 may include a conductive layer 1180. The conductive layer 1180 may be in direct contact with the bit line 1170. Adjacent conductive layers 1180 along the first direction X are spaced apart. For example, the material of the conductive layer 1180 may include, for example, metal silicide or the like.

[0116] For example, the end surface of the gate structure 1130 close to the bit line 1170 may be coplanar with the end surface of the conductive layer 1180 close to the bit line 1170. Fig.24 As shown, an end surface of the third dielectric layer 1131 close to the bit line 1170 along the first direction X may be coplanar with an end surface of the conductive layer 1180 close to the bit line 1170 along the first direction X.

[0117] Exemplarily, the semiconductor structure may further include a first doped region 1143 located at a first end 1141 of the semiconductor column 1140 and a second doped region 1144 located at a second end 1142 of the semiconductor column 1140, wherein the bit line 1170 may be connected to the first doped region 1143. The first doped region 1143 and the second doped region 1144 may be the source and drain of the semiconductor column 1140, respectively. The source and the drain may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). The source and the drain may be separated by the gate structure 1130 in the second direction. That is, the gate structure 1130 is vertically formed between the source and the drain. When a gate voltage applied to the gate layer 1134 of the gate structure 1130 is higher than a threshold voltage of the vertical transistor (including the gate structure 1130 and the semiconductor pillar 1140 ), one or more channels of the vertical transistor may be vertically formed in the semiconductor body 1140 between the source and the drain.

[0118] In an exemplary embodiment of the present application, the semiconductor structure may further include a capacitor 1190 connected to a second end 1142 of the semiconductor column 1140 opposite to the first end 1141 along the second direction Z. The capacitor 1190 may include a first electrode (not shown) connected to the second doped region 1144, a capacitor dielectric (not shown) in contact with the first electrode, and a second electrode (not shown) in contact with the capacitor dielectric. The capacitor 1190 may include, but is not limited to, planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate-plate capacitors. Exemplarily, the capacitor 1190 may be a vertical capacitor in which the first electrode, the capacitor dielectric, and the second electrode are stacked along the second direction, and the capacitor dielectric may be sandwiched between the first electrode and the second electrode.

[0119] Since the contents and structures involved in the method 1000 for manufacturing a semiconductor structure described above may be fully or partially applicable to the semiconductor structure described herein, the contents related or similar thereto will not be described in detail herein.

[0120] Although the exemplary structure and method of making the semiconductor structure are described herein, it is understood that one or more features may be omitted, replaced or added from the method of making the semiconductor structure. In addition, the illustrated layers and materials thereof are merely exemplary.

[0121] Fig.25 is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application.

[0122] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device having the storage system 12 located therein). Fig.25 As shown, the system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to or from the three-dimensional memory 14.

[0123] The three-dimensional memory 14 may include a semiconductor structure described in any embodiment of the present application. According to some embodiments, the controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media card (eMMC) used as a data storage device for mobile devices, and an enterprise storage array, and the mobile device is a smart phone, a tablet computer, a laptop computer, etc. The controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction code (ECC) related to data read from or written to the three-dimensional memory 14. Any other appropriate function may also be performed by the controller 16, for example, formatting the three-dimensional memory 14. The controller 16 may communicate with an external device (e.g., a host 18) according to a specific communication protocol. For example, the controller 16 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0124] The controller 16 and the one or more three-dimensional memories 14 may be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 may be implemented and packaged into different types of final electronic products. Fig.26AIn one example shown in FIG, the controller 16 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a memory card 22 that connects to a host (e.g., Fig.25 The host 18 in the memory card connector 24 is coupled. Fig.26B In another example shown in FIG. 1 , the controller 16 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Fig.25 In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than the storage capacity and / or operating speed of the memory card 22.

[0125] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: Obtaining an initial semiconductor structure, wherein the initial semiconductor structure comprises: A semiconductor layer, comprising a plurality of semiconductor pillars, the semiconductor pillars extending along a second direction and distributed in an array along a first direction and a third direction, wherein the first direction and the third direction intersect, and the second direction is perpendicular to the first direction and the third direction; and A gate structure, located on the sidewall of the semiconductor column and extending along the third direction; removing a portion of the semiconductor layer from a side away from the semiconductor column until the first end of the semiconductor column is exposed; and A bit line is formed which is connected to the first end of the semiconductor pillar and extends along the first direction.

2. The method according to claim 1, characterized in that: Forming a bit line connected to the first end of the semiconductor column and extending along the first direction, comprising: forming a conductive layer at a first end of the semiconductor pillar; and The bit line is formed on the conductive layer.

3. The method according to claim 1, characterized in that Obtaining an initial semiconductor structure, including: forming a plurality of initial semiconductor pillars extending along the first direction and the second direction in the semiconductor layer; and A plurality of gate structures are formed which pass through the initial semiconductor column and extend along the third direction and are arranged along the first direction, wherein the plurality of gate structures divide the initial semiconductor column into a plurality of semiconductor columns extending along the second direction.

4. The method according to claim 3, characterized in that Forming a plurality of gate structures that pass through the initial semiconductor column, extend along the third direction, and are arranged along the first direction, comprising: The gate structure and the isolation structure are formed to pass through the initial semiconductor column and extend along the third direction and are arranged along the first direction, wherein the gate structure and the isolation structure divide the initial semiconductor column into a plurality of semiconductor columns extending along the second direction.

5. The method according to claim 4, characterized in that The gate structure and the isolation structure are formed to pass through the initial semiconductor column, extend along the third direction, and be arranged along the first direction, including: forming first trenches and second trenches that pass through the initial semiconductor pillars and extend along the third direction and are alternately arranged along the first direction; and The gate structure and the isolation structure are formed in the first trench and the second trench respectively.

6. The method according to claim 3, characterized in that A plurality of initial semiconductor pillars extending along the first direction and the second direction are formed in the semiconductor layer, comprising: A plurality of isolation columns extending along the first direction and the second direction are formed in the semiconductor layer, wherein the plurality of isolation columns divide a portion of the semiconductor layer into a plurality of initial semiconductor columns, and the initial semiconductor columns and the isolation columns are alternately arranged along the third direction.

7. The method according to claim 6, characterized in that The semiconductor column and the isolation column have the same height in the second direction, and a portion of the semiconductor layer is removed from a side away from the semiconductor column to expose the first end of the semiconductor column, comprising: A portion of the semiconductor layer is removed along the second direction from a side away from the semiconductor column until the isolation column is exposed.

8. The method according to claim 5, characterized in that Forming a first trench and a second trench that pass through the initial semiconductor column and extend along the third direction and are alternately arranged along the first direction, comprising: forming, in the semiconductor layer, initial first trenches and second trenches that pass through the initial semiconductor pillars and extend along the third direction and are alternately arranged along the first direction; forming a first sacrificial layer and a second sacrificial layer in the initial first trench and the second trench, respectively; removing a portion of the second sacrificial layer along a second direction, and forming a protective layer in the removed space; and The first sacrificial layer is removed, and the width and depth of the initial first trench are increased to form the first trench.

9. The method according to claim 8, characterized in that The gate structure and the isolation structure are formed in the first trench and the second trench respectively, including: forming a first dielectric layer in the first trench; removing a portion of the first dielectric layer along the second direction to form a first gap; forming a gate dielectric layer on a sidewall of the first gap; forming a gate layer on a surface of the gate dielectric layer; removing a portion of the gate layer along the second direction to form a second gap; forming a third gap along the second direction through the gate layer to expose the first dielectric layer; forming a second dielectric layer in the second gap and the third gap, wherein the gate structure includes the first dielectric layer, the second dielectric layer, the gate dielectric layer, and the gate layer that is not removed; removing the protective layer and the remaining second sacrificial layer to form a fourth gap; and The isolation structure is formed in the fourth gap.

10. The method according to any one of claims 1 to 9, characterized in that The method further comprises: A capacitor is formed connected to a second end of the semiconductor pillar opposite to the first end along the second direction.

11. The method according to claim 2, characterized in that Forming a conductive layer at the first end of the semiconductor column, comprising: A transition conductive layer is formed at the first end of the semiconductor pillar, wherein the first end of the semiconductor pillar reacts with the transition conductive layer and changes into the conductive layer.

12. A semiconductor structure, characterized in that: include: A plurality of semiconductor pillars extending along a second direction and distributed in an array along a first direction and a third direction, wherein the first direction and the third direction intersect, and the second direction is perpendicular to the first direction and the third direction; a gate structure, located at a first sidewall of the semiconductor column and extending along the third direction, wherein first ends of the semiconductor columns adjacent to each other along the first direction are isolated by the gate structure; as well as The bit line directly contacts the first end of the semiconductor column and extends along the first direction.

13. The semiconductor structure according to claim 12, characterized in that: The gate structure comprises: a dielectric layer proximate the first end of the semiconductor pillar; a gate dielectric layer located on the dielectric layer and on a first sidewall of the semiconductor pillar; and The gate layer is located on the dielectric layer and on the surface of the gate dielectric layer.

14. The semiconductor structure according to claim 13, characterized in that: The first end of the semiconductor pillar includes a conductive layer, and the conductive layer is in direct contact with the bit line.

15. The semiconductor structure according to claim 14, characterized in that: An end surface of the gate structure close to the bit line is coplanar with an end surface of the conductive layer close to the bit line.

16. The semiconductor structure according to claim 12, characterized in that The semiconductor structure further comprises: An isolation structure is located at a second side wall of the semiconductor column opposite to the first side wall and extends along the third direction, wherein adjacent semiconductor columns along the first direction are spaced apart by the gate structure or the isolation structure.

17. The semiconductor structure according to claim 16, characterized in that: The isolation structure comprises: isolating the conductive layer; and An isolation dielectric layer surrounds the isolation conductive layer.

18. The semiconductor structure according to claim 12, characterized in that: The semiconductor structure further comprises: A capacitor is connected to a second end of the semiconductor column opposite to the first end along the second direction.

19. A storage system, characterized in that: include: At least one three-dimensional memory, each of the three-dimensional memory comprising a semiconductor structure as claimed in any one of claims 12 to 18; as well as The controller is coupled to the semiconductor structure and is used for controlling the three-dimensional memory to store data.

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