Schottky diode and preparation method thereof

Abstract

The embodiment of the invention relates to a Schottky diode and a preparation method thereof, and the method comprises the steps: providing a semiconductor material layer; forming a barrier layer on the semiconductor material layer; the barrier layer is etched to form an opening exposing the semiconductor material layer in the barrier layer, the opening comprises a plurality of sub-openings, and the part, located between the sub-openings, of the barrier layer is not removed and forms an isolation retaining wall structure located between the sub-openings; respectively forming a plurality of sub-metal electrodes in the plurality of sub-openings, wherein the sub-metal electrodes are in direct contact with the semiconductor material layer to form a Schottky diode; and forming a conductive interconnection layer on the plurality of sub-metal electrodes and the barrier layer which is not removed, wherein the sub-metal electrodes are conductively connected through the conductive interconnection layer. Therefore, when the barrier layer is etched, complete etching is easier to realize, the process difficulty is lower, and the effect is better.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a Schottky diode and a method for preparing the same. Background Art

[0002] A Schottky diode is a device made using the metal-semiconductor contact characteristics. When metal and semiconductor are in contact, the electron concentration in the metal is higher than that in the semiconductor, so the electrons in the metal will move toward the semiconductor, thus forming a Schottky barrier at the contact point between the metal and the semiconductor. Under forward bias, electrons move from the semiconductor to the metal side, forming a forward conduction circuit; under reverse bias, the Schottky barrier becomes steeper, preventing electrons from moving to the metal side, and the device exhibits a high reverse resistance characteristic. Therefore, in order to more effectively utilize this contact characteristic, a large metal-semiconductor contact surface is often designed in a Schottky diode.

[0003] In actual preparation, a self-aligned silicide barrier (SAB) is usually formed at the corresponding position of the semiconductor layer, and then the SAB is etched over a large area to form a large-sized opening, and a metal electrode is formed in the opening to accurately locate the position of the metal electrode and meet the requirements of a large area of ​​metal-semiconductor contact surface. However, etching over a large area is prone to the problem of being difficult to etch cleanly, and the residue will hinder the contact between the metal electrode and the semiconductor layer, affecting the formation of the Schottky barrier, and then affecting the device performance. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a Schottky diode and a method for preparing the same in order to solve at least one problem existing in the background technology.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a Schottky diode, the method comprising:

[0006] providing a semiconductor material layer;

[0007] forming a barrier layer on the semiconductor material layer;

[0008] Etching the barrier layer to form an opening in the barrier layer to expose the semiconductor material layer, wherein the opening includes a plurality of sub-openings, and a portion of the barrier layer located between the sub-openings is not removed but is formed as an isolation barrier wall structure located between the sub-openings;

[0009] forming a plurality of sub-metal electrodes in the plurality of sub-openings respectively, wherein the sub-metal electrodes are in direct contact with the semiconductor material layer to form a Schottky diode;

[0010] A conductive interconnection layer is formed on the plurality of sub-metal electrodes and the barrier layer that has not been removed, and the sub-metal electrodes are conductively connected through the conductive interconnection layer.

[0011] In combination with the first aspect of the present application, in an optional implementation manner, in a direction perpendicular to the semiconductor material layer, the projections of the plurality of sub-metal electrodes are in the form of inner and outer nested rings; or,

[0012] In the direction perpendicular to the semiconductor material layer, except for the innermost sub-metal electrode, the projections of the other sub-metal electrodes are in the form of inner-and-outer nested rings, and the projection of the next innermost sub-metal electrode surrounds the projection of the innermost sub-metal electrode.

[0013] In combination with the first aspect of the present application, in an optional implementation manner, the ring width of the sub-metal electrode projected in a ring shape ranges from 0.15 μm to 0.25 μm;

[0014] The distance between two adjacent metal electrodes ranges from 0.2 μm to 0.3 μm.

[0015] In combination with the first aspect of the present application, in an optional implementation manner, after etching the barrier layer, the method further includes:

[0016] Continue etching the semiconductor material layer downward along the plurality of sub-openings to form a plurality of sub-grooves in the semiconductor material layer;

[0017] The bottom of the sub-metal electrode is formed in the sub-groove, and the sub-metal electrode is in direct contact with the semiconductor material layer at the sidewall and bottom wall of the sub-groove.

[0018] In combination with the first aspect of the present application, in an optional implementation, the depth of the sub-groove is equal to half the width of the isolation retaining wall structure.

[0019] In a second aspect, an embodiment of the present application provides a Schottky diode, including:

[0020] a semiconductor material layer;

[0021] A plurality of sub-metal electrodes, located on the semiconductor material layer and directly contacting the semiconductor material layer to form a Schottky diode;

[0022] An isolation retaining wall structure is located between two adjacent sub-metal electrodes;

[0023] The conductive interconnection layer is located on the plurality of sub-metal electrodes and the isolation retaining wall structure, and the sub-metal electrodes are conductively connected through the conductive interconnection layer.

[0024] In conjunction with the second aspect of the present application, in an optional implementation manner, in a direction perpendicular to the semiconductor material layer, the projections of the plurality of sub-metal electrodes are in the form of inner and outer nested rings; or,

[0025] In the direction perpendicular to the semiconductor material layer, except for the innermost sub-metal electrode, the projections of the other sub-metal electrodes are in the form of inner-and-outer nested rings, and the projection of the next innermost sub-metal electrode surrounds the projection of the innermost sub-metal electrode.

[0026] In conjunction with the second aspect of the present application, in an optional implementation manner, the ring width of the sub-metal electrode projected in a ring shape ranges from 0.15 μm to 0.25 μm;

[0027] The distance between two adjacent metal electrodes ranges from 0.2 μm to 0.3 μm.

[0028] In conjunction with the second aspect of the present application, in an optional implementation, a plurality of sub-grooves are provided in the semiconductor material layer, each of the sub-grooves extending from a surface of the semiconductor material layer facing the sub-metal electrode to an interior of the semiconductor material layer;

[0029] The bottom of the sub-metal electrode is located in the sub-groove, the sub-metal electrode is in direct contact with the semiconductor material layer at the side wall and the bottom wall of the sub-groove, and the top of the sub-metal electrode protrudes from the surface of the semiconductor material layer.

[0030] In conjunction with the second aspect of the present application, in an optional implementation, the depth of the sub-groove is equal to half the width of the isolation retaining wall structure.

[0031] On the one hand, the method for preparing a Schottky diode provided in the embodiment of the present application etches a plurality of sub-openings in the barrier layer. Compared with etching a large area of ​​the barrier layer to form a large-sized opening, etching a small area is easier to achieve complete etching, the process difficulty is lower and the effect is better, and the risk of residues at the opening position is reduced, which is beneficial to ensuring direct contact between the metal electrode and the semiconductor material layer and ensuring device performance.

[0032] On the other hand, compared with setting up a whole large-area metal electrode, the Schottky diode provided in the embodiment of the present application sets up multiple sub-metal electrodes in direct contact with the semiconductor material layer. In the preparation process of the small-area sub-metal electrodes, it is easier to achieve complete etching of the barrier layer, reducing the risk of residues formed between the metal electrode and the semiconductor material layer, which is beneficial to ensuring direct contact between the metal electrode and the semiconductor material layer and ensuring device performance.

[0033] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0035] Figure 1 A schematic diagram of the cross-sectional structure of a Schottky diode provided for related technology;

[0036] Figure 2 for Figure 1 A layout of the structure shown;

[0037] Figure 3 A schematic flow chart of a method for preparing a Schottky diode provided in an embodiment of the present application;

[0038] Figures 4 to 17 A schematic diagram of the cross-sectional structure of a Schottky diode during the preparation process provided in an embodiment of the present application;

[0039] Fig.18 A layout of a portion of the structural layers of a Schottky diode provided as an optional example;

[0040] Fig.19 A layout of a part of the structural layers of a Schottky diode provided as another optional example;

[0041] Fig. 20 A layout of a part of the structural layers of a Schottky diode provided as yet another optional example;

[0042] Fig.21 A schematic diagram of the cross-sectional structure of a Schottky diode provided for an optional implementation manner. DETAILED DESCRIPTION

[0043] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0044] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0045] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0046] When an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below may be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0047] Spatially relative terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. In addition to the orientation shown in the figure, the spatially relative terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0048] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0049] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0050] Figure 1 A schematic diagram of the cross-sectional structure of a Schottky diode provided for related technologies, Figure 2 for Figure 1 The layout of the structure shown. Figure 1 and Figure 2 As shown, in the related art, the barrier layer 400 on the semiconductor material layer 100 is usually etched over a large area to form a large-sized opening 411 in the barrier layer 400, and a metal electrode 601 is formed in the opening 411 to meet the demand for a large-area metal-semiconductor contact surface.

[0051] Among them, etching is a very important step in the semiconductor manufacturing process and an important process of graphic processing associated with the photolithography process. Specifically, it is to selectively etch the substrate surface or the thin film covering the surface by chemical or physical methods. At present, the common etching processes in this field are wet etching and dry etching. Wet etching mainly uses chemical reagents to react with the etched material to perform chemical reactions; while dry etching mainly uses reactive gases and plasma to etch away part of the material to be removed and form volatile reaction products, and then extract the reaction products from the reaction chamber.

[0052] In the related art, a dry etching process is usually used to etch the barrier layer 400. When etching a large area, there is often a situation where the etching rate is greater than the reverse extraction of the reaction product. The reaction product remains on the surface of the semiconductor material layer 100, resulting in the problem of incomplete etching. After the metal electrode 601 is formed in the large-sized opening 411, there is a residue (reaction product) between the metal electrode 601 and the semiconductor material layer 100, and the two cannot achieve direct contact, affecting the formation of the Schottky barrier. Of course, in some other etching processes, it may be difficult to etch a large area pattern well. This application uses a dry etching process as an example for explanation. Those skilled in the art are aware of the situation of incomplete etching of large areas in other etching processes, which will not be elaborated here.

[0053] Based on this, the present invention provides a method for preparing a Schottky diode. Figure 3 , the preparation method comprises:

[0054] Step S101: providing a semiconductor material layer;

[0055] Step S102: forming a barrier layer on the semiconductor material layer;

[0056] Step S103: etching the barrier layer to form an opening in the barrier layer to expose the semiconductor material layer, wherein the opening includes a plurality of sub-openings, and a portion of the barrier layer located between the sub-openings is not removed to form an isolation barrier wall structure located between the sub-openings;

[0057] Step S104: forming a plurality of sub-metal electrodes in the plurality of sub-openings respectively, wherein the sub-metal electrodes are in direct contact with the semiconductor material layer to form a Schottky diode;

[0058] Step S105: forming a conductive interconnection layer on the plurality of sub-metal electrodes and the barrier layer that has not been removed, and the sub-metal electrodes are conductively connected via the conductive interconnection layer.

[0059] Therefore, compared with the situation where a large area of ​​the barrier layer is etched to form a large opening, the present embodiment etches a plurality of sub-openings in the barrier layer, and the etching of a small area is easier to achieve complete etching, the process difficulty is lower and the effect is better, and the risk of residues at the opening position is reduced, which is beneficial to ensuring direct contact between the metal electrode and the semiconductor material layer and ensuring device performance.

[0060] First, please refer to Figure 4 , perform step S101: provide a semiconductor material layer 100.

[0061] The material of the semiconductor material layer 100 may include any suitable semiconductor material, such as silicon, germanium, silicon germanium, etc.; in addition, the present application does not exclude the situation where the material of the semiconductor material layer 100 includes at least one III-V or II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0062] Next, please continue to refer to Figure 4 , forming an isolation structure 110 located on top of the semiconductor material layer 100 and embedded in the semiconductor material layer 100. The isolation structure 110 includes but is not limited to a shallow trench isolation structure. The isolation structure 110 defines the active region and each doped region of the device. Please refer to Fig. 20 The isolation structure 110 may include a plurality of ring-shaped portions nested inside and outside, and each ring-shaped portion is used to distinguish different doping regions.

[0063] The isolation structure 110 may be formed by a process commonly used in the art, which will not be described in detail here.

[0064] Please refer to Figure 5 , a buried layer 120 is formed in the semiconductor material layer 100. The buried layer 120 has a second conductivity type; in this embodiment, the buried layer 120 is an N-type buried layer (NBL).

[0065] The formation of the buried layer 120 may specifically include forming a patterned first mask layer 210 on the semiconductor material layer 100, wherein the patterned first mask layer 210 exposes a preset formation area of ​​the buried layer 120; and performing an ion implantation process using the patterned first mask layer 210 as a mask to form a buried layer 120 having a second conductivity type in the semiconductor material layer 100.

[0066] Next, please refer to Figure 6 , a deep well 130 is formed in the semiconductor material layer 100. The deep well 130 has the second conductivity type; in this embodiment, the deep well 130 is a deep N-well (DNW). The deep well 130 is located above the buried layer 120 and is connected to the buried layer 120.

[0067] The formation of the deep well 130 may specifically include forming a patterned second mask layer 220 on the semiconductor material layer 100, wherein the patterned second mask layer 220 exposes a preset formation area of ​​the deep well 130; and performing an ion implantation process using the patterned second mask layer 220 as a mask to form a deep well 130 having a second conductivity type.

[0068] Please refer to Figure 7Next, a first drift region 140 is formed in the semiconductor material layer 100. The first drift region 140 has a second conductivity type; in this embodiment, the first drift region 140 is an N-type drift region, and specifically can be a high voltage N-type drift region (HVN-drift region, HNDR). The first drift region 140 is located above the deep well 130 and is connected to the deep well 130.

[0069] The formation of the first drift region 140 may specifically include forming a patterned third mask layer 230 on the semiconductor material layer 100, wherein the patterned third mask layer 230 exposes a preset formation area of ​​the first drift region 140; and performing an ion implantation process using the patterned third mask layer 230 as a mask to form the first drift region 140 having a second conductivity type.

[0070] Next, please refer to Figure 8 A second drift region 150 is formed in the semiconductor material layer 100, and the second drift region 150 is located in the first drift region 140. The second drift region 150 has a first conductivity type; in this embodiment, the second drift region 150 is a P-type drift region, and specifically can be a PP-drift region (PDRF).

[0071] The formation of the second drift region 150 may specifically include forming a patterned fourth mask layer 240 on the semiconductor material layer 100, wherein the patterned fourth mask layer 240 exposes a preset formation area of ​​the second drift region 150; and performing an ion implantation process using the patterned fourth mask layer 240 as a mask to form the second drift region 150 having a first conductivity type.

[0072] Please refer to Fig. 9 A first well region 160 is formed in the semiconductor material layer 100, and the first well region 160 is located outside the first drift region 140. The first well region 160 has a first conductivity type; in this embodiment, the first well region 160 is a PW (Pwell, P well) region.

[0073] Forming the first well region 160 may specifically include forming a patterned fifth mask layer (not shown) on the semiconductor material layer 100, wherein the patterned fifth mask layer exposes a predetermined formation area of ​​the first well region 160; and performing an ion implantation process using the patterned fifth mask layer as a mask to form the first well region 160 having a first conductivity type. In an actual process, the second drift region 150 and the first well region 160 may be formed in the same process.

[0074] Next, please continue to refer to Fig. 9A second well region 170 is formed in the semiconductor material layer 100, and the second well region 170 is located in the first drift region 140. The second well region 170 has a second conductivity type; in this embodiment, the second well region 170 is a NW (Nwell, N well) region.

[0075] The formation of the second well region may specifically include forming a patterned sixth mask layer (not shown in the figure) on the semiconductor material layer 100, wherein the patterned sixth mask layer exposes a preset formation area of ​​the second well region 170; and performing an ion implantation process using the patterned sixth mask layer as a mask to form a second well region 170 having a second conductivity type.

[0076] Next, please refer to Fig.10 A first conductive lead-out region 161 is formed on the surface of the semiconductor material layer 100. The first conductive lead-out region 161 is located on the top of the first well region 160 and is connected to the first well region 160, and is used to conductively lead out the first well region 160. The conductivity type of the first conductive lead-out region 161 is the same as that of the first well region 160, and the ion doping concentration is greater than the ion doping concentration of the first well region 160. In this embodiment, the first conductive lead-out region 161 is a P+ lead-out region (SP region).

[0077] The formation of the first conductive lead-out region 161 may specifically include forming a patterned seventh mask layer (not shown in the figure) on the semiconductor material layer 100, wherein the patterned seventh mask layer exposes a preset formation area of ​​the first conductive lead-out region 161; and performing an ion implantation process using the patterned seventh mask layer as a mask to form the first conductive lead-out region 161 on the surface layer of the semiconductor material layer 100.

[0078] Please continue to refer to Fig.10 A second conductive lead-out region 171 is formed on the surface of the semiconductor material layer 100. The second conductive lead-out region 171 is located on the top of the second well region 170 and is connected to the second well region 170, and is used to conductively lead out the second well region 170. The conductivity type of the second conductive lead-out region 171 is the same as that of the second well region 170, and the ion doping concentration is greater than the ion doping concentration of the second well region 170. In this embodiment, the second conductive lead-out region 171 is an N+ lead-out region (SN region).

[0079] The formation of the second conductive lead-out region 171 may specifically include forming a patterned eighth mask layer (not shown in the figure) on the semiconductor material layer 100, wherein the patterned eighth mask layer exposes a preset formation area of ​​the second conductive lead-out region 171; using the patterned eighth mask layer as a mask, performing an ion implantation process to form the second conductive lead-out region 171 on the surface layer of the semiconductor material layer 100.

[0080] Please refer to Fig.11A gate dielectric layer (not shown) and a gate layer 300 are formed on the semiconductor material layer 100. The gate layer 300 is located on the gate dielectric layer and covers at least a portion of the second drift region 150. The material of the gate dielectric layer includes any suitable dielectric material; the material of the gate layer 300 may include polysilicon.

[0081] Please refer to Fig.13 , executing step S102 : forming a barrier layer 400 on the semiconductor material layer 100 .

[0082] In this embodiment, the barrier layer 400 may include a self-aligned silicide barrier layer (Self-Aligned Block, SAB).

[0083] like Fig.12 and Fig.13 As shown, forming the barrier layer 400 may specifically include forming a barrier layer material 401 covering the semiconductor material layer 100; forming a patterned ninth mask layer (not shown in the figure) on the barrier layer material 401, the patterned ninth mask layer exposing a preset formation area of ​​the barrier layer 400; using the patterned ninth mask layer as a mask, performing an etching process to form the barrier layer 400 on the semiconductor material layer 100.

[0084] Please refer to Fig.15 , step S103 is performed: etching the barrier layer 400 to form an opening in the barrier layer 400 to expose the semiconductor material layer 100, the opening includes a plurality of sub-openings 410, and the portion of the barrier layer 400 located between the sub-openings 410 is not removed but formed as an isolation barrier wall structure 420 located between the sub-openings 410. Therefore, compared with etching a large area of ​​the barrier layer 400 to form a large-sized opening, in this embodiment, etching a plurality of sub-openings 410 in the barrier layer 400, the etching of a small area is easier to achieve complete etching, the risk of residues at the opening position is reduced, the process difficulty is lower and the effect is better, which is conducive to ensuring the direct contact between the sub-metal electrode 600 formed in the subsequent process and the semiconductor material layer 100, and the device performance is guaranteed.

[0085] In this embodiment, the process of etching the barrier layer 400 includes a dry etching process. It is understandable that in some other etching processes, it may be difficult to etch a large area pattern well. This embodiment specifically uses the dry etching process as an example for description, and the method for preparing the opening provided in this embodiment is also applicable to other etching processes.

[0086] In an optional specific implementation, please refer to Fig.21After executing step S103, the preparation method may further include: continuing to etch the semiconductor material layer 100 downward along the multiple sub-openings 410 to form multiple sub-grooves 180 in the semiconductor material layer 100; the bottom of the sub-metal electrode 600 is formed in the sub-groove 180, and the sub-metal electrode 600 is in direct contact with the semiconductor material layer 100 at the side wall 181 and the bottom wall 182 of the sub-groove 180. It can be understood that compared with the whole large-area metal electrode formed in the prior art, in this embodiment, the sub-metal electrodes 600 are separated by the isolation retaining wall structure 420, and the isolation retaining wall structure 420 occupies a part of the area originally used for metal-semiconductor contact, resulting in a loss of metal-semiconductor contact area. Therefore, in the embodiment of the present application, multiple sub-grooves 180 are formed in the semiconductor material layer 100, and the bottom of the sub-metal electrode 600 is formed in the sub-groove 180, which increases the contact area between the sub-metal electrode 600 and the semiconductor material layer 100, reduces the loss of metal-semiconductor contact area, and is conducive to ensuring device performance.

[0087] Furthermore, the depth of the sub-groove 180 is equal to half the width of the isolation retaining wall structure 420. Therefore, the sum of the areas of the semiconductor material layer 100 at the two sidewalls 181 of the sub-groove 180 is equal to the contact area between the isolation retaining wall structure 420 and the semiconductor material layer 100, and the sub-metal electrode 600 is in direct contact with the semiconductor material layer 100 at the sidewall 181 of the sub-groove 180, which can basically make up for the loss of the metal-semiconductor contact area.

[0088] Optionally, refer to Fig.14 and Fig.15 After executing step S102, the preparation method may further include: forming a dielectric layer 500, wherein the dielectric layer 500 at least covers the semiconductor material layer 100 and the barrier layer 400; etching the dielectric layer 500 to form a plurality of through holes 510 in the dielectric layer 500, wherein some of the through holes 510 expose the barrier layer 400; step S103 includes: continuing to etch the barrier layer 400 downward along some of the through holes 510 that expose the barrier layer 400, so as to form an opening in the barrier layer 400 that exposes the semiconductor material layer 100, wherein the opening includes a plurality of sub-openings 410, and portions of the barrier layer 400 located between the sub-openings 410 are not removed but are formed as isolation barrier wall structures 420 located between the sub-openings 410.

[0089] Please refer to Fig.15 The plurality of through holes 510 in the dielectric layer 500 also include a portion of the through hole 510 exposing the first conductive lead-out region 161, a portion of the through hole 150 exposing the second conductive lead-out region 171, and a portion of the through hole 510 exposing the gate layer 300. In the subsequent process, please refer to Fig.16, a conductive contact structure 610 may be formed in the through hole 510 to achieve conductive extraction. It can be understood that the conductive contact structure 610 may be prepared in the same process as forming the sub-metal electrode 600.

[0090] Step S104 : forming a plurality of sub-metal electrodes 600 in the plurality of sub-openings 410 respectively, wherein the sub-metal electrodes 600 are in direct contact with the semiconductor material layer 100 to form Schottky diodes.

[0091] In an optional example, in a direction perpendicular to the semiconductor material layer 100, the projections of the plurality of sub-metal electrodes 600 are in a grid shape, see Fig.19 , the plurality of sub-metal electrodes 600 are arranged in a grid shape, the isolation retaining wall structure 420 is arranged in a grid shape, and the plurality of sub-metal electrodes 600 are spaced apart from each other.

[0092] In another optional example, in a direction perpendicular to the semiconductor material layer 100, the projections of the plurality of sub-metal electrodes 600 are in the shape of interdigitated fingers, see Fig. 20 , multiple sub-metal electrodes 600 are arranged in a finger-shaped arrangement, specifically, the multiple sub-metal electrodes 600 include a first part of sub-metal electrodes and a second part of sub-metal electrodes, the first part of sub-metal electrodes extend along a first direction, the second part of sub-metal electrodes extend along a second direction, and the first part of sub-metal electrodes are connected to the second part of sub-metal electrodes; wherein the first direction and the second direction are both parallel to the plane of the semiconductor material layer. Thus, the multiple sub-metal electrodes 600 are conductively interconnected to form a whole.

[0093] In yet another alternative example, see Fig. 20 , in the direction perpendicular to the semiconductor material layer 100, the projections of the multiple sub-metal electrodes 600 are in the form of nested rings. It can be understood that the design of the sub-metal electrode 600 with a ring structure allows more electrodes to be integrated on the limited semiconductor material layer 100 to reduce the loss of the metal-semiconductor contact area; and the sub-metal electrode 600 with a ring structure can provide a more uniform current distribution, ensure the performance of the device, and reduce the turn-on voltage of the device while ensuring that the reverse breakdown voltage remains unchanged, so as to realize the function of fast turn-on of the Schottky diode. Specifically, the projections of the multiple sub-metal electrodes 600 are in the form of concentric rings.

[0094] In another optional example, in the direction perpendicular to the semiconductor material layer 100, except for the innermost sub-metal electrode 600, the projections of the other sub-metal electrodes 600 are in the form of an inner-outer nested ring, and the projection of the second innermost sub-metal electrode 600 surrounds the projection of the innermost sub-metal electrode 600. It can be understood that in this example, the innermost sub-metal electrode 600 is a whole structure, and no isolation retaining wall structure 420 is formed inside it. The sub-metal electrode 600 with an annular structure allows more electrodes to be integrated on a limited semiconductor material layer 100 to reduce the loss of metal-semiconductor contact area; and the sub-metal electrode 600 with an annular structure can provide a more uniform current distribution to ensure device performance.

[0095] Optionally, the ring width of the sub-metal electrode 600 projected in a ring shape ranges from 0.15μm to 0.25μm; the spacing between two adjacent sub-metal electrodes 600 ranges from 0.2μm to 0.3μm. It can be understood that the width of the sub-opening 410 ranges from 0.15μm to 0.25μm; the width of the isolation retaining wall structure 420 ranges from 0.2μm to 0.3μm. Therefore, setting the ring width and spacing of the sub-metal electrode 600 within this range can avoid the width of the isolation retaining wall structure 420 being too large, which will lose more metal-semiconductor contact area, and can also avoid the size of the sub-opening 410 being too small, which will increase the process accuracy requirements and the process difficulty, so that the process can be compatible with the existing semiconductor process while ensuring the process effect, and by adjusting the device structure details, the device turn-on voltage can be reduced while ensuring the reverse breakdown voltage remains unchanged, thereby improving the device performance.

[0096] Step S105: A conductive interconnection layer 700 is formed on the plurality of sub-metal electrodes 600 and the barrier layer 400 that has not been removed, and each sub-metal electrode 600 is conductively connected through the conductive interconnection layer 700. Thus, the plurality of sub-metal electrodes 600 are interconnected to form a whole. In actual preparation, the conductive interconnection layer 700 may also be formed on the conductive contact structure 610.

[0097] The present application also provides a Schottky diode. Fig.17 , including: a semiconductor material layer 100; a plurality of sub-metal electrodes 600, located on the semiconductor material layer 100, directly contacting the semiconductor material layer 100 to form a Schottky diode; an isolation retaining wall structure 420, located between two adjacent sub-metal electrodes 600; a conductive interconnection layer 700, located on the plurality of sub-metal electrodes 600 and the isolation retaining wall structure 420, and each sub-metal electrode 600 is conductively connected through the conductive interconnection layer 700.

[0098] Therefore, compared with setting up a whole large-area metal electrode, the present embodiment sets up multiple sub-metal electrodes 600 in direct contact with the semiconductor material layer 100. In the preparation process of the small-area sub-metal electrode 600, it is easier to achieve complete etching of the barrier layer 400, thereby reducing the risk of residues formed between the metal electrode and the semiconductor material layer 100, which is beneficial to ensuring direct contact between the metal electrode and the semiconductor material layer 100 and ensuring device performance.

[0099] In an alternative example, see Fig.19 , in a direction perpendicular to the semiconductor material layer 100, the projections of the plurality of sub-metal electrodes 600 are in a grid shape. In another optional example, please refer to Fig. 20 In a direction perpendicular to the semiconductor material layer 100 , the projections of the plurality of sub-metal electrodes 600 are in the shape of interdigitated fingers.

[0100] In yet another alternative example, see Fig. 20 , in the direction perpendicular to the semiconductor material layer 100, the projections of the plurality of sub-metal electrodes 600 are in the form of a ring with inner and outer nesting. It can be understood that the design of the sub-metal electrode 600 with a ring structure allows more electrodes to be integrated on a limited semiconductor material layer 100 to reduce the loss of metal-semiconductor contact area; and the sub-metal electrode 600 with a ring structure can provide a more uniform current distribution, ensure device performance, and reduce the turn-on voltage of the device while ensuring that the reverse breakdown voltage remains unchanged.

[0101] In another optional example, in a direction perpendicular to the semiconductor material layer 100, except for the innermost sub-metal electrode 600, the projections of the other sub-metal electrodes 600 are in a ring shape with inner and outer nesting, and the projections of the sub-metal electrodes 600 located next to the innermost sub-metal electrode 600 surround the projection of the innermost sub-metal electrode 600. It can be understood that in this example, the innermost sub-metal electrode 600 is a whole structure, and the isolation retaining wall structure 420 is not formed therein.

[0102] Optionally, the ring width of the sub-metal electrode 600 projected in a ring shape ranges from 0.15μm to 0.25μm; the spacing between two adjacent sub-metal electrodes 600 ranges from 0.2μm to 0.3μm. It can be understood that the width of the isolation barrier structure 420 ranges from 0.2μm to 0.3μm. Therefore, by setting the ring width and spacing of the sub-metal electrode 600 within this range, it is possible to avoid the width of the isolation barrier structure 420 being too large, which would result in a loss of more metal-semiconductor contact area, and it is also possible to avoid the size of the sub-metal electrode 600 being too small, which would increase the process precision requirements and the process difficulty, so that the process can be compatible with the existing semiconductor process while ensuring the process effect, and by adjusting the device structure details, it is possible to reduce the device turn-on voltage and improve the device performance while ensuring that the reverse breakdown voltage remains unchanged.

[0103] In an alternative embodiment, please refer to Fig.21 , there are multiple sub-grooves 180 in the semiconductor material layer 100, each sub-groove 180 extends from the surface of the semiconductor material layer 100 facing the sub-metal electrode 600 to the inside of the semiconductor material layer 100; the bottom of the sub-metal electrode 600 is located in the sub-groove 180, the sub-metal electrode 600 is in direct contact with the semiconductor material layer 100 at the side wall 181 and the bottom wall 182 of the sub-groove 180, and the top of the sub-metal electrode 600 protrudes from the surface of the semiconductor material layer 100. It can be understood that compared with the large-area metal electrode formed in the prior art, in this embodiment, the sub-metal electrodes 600 are separated by the isolation retaining wall structure 420, and the isolation retaining wall structure 420 occupies a part of the area originally used for metal-semiconductor contact, resulting in a loss of metal-semiconductor contact area. Therefore, the embodiment of the present application forms a plurality of sub-grooves 180 in the semiconductor material layer 100, and the bottom of the sub-metal electrode 600 is formed in the sub-groove 180, thereby increasing the contact area between the sub-metal electrode 600 and the semiconductor material layer 100, reducing the metal-semiconductor contact area loss, and being beneficial to ensuring device performance.

[0104] Furthermore, the depth of the sub-groove 180 is equal to half the width of the isolation retaining wall structure 420. Therefore, the sum of the areas of the semiconductor material layer 100 at the two sidewalls 181 of the sub-groove 180 is equal to the contact area between the isolation retaining wall structure 420 and the semiconductor material layer 100, and the sub-metal electrode 600 is in direct contact with the semiconductor material layer 100 at the sidewall 181 of the sub-groove 180, which can basically make up for the loss of the metal-semiconductor contact area.

[0105] The method for preparing a Schottky diode provided in the present application forms a plurality of sub-openings by etching in a barrier layer. Compared with etching a large area of ​​the barrier layer to form a large-sized opening, etching a small area is easier to achieve complete etching, which is more process-friendly, makes the process easier to control, reduces the risk of residues at the opening position, and is beneficial to ensuring direct contact between the metal electrode and the semiconductor material layer, so that the prepared Schottky diode is more in line with design expectations; on this basis, the embodiment of the present application also proposes detailed improvements to the Schottky diode structure to compensate for the loss of metal-semiconductor contact area, avoid the device performance being affected by the isolation barrier wall structure, and reduce the device turn-on voltage while ensuring that the reverse breakdown voltage remains unchanged, thereby realizing the function of fast turn-on of the Schottky diode and further improving the device performance.

[0106] It should be noted that the Schottky diode embodiment provided in this application and the Schottky diode preparation method embodiment belong to the same concept; the technical features in the technical solutions recorded in each embodiment can be arbitrarily combined without conflict. However, it should be further noted that the Schottky diode provided in the embodiment of this application, the combination of its various technical features can already solve the technical problem to be solved by this application; therefore, the Schottky diode provided in the embodiment of this application may not be limited by the Schottky diode preparation method provided in the embodiment of this application, and any Schottky diode prepared by the preparation method that can form the Schottky diode structure provided in the embodiment of this application is within the scope of protection of this application.

[0107] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes may also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may also be combined arbitrarily to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A method for preparing a Schottky diode, characterized in that: The method comprises: providing a semiconductor material layer; forming a barrier layer on the semiconductor material layer; Etching the barrier layer to form an opening in the barrier layer to expose the semiconductor material layer, wherein the opening includes a plurality of sub-openings, and a portion of the barrier layer located between the sub-openings is not removed but is formed as an isolation barrier wall structure located between the sub-openings; forming a plurality of sub-metal electrodes in the plurality of sub-openings respectively, wherein the sub-metal electrodes are in direct contact with the semiconductor material layer to form a Schottky diode; A conductive interconnection layer is formed on the plurality of sub-metal electrodes and the barrier layer that has not been removed, and the sub-metal electrodes are conductively connected through the conductive interconnection layer.

2. The method for preparing a Schottky diode according to claim 1, characterized in that: In a direction perpendicular to the semiconductor material layer, the projections of the plurality of sub-metal electrodes are in the form of inner and outer nested rings; or, In the direction perpendicular to the semiconductor material layer, except for the innermost sub-metal electrode, the projections of the other sub-metal electrodes are in the form of inner-and-outer nested rings, and the projection of the next innermost sub-metal electrode surrounds the projection of the innermost sub-metal electrode.

3. The method for preparing a Schottky diode according to claim 2, characterized in that: The ring width of the sub-metal electrode projected in a ring shape ranges from 0.15 μm to 0.25 μm; The distance between two adjacent metal electrodes ranges from 0.2 μm to 0.3 μm.

4. The method for preparing a Schottky diode according to claim 1, characterized in that: After etching the barrier layer, the method further comprises: Continue etching the semiconductor material layer downward along the plurality of sub-openings to form a plurality of sub-grooves in the semiconductor material layer; The bottom of the sub-metal electrode is formed in the sub-groove, and the sub-metal electrode is in direct contact with the semiconductor material layer at the sidewall and bottom wall of the sub-groove.

5. The method for preparing a Schottky diode according to claim 4, characterized in that: The depth of the sub-groove is equal to half the width of the isolation retaining wall structure.

6. A Schottky diode, characterized in that: include: a semiconductor material layer; A plurality of sub-metal electrodes, located on the semiconductor material layer and directly contacting the semiconductor material layer to form a Schottky diode; An isolation retaining wall structure is located between two adjacent sub-metal electrodes; The conductive interconnection layer is located on the plurality of sub-metal electrodes and the isolation retaining wall structure, and the sub-metal electrodes are conductively connected through the conductive interconnection layer.

7. The Schottky diode according to claim 6, characterized in that: In a direction perpendicular to the semiconductor material layer, the projections of the plurality of sub-metal electrodes are in the form of inner and outer nested rings; or, In the direction perpendicular to the semiconductor material layer, except for the innermost sub-metal electrode, the projections of the other sub-metal electrodes are in the form of inner-and-outer nested rings, and the projection of the next innermost sub-metal electrode surrounds the projection of the innermost sub-metal electrode.

8. The Schottky diode according to claim 7, characterized in that: The ring width of the sub-metal electrode projected in a ring shape ranges from 0.15 μm to 0.25 μm; The distance between two adjacent metal electrodes ranges from 0.2 μm to 0.3 μm.

9. The Schottky diode according to claim 6, characterized in that: A plurality of sub-grooves are provided in the semiconductor material layer, each of the sub-grooves extending from a surface of the semiconductor material layer facing the sub-metal electrode to the interior of the semiconductor material layer; The bottom of the sub-metal electrode is located in the sub-groove, the sub-metal electrode is in direct contact with the semiconductor material layer at the side wall and the bottom wall of the sub-groove, and the top of the sub-metal electrode protrudes from the surface of the semiconductor material layer.

10. The Schottky diode according to claim 9, characterized in that: The depth of the sub-groove is equal to half the width of the isolation retaining wall structure.

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