Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and relates to the technical field of semiconductors, and the semiconductor device comprises a semiconductor body, a channel layer, a gate structure, a source electrode and a drain electrode. The channel layer is arranged on the first surface and is in electric contact with the well region in the semiconductor body, the channel layer comprises a two-dimensional semiconductor material, the band gap range of the material is 0.28 eV-4. 0eV, and the electron mobility is greater than or equal to 100cm < 2 > / Vs. The gate structure is disposed on a side of the channel layer away from the semiconductor body. The source electrode is at least partially arranged on the first surface and is in electric contact with the channel layer. The drain electrode is arranged on the second surface. The channel layer is not limited by lattice matching, a high-temperature processing technology is not needed, the source electrode and the channel layer are in direct electric contact to form ohmic contact, a heavily doped region does not need to be formed, the device has high mobility, the structure is simpler, the production technology is simplified, the device quality is improved, and the purposes of reducing cost and improving efficiency are achieved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] As a typical third-generation wide bandgap semiconductor material, silicon carbide has excellent properties such as high critical breakdown electric field, wide bandgap, high thermal conductivity and high electron saturation drift velocity, but it also has a more obvious disadvantage, namely poor mobility. How to improve the mobility of semiconductor devices is the key research direction in this field. Summary of the invention

[0003] Embodiments of the present application provide a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, which are used to improve the mobility of the semiconductor device.

[0004] To achieve the above objectives, the embodiments of the present application provide the following technical solutions: In a first aspect, a semiconductor device is provided, the semiconductor device comprising a semiconductor body, a channel layer, a gate structure, a source and a drain. The semiconductor body is set to a first conductivity type, including a first surface and a second surface opposite to each other, and the semiconductor body also includes a well region set to a second conductivity type, and the well region is arranged on the first surface. The channel layer is arranged on the first surface and is in electrical contact with the well region, and the channel layer comprises a two-dimensional semiconductor material, the band gap range of the material is 0.28eV~4.0eV, and the electron mobility is greater than or equal to 100cm 2 / Vs. The gate structure is disposed on a side of the channel layer away from the semiconductor body. The source electrode is at least partially disposed on the first surface and is in electrical contact with the channel layer. The drain electrode is disposed on the second surface.

[0005] In some embodiments, the material of the channel layer includes at least one of two-dimensional black phosphorus, two-dimensional indium arsenide, bismuth selenide oxide, bismuth oxyselenite, palladium diselenide, and indium selenide.

[0006] In some embodiments, a portion of the source is disposed on the first surface, and another portion of the source is disposed between the channel layer and the gate structure.

[0007] In some embodiments, the gate structure includes a first gate conductive layer and a second gate conductive layer that are stacked, the second gate conductive layer is disposed on a side of the first gate conductive layer away from the semiconductor body, and a material of the second gate conductive layer includes graphene.

[0008] In some embodiments, the material of the source electrode includes graphene, and / or the material of the drain electrode includes graphene.

[0009] In a second aspect, the present application further provides a method for preparing a semiconductor device, comprising the following steps S10 to S50: Step S10: forming a well region in a semiconductor body, wherein the semiconductor body is set to a first conductivity type and includes a first surface and a second surface opposite to each other, and the well region is set to a second conductivity type and is located on the first surface.

[0010] Step S20: forming a channel layer on the first surface, the channel layer being in electrical contact with the well region, the channel layer comprising a two-dimensional semiconductor material, the band gap of the material being in the range of 0.28 eV to 4.0 eV, and the electron mobility being greater than or equal to 100 cm 2 / Vs.

[0011] Step S30: forming a source electrode, wherein at least a portion of the source electrode is located on the first surface and is in electrical contact with the channel layer.

[0012] Step S40: forming a gate structure, wherein the gate structure is located on a side of the channel layer away from the semiconductor body.

[0013] Step S50: forming a drain electrode on the second surface.

[0014] In some embodiments, forming the channel layer on the first surface includes: transferring the channel layer to the first surface using a dry transfer process or a wet transfer process.

[0015] On the other hand, an embodiment of the present application further provides a power module, which includes a substrate and a semiconductor device as described in any of the above embodiments, wherein the substrate is used to carry the semiconductor device.

[0016] In another aspect, an embodiment of the present application further provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and a semiconductor device as in any of the above embodiments, and the semiconductor device is electrically connected to the circuit board.

[0017] On the other hand, an embodiment of the present application also provides a vehicle, which includes a load and a power conversion circuit as described in the above embodiment, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0018] In the embodiment provided in the present application, the semiconductor device includes a semiconductor body, a channel layer, a gate structure, a source electrode and a drain electrode, wherein the channel layer directly adopts an electron mobility greater than or equal to 100cm 2 / Vs material formation, two-dimensional semiconductor materials are not restricted by lattice matching and do not need to undergo high-temperature processing, thus ensuring device dimensional stability, surface roughness and device consistency. In addition, the band gap range of the channel layer material is 0.28eV~4.0eV, with good voltage resistance and thermal stability.

[0019] In the embodiments provided in the present application, the source electrode and the channel layer are in direct electrical contact to form an ohmic contact, and there is no need to form a heavily doped region. The device structure is simpler, which is conducive to optimizing the production process steps.

[0020] That is, the semiconductor device provided in the embodiment of the present application not only has a higher mobility, but also has a simpler structure, which is conducive to simplifying the production process, improving device quality, and achieving the goal of reducing costs and increasing efficiency.

[0021] In addition, in order to prepare the semiconductor device, the present application also provides a preparation method, which has a simple process and is easy to operate, and can be prepared using existing relatively mature processes, and the production process is low in difficulty. That is, the preparation method provided in the embodiment of the present application is more concise, the process steps are optimized, the preparation cost is lower, and it is conducive to the simple and efficient preparation of high-mobility semiconductor devices.

[0022] The above-mentioned power module, power conversion circuit and vehicle have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above-mentioned embodiments, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application; Figure 2 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application; Figure 3~Figure 9 A diagram of each step of preparing a semiconductor device provided in an embodiment of the present application; Fig.10 A schematic diagram of the structure of a power module provided in an embodiment of the present application; Fig.11 A schematic diagram of the structure of a power conversion circuit provided in an embodiment of the present application; Fig.12 A schematic diagram of the structure of a vehicle provided in an embodiment of the present application.

[0024] Wherein, the accompanying drawings are marked as follows: 10-semiconductor device; 11-semiconductor body; 12-channel layer; 13-gate structure 13; 14-source; 15-drain; P1-first surface; P2-second surface; 16-well region; 17-gate insulating layer; 131-first gate conductive layer 131; 132-second gate conductive layer; 200-power module; 201-substrate; 300-power conversion circuit; 301-circuit board; 400-vehicle; 401-load. DETAILED DESCRIPTION

[0025] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0026] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0027] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0028] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0029] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0030] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0031] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0032] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0033] As mentioned in the background art, how to improve the mobility of semiconductor devices is a key research direction in this field.

[0034] At present, in order to improve the mobility of devices, the industry mainly adopts boron doping annealing technology and the method of optimizing the trench structure. However, in the boron doping annealing technology, the high temperature annealing temperature is usually 1700℃, and the silicon carbide material will evaporate, thus affecting the dimensional stability and surface roughness of the device. In addition, the annealing uniformity is difficult to control, which easily affects the consistency of the device. In addition, the method of optimizing the trench structure will cause the device to have a right angle (or obtuse angle) structure at the bottom of the groove angle, which will intensify the local electric field and make the oxide layer easy to break down.

[0035] To avoid the above problems, the present application embodiment provides a semiconductor device 10, such as Figure 1 As shown, Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application.

[0036] The semiconductor device 10 includes a semiconductor body 11, a channel layer 12, a gate structure 13, a source 14 and a drain 15. The semiconductor body 11 is set to a first conductivity type, including a first surface P1 and a second surface P2 opposite to each other, and the semiconductor body 11 also includes a well region 16 set to a second conductivity type, and the well region 16 is arranged on the first surface P1. Exemplarily, the first conductivity type may be an N-type conductivity type, and the second conductivity type may be a P-type conductivity type.

[0037] The channel layer 12 is disposed on the first surface P1 and is in electrical contact with the well region 16. The channel layer 12 includes a two-dimensional semiconductor material. The band gap of the material ranges from 0.28 eV to 4.0 eV, such as 0.28 eV, 0.30 eV, 0.80 eV, 1.2 eV, ... 4.0 eV, etc., and the electron mobility is greater than or equal to 100 cm 2 / Vs, e.g. 100cm 2 / Vs, 130cm 2 / Vs, 150cm 2 / Vs, 200cm 2 / Vs, etc. The gate structure 13 is disposed on a side of the channel layer 12 away from the semiconductor body 11. The source 14 is at least partially disposed on the first surface P1 and is in electrical contact with the channel layer 12. The drain 15 is disposed on the second surface P2.

[0038] According to relevant research, boron doping annealing technology can increase the device mobility to 100cm 2 / Vs, and in the embodiment of the present application, the electron mobility is greater than or equal to 100cm 2 / Vs material forms the channel layer 12. The two-dimensional semiconductor material of the channel layer 12 is not restricted by lattice matching and does not need to undergo a high-temperature treatment process, thereby ensuring device dimensional stability, surface roughness, and device consistency. In addition, the band gap range of the material of the channel layer 12 is 0.28eV~4.0eV, and has good voltage resistance and thermal stability.

[0039] In addition, in the embodiment of the present application, the source electrode 14 is in direct electrical contact with the channel layer 12 to form an ohmic contact, and there is no need to form a heavily doped region. The device structure is simpler, which is conducive to optimizing the production process steps.

[0040] That is, the semiconductor device 10 provided in the embodiment of the present application not only has a higher mobility, but also has a simpler structure, which is conducive to simplifying the production process, improving device quality, and achieving the goal of reducing costs and increasing efficiency.

[0041] Exemplarily, in some embodiments, the material of the channel layer 12 includes at least one of two-dimensional black phosphorus, two-dimensional indium arsenide, bismuth selenide oxide, bismuth oxyselenite, palladium diselenide, and indium selenide.

[0042] All of the above materials are two-dimensional semiconductor materials, and all have high electron mobility, adjustable band gap and good electronic properties. For example, the band gap of two-dimensional black phosphorus is about 1.7eV, and the electron mobility is about 1000cm 2 / Vs. The band gap of two-dimensional indium arsenide (InAs) is about 1.59 eV, and the electron mobility is about 490 cm 2 / Vs. The band gap of a single layer of bismuth oxide selenide (Bi2O2Se) is about 0.8 eV, and the electron mobility is about 450 cm 2 / Vs. The band gap of a single layer of bismuth selenite (Bi2SeO5) is about 3.9 eV, and the electron mobility is about 300 cm 2 / Vs. The band gap of a single layer of palladium diselenide (PdSe2) is about 1.37 eV, and the electron mobility is about 130 cm 2 / Vs. The band gap of a single layer of indium selenide (InSe) is about 2.11 eV, and the electron mobility is about 1000 cm 2 / Vs.

[0043] Exemplarily, taking two-dimensional black phosphorus as an example, when the first conductivity type of the semiconductor body 11 is N-type conductivity type and the second conductivity type of the well region 16 is P-type conductivity type, the two-dimensional black phosphorus is P-type two-dimensional black phosphorus.

[0044] The two-dimensional black phosphorus semiconductor material has the advantages of van der Waals forces between layers, high mobility, ultra-thin nanometer thickness, no need to consider lattice matching restrictions, innovative integration, etc. It is easy to process, conducive to application in the preparation process, and can improve the mobility of the semiconductor device 10.

[0045] The same goes for other materials, which will not be elaborated here one by one.

[0046] In some embodiments, Figure 1 As shown, a portion of the source 14 is disposed on the first surface P1 , and another portion is disposed between the channel layer 12 and the gate structure 13 .

[0047] For example, Figure 1 As shown, the semiconductor device 10 further includes a gate insulating layer 17. A portion of the source 14 is disposed on the first surface P1 and electrically contacts the well region 16, and another portion is disposed between the channel layer 12 and the gate structure 13 and electrically contacts the channel layer 12. The gate insulating layer 17 is located between the source 14 and the gate structure 13 to prevent the source 14 and the gate structure 13 from short-circuiting.

[0048] The gate structure 13 is used to control the conduction state of the channel. When the device is turned on, the current flows from the source 14 through the channel layer 12 , the well region 16 and the JFET region (or the epitaxial layer in the semiconductor body 11 ) and finally reaches the drain 15 .

[0049] In some embodiments, Figure 1 As shown, the gate structure 13 includes a first gate conductive layer 131 and a second gate conductive layer 132 which are stacked. The second gate conductive layer 132 is disposed on a side of the first gate conductive layer 131 away from the semiconductor body 11 , and the material of the second gate conductive layer 132 includes graphene.

[0050] Exemplarily, the material of the first gate conductive layer 131 includes polysilicon, and the material of the gate insulating layer 17 includes silicon dioxide. The contact surface defects between polysilicon and silicon dioxide are relatively few, which is beneficial to improving device performance.

[0051] Graphene with atomic layer thickness is thin and light, has high strength, and has good thermal conductivity and electrical conductivity. The material of the second gate conductive layer 132 includes graphene, so that the semiconductor device 10 has good heat dissipation and is easy to integrate.

[0052] In addition, the van der Waals force of graphene allows it to be combined with any substrate without being restricted by lattice matching, which is conducive to the simplification of the preparation process, that is, good electrical contact can be formed between the second gate conductive layer 132 and the first gate conductive layer 131, and the preparation process corresponding to the gate structure 13 is relatively simple.

[0053] In some embodiments, the material of the source electrode 14 includes graphene, and / or the material of the drain electrode 15 includes graphene.

[0054] Two-dimensional graphene materials have excellent mechanical properties, and their thickness can reach the thickness of an atomic layer. They have good thermal conductivity and electrical conductivity. The van der Waals force of graphene enables it to be combined with any substrate without being restricted by lattice matching. Based on this, the source 14 and / or the drain 15 are formed using graphene materials. The corresponding preparation process is relatively simple and is beneficial to improving the heat dissipation and high temperature resistance of the semiconductor device 10.

[0055] Since the interaction between graphene and two-dimensional semiconductor materials is weak, it is beneficial to reduce the Fermi pinning effect and form a good ohmic contact. The source 14 and the channel layer 12 are in direct electrical contact to form an ohmic contact. There is no need to form a heavily doped region, and the device structure is simpler, which is beneficial to optimize the production process steps and achieve the goal of reducing costs and increasing efficiency.

[0056] For example, in some embodiments, Figure 1 As shown, the material of the channel layer 12 of the semiconductor device 10 includes two-dimensional black phosphorus, the material of the first gate conductive layer 131 in the gate structure 13 includes polysilicon, the material of the second gate conductive layer 132 includes graphene, the material of the source 14 includes graphene, and the material of the drain 15 includes graphene, that is, graphene is used as the electrode of the semiconductor device 10 and two-dimensional black phosphorus is used as the transmission channel.

[0057] Graphene with atomic layer thickness is thin and light, and has high strength, good thermal conductivity and electrical conductivity, which makes the device have good heat dissipation and easy integration. Two-dimensional black phosphorus has excellent properties such as high mobility and interlayer van der Waals force. As a channel material, it is not restricted by lattice matching and has integration diversity, making it suitable for ultrafast response devices. At the same time, the interaction between graphene and two-dimensional black phosphorus materials is weak, which greatly reduces the Fermi pinning effect and forms a good ohmic contact with the two-dimensional semiconductor channel. No additional injection process is required to form a heavily doped region to achieve ohmic contact between the metal and the semiconductor, which is conducive to optimizing the process steps and achieving the goal of reducing costs and increasing efficiency.

[0058] Based on this, the semiconductor device 10 has the characteristics of high temperature resistance and high mobility, and has a simple structure. The corresponding preparation process is simplified, that is, a high-mobility and high-temperature resistant semiconductor device can be prepared simply and efficiently at a lower cost.

[0059] In a second aspect, the present application also provides a method for preparing a semiconductor device, such as Figure 2 As shown, Figure 2 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application, Figure 3~Figure 9 A diagram of the various steps of preparing a semiconductor device provided in an embodiment of the present application.

[0060] The preparation method comprises the following steps S10 to S50: Step S10: Figure 3 As shown, a well region 16 is formed in the semiconductor body 11 , wherein the semiconductor body 11 is set to a first conductivity type and includes a first surface P1 and a second surface P2 opposite to each other, and the well region 16 is set to a second conductivity type and is located at the first surface P1 .

[0061] Exemplarily, a mask may be formed and patterned, and ions may be implanted into the semiconductor body 11 under the action of the mask to form the well region 16 .

[0062] Step S20: Figure 4 As shown, a channel layer 12 is formed on the first surface P1, the channel layer 12 is in electrical contact with the well region 16, and the channel layer 12 includes a two-dimensional semiconductor material, the band gap range of the material is 0.28eV~4.0eV, and the electron mobility is greater than or equal to 100cm 2 / Vs.

[0063] Illustratively, in some embodiments, forming the channel layer 12 on the first surface P1 includes: transferring the channel layer 12 to the first surface P1 by using a dry transfer process or a wet transfer process.

[0064] For example, in some embodiments, the material of the channel layer 12 includes at least one of two-dimensional black phosphorus, two-dimensional indium arsenide, bismuth selenide oxide, bismuth oxyselenite, palladium diselenide, indium selenide, etc. Taking two-dimensional black phosphorus as an example, since the two-dimensional black phosphorus layers are acted upon by van der Waals forces, they can be transferred to the semiconductor body 11 through a dry transfer process or a wet transfer process without the need for high-temperature treatment processes, mask preparation and removal, and ion implantation. The preparation process is simple, which is beneficial to ensuring device size stability, surface roughness, and device consistency.

[0065] Step S30: Figure 5 As shown, a source electrode 14 is formed, and at least a portion of the source electrode 14 is located on the first surface P1 and is in electrical contact with the channel layer 12 .

[0066] For example, Figure 5 As shown, a portion of the source electrode 14 is disposed on the first surface P1 , and another portion is disposed on the channel layer 12 . The material of the source electrode 14 includes graphene.

[0067] In some embodiments, the source electrode 14 may be formed by a chemical vapor deposition process to form a whole layer of graphene, and then patterned to obtain the desired source electrode 14 .

[0068] In some other embodiments, the graphene material of the source electrode 14 may be transferred to the first surface P1 through a wet transfer process and electrically contact the channel layer 12 .

[0069] The van der Waals force of graphene enables it to bond to any substrate without being restricted by lattice matching. Therefore, graphene electrodes can be prepared through only a wet transfer process step. There is no need for mask preparation and removal, photolithography and other process steps, and the preparation method is relatively simple.

[0070] Taking the case where the material of the channel layer 12 includes two-dimensional black phosphorus and the material of the source electrode 14 includes graphene as an example, the two-dimensional black phosphorus and the graphene can directly form an ohmic contact, and there is no need for the step of multiple ion implantation to form a heavily doped region in the related art. That is, in the embodiment of the present application, the source electrode 14 and the channel layer 12 can directly make electrical contact to form an ohmic contact, and multiple ion implantation is no longer required, so the process steps are simplified.

[0071] Step S40: Figure 6~Figure 8 As shown, a gate structure 13 is formed, and the gate structure 13 is located on a side of the channel layer 12 away from the semiconductor body 11 .

[0072] like Figure 6As shown, after the source 14 is formed, a gate insulating layer 17 is first formed. On the one hand, the gate insulating layer 17 can provide a flat surface for the subsequent preparation of the gate structure 13. On the other hand, the gate insulating layer 17 can play a protective and isolating role to prevent the gate structure 13 from being electrically connected to the source 14 and causing a short circuit.

[0073] Afterwards, if Figure 7 As shown, a first gate conductive layer 131 is formed, and the material of the first gate conductive layer 131 includes polysilicon.

[0074] Then, if Figure 8 As shown, a second gate conductive layer 132 is formed. In some embodiments, the material of the second gate conductive layer 132 includes graphene. For example, the graphene material is transferred to a side of the first gate conductive layer 131 away from the semiconductor body 11 through a wet transfer process.

[0075] The first gate conductive layer 131 and the second gate conductive layer 132 which are stacked together form a gate structure 13 .

[0076] Step S50: Fig. 9 As shown, a drain electrode 15 is formed on the second surface P2.

[0077] In some embodiments, the material of the drain 15 includes graphene. Exemplarily, the graphene material can be transferred to the second surface P2 by a wet transfer process to form the drain 15 .

[0078] At this point, the semiconductor device 10 is completed.

[0079] The above preparation method has simple process and is easy to operate. It can be prepared using existing relatively mature processes and has low production process difficulty.

[0080] Two-dimensional semiconductor materials with high mobility, such as two-dimensional black phosphorus, have excellent performance. As channel materials, they are not restricted by lattice matching, have integrated diversity, and are suitable for ultrafast response devices. In the embodiment of the present application, two-dimensional semiconductor materials with high mobility, such as two-dimensional black phosphorus, are transferred to the semiconductor body 11 through a dry transfer process or a wet transfer process to form a channel layer 12 to prepare a high-mobility semiconductor device 10. The process is simple and highly operable, and no high-temperature annealing or ion doping processes are required, which is beneficial to improving the dimensional stability, surface roughness, and device consistency of the device. In addition, there is no need to perform processes such as trench etching, which is beneficial to improving the uniformity of the electric field and avoiding premature breakdown of the device.

[0081] In addition, graphene with atomic layer thickness is light, thin and strong, and has good thermal conductivity and electrical conductivity, which makes the device have good heat dissipation and easy integration. In the embodiments of the present application, graphene can be combined with any substrate and is not restricted by lattice matching. Graphene materials are used to prepare gate source electrodes and drain electrodes. The relevant electrodes can be prepared through wet transfer process steps, without the need to prepare a mask or perform processes such as photolithography, and the preparation method is simpler.

[0082] The interaction between graphene and two-dimensional black phosphorus material is weak, which greatly reduces the Fermi pinning effect and can form a good ohmic contact. That is, in the embodiment of the present application, no additional injection process is required to form a heavily doped region to achieve ohmic contact between the metal and the semiconductor material, thereby optimizing the process steps and achieving the purpose of reducing costs and increasing efficiency.

[0083] That is, the preparation method provided in the embodiment of the present application is simpler, the process steps are optimized, and the preparation cost is lower, which is conducive to the simple and efficient preparation of a semiconductor device 10 with high mobility and high temperature resistance.

[0084] On the other hand, an embodiment of the present application further provides a power module, Fig.10 A schematic diagram of the structure of a power module provided in an embodiment of the present application.

[0085] like Fig.10 As shown, the power module 200 includes a substrate 201 and the semiconductor device 10 in any of the above embodiments, and the substrate 201 is used to carry the semiconductor device 10 .

[0086] Exemplarily, the power module 200 can be used as one of a power amplifier, a power converter, a power controller, a power management module, or a power regulator. The power amplifier is used to amplify the power of an electrical signal. The power converter is used to convert electrical energy from one form to another form. For example, the power converter can be an AC / DC converter or a DC / DC converter. The power controller is used to control the device of power flow. The power management module is used to manage the power supply to ensure that the power is stably and efficiently distributed to different parts of the electronic device. The power regulator is used to adjust the power output to meet the needs of a specific application.

[0087] On the other hand, an embodiment of the present application further provides a power conversion circuit, Fig.11 A schematic diagram of the structure of a power conversion circuit provided in an embodiment of the present application.

[0088] like Fig.11 As shown, the power conversion circuit 300 includes a circuit board 301 and a semiconductor device 10 in any of the above embodiments. The semiconductor device 10 is electrically connected to the circuit board 301. The power conversion circuit 300 can be used for current conversion, voltage conversion or power factor correction.

[0089] Exemplarily, the power conversion circuit 300 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current into direct current, the AC / AC converter is used to convert alternating current into alternating current, the DC / DC converter is used to convert direct current into direct current, the DC / AC inverter is used to convert direct current into alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce the harmonic pollution of the power grid.

[0090] On the other hand, an embodiment of the present application further provides a vehicle, Fig.12 A schematic diagram of the structure of a vehicle provided in an embodiment of the present application.

[0091] like Fig.12 As shown, the vehicle 400 includes a load 401 and the power conversion circuit 300 in the above embodiment, and the power conversion circuit 300 is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load 401 to power the load 401.

[0092] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body is set to a first conductivity type, comprising a first surface and a second surface opposite to each other; the semiconductor body further comprises a well region set to a second conductivity type, the well region being arranged on the first surface; A channel layer is disposed on the first surface and is in electrical contact with the well region; the channel layer comprises a two-dimensional semiconductor material, the band gap of the material ranges from 0.28 eV to 4.0 eV, and the electron mobility is greater than or equal to 100 cm 2 / Vs; A gate structure, disposed on a side of the channel layer away from the semiconductor body; a source electrode, at least partially disposed on the first surface and in electrical contact with the channel layer; The drain is disposed on the second surface.

2. The semiconductor device according to claim 1, wherein: The material of the channel layer includes at least one of two-dimensional black phosphorus, two-dimensional indium arsenide, bismuth selenide oxide, bismuth oxyselenite, palladium diselenide, and indium selenide.

3. The semiconductor device according to claim 1, wherein: A portion of the source is disposed on the first surface, and another portion is disposed between the channel layer and the gate structure.

4. The semiconductor device according to claim 1, wherein: The gate structure comprises a first gate conductive layer and a second gate conductive layer which are stacked, wherein the second gate conductive layer is arranged on a side of the first gate conductive layer away from the semiconductor body; The material of the second gate conductive layer includes graphene.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that The material of the source electrode includes graphene, and / or the material of the drain electrode includes graphene.

6. A method for preparing a semiconductor device, characterized in that: include: forming a well region in a semiconductor body, wherein the semiconductor body is set to a first conductivity type and comprises a first surface and a second surface opposite to each other; the well region is set to a second conductivity type and is located on the first surface; A channel layer is formed on the first surface, the channel layer being in electrical contact with the well region; the band gap of the material of the channel layer is in the range of 0.28 eV to 4.0 eV, and the electron mobility is greater than or equal to 100 cm 2 / Vs; forming a source electrode, wherein at least a portion of the source electrode is located on the first surface and is in electrical contact with the channel layer; forming a gate structure, wherein the gate structure is located on a side of the channel layer away from the semiconductor body; A drain electrode is formed on the second surface.

7. The preparation method according to claim 6, characterized in that: Forming a channel layer on the first surface includes: The channel layer is transferred onto the first surface by using a dry transfer process or a wet transfer process.

8. A power module, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 5; A substrate is used to carry the semiconductor device.

9. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is electrically connected to the circuit board.

10. A vehicle, characterized in that: include: A load and a power conversion circuit as claimed in claim 9, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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