Semiconductor device

Abstract

Embodiments relate to a semiconductor device. The leakage current can be reduced. The semiconductor device includes: a first electrode; a semiconductor portion provided on the first electrode; an insulating member disposed within the semiconductor portion; a first insulating film provided on a portion of the semiconductor portion; a second insulating film provided on the other portion of the semiconductor portion and thicker than the first insulating film; a second electrode provided in the insulating member; a first wiring that is connected to the second electrode, is provided on the insulating member and the second insulating film, and is not provided on the first insulating film; and a third electrode provided on the semiconductor portion, on the insulating member, and on the first insulating film.

Description

[0001] Related Application:

[0002] This application claims priority from Japanese Patent Application No. 2023-158386 (filing date: September 22, 2023) as a prior application. The present application incorporates the entire contents of the prior application by reference. Technical Field

[0003] Embodiments relate to a semiconductor device. Background Art

[0004] In a vertical power control semiconductor device, a gate electrode is sometimes disposed in a trench. In such a semiconductor device, it is desired to reduce leakage current in an off state. Summary of the invention

[0005] The semiconductor device involved in the embodiment comprises: a first electrode; a semiconductor part, which is arranged on the first electrode; an insulating part, which is arranged in the semiconductor part; a first insulating film, which is arranged on a part of the semiconductor part; a second insulating film, which is arranged on another part of the semiconductor part and is thicker than the first insulating film; a second electrode, which is arranged in the insulating part; a first wiring, which is connected to the second electrode and is arranged on the insulating part and on the second insulating film, but not on the first insulating film; and a third electrode, which is arranged on the semiconductor part, the insulating part and on the first insulating film.

[0006] According to this embodiment, a semiconductor device capable of reducing leakage current can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a plan view showing a semiconductor device according to an embodiment.

[0008] Figure 2 yes Figure 1 A cross-sectional view along line AA' is shown.

[0009] Figure 3 yes Figure 1 A cross-sectional view taken along line BB' is shown.

[0010] Figure 4 yes Figure 1 A cross-sectional view taken along line CC' is shown.

[0011] Figure 5 yes Figure 1 A cross-sectional view taken along line DD' is shown.

[0012] Figure 6 yes Figure 1 A cross-sectional view along line EE' is shown.

[0013] Figure 7 yes Figure 1 A cross-sectional view along line FF' is shown.

[0014] Figure 8 yes Figure 1 A cross-sectional view taken along line G-G' is shown.

[0015] Fig. 9 It is a plan view showing a semiconductor device according to a comparative example.

[0016] Fig.10 yes Fig. 9 A cross-sectional view taken along line H-H' is shown.

[0017] Fig.11 yes Fig. 9 A cross-sectional view taken along line II' is shown. DETAILED DESCRIPTION

[0018] <Implementation Method>

[0019] Figure 1 It is a plan view showing a semiconductor device according to this embodiment.

[0020] Figure 2 yes Figure 1 A cross-sectional view along line AA' is shown.

[0021] Figure 3 yes Figure 1 A cross-sectional view taken along line BB' is shown.

[0022] Figure 4 yes Figure 1 A cross-sectional view taken along line CC' is shown.

[0023] Figure 5 yes Figure 1 A cross-sectional view taken along line DD' is shown.

[0024] Figure 6 yes Figure 1 A cross-sectional view along line EE' is shown.

[0025] Figure 7 yes Figure 1 A cross-sectional view along line FF' is shown.

[0026] Figure 8 yes Figure 1 A cross-sectional view taken along line G-G' is shown.

[0027] In addition, each figure is schematic, and is appropriately emphasized or simplified. In addition, even when the same component is shown, the position or size ratio is not necessarily exactly the same between the figures.

[0028] like Figures 1 to 8 As shown, in the semiconductor device 1 according to the present embodiment, a cell region Rc, a lead-out region Rd, and an end region Re are provided. The end region Re is arranged in a frame shape along the edge 1e of the semiconductor device 1. The cell region Rc is surrounded by the end region Re. The lead-out region Rd is arranged in a part of the region between the end region Re and the cell region Rc.

[0029] In the semiconductor device 1, there are provided a drain electrode 11 (first electrode), a semiconductor portion 20, a gate electrode 12 (second electrode), an FP (field plate) electrode 13 (fourth electrode), a source electrode 14 (third electrode), a gate lead-out wiring 15 (first wiring), an FP lead-out wiring 16, an end conductive film 17, a gate wiring 18, an FP wiring 19, an insulating component 31, an insulating thin film 32 (first insulating film), an insulating thick film 33 (second insulating film), and an interlayer insulating film 34.

[0030] In addition, Figure 1 , the semiconductor portion 20, the gate electrode 12, the FP electrode 13, the gate lead wiring 15, the FP lead wiring 16, the terminal conductive film 17, the insulating member 31, the insulating thin film 32 and the insulating thick film 33 are shown, while the source electrode 14, the gate wiring 18, the FP wiring 19 and the interlayer insulating film 34 are omitted. Figure 1 In FIG. 1 , an edge 1 e of the semiconductor device 1 is present on the left side of the figure, and a region where an end region Re, a lead-out region Rd, and a cell region Rc are arranged is shown toward the right side of the figure.

[0031] The semiconductor portion 20 is disposed on the drain electrode 11. The semiconductor portion 20 is made of a semiconductor material, such as silicon (Si), and is formed of, for example, single crystal silicon. In the semiconductor portion 20, impurities are selectively introduced into each portion to define the conductivity type and carrier concentration. The detailed structure of the semiconductor portion 20 will be described later.

[0032] A plurality of insulating members 31 are provided. Each insulating member 31 is arranged in the upper portion of the semiconductor portion 20 in the cell region Rc and the lead-out region Rd, and extends in one direction (X direction described later). The upper portion of the semiconductor portion 20 is arranged between adjacent insulating members 31. In the Y direction described later, the plurality of insulating members 31 are arranged in parallel with each other, for example, periodically.

[0033] The insulating film 32 is disposed on the insulating member 31 and on the semiconductor portion 20 between the insulating members 31 in the cell region Rc. The insulating film 32 is in contact with the semiconductor portion 20 and the insulating member 31.

[0034] The insulating thick film 33 is arranged on the insulating member 31 and on the semiconductor portion 20 between the insulating members 31 in the lead-out region Rd. The insulating thick film 33 is in contact with the semiconductor portion 20, the insulating member 31, and the insulating thin film 32. The insulating thick film 33 is arranged on the side of the end region Re with respect to the insulating thin film 32. The insulating thick film 33 is thicker than the insulating thin film 32, but thinner than the insulating member 31.

[0035] The insulating member 31, the insulating thin film 32 and the insulating thick film 33 are made of an insulating material, such as silicon oxide (SiO). Figure 4 As shown in FIG. 1 , on the semiconductor portion 20, the lower surface of the insulating thick film 33 is located at substantially the same position as the lower surface of the insulating thin film 32. On the other hand, the upper surface of the insulating thick film 33 is located higher than the upper surface of the insulating thin film 32. Therefore, a step 35 is formed at the boundary between the upper surface of the insulating thin film 32 and the upper surface of the insulating thick film 33.

[0036] Hereinafter, in this specification, for the sake of convenience, an XYZ orthogonal coordinate system is used. The direction in which the insulating member 31 extends is set as the "X direction" (first direction), the direction in which the plurality of insulating members 31 are arranged is set as the "Y direction" (second direction), and the direction from the drain electrode 11 toward the source electrode 14 is set as the "Z direction" (third direction). In addition, the Z direction is also referred to as "upward", and the opposite direction is also referred to as "downward", but this expression is also for convenience and has nothing to do with the direction of gravity.

[0037] The gate electrode 12 and the FP electrode 13 are arranged in the insulating member 31, and extend in the X direction respectively. In each insulating member 31, the gate electrode 12 and the FP electrode 13 are arranged in the Y direction, and one FP electrode 13 is arranged between two gate electrodes 12. The FP electrode 13 is insulated from the gate electrode 12 by the insulating member 31. The lower end of the FP electrode 13 is located below the lower end of the gate electrode 12. In addition, the end of the FP electrode 13 in the X direction is located on the side of the end region Re than the end of the gate electrode 12 in the X direction. The gate electrode 12 and the FP electrode 13 are made of a conductive material, for example, polysilicon containing impurities.

[0038] The gate lead-out wiring 15 is arranged on the insulating component 31 and the insulating thick film 33 in the lead-out region Rd. The gate lead-out wiring 15 is not arranged on the insulating thin film 32. The gate lead-out wiring 15 is made of a conductive material, for example, polysilicon containing impurities. The gate lead-out wiring 15 is connected to at least one end of the gate electrode 12 in the X direction. In addition, in this specification, "connection" means electrical connection. Specifically, the lower surface of the portion of the gate lead-out wiring 15 on the side of the cell region Rc is integrated with the upper surface of the portion of the gate electrode 12 on the side of the end region Re.

[0039] The FP lead-out wiring 16 is arranged on the insulating member 31 and the insulating thick film 33 in the lead-out region Rd. The FP lead-out wiring 16 is not arranged on the insulating thin film 32. The FP lead-out wiring 16 is arranged on the side closer to the end region Re than the gate lead-out wiring 15, and is separated from the gate lead-out wiring 15. The FP lead-out wiring 16 is made of a conductive material, for example, polysilicon containing impurities. The FP lead-out wiring 16 is connected to the X-direction end of the FP electrode 13. Specifically, the lower surface of the portion of the FP lead-out wiring 16 on the cell region Rc side is integrated with the upper surface of the portion of the FP electrode 13 on the end region Re side.

[0040] The terminal conductive film 17 is disposed on the insulating thick film 33 in a portion of the terminal region Re on the lead-out region Rd side. The terminal conductive film 17 is separated from the FP lead-out wiring 16. The terminal conductive film 17 is made of, for example, polysilicon containing impurities.

[0041] The interlayer insulating film 34 is disposed on the insulating member 31, the insulating thin film 32, and the insulating thick film 33 in the cell region Rc, the lead region Rd, and the portion of the terminal region Re on the lead region Rd side. The interlayer insulating film 34 covers the gate lead wiring 15, the FP lead wiring 16, and the terminal conductive film 17.

[0042] The gate wiring 18 is arranged on the interlayer insulating film 34 in the lead-out region Rd. When viewed from above, the gate wiring 18 is arranged in a region overlapping with the gate lead-out wiring 15, and is connected to the gate lead-out wiring 15 via a gate contact 18a that penetrates the interlayer insulating film 34. The gate lead-out wiring 15 is connected to a gate pad (not shown) arranged on the interlayer insulating film 34. Therefore, the gate electrode 12 is connected to the gate pad via the gate lead-out wiring 15 and the gate wiring 18.

[0043] The FP wiring 19 is arranged on the interlayer insulating film 34 in the lead-out region Rd. The gate wiring 18 is arranged in a region overlapping with the FP lead-out wiring 16 when viewed from above, and is connected to the FP lead-out wiring 16 via a FP contact 19a penetrating the interlayer insulating film 34.

[0044] The source electrode 14 is arranged on the interlayer insulating film 34 in the cell region Rc. Therefore, the source electrode 14 is arranged on the semiconductor portion 20, the insulating member 31, and the insulating film 32. The source electrode 14 is connected to the semiconductor portion 20 via a source contact 14a that penetrates the interlayer insulating film 34. In addition, the source electrode 14 is connected to the FP wiring 19. Thus, the FP electrode 13 is connected to the source electrode 14 via the FP lead-out wiring 16 and the FP wiring 19.

[0045] An insulating protective film (not shown) is provided on the semiconductor portion 20, the interlayer insulating film 34, the gate wiring 18, the FP wiring 19, and the source electrode 14. However, a portion of the source electrode 14 and a portion of the gate pad (not shown) are exposed from the protective film to form an area for external wiring bonding.

[0046] In the semiconductor portion 20 , a drain layer 21 , a drift layer 22 , a base layer 23 , a base contact layer 24 , a source layer 25 , a source contact layer 26 , a terminal p-type layer 28 , and a terminal n-type layer 29 are provided.

[0047] The drain layer 21 is disposed on the entire surface of the drain electrode 11 and is in contact with the drain electrode 11. The conductivity type of the drain layer 21 is n + The drift layer 22 is disposed on the entire surface of the drain layer 21 and is in contact with the drain layer 21. The conductivity type of the drift layer 22 is n - In addition, "n + "Type" indicates that the carrier concentration is higher than that of "n-type". - The “n-type” exhibits a lower carrier concentration than the “n-type”. The same is true for the p-type. The first semiconductor layer is formed by the drain layer 21 and the drift layer 22.

[0048] The base layer 23 is disposed on a portion of the drift layer 22 in the cell region Rc. The base layer 23 is opposed to the gate electrode 12 via the insulating member 31. The conductivity type of the base layer 23 is p-type. The base contact layer 24 is disposed between the base layer 23 and the source electrode 14 and is in contact with the base layer 23 and the source electrode 14. The conductivity type of the base contact layer 24 is p-type. + The base layer 23 is connected to the source contact 14a of the source electrode 14 via the base contact layer 24. When viewed from above, the base layer 23 and the base contact layer 24 are separated from the gate lead-out wiring 15. The base layer 23 and the base contact layer 24 form a second semiconductor layer.

[0049] The source layer 25 is disposed on the base layer 23 in a region in contact with the insulating member 31. The conductivity type of the source layer 25 is n-type. The source contact layer 26 is disposed between two adjacent source layers 25 on the base layer 23. The source contact layer 26 is in contact with the base layer 23 and the source layer 25, and is separated from the insulating member 31. The conductivity type of the source contact layer 26 is n-type. + The upper surface of the source layer 25 and the upper surface of the source contact layer 26 are in contact with the lower surface of the source contact 14a of the source electrode 14. Thus, the source layer 25 and the source contact layer 26 are connected to the source electrode 14. The source layer 25 and the source contact layer 26 form a third semiconductor layer.

[0050] The terminal p-type layer 28 is disposed on the drift layer 22 in the terminal region Re. The conductivity type of the terminal p-type layer 28 is p-type. The terminal n-type layer 29 is disposed on a portion of the terminal p-type layer 28 and is separated from the drift layer 22 via the terminal p-type layer 28. The conductivity type of the terminal n-type layer 29 is n-type. + type.

[0051] Next, the effects of this embodiment will be described.

[0052] In the semiconductor device 1, when a source potential, such as a ground potential, is applied to the source electrode 14 and a drain potential higher than the source potential is applied to the drain electrode 11, if a conduction potential, such as a positive potential, is applied to the gate electrode 12, an inversion layer is formed in a portion of the base layer 23 that is in contact with the insulating member 31, and the semiconductor device 1 is turned on. As a result, current flows between the source and the drain.

[0053] On the other hand, if an off potential such as a ground potential is applied to the gate electrode 12, the inversion layer disappears and the semiconductor device 1 is turned off. As a result, the current between the source and the drain is cut off. At this time, the drain layer 21, the drift layer 22 and the base layer 23 are at the drain potential.

[0054] In the semiconductor device 1, the gate lead-out wiring 15 is separated from the drift layer 22 via the insulating thick film 33 which is thicker than the insulating thin film 32, and is therefore not easily affected by the potential of the drift layer 22. In addition, when viewed from above, the gate lead-out wiring 15 is separated from the base layer 23 and the base contact layer 24, and is therefore not easily affected by the potential of the base layer 23. Thus, it is possible to suppress the potential of the gate electrode 12 from increasing relative to the off potential due to capacitive coupling, and to reduce the leakage current in the off state.

[0055] <Comparative Example>

[0056] Fig. 9 It is a plan view showing a semiconductor device according to this comparative example.

[0057] Fig.10 yes Fig. 9 A cross-sectional view taken along line H-H' is shown.

[0058] Fig.11 yes Fig. 9 A cross-sectional view taken along line II' is shown.

[0059] like Figures 9 to 11 As shown, in the semiconductor device 101 according to the comparative example, a portion 15a of the gate lead wiring 15 on the cell region Rc side is disposed on the insulating film 32. Thus, the gate lead wiring 15 faces the base layer 23 and the drift layer 22 via the insulating film 32.

[0060] Therefore, when the semiconductor device 101 is turned off, the gate lead wiring 15 is capacitively coupled with the base layer 23 and the drift layer 22, and the potential of the gate lead wiring 15 rises relative to the off potential. As a result, the potential of the gate electrode 12 also rises relative to the off potential, and the leakage current increases.

[0061] According to the above-described embodiments, a semiconductor device capable of reducing leakage current can be realized.

[0062] Several embodiments of the present invention are described above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope or spirit of the invention and are included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device, wherein: have: 1st electrode; A semiconductor portion, disposed on the first electrode; an insulating member disposed in the semiconductor portion; a first insulating film provided on a portion of the semiconductor portion; A second insulating film, provided on the other part of the semiconductor portion, is thicker than the first insulating film; a second electrode disposed in the insulating member; a first wiring connected to the second electrode, provided on the insulating member and the second insulating film but not provided on the first insulating film; as well as The third electrode is provided on the semiconductor portion, the insulating member and the first insulating film.

2. The semiconductor device according to claim 1, wherein: Also available: The fourth electrode is provided in the insulating member, is insulated from the second electrode, and is connected to the third electrode.

3. The semiconductor device according to claim 2, wherein: The insulating member extends in a first direction, In the insulating member, the second electrode and the fourth electrode are arranged along a second direction orthogonal to the first direction. The first direction and the second direction intersect with a third direction from the first electrode toward the third electrode.

4. The semiconductor device according to claim 1, wherein: The second insulating film is located closer to a distal end of the insulating member than the first insulating film.

5. The semiconductor device according to claim 1, wherein: The insulating member is in contact with the first insulating film and the second insulating film.

6. The semiconductor device according to any one of claims 1 to 5, wherein: The semiconductor portion has: a first semiconductor layer of a first conductivity type connected to the first electrode; a second semiconductor layer of a second conductivity type, provided on a portion of the first semiconductor layer and opposed to the second electrode via the insulating member; as well as The third semiconductor layer of the first conductivity type is provided on a portion of the second semiconductor layer and is connected to the third electrode.

7. The semiconductor device according to claim 6, wherein: When viewed from above, the second semiconductor layer is separated from the first wiring.

8. The semiconductor device according to claim 1, wherein: The semiconductor portion comprises silicon, The insulating member, the first semiconductor film, and the second semiconductor film include silicon oxide.

9. A semiconductor device, wherein: have: 1st electrode; a first semiconductor layer of a first conductivity type, disposed on the first electrode; a second semiconductor layer of a second conductivity type, disposed on a portion of the first semiconductor layer; a third semiconductor layer of the first conductivity type, disposed on a portion of the second semiconductor layer; a second electrode facing the second semiconductor layer via an insulating member; a first wiring, provided on the first semiconductor layer, connected to the second electrode, and spaced apart from the second semiconductor layer when viewed from above; as well as The third electrode is connected to the third semiconductor layer and the second electrode.

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