Semiconductor device

Abstract

The invention discloses a semiconductor device which comprises a semiconductor layer and a trench gate structure, the semiconductor layer is provided with a first surface and a second surface which are opposite to each other, at least part of the trench gate structure is located in a trench extending from the first surface to the second surface of the semiconductor layer, and the semiconductor layer comprises a shielding layer extending along a second direction, the bottom interval of the trench gate structure which is located between the trench gate structure and the second surface of the semiconductor layer and extends along the first direction is adjacent to the shielding layer, the first direction and the second direction are parallel to the first surface of the semiconductor layer, and an included angle which is not zero is formed between the first direction and the second direction. According to the semiconductor device provided by the invention, the shielding layer which is provided with the plurality of beam-shaped structures and extends along the second direction is formed below the groove extending along the first direction, and the width of the interval region between the adjacent beam-shaped structures along the first direction and the width of the beam-shaped structures are controlled, so that the electric field optimization of the corner at the bottom of the groove gate is realized; and meanwhile, the on-resistance is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and more specifically, to a semiconductor device with a trench gate structure. Background Art

[0002] Compared with the planar transistor structure, the vertical transistor structure is conducive to balancing the blocking voltage and on-resistance in the same area. When multiple discrete devices are used in a power device module or in the same system, the variation in characteristics between transistor devices is also an important consideration for the robustness of the integrated system. During the manufacturing process, transistors need to go through a large number of different process steps, so the device characteristics of the transistors will also vary due to differences in the manufacturing process.

[0003] As a power semiconductor device, there are many ways to improve the Rsp (on-resistance or switching loss) of MOSFET. For trench-type transistors, the electric field will be concentrated at the bottom corner of the trench during use, so the withstand voltage and reliability are poor.

[0004] In order to compensate for this shortcoming, the bottom corners of the trench need to be shielded. However, the shielding method of traditional technology usually leads to an increase in on-resistance, requires a thicker hard mask layer, or causes problems such as an increase in design size. Summary of the invention

[0005] In view of the above problems, an object of the present invention is to provide a semiconductor device, wherein a shielding layer having a plurality of beam-like structures and extending along a second direction is formed under a trench extending along a first direction, and by controlling the width of the spacing area between adjacent beam-like structures along the first direction and the width of the beam-like structures, the electric field at the bottom corner of the trench gate is optimized, while the on-resistance is reduced.

[0006] According to one aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor layer and a trench gate structure, the semiconductor layer having a first surface and a second surface relative to each other, at least a portion of the trench gate structure being located in a trench extending from the first surface to the second surface of the semiconductor layer, wherein the semiconductor layer comprises: a shielding layer extending along a second direction, the shielding layer being located between the trench gate structure and the second surface of the semiconductor layer, the bottom of the trench gate structure extending along the first direction being spaced adjacent to the shielding layer, the first direction and the second direction being parallel to the first surface of the semiconductor layer, and the first direction and the second direction forming an angle which is not zero.

[0007] Optionally, the shielding layer includes a plurality of beam-like structures extending along the second direction, and the plurality of beam-like structures are arranged at intervals along the first direction.

[0008] Optionally, an angle between the first direction and the second direction is greater than 45° and less than 135°.

[0009] Optionally, along the first direction, the spacing region between two adjacent beam-like structures and an adjacent beam-like structure form a cellular region, and in the cellular region, the spacing width of the spacing region along the first direction is greater than or equal to the width of the beam-like structure.

[0010] Optionally, in the cell region, the ion doping concentration of the shielding layer is increased to reduce the width of the beam-like structure.

[0011] Optionally, a ratio of a width of the beam-like structure to a spacing width of the spacing area is greater than or equal to 1 / 3 and less than or equal to 1.

[0012] Optionally, the semiconductor layer further includes: a source region, located between adjacent trench gate structures, extending from the first surface to the second surface of the semiconductor layer, and adjacent to a side wall of a trench gate structure on one side; a body region, located between adjacent trench gate structures, adjacent to the side walls of the adjacent trench gate structures on both sides, and a portion of the upper surface of the body region adjacent to the lower surface of the source region; an epitaxial layer, located between the body region and the second surface of the semiconductor layer, the epitaxial layer separating the adjacent beam-like structures and adjacent to a portion of the lower surface of the body region

[0013] Optionally, the shielding layer and the body region are of the second conductivity type.

[0014] Optionally, the doping concentration of the shielding layer is greater than the doping concentration of the body region.

[0015] Optionally, a distance between a lower surface of the trench gate structure and the first surface is greater than a distance between a lower surface of the body region and the first surface.

[0016] Optionally, the semiconductor layer also includes: a body contact region, the body contact region is located between two source regions between adjacent trench gate structures, the source region divides the body contact region and the trench gate structure, the body contact region extends from the first surface to the second surface and is adjacent to the body region, wherein the body contact region is of the second conductivity type.

[0017] Optionally, the body contact region extends along a first direction; or the body contact region includes a plurality of regions spaced apart and distributed along the first direction, and each region of the body contact region on the first surface is surrounded by the source region.

[0018] Optionally, the trench gate structure includes a gate dielectric layer and a gate conductor, the gate dielectric layer covers the inner surface of the trench, the gate conductor is located in the trench, and the gate dielectric layer is located between the gate conductor and the semiconductor layer to separate the gate conductor and the semiconductor layer.

[0019] Optionally, the semiconductor layer also includes: a substrate, located between the epitaxial layer and the second surface; a drain contact region, located on the side of the substrate close to the second surface; a source metal layer, located on the first surface of the semiconductor layer and adjacent to at least part of the source region; an interlayer dielectric layer, located between the first surface of the semiconductor layer and the source metal layer, the interlayer dielectric layer separating the trench gate structure from the source metal layer.

[0020] Optionally, the semiconductor layer includes a SiC semiconductor layer or a Si semiconductor layer.

[0021] The semiconductor device provided by the present invention forms a shielding layer under a trench extending along a first direction, and the shielding layer includes a plurality of beam-like structures extending along a second direction. By controlling the spacing width between adjacent beam-like structures and the width of the beam-like structures along the first direction, the electric field at the bottom corner of the trench gate is optimized, and the on-resistance is reduced at the same time, wherein the angle between the extension direction of the trench gate structure and the extension direction of the beam-like structure can be an acute angle, a right angle, or an obtuse angle.

[0022] Furthermore, in the present application, the beam-like structure of the shielding layer extending along the second direction does not form a channel in the partial area in contact with the trench gate, and only forms a channel in the area between adjacent beam-like structures. Therefore, the narrower the width of the beam-like structure along the first direction, the more helpful it is to reduce the on-resistance. In addition, the shielding layer does not need to be implanted with ultra-high energy ions, so the width of the shielding layer along the first direction can be effectively controlled in the manufacturing process.

[0023] Further, along the first direction, a spacing between adjacent beam-like structures in the shielding layer and an adjacent shielding layer form a cellular region. In a cellular region, controlling the width of the shielding layer along the first direction to be smaller than the spacing between adjacent shielding layers can maintain the withstand voltage and reliability of the semiconductor device at a certain level while improving the Rsp (on-resistance) characteristic. Specifically, in a cellular region, the ratio of the width of the beam-like structure to the spacing between adjacent beam-like structures is less than or equal to 1 but greater than or equal to 1 / 3.

[0024] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0026] Figure 1 shows a schematic diagram of the three-dimensional structure of a semiconductor device according to a first embodiment of the present invention;

[0027] Figure 2 The first embodiment of the present invention is shown along Figure 1 A schematic cross-sectional view of a semiconductor device taken along line AA;

[0028] Figure 3 The first embodiment of the present invention is shown along Figure 1 A schematic cross-sectional view of a semiconductor device taken along line BB;

[0029] Figure 4 The first embodiment of the present invention is shown along Figure 1 A schematic cross-sectional view of a semiconductor device taken along line CC;

[0030] Figure 5 The first embodiment of the present invention is shown along Figure 1 A schematic cross-sectional view of a semiconductor device taken along line DD;

[0031] Figure 6 A diagram showing the positional relationship between a shielding layer and a trench along a horizontal plane of a semiconductor device according to a first embodiment of the present invention is shown;

[0032] Figure 7 A diagram showing the positional relationship between a shielding layer and a trench along a horizontal plane of a semiconductor device according to a second embodiment of the present invention is shown;

[0033] Figure 8 A diagram showing the positional relationship between a shielding layer and a trench along a horizontal plane of a semiconductor device according to a third embodiment of the present invention;

[0034] Fig. 9 A diagram showing the positional relationship between a shielding layer and a trench along a horizontal plane of a semiconductor device according to a fourth embodiment of the present invention;

[0035] Fig.10 shows a schematic diagram of the three-dimensional structure of a semiconductor device according to a fifth embodiment of the present invention;

[0036] Fig.11 The fifth embodiment of the present invention is shown along Fig.10 Schematic diagram of the cross-section of the semiconductor device taken along line CC. DETAILED DESCRIPTION

[0037] The present application will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0038] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0039] If the purpose is to describe the situation of being directly on another layer or another area, this article will use expressions such as "directly on..." or "on... and adjacent to...".

[0040] The power device generally includes an active component region, an edge termination region, and a crack-stop or shielding region. The active component region includes an active component array. The present disclosure relates to an active component structure. The size of the active component may vary depending on product requirements, and there may be a body region between active components in the active component region.

[0041] Many specific details of the present application are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to make the present application more clearly understood. However, as those skilled in the art will appreciate, the present application may be implemented without following these specific details.

[0042] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.

[0043] Figure 1 shows a schematic diagram of the three-dimensional structure of a semiconductor device according to a first embodiment of the present invention; Figure 2 The first embodiment of the present invention is shown along Figure 1 A schematic cross-sectional view of a semiconductor device taken along line AA; Figure 3 The first embodiment of the present invention is shown along Figure 1 A schematic cross-sectional view of a semiconductor device taken along line BB; Figure 4 The first embodiment of the present invention is shown along Figure 1 A schematic cross-sectional view of a semiconductor device taken along line CC; Figure 5 The first embodiment of the present invention is shown along Figure 1 The schematic cross-sectional view of the semiconductor device taken along line DD in FIG. Figure 1The structure above the semiconductor layer and part of the trench gate structure are omitted in order to more clearly express the positional relationship between various structures and regions.

[0044] like Figures 1 to 5 As shown, the semiconductor device 10 of the first embodiment of the present application includes a semiconductor layer 100, a plurality of trench gate structures 150 located in the semiconductor layer 100, an interlayer dielectric layer 160 located on the semiconductor layer 100, and a source metal layer 170. The semiconductor layer 100 has a first surface and a second surface that are oppositely arranged, and a plurality of trenches 102 extending from the first surface to the second surface of the semiconductor layer 100, and the plurality of trench gate structures 150 are located in the corresponding trenches 102.

[0045] In this embodiment, the semiconductor layer 100 is, for example, a SiC substrate, a Si substrate, or a stacked structure of a SiC substrate and an epitaxial layer. However, the present application is not limited thereto, and those skilled in the art may set other materials and layers of the semiconductor layer 100 as needed.

[0046] The semiconductor layer 100 includes a substrate 101, an epitaxial layer 103, a shielding layer 120, a body region 110, a source region 130, a body contact region 140, and a drain contact region 180. The source region 130, the substrate 101, and the epitaxial layer 103 are of a first conductivity type, the body region 110, the body contact region 140, and the shielding layer 120 are of a second conductivity type, the doping concentration of the body contact region 140 is greater than the doping concentration of the body region 110, and the first conductivity type is opposite to the second conductivity type. The first conductivity type is one of a P type and an N type, and the second conductivity type is the other of a P type and an N type.

[0047] The trench gate structure 150 includes a gate dielectric layer 151 and a gate conductor 152. The gate dielectric layer 151 covers the inner surface of the trench 102, the gate conductor 152 is located in the trench 102, and the gate dielectric layer 151 is located between the semiconductor layer 100 and the gate conductor 152, and is used to separate the semiconductor layer 100 from the gate conductor 152. A plurality of trench gate structures 150 extend along a first direction, that is, the first direction is the length direction of the trench gate structure 150, and a plurality of trench gate structures 150 are spaced and distributed along a second direction, that is, the second direction is the width direction of the trench gate structure 150, and the third direction is the direction from the second surface to the first surface of the semiconductor layer 100. Optionally, the first direction, the second direction and the third direction are respectively represented as the X-axis, the Y-axis and the Z-axis directions, and the first direction, the second direction and the third direction are perpendicular to each other. The trench gate structure 150 has two sidewalls 150 a and a lower surface 150 b . Optionally, the Y-axis direction is the <11-20> direction or the <1-100> direction, and the plane of the sidewall 150 a is the (11-20) plane or the (1-100) plane.

[0048] The body region 110 is located between two adjacent trench gate structures 150, and extends along the width direction and the length direction of the trench gate structure. One side of the body region 110 is adjacent to the side wall 150a of one of the trench gate structures 150, and the other side is adjacent to the side wall 150a of the other trench gate structure 150. In addition, the distance between the lower surface of the body region 110 and the first surface is smaller than the distance between the lower surface of the trench gate structure 150 and the first surface.

[0049] The source region 130 extends from the first surface to the second surface of the semiconductor layer 100 and is adjacent to the body region 110. At the same time, the source region 130 is located between two adjacent trench gate structures 150 and is adjacent to a sidewall 150a of the trench gate structure 150. The body contact region 140 is located between the source regions 130, and divides the source region 130 located between the two adjacent trench gate structures 150 into two parts. The two parts of the source region 130 are respectively adjacent to the sidewall 150a of one of the adjacent trench gate structures 150, that is, in the second direction, the source region 130, the body contact region 140 and the source region 130 are sequentially located between the adjacent trench gate structures 150 on the first surface of the semiconductor layer 100, and in the third direction, the source region 130 and the body contact region 140 are located above the body region 110. In this embodiment, Figure 1 The figure shows that the body contact region 140 extends along the first direction, thereby separating the source region 130 between two adjacent trench gate structures 150 into two parts. The depth of the body contact region 140 extending from the first surface to the second surface in the semiconductor layer 100 is deeper than the depth of the source region 130 extending in the semiconductor layer 100, and is less than the extension depth of the body region 110 in the semiconductor layer 100. The bottom of the trench of the trench gate structure 150 is located below the body region 110, that is, the depth of the trench gate structure 150 extending from the first surface to the second surface of the semiconductor layer 100 is greater than the extension depth of the body region 110 in the semiconductor layer 100.

[0050] The substrate 101 is located below the body region 110, i.e., close to the second surface of the semiconductor layer 100. The epitaxial layer 103 is located between the body region 110 and the substrate 101. The drain contact region 180 is adjacent to the substrate 101 and is located on a surface of the substrate 101 away from the epitaxial layer 103, i.e., the drain contact region 180 extends from the second surface of the semiconductor layer 100 to the first surface.

[0051] The shielding layer 120 is located below the body region 110 and the trench gate structure 150, and specifically is adjacent to the lower surface of the body region 110, the lower surface 150b of the trench gate structure 150, and part of the side surface. The shielding layer 120 includes a plurality of beam-like structures extending along the second direction and arranged at intervals along the first direction, and the upper surface of a beam-like structure is alternately adjacent to the lower surfaces of the plurality of body regions 110 and the lower surfaces of the plurality of trench gate structures 150 in sequence. And because the plurality of beam-like structures are distributed at intervals along the first direction, that is, along the first direction, the interval area between two adjacent beam-like structures exposes the lower surfaces of the body region 110 and the trench gate structure 150. In addition, along the extension direction of the beam-like structures, the first ends of the plurality of beam-like structures are connected together, and the second ends of the plurality of beam-like structures are also connected together, for example, with reference to Figure 6 .

[0052] refer to Figure 2 In the cross section of the semiconductor device 10 obtained along the second direction and on a vertical surface of a beam-like structure having a shielding layer 120, the depth of the lower surface of the shielding layer 120 extending in the semiconductor layer 100 is substantially the same, but the upper surface of the shielding layer 120, as described above, is alternately adjacent to the lower surfaces of the plurality of body regions 110 and the lower surfaces of the plurality of trench gate structures 150 in the second direction. In this area, since the shielding layer 120 covers the entire bottom of the trench gate structure 150, and the lower part of the body region 110 is also covered by the shielding layer 120, the current cannot flow through this area and a channel cannot be formed. At the same time, since the shielding layer 120 is in direct contact with the bottom of the trench gate structure 150, the shielding layer 120 in this area can very well protect the bottom corner of the trench gate structure 150 from being broken down.

[0053] refer to Figure 3 In a cross section of the semiconductor device 10 obtained along the second direction and on a vertical surface of a beam-shaped structure without the shielding layer 120, the lower surface of the body region 110 is in direct contact with the epitaxial layer 103. Since there is no shielding layer 120 in the spacing region, the bottom of the trench gate structure 150 is also in direct contact with the epitaxial layer 103, so there is no factor that hinders the flow of current in the spacing region, and therefore the spacing region is the most ideal structure for reducing on-resistance.

[0054] The interlayer dielectric layer 160 is located on the first surface of the semiconductor layer 100. The interlayer dielectric layer 160 includes a plurality of layers extending in the first direction and arranged at intervals in the second direction, so that the bottom of the interlayer dielectric layer 160 can cover the portion of the trench gate structure 150 exposed on the first surface of the semiconductor layer 100, and at least expose the source region 130 and the body contact region 140 on the first surface. The source metal layer 170 is located on the first surface of the semiconductor layer 100 and contacts at least a portion of the surface of the source region 130 and the body contact region 140 exposed on the first surface. The interlayer dielectric layer 160 is used to isolate the trench gate structure 150 from the source metal layer 170. The source metal layer 170 and the interlayer dielectric layer 160 can be a multilayer structure of different materials. As an example of a multilayer source metal layer 170, the source metal layer 170 includes a tungsten (W) layer directly covering the body contact region 140 and the source region 130 and an aluminum copper (AlCu) layer directly covering the tungsten layer. Optionally, this embodiment also includes parts not shown in the figure, for example, a gate contact region is opened directly above the gate conductor 152 so that the gate conductor 152 is connected to the gate metal layer, the gate contact region is directly located on the gate conductor 152, and the gate conductor 152 is isolated from the source metal layer 170 by the interlayer dielectric layer 160.

[0055] refer to Figure 4 In the cross-sectional view of the semiconductor device 10 obtained along the first direction and located in the region of the source region 130, since the cross-sectional view is relatively close to the body contact region 140, there is no interlayer dielectric layer 160 above the source region 130. Of course, in the region close to the trench gate structure 150, in order to ensure the isolation effect of the interlayer dielectric layer 160, the interlayer dielectric layer 160 can cover part of the upper surface of the source region 130, so in the cross-sectional view of the semiconductor device 10 obtained in the region close to the trench gate structure 150, there can also be an interlayer dielectric layer 160 on the source region 130.

[0056] In this embodiment, further reference is made to Figure 4 river Figure 5 In the first direction, the multiple beam-like structures of the shielding layer 120 are arranged at intervals. In order to enable the beam-like structures to also shield the bottom of the trench gate 150 between adjacent beam-like structures, it is necessary to consider the width Wa of the beam-like structure along the first direction and the width Wb of the spacing area between two adjacent beam-like structures. In this way, it is possible to achieve shielding the bottom of the trench gate structure 150 while manufacturing a semiconductor device with low on-resistance.

[0057] Specifically, for example, a cell region includes a beam-like structure and an adjacent spacing region (W=Wa+Wb) along a width W of the first direction. In this cell region, since the beam-like structure region is a region where no channel is formed, the narrower the width Wa of the beam-like structure, the more helpful it is to reduce the on-resistance Ron. In this embodiment, the width Wa of the beam-like structure is less than or equal to the width Wb of the spacing region. In addition, in this application, there is no need to perform ultra-high energy ion implantation (Ultra-High energy implant, above 2.5 MeV), so it is beneficial to achieve a narrower width Wa of the beam-like structure in terms of process.

[0058] In addition, while ensuring the withstand voltage and reliability of the semiconductor device, the smaller the ratio (Wa / Wb) of the width Wa of the beam structure to the width Wb of the spacing region, the better the Rsp (on-resistance) characteristics of the semiconductor device can be improved. Therefore, the width Wa of the beam structure can be set smaller than the width Wb of the spacing region between two adjacent beam structures. At the same time, by increasing the ion concentration of the shielding layer 120, the width Wa of the beam structure in a cell region can be further narrowed, while the width Wb of the spacing region between two adjacent beam structures can be widened.

[0059] In this embodiment, a ratio (Wa / Wb) between a width Wa of a beam-like structure and a width Wb of a spacing region between two adjacent beam-like structures is less than or equal to 1 and greater than or equal to 1 / 3.

[0060] Furthermore, since the beam-like structure already has a portion in contact with the body region 110 in the extending direction thereof, no additional pick-up layer is required to connect the shielding layer 120 and the body region 110 .

[0061] The semiconductor device of this embodiment can be used as a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), and can also be used as an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), for example, the conductivity type of the drain contact region 180 is set to the first conductivity type or the second conductivity type. However, the embodiment of the present application is not limited to this, and those skilled in the art can set the conductivity type of each region in the semiconductor layer 100 in other ways as needed to use the semiconductor device as a MOSFET or an IGBT.

[0062] In this embodiment, when the semiconductor device is in the on state, the body region 110 and the adjacent sidewalls 150a on both sides of the trench gate structure 150 are inverted, thereby forming a channel. In addition, since the multiple beam-like structures of the shielding layer 120 are spaced apart along the second direction, the channel current can only flow from the area between two adjacent beam-like structures, and by controlling the width of the beam-like structure along the first direction and the spacing between two adjacent beam-like structures along the first direction, the bottom corner of the trench gate structure 150 in the channel area can be protected from being broken down by the electric field, thereby reducing the on resistance of the semiconductor device and improving the overall performance of the device.

[0063] Furthermore, the semiconductor device of this embodiment further includes a drain metal layer (not shown) located on the second surface of the semiconductor layer 100 and connected to the drain contact region 180 .

[0064] Figure 7 A diagram showing the positional relationship between a shielding layer and a trench along a horizontal plane of a semiconductor device according to a second embodiment of the present invention is shown.

[0065] like Figure 7 As shown, the similarities between the semiconductor device of the second embodiment of the present application and the first embodiment are not repeated here, and reference may be made to Figures 1 to 6 The difference is that, compared with the first embodiment, in the shielding layer 120 in the second embodiment, the first ends of the multiple beam-like structures are not connected together along the extension direction of the beam-like structures, and the second ends of the multiple beam-like structures are not connected together, so that the shielding layer 120 includes multiple parallel and mutually separated beam-like structures, and adjacent beam-like structures are separated by the epitaxial layer.

[0066] Figure 8 A diagram showing the positional relationship between a shielding layer and a trench along a horizontal plane of a semiconductor device according to a third embodiment of the present invention is shown.

[0067] like Figure 8 As shown, the similarities between the semiconductor device of the third embodiment of the present application and the first embodiment are not repeated here, and reference may be made to Figures 1 to 6 The difference is that, compared with the first embodiment, the angle between the second direction (Y) in which the beam-like structure in the shielding layer 120 extends and the first direction (X) is an obtuse angle. Specifically, the angle between the second direction (Y) in which the beam-like structure in the shielding layer 120 extends and the first direction (X) is in the range of greater than 90° and less than 135°.

[0068] Fig. 9 A diagram showing the positional relationship between a shielding layer and a trench along a horizontal plane of a semiconductor device according to a fourth embodiment of the present invention is shown.

[0069] like Fig. 9As shown, the similarities between the semiconductor device of the fourth embodiment of the present application and the first embodiment are not repeated here, and reference may be made to Figures 1 to 6 The difference is that, compared with the first embodiment, the angle between the second direction (Y) in which the beam-like structure in the shielding layer 120 extends and the first direction (X) is an acute angle. Specifically, the angle between the second direction (Y) in which the beam-like structure in the shielding layer 120 extends and the first direction (X) is in the range of greater than 45° and less than 90°.

[0070] Fig.10 shows a schematic diagram of the three-dimensional structure of a semiconductor device according to a fifth embodiment of the present invention; Fig.11 The fifth embodiment of the present invention is shown along Fig.10 Schematic diagram of the cross-section of the semiconductor device taken along line CC.

[0071] like Fig.10 and Fig.11 As shown, the similarities between the semiconductor device of the fifth embodiment of the present application and the first embodiment are not repeated here, and reference may be made to Figures 1 to 6 The difference is that, compared with the first embodiment, the body contact region 140 in the fifth embodiment includes a plurality of block regions, and the plurality of block regions are arranged at intervals along the first direction, and on the first surface, the body contact region 140 is surrounded by the source region 130 .

[0072] The semiconductor device provided by the present invention forms a shielding layer under a trench extending along a first direction, and the shielding layer includes a plurality of beam-like structures extending along a second direction. By controlling the spacing between adjacent beam-like structures and the width of the beam-like structures along the first direction, the electric field at the bottom corner of the trench gate is optimized, and the on-resistance is reduced at the same time, wherein the angle between the extension direction of the trench gate structure and the extension direction of the beam-like structure can be an acute angle, a right angle, or an obtuse angle.

[0073] Furthermore, in the present application, the beam-like structure of the shielding layer extending along the second direction does not form a channel in the partial area in contact with the trench gate, and only forms a channel in the area between adjacent beam-like structures. Therefore, the narrower the width of the beam-like structure along the first direction, the more helpful it is to reduce the on-resistance. In addition, the shielding layer does not need to be implanted with ultra-high energy ions, so the width of the shielding layer along the first direction can be effectively controlled in the manufacturing process.

[0074] Further, along the first direction, a spacing between adjacent beam-like structures in the shielding layer and an adjacent shielding layer form a cellular region, and in a cellular region, the width of the shielding layer along the first direction is controlled to be smaller than the spacing between adjacent shielding layers, so that the withstand voltage and reliability of the semiconductor device are maintained at a certain level while improving Rsp. Specifically, in a cellular region, the ratio of the width of the beam-like structure to the spacing between adjacent beam-like structures is less than or equal to 1 but greater than or equal to 1 / 3.

[0075] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, comprising: A semiconductor layer and a trench gate structure, wherein the semiconductor layer has a first surface and a second surface opposite to each other, and at least a portion of the trench gate structure is located in a trench extending from the first surface to the second surface of the semiconductor layer, Wherein, the semiconductor layer comprises: A shielding layer extending along the second direction, the shielding layer is located between the trench gate structure and the second surface of the semiconductor layer, the bottom gap of the trench gate structure extending along the first direction is adjacent to the shielding layer, the first direction and the second direction are parallel to the first surface of the semiconductor layer, and the first direction and the second direction form an angle that is not 0.

2. The semiconductor device according to claim 1, wherein The shielding layer includes a plurality of beam-shaped structures extending along the second direction, and the plurality of beam-shaped structures are arranged at intervals along the first direction.

3. The semiconductor device according to claim 2, wherein: An angle between the first direction and the second direction is greater than 45° and less than 135°.

4. The semiconductor device according to claim 2, wherein: Along the first direction, the spacing area between two adjacent beam-like structures and an adjacent beam-like structure form a cell area. In the cellular region, a spacing width of the spacing regions along a first direction is greater than or equal to a width of the beam-like structure.

5. The semiconductor device according to claim 4, wherein: In the cell region, the ion doping concentration of the shielding layer is increased to reduce the width of the beam-like structure.

6. The semiconductor device according to claim 4 or 5, wherein: The ratio of the width of the beam-like structure to the spacing width of the spacing area is greater than or equal to 1 / 3 and less than or equal to 1.

7. The semiconductor device according to claim 6, wherein: The semiconductor layer further comprises: A source region, located between adjacent trench gate structures, extending from the first surface to the second surface of the semiconductor layer, with one side adjacent to a sidewall of one of the trench gate structures; A body region, located between adjacent trench gate structures, with two sides respectively adjacent to side walls of the adjacent trench gate structures, and a portion of an upper surface of the body region adjacent to a lower surface of the source region; The epitaxial layer is located between the body region and the second surface of the semiconductor layer, wherein the epitaxial layer separates the adjacent beam-shaped structures and is adjacent to a lower surface of a portion of the body region.

8. The semiconductor device according to claim 7, wherein: The shielding layer and the body region are of the second conductivity type.

9. The semiconductor device according to claim 8, wherein: The doping concentration of the shielding layer is greater than the doping concentration of the body region.

10. The semiconductor device according to claim 7, wherein: A distance between a lower surface of the trench gate structure and the first surface is greater than a distance between a lower surface of the body region and the first surface.

11. The semiconductor device according to claim 7, wherein: The semiconductor layer further comprises: a body contact region, the body contact region being located between two source regions between adjacent trench gate structures, the source region dividing the body contact region and the trench gate structure, the body contact region extending from the first surface to the second surface and being adjacent to the body region, Wherein, the body contact region is of the second conductivity type.

12. The semiconductor device according to claim 11, wherein The body contact region extends along a first direction; or The body contact region includes a plurality of regions spaced apart and distributed along a first direction, and a region of each of the body contact regions on the first surface is surrounded by the source region.

13. The semiconductor device according to claim 11, wherein The trench gate structure comprises a gate dielectric layer and a gate conductor, wherein the gate dielectric layer covers the inner surface of the trench, the gate conductor is located in the trench, and the gate dielectric layer is located between the gate conductor and the semiconductor layer to separate the gate conductor and the semiconductor layer.

14. The semiconductor device according to claim 13, wherein: The semiconductor layer further comprises: a substrate, located between the epitaxial layer and the second surface; a drain contact region, located on a side of the substrate close to the second surface; A source metal layer, located on the first surface of the semiconductor layer and adjacent to at least a portion of the source region; An interlayer dielectric layer is located between the first surface of the semiconductor layer and the source metal layer, and the interlayer dielectric layer separates the trench gate structure and the source metal layer.

15. The semiconductor device according to claim 1, wherein The semiconductor layer includes a SiC semiconductor layer or a Si semiconductor layer.

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