Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device includes a semiconductor substrate including a first active region and a second active region; the first dielectric layer is arranged on the first active region; the second dielectric layer is arranged on the second active region; a first gate electrode disposed over the first dielectric layer; and a second gate electrode disposed over the second dielectric layer. The first active region and the second active region have different conductivity types. The first dielectric layer and the second dielectric layer include the same dielectric material. A dipole concentration of the first dielectric layer is different from a dipole concentration of the second dielectric layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0127958, filed on September 25, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Techniques and embodiments disclosed in the present disclosure generally relate to semiconductor devices and methods of manufacturing the same, and more particularly, to semiconductor devices including transistors having different threshold voltages and methods of manufacturing the same. Background Art

[0004] As the integration density of semiconductor devices increases, the difficulty of designing integrated circuits (ICs) increases exponentially.

[0005] In the development process of semiconductor devices, the number of devices included per unit chip area is rapidly increasing while the size of each device is gradually decreasing, and such high integration in semiconductor devices leads to increased complexity in the manufacturing process of integrated circuits (ICs).

[0006] For example, as the size of each semiconductor device decreases, increasing the thickness of a dielectric layer to adjust a threshold voltage (Vt) may become impossible or may cause difficulties in a manufacturing process of the semiconductor device.

[0007] Therefore, various methods are needed to manufacture semiconductor devices with excellent performance while overcoming the limitations caused by the high integration of semiconductor devices. Summary of the invention

[0008] Various embodiments of the present disclosure are directed to a semiconductor device including a plurality of transistors having adjusted threshold voltage characteristics.

[0009] According to an embodiment of the present disclosure, a semiconductor device may include: a semiconductor substrate including a first active region and a second active region; a first dielectric layer disposed on the first active region; a second dielectric layer disposed on the second active region; a first gate electrode disposed on the first dielectric layer; and a second gate electrode disposed on the second dielectric layer. The first active region and the second active region may have different conductivity types, the first dielectric layer and the second dielectric layer may include the same dielectric material, and the dipole concentration of the first dielectric layer may be different from the dipole concentration of the second dielectric layer.

[0010] In an embodiment, each of the first dielectric layer and the second dielectric layer may include a first sub-dielectric layer and a second sub-dielectric layer, the second sub-dielectric layer being disposed on the first sub-dielectric layer.

[0011] According to an embodiment, the first sub-dielectric layer and the second sub-dielectric layer may have different silicon concentrations.

[0012] According to an embodiment, the first sub-dielectric layer and the second sub-dielectric layer may have different nitrogen concentrations.

[0013] According to an embodiment, each of the first dielectric layer and the second dielectric layer may include at least one defect where dipole diffusion occurs.

[0014] According to an embodiment, the concentration of defects of the first dielectric layer and the concentration of defects of the second dielectric layer may be controlled by thermal treatment.

[0015] According to an embodiment, the first dielectric layer may include a dipole material diffused into the first dielectric layer from an upper portion of the first dielectric layer.

[0016] According to an embodiment, the dipole material includes at least one of hafnium (Hf), aluminum (Al), lanthanum (La), zirconium (Zr), scandium (Sc), and erbium (Er).

[0017] According to an embodiment, the semiconductor substrate may further include: a third active region and a fourth active region; a third gate electrode disposed to overlap the third active region; a fourth gate electrode disposed to overlap the fourth active region; a third dielectric layer disposed between the third active region and the third gate electrode; and a fourth dielectric layer disposed between the fourth active region and the fourth gate electrode. The third active region and the fourth active region may have different conductivity types, the first active region and the third active region may have the same conductivity type, and the third dielectric layer and the fourth dielectric layer may include the same dielectric material.

[0018] According to an embodiment, a dipole concentration of the third dielectric layer may be different from a dipole concentration of the fourth dielectric layer.

[0019] According to an embodiment, the first dielectric layer and the third dielectric layer may include different dielectric materials.

[0020] According to an embodiment, each of the third dielectric layer and the fourth dielectric layer may include a third sub-dielectric layer and a fourth sub-dielectric layer disposed over the third sub-dielectric layer.

[0021] According to an embodiment, the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer may include the same dielectric material.

[0022] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include: forming a first dielectric layer over a first active region included in a semiconductor substrate; forming a second dielectric layer over a second active region included in the semiconductor substrate; forming a metal pattern layer over the second dielectric layer; forming a dipole material layer over the first dielectric layer and the metal pattern layer; diffusing the dipole material from the dipole material layer to the first dielectric layer and the second dielectric layer; forming a first gate electrode overlapping the first dielectric layer; and forming a second gate electrode overlapping the second dielectric layer, wherein the first dielectric layer and the second dielectric layer include the same dielectric material, and the first active region and the second active region have different conductivity types.

[0023] According to an embodiment, the method may further include: forming an interlayer dielectric layer over the first active region and the second active region. Forming the first dielectric layer may include: forming a first sub-dielectric layer overlapping the interlayer dielectric layer; and forming a second sub-dielectric layer overlapping the first sub-dielectric layer. Forming the second dielectric layer may include: forming a first sub-dielectric layer overlapping the interlayer dielectric layer; and forming a second sub-dielectric layer overlapping the first sub-dielectric layer.

[0024] According to an embodiment, the method may further include: forming a first defect control layer on the first dielectric layer; forming a second defect control layer on the second dielectric layer; performing heat treatment to control the defect concentration of the first dielectric layer and the defect concentration of the second dielectric layer; and removing the first defect control layer and the second defect control layer.

[0025] According to an embodiment, the first defect-controlling layer or the second defect-controlling layer may include a plurality of sub-controlling layers.

[0026] According to an embodiment, the plurality of sub-control layers may include at least one of titanium nitride (TiN), titanium aluminide (TiAl), and polysilicon (Si).

[0027] According to an embodiment, the method may further include removing the metal pattern layer.

[0028] According to an embodiment, the dipole material includes at least one of hafnium (Hf), aluminum (Al), lanthanum (La), zirconium (Zr), scandium (Sc), and erbium (Er).

[0029] It is to be understood that both the foregoing general description and the following detailed description of the embodiments of the present disclosure are illustrative and descriptive and are intended to provide further description of the embodiments as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other features and advantageous aspects of embodiments of the present disclosure will become readily apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0031] Figure 1is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0032] Figure 2 is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0033] Figure 3 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0034] Figures 4A to 4G is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0035] Figure 5 is a flowchart illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0036] FIG. 6A to FIG. 6I is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] The present disclosure provides embodiments and examples of semiconductor devices including transistors with different threshold voltages and methods for manufacturing the semiconductor devices, which can be used in a configuration to substantially solve one or more technical or engineering problems and alleviate limitations or disadvantages encountered in some other semiconductor device designs. Various embodiments of the present disclosure relate to a semiconductor device including a plurality of transistors with adjusted threshold voltage characteristics. Recognizing the above problems, embodiments of the present disclosure provide a semiconductor device that can adjust the threshold voltage of each transistor by adjusting the characteristics of a dielectric layer.

[0038] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the accompanying drawings to refer to the same or similar parts. Although the present disclosure is susceptible to a variety of modifications and alternative forms, specific embodiments thereof are illustrated by way of example in the accompanying drawings. However, the present disclosure should not be construed as being limited to the embodiments set forth herein.

[0039] Hereinafter, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to specific embodiments, but includes various modifications, equivalents and / or alternatives of the embodiments. The embodiments of the present disclosure can provide various effects that can be directly or indirectly identified by the present disclosure.

[0040] The drawings may not necessarily be drawn to scale, and in some examples, the scale of at least some structures in the drawings may be enlarged to clearly illustrate the features of the embodiments. When a multilayer structure having two or more layers is disclosed in a drawing or detailed description, the relative positional relationship or arrangement order of the layers only reflects a specific embodiment, and the scope or spirit of the present disclosure is not limited thereto, and it should be noted that the relative positional relationship or arrangement order of the layers may also be changed as needed. In addition, the drawings or detailed descriptions of the multilayer structure may not reflect all the layers present in a particular multilayer structure (for example, one or more additional layers may exist between the two shown layers). As a specific example, when the first layer in the multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" a substrate, the first layer may be formed directly on the second layer or substrate, but may also represent a structure in which one or more other layers exist between the first layer and the second layer or between the first layer and the substrate.

[0041] Hereinafter, a semiconductor device and a method of manufacturing the same according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0042] Threshold voltage (Vt) may refer to a minimum voltage required to create a conductive channel for operation of a transistor included in a semiconductor device. When the threshold voltage is applied to a gate electrode included in the transistor, a conductive channel may be formed in a substrate (ie, an active region) included in the transistor.

[0043] The threshold voltage may be affected by various factors, for example, a work function difference between the gate and the substrate of the transistor, an amount of charge in a depletion layer in the substrate, a capacitance of a dielectric layer between the gate and the substrate, a thickness of the dielectric layer, an interface potential (i.e., a body potential), etc. More specifically, the threshold voltage may be inversely proportional to the capacitance of a dielectric layer included in the transistor, and may be inversely proportional to the concentration of a dipole material included in the dielectric layer.

[0044] Figure 1 is a cross-sectional view showing a semiconductor device 1 according to an embodiment of the present disclosure.

[0045] refer to Figure 1 , the semiconductor device 1 may include a plurality of transistors (TR1, TR2, TR3, TR4, TR5, TR6) disposed on a semiconductor substrate 10. The semiconductor substrate 10 may include a plurality of active regions (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6) doped with N-type impurities or P-type impurities.

[0046] In an embodiment, the first active region (ACT1), the third active region (ACT3) and the fifth active region (ACT5) may be regions doped with N-type impurities, and the second active region (ACT2), the fourth active region (ACT4) and the sixth active region (ACT6) may be regions doped with P-type impurities.

[0047] Although not shown in the drawings, the active regions (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6) may include source / drain regions, and the semiconductor substrate 10 may include a plurality of isolation regions formed to isolate the plurality of transistors (TR1, TR2, TR3, TR4, TR5, TR6) from each other.

[0048] Interlayer dielectric layers (110a, 110b, 110c, 110d, 110e, 110f) may be formed on active regions (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6), respectively. Although for ease of description, interlayer dielectric layers (110a, 110b, 110c, 110d, 110e, 110f) are provided for transistors (TR1, TR2, TR3, TR4, TR5, TR6), respectively, other embodiments are possible, and it should be noted that interlayer dielectric layers (110a, 110b, 110c, 110d, 110e, 110f) may also be formed as only one layer.

[0049] The interlayer dielectric layer (e.g., 110a) can reduce interface defects between the semiconductor substrate 10 and the dielectric layer (e.g., 120a). In an embodiment, the interlayer dielectric layer (e.g., 110a) can be formed of a low permittivity material having a low dielectric constant. For example, the interlayer dielectric layer (e.g., 110a) can include silicon oxide (SiO) or silicon oxynitride (SiON).

[0050] A plurality of dielectric layers (120a, 120b, 120c, 120d, 120e, 120f) may be disposed on the interlayer dielectric layers (110a, 110b, 110c, 110d, 110e, 110f), respectively. The dielectric layers (120a, 120b, 120c, 120d, 120e, 120f) may include a dipole material having a higher dielectric constant (i.e., a higher permittivity) than the interlayer dielectric layers (110a, 110b, 110c, 110d, 110e, 110f), respectively. In more detail, dielectric layer 120a may include a dipole material having a higher dielectric constant than interlayer dielectric layer 110a, dielectric layer 120b may include a dipole material having a higher dielectric constant than interlayer dielectric layer 110b, dielectric layer 120c may include a dipole material having a higher dielectric constant than interlayer dielectric layer 110c, dielectric layer 120d may include a dipole material having a higher dielectric constant than interlayer dielectric layer 110d, dielectric layer 120e may include a dipole material having a higher dielectric constant than interlayer dielectric layer 110e, and dielectric layer 120f may include a dipole material having a higher dielectric constant than interlayer dielectric layer 110f. For example, the dipole material may include hafnium (Hf), aluminum (Al), lanthanum (La), zirconium (Zr), scandium (Sc), erbium (Er), etc.

[0051] In an embodiment, each of the dielectric layers (120a, 120b, 120c, 120d, 120e, 120f) may be provided as a layered structure including a dielectric material. For example, the dielectric material may be formed of any one of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium zirconium oxide (HfZrO), hafnium zirconium silicate (HfSiZrO), hafnium oxynitride (HfON), and hafnium silicate nitride (HfSiON).

[0052] More specifically, each dielectric layer (eg, 120a) may include a plurality of sub-dielectric layers (eg, 122a and 124a).

[0053] In an embodiment, each sub-dielectric layer (e.g., 122a and 124a) may include at least one of the above-mentioned dielectric materials (e.g., hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium zirconium oxide (HfZrO), hafnium zirconium silicate (HfSiZrO), hafnium oxynitride (HfON), and hafnium silicate nitride (HfSiON)). The diffusivity of the dipole material may differ depending on the type of sub-dielectric material (e.g., 122a and 124a) included in each dielectric layer (e.g., 120a). In addition, the threshold voltage of the transistors (TR1, TR2, TR3, TR4, TR5, TR6) each including a dielectric layer (e.g., 120a) may vary depending on the concentration of the dipole material.

[0054] The diffusivity of the dipole material may refer to the extent of diffusion of the dipole material into the dielectric material during a drive-in diffusion process such as a thermal treatment.

[0055] When the diffusivity of the dipole material is high, the concentration of the dipole material diffused into the dielectric layer (e.g., 120a) can increase. As the concentration of the dipole material increases, the dielectric constant can increase, so that the threshold voltage (Vt) of the transistor (e.g., TR1) including the dielectric layer (e.g., 120a) can be reduced.

[0056] The dielectric layers (120a, 120b, 120c, 120d, 120e, 120f) respectively included in the transistors may include different concentrations of dipoles, and depending on the concentrations of the dipoles, a difference in threshold voltage (Vt) may occur in each of the transistors (TR1, TR2, TR3, TR4, TR5, TR6).

[0057] In an embodiment, the first dielectric layer 120a included in the first transistor (TR1) and the second dielectric layer 120b included in the second transistor (TR2) may include the same dielectric material. The conductivity type of the first active area ACT1 included in the first transistor (TR1) may be different from the conductivity type of the second active area ACT2 included in the second transistor (TR2).

[0058] In addition, the dipole concentration of the first dielectric layer 120a may be different from the dipole concentration of the second dielectric layer 120b. Figure 3 and FIG. 4A to FIG. 4G A method for controlling the dipole concentration of the first dielectric layer 120 a and the dipole concentration of the second dielectric layer 120 b is described in detail.

[0059] The third dielectric layer 120c included in the third transistor (TR3) and the fourth dielectric layer 120d included in the fourth transistor (TR4) may include the same dielectric material. However, the third dielectric layer 120c may include a different dielectric material from the first dielectric layer 120a.

[0060] In an embodiment, the semiconductor device 1 may control the threshold voltage of each of the transistors ( TR1 , TR2 , TR3 , TR4 , TR5 , TR6 ) by adjusting the concentration of the dielectric material included in the dielectric layer.

[0061] refer to Figure 1, the first dielectric layer 120a and the second dielectric layer 120b may include the same dielectric material, the third dielectric layer 120c and the fourth dielectric layer 120d may include the same dielectric material, and the fifth dielectric layer 120e and the sixth dielectric layer 120f may include the same dielectric material. In addition, the first dielectric layer 120a, the third dielectric layer 120c, and the fifth dielectric layer 120e may include different dielectric materials.

[0062] The gate electrodes (130a, 130b, 130c, 130d, 130e, 130f) may be disposed on the dielectric layers (120a, 120b, 120c, 120d, 120e, 120f), respectively.

[0063] The dielectric layers (120a, 120b, 120c, 120d, 120e, 120f) may be respectively disposed between the gate electrodes (130a, 130b, 130c, 130d, 130e, 130f) and the active regions (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6). In more detail, the dielectric layer 120a can be set between the gate electrode 130a and the active area (ACT1), the dielectric layer 120b can be set between the gate electrode 130b and the active area (ACT2), the dielectric layer 120c can be set between the gate electrode 130c and the active area (ACT3), the dielectric layer 120d can be set between the gate electrode 130d and the active area (ACT4), the dielectric layer 120e can be set between the gate electrode 130e and the active area (ACT5), and the dielectric layer 120f can be set between the gate electrode 130f and the active area (ACT6).

[0064] Each of the gate electrodes (130a, 130b, 130c, 130d, 130e, 130f) may include any one of tungsten (W), copper (Cu), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni) and conductive metal nitride or a combination thereof.

[0065] In an embodiment, the first to sixth gate electrodes ( 130 a , 130 b , 130 c , 130 d , 130 e , 130 f ) may include the same conductive material.

[0066] The threshold voltage may be affected by various factors, such as the work function difference between the gate electrode (e.g., 130a) and the semiconductor substrate 10, the dielectric constant of the interlayer dielectric layer (e.g., 110a) and the dielectric layer (e.g., 120a), and the thickness of the interlayer dielectric layer (e.g., 110a) and the dielectric layer (e.g., 120a).

[0067] The gate electrodes (130a, 130b, 130c, 130d, 130e, 130f) included in the first to sixth transistors (TR1, TR2, TR3, TR4, TR5, TR6) respectively included in the semiconductor device 1 can be formed of the same material and can respectively include interlayer dielectric layers (110a, 110b, 110c, 110d, 110e, 110f) having the same thickness, so that the threshold voltage of the first to sixth transistors (TR1, TR2, TR3, TR4, TR5, TR6) can be determined by the dielectric constant of the dielectric layer (120a, 120b, 120c, 120d, 120e, 120f).

[0068] In an embodiment, the dielectric constant of the dielectric layer (120a, 120b, 120c, 120d, 120e, 120f) may be determined by the concentration of dielectric materials constituting the sub-dielectric layers (eg, 122a and 124a) and the concentration of dipole materials included in the dielectric layer (eg, 120a).

[0069] Furthermore, the concentration of such dipole materials may be controlled depending on the type of dielectric material constituting the sub-dielectric layers (eg, 122a and 124a).

[0070] Hereinafter, a difference in threshold voltage depending on a specific dielectric material included in a dielectric layer will be described.

[0071] In an embodiment, the first sub-dielectric layer 122a included in the first dielectric layer 120a and the first sub-dielectric layer 122b included in the second dielectric layer 120b may be formed of hafnium silicate nitride (HfSiON), and the second sub-dielectric layer 124a included in the first dielectric layer 120a and the second sub-dielectric layer 124b included in the second dielectric layer 120b may be formed of hafnium oxynitride (HfON).

[0072] In addition, the third sub-dielectric layer 122c included in the third dielectric layer 120c and the third sub-dielectric layer 122d included in the fourth dielectric layer 120d may be formed of hafnium silicate (HfSiO), and the fourth sub-dielectric layer 124c included in the third dielectric layer 120c and the fourth sub-dielectric layer 124d included in the fourth dielectric layer 120d may be formed of hafnium oxynitride (HfON).

[0073] In addition, the fifth sub-dielectric layer 122e included in the fifth dielectric layer 120e and the fifth sub-dielectric layer 122f included in the sixth dielectric layer 120f may be formed of hafnium silicate (HfSiO), and the sixth sub-dielectric layer 124e included in the fifth dielectric layer 120e and the sixth sub-dielectric layer 124f included in the sixth dielectric layer 120f may be formed of hafnium oxide (HfO).

[0074] The dipole material diffused into the dielectric layers (120a, 120b, 120c, 120d, 120e, 120f) may be any one of hafnium (Hf), aluminum (Al), lanthanum (La), zirconium (Zr), scandium (Sc), and erbium (Er).

[0075] For example, the same type of dipole material (eg, lanthanum) is diffused into each of the dielectric layers (120a, 120b, 120c, 120d, 120e, 120f).

[0076] The diffusivity of the dipole material in the dielectric layer (120a, 120b, 120c, 120d, 120e, 120f) may vary depending on the type of dielectric material included in the dielectric layer (120a, 120b, 120c, 120d, 120e, 120f).

[0077] For example, the diffusivity of the dipole material may be determined according to whether the dielectric material contains nitrogen (N), or may also be determined according to the concentration of nitrogen (N).

[0078] In an embodiment, nitrogen (N) may hinder diffusion of the dipole material with respect to the dielectric material, and a concentration of nitrogen (N) and a diffusion rate of the dipole material may be inversely proportional to each other.

[0079] The concentration of the dipole material included in the first to sixth dielectric layers (120a, 120b, 120c, 120d, 120e, 120f) may vary according to the difference in diffusion rate. Specifically, the concentration of the dipole material included in the first dielectric layer 120a and the second dielectric layer 120b may be lower than the concentration of the dipole material included in the third dielectric layer 120c and the fourth dielectric layer 120d. In addition, the concentration of the dipole material included in the third dielectric layer 120c and the fourth dielectric layer 120d may be lower than the concentration of the dipole material included in the fifth dielectric layer 120e and the sixth dielectric layer 120f.

[0080] Therefore, in relation to the first to sixth dielectric layers (120a, 120b, 120c, 120d, 120e, 120f), the threshold voltage of each of the third dielectric layer 120c and the fourth dielectric layer 120d may be lower than the threshold voltage of each of the first dielectric layer 120a and the second dielectric layer 120b. In addition, the threshold voltage of each of the fifth dielectric layer 120e and the sixth dielectric layer 120f may be lower than the threshold voltage of each of the third dielectric layer 120c and the fourth dielectric layer 120d.

[0081] Will refer to FIG. 4A to FIG. 4G The manufacturing process of controlling the dielectric layers (120a, 120b, 120c, 120d, 120e, 120f) to have different dielectric materials is described in detail.

[0082] In an embodiment, a metal pattern layer may be disposed on a dielectric layer (120b, 120d, 120f) formed on an active region doped with a P-type impurity, and a dipole material may diffuse into the dielectric layer (120b, 120d, 120f) after passing through the metal pattern layer, so that the dipole concentration of the dielectric layers (e.g., 120a and 120b) containing the same dielectric material may be adjusted to vary. More specifically, a difference in the diffusivity of the dipole material may occur depending on the thickness of the metal pattern layer, and a difference in the threshold voltage may occur depending on the diffusivity of the dipole material.

[0083] Figure 2 is a cross-sectional view showing a semiconductor device 2 according to another embodiment of the present disclosure.

[0084] refer to Figure 2 , the semiconductor device 2 may include a plurality of transistors (TR7, TR8, TR9, TR10, TR11, TR12) disposed on a semiconductor substrate 20. The semiconductor substrate 20 may include a plurality of active regions (ACT7, ACT8, ACT9, ACT10, ACT11, ACT12) doped with N-type impurities or P-type impurities.

[0085] In an embodiment, the seventh active region (ACT7), the ninth active region (ACT9) and the eleventh active region (ACT11) may be regions doped with N-type impurities, and the eighth active region (ACT8), the tenth active region (ACT10) and the twelfth active region (ACT12) may be regions doped with P-type impurities.

[0086] Although not shown in the drawings, the active regions (ACT7, ACT8, ACT9, ACT10, ACT11, ACT12) may include source / drain regions, and the semiconductor substrate 20 may include isolation regions formed to isolate the plurality of transistors (TR7, TR8, TR9, TR10, TR11, TR12) from each other.

[0087] Interlayer dielectric layers (210a, 210b, 210c, 210d, 210e, 210f) may be formed on active regions (ACT7, ACT8, ACT9, ACT10, ACT11, ACT12), respectively. Although for ease of description, interlayer dielectric layers (210a, 210b, 210c, 210d, 210e, 210f) are provided for transistors (TR7, TR8, TR9, TR10, TR11, TR12), respectively, other embodiments are possible, and it should be noted that interlayer dielectric layers (210a, 210b, 210c, 210d, 210e, 210f) may also be formed as only one layer.

[0088] The interlayer dielectric layer (e.g., 210a) can reduce interface defects between the semiconductor substrate 20 and the dielectric layer (e.g., 220a). In an embodiment, the interlayer dielectric layer (e.g., 210a) can be formed of a low permittivity material having a low dielectric constant. For example, the interlayer dielectric layer (e.g., 210a) can include silicon oxide (SiO) or silicon oxynitride (SiON).

[0089] A plurality of dielectric layers (220a, 220b, 220c, 220d, 220e, 220f) may be disposed on the interlayer dielectric layers (210a, 210b, 210c, 210d, 210e, 210f), respectively. The dielectric layers (220a, 220b, 220c, 220d, 220e, 220f) may include a dipole material having a higher dielectric constant (i.e., a higher permittivity) than the interlayer dielectric layers (210a, 210b, 210c, 210d, 210e, 210f), respectively. In more detail, dielectric layer 220a may include a dipole material having a higher dielectric constant than interlayer dielectric layer 210a, dielectric layer 220b may include a dipole material having a higher dielectric constant than interlayer dielectric layer 210b, dielectric layer 220c may include a dipole material having a higher dielectric constant than interlayer dielectric layer 210c, dielectric layer 220d may include a dipole material having a higher dielectric constant than interlayer dielectric layer 210d, dielectric layer 220e may include a dipole material having a higher dielectric constant than interlayer dielectric layer 210e, and dielectric layer 220f may include a dipole material having a higher dielectric constant than interlayer dielectric layer 210f. For example, the dipole material may include hafnium (Hf), aluminum (Al), lanthanum (La), zirconium (Zr), scandium (Sc), erbium (Er), etc.

[0090] In an embodiment, each of the dielectric layers (220a, 220b, 220c, 220d, 220e, 220f) may be provided as a layered structure including a dielectric material. For example, the dielectric material may be formed of any one of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium zirconium oxide (HfZrO), hafnium zirconium silicate (HfSiZrO), hafnium oxynitride (HfON), and hafnium silicate nitride (HfSiON).

[0091] The dielectric layers (220a, 220b, 220c, 220d, 220e, 220f) may be layers including the same dielectric material, but concentrations of dipole materials respectively included in the dielectric layers (220a, 220b, 220c, 220d, 220e, 220f) may be different from each other.

[0092] Depending on the concentration of defects included in the dielectric layer, the diffusion rate of the dipole material may vary. In addition, the threshold voltage of each transistor (TR7, TR8, TR9, TR10, TR11, TR12) including the dielectric layer (e.g., 220a) may vary depending on the concentration of the dipole material.

[0093] When the defect concentration of the dielectric layer is high, the concentration of the dipole material diffused into the dielectric layer may increase. As the concentration of the dipole material increases, the dielectric constant may increase, so that the threshold voltage of the transistor (eg, TR1) including the dielectric layer (eg, 220a) may decrease.

[0094] The dielectric layers (220a, 220b, 220c, 220d, 220e, 220f) respectively included in the transistors may include different concentrations of dipoles, and depending on the concentrations of these dipoles, each of the transistors (TR7, TR8, TR9, TR10, TR11, TR12) may have a difference in threshold voltage (Vt).

[0095] The defect concentration of the dielectric layer (220a, 220b, 220c, 220d, 220e, 220f) may be controlled through a cleaning process.

[0096] The cleaning process may be a thermal treatment process in which oxygen included in the dielectric layer (eg, 220a) is diffused into a defect control layer disposed above the dielectric layer (eg, 220a), thereby controlling a defect concentration caused by oxygen vacancies in the dielectric layer (eg, 220a).

[0097] The defect-controlling layer may include a plurality of sub-controlling layers. In an embodiment, oxygen diffusion of the dielectric layer (eg, 220a) relative to the defect-controlling layer may be controlled according to the type of sub-controlling layers to be stacked.

[0098] For example, the sub-control layer may be formed of any one of titanium nitride (TiN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), and tantalum nitride (TaN). Depending on the composition and thickness of the sub-control layer, the degree of oxygen removal during the cleaning process may differ. The diffusion rate of the dipole material in the dielectric layer (e.g., 220a) may be controlled according to the defect concentration difference caused by oxygen removal.

[0099] Will refer to Figure 5 and FIG. 6A to FIG. 6I A method for controlling (or adjusting) the defect concentration of the dielectric layers (220a, 220b, 220c, 220d, 220e, 220f) is described in detail.

[0100] In an embodiment, semiconductor device 2 may include a plurality of dielectric layers having different defect concentrations, such that semiconductor device 2 can control (or adjust) threshold voltages of transistors ( TR7 , TR8 , TR9 , TR10 , TR11 , TR12 ).

[0101] exist Figure 2 In the embodiment, the seventh dielectric layer 220a and the eighth dielectric layer 220b may have the same defect concentration, the ninth dielectric layer 220c and the tenth dielectric layer 220d may have the same defect concentration, and the eleventh dielectric layer 220e and the twelfth dielectric layer 220f may have the same defect concentration. The dielectric layers (220a, 220b) of two transistors (e.g., TR7, TR8) adjacent to each other and having active regions of different impurity types may have the same defect concentration.

[0102] The gate electrodes (230a, 230b, 230c, 230d, 230e, 230f) may be disposed on the dielectric layers (220a, 220b, 220c, 220d, 220e, 220f), respectively.

[0103] The dielectric layers (220a, 220b, 220c, 220d, 220e, 220f) may be respectively disposed between the gate electrodes (230a, 230b, 230c, 230d, 230e, 230f) and the active regions (ACT7, ACT8, ACT9, ACT10, ACT11, ACT12). In more detail, the dielectric layer 220a can be set between the gate electrode 230a and the active area (ACT7), the dielectric layer 220b can be set between the gate electrode 230b and the active area (ACT8), the dielectric layer 220c can be set between the gate electrode 230c and the active area (ACT9), the dielectric layer 220d can be set between the gate electrode 230d and the active area (ACT10), the dielectric layer 220e can be set between the gate electrode 230e and the active area (ACT11), and the dielectric layer 220f can be set between the gate electrode 230f and the active area (ACT12).

[0104] Each of the gate electrodes (230a, 230b, 230c, 230d, 230e, 230f) may include any one of tungsten (W), copper (Cu), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni) and conductive metal nitride or a combination thereof.

[0105] In an embodiment, the seventh to twelfth gate electrodes ( 230 a , 230 b , 230 c , 230 d , 230 e , 230 f ) may include the same conductive material.

[0106] The threshold voltage may be affected by various factors, such as the work function difference between the gate electrode (e.g., 230a) and the semiconductor substrate 20, the dielectric constants of the interlayer dielectric layer (e.g., 210a) and the dielectric layer (e.g., 220a), and the thicknesses of the interlayer dielectric layer (e.g., 210a) and the dielectric layer (e.g., 220a).

[0107] The gate electrodes (230a, 230b, 230c, 230d, 230e, 230f) respectively included in the seventh to twelfth transistors (TR7, TR8, TR9, TR10, TR11, TR12) included in the semiconductor device 2 can be formed of the same material and can respectively include interlayer dielectric layers (210a, 210b, 210c, 210d, 210e, 210f) having the same thickness, so that the threshold voltage of the seventh to twelfth transistors (TR7, TR8, TR9, TR10, TR11, TR12) can be determined by the dielectric constant of the dielectric layer (220a, 220b, 220c, 220d, 220e, 220f).

[0108] In an embodiment, the dielectric constant of the dielectric layers (220a, 220b, 220c, 220d, 220e, 220f) may be determined according to the concentration of defects included in each dielectric layer (eg, 220a) and the concentration of the dipole material diffused into the defects.

[0109] In an embodiment, a metal pattern layer may be disposed on a dielectric layer (220b, 220d, 220f) formed on an active region doped with P-type impurities, and a dipole material may diffuse into the dielectric layer (220b, 220d, 220f) after passing through the metal pattern layer, so that the dipole concentration of dielectric layers (e.g., 220a and 220b) containing the same defect concentration may be adjusted to vary.

[0110] Figure 3 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0111] Figures 4A to 4G 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to various embodiments of the present disclosure.

[0112] Reference Figure 3 and Figure 4A, the first to sixth active regions (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6) may be defined in the semiconductor substrate 10, and interlayer dielectric layers (110a, 110b, 110c, 110d, 110e, 110f) may be formed on the active regions (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6), respectively (see S100).

[0113] In an embodiment, the semiconductor substrate 10 may be a single crystal silicon substrate, an epitaxial substrate formed by epitaxial growth, a silicon-on-insulator (SOI) substrate, or a germanium substrate.

[0114] In an embodiment, the first active region (ACT1), the third active region (ACT3) and the fifth active region (ACT5) may be regions doped with N-type impurities, and the second active region (ACT2), the fourth active region (ACT4) and the sixth active region (ACT6) may be regions doped with P-type impurities.

[0115] The active regions ( ACT1 , ACT2 , ACT3 , ACT4 , ACT5 , ACT6 ) may be defined by isolation regions included in the semiconductor substrate 10 .

[0116] The interlayer dielectric layers ( 110 a , 110 b , 110 c , 110 d , 110 e , 110 f ) may include silicon oxide (SiO) or silicon oxynitride (SiON), and may be formed through the same process.

[0117] A pre-lower dielectric layer (120a, 120b, 120c, 120d, 120e, 120f) may be formed on the interlayer dielectric layer (110a, 110b, 110c, 110d, 110e, 110f). For example, the pre-lower dielectric layer (120a, 120b, 120c, 120d, 120e, 120f) may be a layer including hafnium silicate (HfSiO).

[0118] refer to Figure 3 , Figure 4B , Figure 4C and Figure 4D , the properties of the sub-dielectric layers overlapping with different active regions may be adjusted by selectively performing a plasma nitridation process on the front lower dielectric layer (120a, 120b, 120c, 120d, 120e, 120f).

[0119] refer to Figure 4B, a silicon nitride layer 123 may be selectively formed on the front lower dielectric layer (120a, 120b, 120c, 120d, 120e, 120f) overlapping the remaining active areas except the first active area (ACT1) and the second active area (ACT 2), and a plasma nitridation process may be performed.

[0120] Nitrogen may be diffused into the first sub-dielectric layer (122a, 122b) overlapping the first active region (ACT1) and the second active region (ACT2) through a plasma nitridation process. Through the above plasma nitridation process, the first sub-dielectric layer (122a, 122b) may include hafnium silicate nitride (HfSiON).

[0121] The third sub-dielectric layer (122c, 122d) and the fifth sub-dielectric layer (122e, 122f) may be protected by the silicon nitride layer 123 to prevent nitrogen diffusion. Therefore, the third sub-dielectric layer (122c, 122d) and the fifth sub-dielectric layer (122e, 122f) may be layers formed of hafnium silicate (HfSiO).

[0122] refer to Figure 4C , the silicon nitride layer 123 may be removed, and a pre-upper dielectric layer 124 may be formed over the first sub-dielectric layer (122a, 122b), the third sub-dielectric layer (122c, 122d), and the fifth sub-dielectric layer (122e, 122f).

[0123] For example, the front upper dielectric layer 124 may be a layer including hafnium oxide (HfO). The silicon nitride layer 125 may be selectively formed on the front upper dielectric layer 124, and then a plasma nitridation process may be performed on the silicon nitride layer 125.

[0124] For example, the silicon nitride layer 125 may be formed on the front upper dielectric layer 124 overlapping the fifth active region (ACT5) and the sixth active region (ACT6), and a plasma nitridation process may be performed on the silicon nitride layer.

[0125] Nitrogen may be diffused into the second sub-dielectric layer (124a, 124b) and the fourth sub-dielectric layer (124c, 124d) by a plasma nitridation process. Here, the second sub-dielectric layer 124a may overlap with the first active region (ACT1), the second sub-dielectric layer 124b may overlap with the second active region (ACT2), the fourth sub-dielectric layer 124c may overlap with the third active region (ACT3), and the fourth sub-dielectric layer 124d may overlap with the fourth active region (ACT4). Through the above-mentioned plasma nitridation process, the second sub-dielectric layer (124a, 124b) and the fourth sub-dielectric layer (124c, 124d) may include hafnium oxynitride (HfON).

[0126] The sixth sub-dielectric layer (124e, 124f) may be protected by a silicon nitride layer to prevent nitrogen diffusion. Therefore, the sixth sub-dielectric layer (124e, 124f) may be a hafnium oxide (HfO) layer.

[0127] The first to sixth dielectric layers (120a, 120b, 120c, 120d, 120e, 120f) formed to overlap the active regions (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6) included in the semiconductor substrate 10, respectively, may be formed by depositing such dielectric layers and plasma nitridation processes. In addition, the dielectric layer may include sub-dielectric layers (122a, 122b, 122c, 122d, 122e, 122f, 124a, 124b, 124c, 124d, 124e, 124f). In more detail, the first dielectric layer may include some of the sub-dielectric layers (see S110), and the second dielectric layer may include the remaining sub-dielectric layers (see S120).

[0128] refer to Figure 4D , the metal pattern layer 126 can be selectively disposed on the dielectric layer (120b, 120d, 120f) located above the active area (ACT2, ACT4, ACT6) doped with P-type impurities. After the metal pattern layer 126 is formed on the entire active area (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6), at least a portion of the metal pattern layer can be patterned so that the resulting metal pattern layer 26 can be selectively disposed on the active area (ACT2, ACT4, ACT6) doped with P-type impurities (see S130).

[0129] The metal pattern layer 126 may include a first layer and a second layer arranged alternately. Here, the first layer may include any one of titanium nitride (TiN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN) and tantalum nitride (TaN), and the second layer may include any one of aluminum (Al), niobium (Nb) and tungsten (W).

[0130] refer to Figure 3 and Figure 4E , a dipole material layer 127 may be formed on the first dielectric layer 120a, the third dielectric layer 120c, the fifth dielectric layer 120e and the metal pattern layer 126 (see S140), and the dipole material may diffuse from the dipole material layer 127 into the dielectric layers (120a, 120b, 120c, 120d, 120e, 120f) (see S150).

[0131] For example, the dipole material may include hafnium (Hf), aluminum (Al), lanthanum (La), zirconium (Zr), scandium (Sc), erbium (Er), and the like.

[0132] The second dielectric layer 120 b , the fourth dielectric layer 120 d , and the sixth dielectric layer 120 f may be formed such that the dipole material may diffuse into the second, fourth, and sixth dielectric layers ( 120 b , 120 d , 120 f ) after passing through the metal pattern layer 126 .

[0133] Therefore, the second dielectric layer 120b may have a lower dipole material concentration than the first dielectric layer 120a, the fourth dielectric layer 120d may have a lower dipole material concentration than the third dielectric layer 120c, and the sixth dielectric layer 120f may have a lower dipole material concentration than the fifth dielectric layer 120e.

[0134] Furthermore, the diffusivity of the dipole material may be inversely proportional to the concentration of nitrogen contained in the dielectric layer, such that the first and second dielectric layers 120a and 120b may have the lowest dipole concentration, while the fifth and sixth dielectric layers 120e and 120f may have the highest dipole concentration.

[0135] refer to Figure 3 and Figure 4F , after the dipole diffusion, the metal pattern layer 126 and the dipole material layer 127 may be removed (see S160 ).

[0136] Since the metal pattern layer 126 is removed, the height of each constituent element included in the semiconductor substrate 10 can be uniformly controlled. However, in order to adjust the characteristics (such as work function, etc.) of the gate electrode, the metal pattern layer 126 may not be removed. In this case, the gate electrode layer may include the metal pattern layer 126.

[0137] refer to Figure 3 and Figure 4G , gate electrodes (130a, 130b, 130c, 130d, 130e, 130f) may be disposed on dielectric layers (120a, 120b, 120c, 120d, 120e, 120f), respectively (S170, S180).

[0138] Each of the gate electrodes (130a, 130b, 130c, 130d, 130e, 130f) may include any one of tungsten (W), copper (Cu), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni) and conductive metal nitride or a combination thereof.

[0139] Figure 5 is a flowchart illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0140] FIG. 6A to FIG. 6Iis a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0141] Reference Figure 5 and Fig. 6A , the seventh to twelfth active regions (ACT7, ACT8, ACT9, ACT10, ACT11, ACT12) may be defined in the semiconductor substrate 20, and interlayer dielectric layers (210a, 210b, 210c, 210d, 210e, 210f) may be formed on the active regions (ACT7, ACT8, ACT9, ACT10, ACT11, ACT12), respectively (see S300).

[0142] In an embodiment, semiconductor substrate 20 may be a single crystal silicon substrate, an epitaxial substrate formed by epitaxial growth, a silicon-on-insulator (SOI) substrate, or a germanium substrate.

[0143] In an embodiment, the seventh active region (ACT7), the ninth active region (ACT9) and the eleventh active region (ACT11) may be regions doped with N-type impurities, and the eighth active region (ACT8), the tenth active region (ACT10) and the twelfth active region (ACT12) may be regions doped with P-type impurities.

[0144] The active regions ( ACT7 , ACT8 , ACT9 , ACT10 , ACT11 , ACT12 ) may be defined by isolation regions included in the semiconductor substrate 20 .

[0145] The interlayer dielectric layers ( 210 a , 210 b , 210 c , 210 d , 210 e , 210 f ) may include silicon oxide (SiO) or silicon oxynitride (SiON), and may be formed through the same process.

[0146] A plurality of dielectric layers ( 220 a , 220 b , 220 c , 220 d , 220 e , 220 f ) may be formed on the interlayer dielectric layers ( 210 a , 210 b , 210 c , 210 d , 210 e , 210 f ), respectively (see S310 and S320 ).

[0147] Each of the dielectric layers (220a, 220b, 220c, 220d, 220e, 220f) may be formed as a layered structure including a dielectric material. For example, the dielectric material may be formed of any one of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium zirconium oxide (HfZrO), hafnium zirconium silicate (HfSiZrO), hafnium oxynitride (HfON), and hafnium silicate nitride (HfSiON).

[0148] The following will refer to Figure 5 and FIG. 6A to FIG. 6EA method for selectively forming a defect-controlling layer including different sub-controlling layers over a dielectric layer (220a, 220b, 220c, 220d, 220e, 220f) is described.

[0149] refer to Fig. 6A , a first metal layer 411 and a second metal layer 412 may be formed on the dielectric layer ( 220 a , 220 b , 220 c , 220 d , 220 e , 220 f ).

[0150] For example, the first metal layer 411 may be a titanium nitride (TiN) layer and may be deposited by a physical vapor deposition (PVD) process. In addition, the second metal layer 412 may be a titanium aluminide (TiAl) layer and may be deposited by an atomic layer deposition (ALD) process.

[0151] The following will refer to Figure 6B A method for adjusting the sub-control layer for each dielectric layer (220a, 220b, 220c, 220d, 220e, 220f) is described.

[0152] More specifically, a mask (MASK) may be disposed to overlap a portion of the semiconductor substrate 20 , and the second metal layer 412 may be selectively removed.

[0153] Reference Figure 6B , the mask can be set to overlap the seventh active region (ACT7), the eighth active region (ACT8), the ninth active region (ACT9) and the tenth active region (ACT 10), and the second metal layer 412 overlapping the eleventh active region (ACT11) and the twelfth active region (ACT 12) can be selectively removed.

[0154] Reference Figure 6C , the third metal layer 413 may be formed on the first metal layer 411 or the second metal layer 412. The third metal layer 413 may be a titanium nitride (TiN) layer, and may be deposited by a physical vapor deposition (PVD) process.

[0155] Reference Fig.6D , a mask (MASK) may be disposed to overlap a portion of the semiconductor substrate 20 , and the third metal layer 412 may be selectively removed.

[0156] The mask (MASK) may overlap the ninth active region (ACT9), the tenth active region (ACT10), the eleventh active region (ACT11), and the twelfth active region (ACT12), and may selectively remove the third metal layer 413 overlapping each of the seventh active region (ACT7) and the eighth active region (ACT8).

[0157] The following will refer to Fig. 6E A method for forming a polysilicon layer 414 over the second metal layer 412 or the third metal layer 413 and performing a cleaning process on the polysilicon layer 414 is described.

[0158] The defect-controlling layers (400a, 400b, 400c, 400d, 400e, 400f) respectively formed on the dielectric layers (220a, 220b, 220c, 220d, 220e, 220f) may include a plurality of sub-controlling layers made of different materials (see S330 and S340).

[0159] For example, each of the seventh defect-control layer 400a overlapping the seventh dielectric layer 220a and the eighth defect-control layer 400b overlapping the eighth dielectric layer 220b may include a first metal layer 411, a second metal layer 412, and a polysilicon layer 414 as sub-control layers.

[0160] The seventh defect-controlling layer 400 a and the eighth defect-controlling layer 400 b may include a PVD titanium nitride (TiN) layer and an ALD titanium aluminide (TiAl) layer.

[0161] Each of the ninth defect-control layer 400c overlapping the ninth dielectric layer 220c and the tenth defect-control layer 400d overlapping the tenth dielectric layer 220d may include a first metal layer 411, a second metal layer 412, a third metal layer 413, and a polysilicon layer 414 as sub-control layers.

[0162] Each of the ninth defect-control layer 400 c and the tenth defect-control layer 400 d may include a PVD titanium nitride (TiN) layer, an ALD titanium aluminide (TiAl) layer, and a PVD titanium nitride (TiN) layer.

[0163] Each of the eleventh defect-control layer 400e overlapping the eleventh dielectric layer 220e and the twelfth defect-control layer 400f overlapping the twelfth dielectric layer 220f may include a first metal layer 411, a third metal layer 413, and a polysilicon layer 414 as sub-control layers.

[0164] Each of the eleventh defect-control layer 400e and the twelfth defect-control layer 400f may include two PVD titanium nitride (TiN) layers.

[0165] The cleaning process may refer to a process of diffusing oxygen included in the dielectric layer into the defect control layer through a heat treatment (see S350 ). As a result, the defect concentration inside the dielectric layer may be controlled according to the amount of diffused oxygen.

[0166] Defects may refer to oxygen vacancies contained in the dielectric layer. As the defect concentration increases, the dipole material may diffuse more easily into the dielectric layer. Therefore, when the defect concentration of the dielectric layer is controlled by the defect control layer, the dipole concentration of the dielectric layer may be controlled. The threshold voltage of each transistor including the dielectric layer may be controlled by adjusting the dipole concentration.

[0167] The defect concentration distribution of the dielectric layer may vary according to the type of sub-control layers included in the defect-control layer and the thickness of each sub-control layer.

[0168] For example, the scavenging effect caused by titanium nitride (TiN) can be greater than the oxygen scavenging effect caused by titanium aluminide (TiAl). If the scavenging effect is large, the amount of oxygen to be removed from the dielectric layer can be increased, and the defect concentration inside the dielectric layer can also be increased, so that the dipole material can easily penetrate into the dielectric layer. Therefore, as the proportion of titanium nitride (TiN) included in the defect control layer increases, a dielectric layer with a lower threshold voltage can be obtained.

[0169] In an embodiment, the defect concentration of each of the seventh dielectric layer 220a and the eighth dielectric layer 220b may be lower than the defect concentration of each of the ninth dielectric layer 220c and the tenth dielectric layer 220d, and the defect concentration of each of the ninth dielectric layer 220c and the tenth dielectric layer 220d may be lower than the defect concentration of each of the eleventh dielectric layer 220e and the twelfth dielectric layer 220e. When the defect concentration is low, it is difficult for the dipole material to diffuse into the dielectric layer, so that the threshold voltage may be high.

[0170] The polysilicon layer 414 may prevent unintended oxidation from occurring in the defect-controlling layer during a cleaning process.

[0171] In some other embodiments, a polysilicon layer may be disposed between the sub-control layers so that the defect concentration of the dielectric layer due to oxygen removal may be controlled during the cleaning process.

[0172] More specifically, when the defect-controlling layer includes polysilicon and titanium nitride (TiN), the higher the ratio of titanium nitride (Ti) compared to polysilicon, the greater the oxygen removal effect during the cleaning process.

[0173] In addition, as the titanium nitride (TiN) layer is disposed closer to the dielectric layer, the oxygen removal effect caused by the cleaning process can be increased. Therefore, the ratio of polysilicon to titanium nitride (TiN) or the positional relationship between the polysilicon layer and the titanium nitride (TiN) layer can be controlled to adjust the defect concentration of the dielectric layer.

[0174] Reference Figure 5 and Fig. 6F, the defect control layer (400a, 400b, 400c, 400d, 400e, 400f) may be removed (see S360).

[0175] refer to Figure 6G The metal pattern layer 415 may be selectively formed on the dielectric layer (220b, 220d, 220f) disposed above the active region (ACT8, ACT10, ACT12) doped with P-type impurities.

[0176] After the metal pattern layer is formed on the entire active area (ACT7, ACT8, ACT9, ACT10, ACT11, ACT12), at least a portion of the metal pattern layer 415 can be patterned so that the resulting metal pattern layer 415 can be selectively disposed above the active area (ACT8, ACT10, ACT12) doped with P-type impurities (see S370).

[0177] The metal pattern layer 415 may include a first layer and a second layer arranged alternately. Here, the first layer may include any one of titanium nitride (TiN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN) and tantalum nitride (TaN), and the second layer may include any one of aluminum (Al), niobium (Nb) and tungsten (W).

[0178] Reference Figure 5 and Figure 6H , a dipole material layer 416 can be formed on the seventh dielectric layer 220a, the ninth dielectric layer 220c, the eleventh dielectric layer 220e and the metal pattern layer 415, and the dipole material can diffuse from the dipole material layer 416 to the dielectric layers (220a, 220b, 220c, 220d, 220e, 220f) (see S380 and S390).

[0179] For example, the dipole material may include hafnium (Hf), aluminum (Al), lanthanum (La), zirconium (Zr), scandium (Sc), erbium (Er), and the like.

[0180] The eighth dielectric layer 220b, the tenth dielectric layer 220d, and the twelfth dielectric layer 220f may be formed such that the dipole material may diffuse into the eighth, tenth, and twelfth dielectric layers (220b, 220d, 120f) after passing through the metal pattern layer 415. As a result, the eighth dielectric layer 220b may have a lower dipole material concentration than the seventh dielectric layer 220a, the tenth dielectric layer 220d may have a lower dipole material concentration than the ninth dielectric layer 220c, and the twelfth dielectric layer 220f may have a lower dipole material concentration than the eleventh dielectric layer 220e.

[0181] Furthermore, the diffusivity of the dipole material may be proportional to the concentration of defects included in the dielectric layer, such that the seventh and eighth dielectric layers 220a and 220b may have the lowest dipole concentration, and the eleventh and twelfth dielectric layers 220e and 220f may have the highest dipole concentration.

[0182] Reference Figure 5 and Fig.6I , after the dipole diffusion, the metal pattern layer 415 and the dipole material layer 416 may be removed (see S400). Since the metal pattern layer 415 is removed, the height of each constituent element included in the semiconductor substrate 20 may be uniformly controlled. However, in order to adjust the characteristics (such as work function, etc.) of the gate electrode, the metal pattern layer 415 may not be removed. In this case, the gate electrode layer may include the metal pattern layer 415.

[0183] Thereafter, gate electrodes (230a, 230b, 230c, 230d, 230e, 230f) may be disposed on the dielectric layers (220a, 220b, 220c, 220d, 220e, 220f), respectively (see S410 and S420).

[0184] Each of the gate electrodes (230a, 230b, 230c, 230d, 230e, 230f) may include any one of tungsten (W), copper (Cu), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni) and conductive metal nitride or a combination thereof.

[0185] As is apparent from the above description, the semiconductor device according to the embodiment of the present disclosure can adjust the threshold voltage of each transistor by adjusting the characteristics of the dielectric layer.

[0186] The embodiments of the present disclosure may provide various effects that can be directly or indirectly recognized through the above-mentioned present disclosure.

[0187] Those skilled in the art will appreciate that the present disclosure can be implemented in other specific ways than those set forth herein. In addition, claims not explicitly set forth in the appended claims may be set forth as a combination of embodiments, or may be included as new claims through subsequent amendments after application submission.

[0188] Although multiple exemplary embodiments of the present disclosure have been described, it should be understood that modifications and / or enhancements to the disclosed embodiments and other embodiments may be designed based on the content described and / or illustrated in the present disclosure. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: A semiconductor substrate including a first active region and a second active region; A first dielectric layer disposed on the first active region; a second dielectric layer disposed on the second active region; a first gate electrode disposed on the first dielectric layer; as well as a second gate electrode disposed on the second dielectric layer, in: The first active region and the second active region have different conductivity types, The first dielectric layer and the second dielectric layer include the same dielectric material, and The first dielectric layer has a dipole concentration that is different from the dipole concentration of the second dielectric layer.

2. The semiconductor device according to claim 1, wherein Each of the first dielectric layer and the second dielectric layer comprises: a first sub-dielectric layer; and The second sub-dielectric layer is disposed on the first sub-dielectric layer.

3. The semiconductor device according to claim 2, wherein: The first sub-dielectric layer and the second sub-dielectric layer have different silicon concentrations.

4. The semiconductor device according to claim 2, wherein: The first sub-dielectric layer and the second sub-dielectric layer have different nitrogen concentrations.

5. The semiconductor device according to claim 1, wherein Each of the first dielectric layer and the second dielectric layer includes defects where dipole diffusion occurs.

6. The semiconductor device according to claim 5, wherein: The concentration of the defects in the first dielectric layer and the concentration of the defects in the second dielectric layer are controlled by heat treatment.

7. The semiconductor device according to claim 1, wherein The first dielectric layer includes a dipole material diffused from an upper portion of the first dielectric layer to an inner portion of the first dielectric layer.

8. The semiconductor device according to claim 7, wherein: The dipole material includes at least one of hafnium Hf, aluminum Al, lanthanum La, zirconium Zr, scandium Sc and erbium Er.

9. The semiconductor device according to claim 1, wherein: The semiconductor substrate further comprises: a third active region and a fourth active region; a third gate electrode arranged to overlap the third active region; a fourth gate electrode arranged to overlap with the fourth active region; a third dielectric layer disposed between the third active region and the third gate electrode; and a fourth dielectric layer disposed between the fourth active region and the fourth gate electrode, in: The third active region and the fourth active region have different conductivity types, The first active region and the third active region have the same conductivity type, and The third dielectric layer and the fourth dielectric layer include the same dielectric material.

10. The semiconductor device according to claim 9, wherein The dipole concentration of the third dielectric layer is different from the dipole concentration of the fourth dielectric layer.

11. The semiconductor device according to claim 9, wherein: The first dielectric layer and the third dielectric layer include different dielectric materials.

12. The semiconductor device according to claim 9, wherein: Each of the third dielectric layer and the fourth dielectric layer comprises: a third sub-dielectric layer; and The fourth sub-dielectric layer is disposed on the third sub-dielectric layer.

13. The semiconductor device according to claim 9, wherein: The first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer include a same dielectric material.

14. A method for manufacturing a semiconductor device, the method comprising: forming a first dielectric layer over a first active region included in a semiconductor substrate; forming a second dielectric layer over a second active region included in the semiconductor substrate; forming a metal pattern layer on the second dielectric layer; forming a dipole material layer on the first dielectric layer and the metal pattern layer; diffusing a dipole material from the dipole material layer into the first dielectric layer and the second dielectric layer; forming a first gate electrode overlapping the first dielectric layer; as well as forming a second gate electrode overlapping the second dielectric layer, in: The first dielectric layer and the second dielectric layer include the same dielectric material, and The first active region and the second active region have different conductivity types.

15. The method according to claim 14, further comprising forming an interlayer dielectric layer over the first active region and the second active region, in, Forming the first dielectric layer includes: forming a first sub-dielectric layer overlapping the interlayer dielectric layer; and forming a second sub-dielectric layer overlapping the first sub-dielectric layer, and Wherein, forming the second dielectric layer comprises: forming the first sub-dielectric layer overlapping the interlayer dielectric layer; and The second sub-dielectric layer overlapping the first sub-dielectric layer is formed.

16. The method according to claim 14, further comprising: forming a first defect-controlling layer on the first dielectric layer; forming a second defect-controlling layer on the second dielectric layer; performing a thermal process to control a defect concentration of the first dielectric layer and a defect concentration of the second dielectric layer; and The first defect-controlling layer and the second defect-controlling layer are removed.

17. The method according to claim 16, wherein: The first defect-controlling layer or the second defect-controlling layer includes a plurality of sub-controlling layers.

18. The method according to claim 17, wherein: The plurality of sub-control layers include at least one of titanium nitride TiN, titanium aluminide TiAl, and polysilicon Si.

19. The method according to claim 14, further comprising: The metal pattern layer is removed.

20. The method according to claim 14, wherein: The dipole material includes at least one of hafnium Hf, aluminum Al, lanthanum La, zirconium Zr, scandium Sc and erbium Er.

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