Semiconductor device

Abstract

The embodiment of the invention relates to a semiconductor device. According to one embodiment, a semiconductor device includes a transistor region and a diode region. The transistor region includes: a first semiconductor region of a first conductivity type in a semiconductor layer; a second semiconductor region of a second conductivity type over the first semiconductor region; a third semiconductor region of the first conductivity type over the second semiconductor region; a fourth semiconductor region of the second conductivity type and a fifth semiconductor region of the first conductivity type, which are alternately arranged in the first direction on the third semiconductor region; a sixth semiconductor region of the first conductivity type between the third semiconductor region and the fourth semiconductor region, the sixth semiconductor region having a first conductivity type impurity concentration higher than that of the third semiconductor region and lower than that of the fifth semiconductor region; a first trench separated from the sixth semiconductor region; a gate electrode in the first trench; a first electrode having a first portion having a bottom surface in contact with the third semiconductor region and a side surface in contact with the fourth, fifth, and sixth semiconductor regions; and a second electrode.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2023-158094 (filing date: September 22, 2023). This application includes all the contents of this application by reference to the basic application. Technical Field

[0002] Embodiments of the present invention relate to a semiconductor device. Background Art

[0003] As an example of a semiconductor device for power, there is an Insulated Gate Bipolar Transistor (IGBT). For example, an IGBT is provided with a p-type collector region, an n-type drift region, and a p-type base region on a collector electrode. Moreover, a gate electrode is provided by sandwiching a gate insulating film in a groove that penetrates the p-type base region and reaches the n-type drift region. Furthermore, an n-type emitter region connected to an emitter electrode is provided in a region adjacent to the groove on the surface of the p-type base region.

[0004] In recent years, Reverse-Conducting IGBT (RC-IGBT) in which IGBT and freewheeling diode are formed on the same semiconductor chip has been widely developed and commercialized. RC-IGBT is used as a switching element of an inverter circuit, for example. The freewheeling diode has the function of causing current to flow in the opposite direction to the on-current of the IGBT. Forming the IGBT and the freewheeling diode on the same semiconductor chip has many advantages, such as reducing the chip size due to the sharing of the terminal area and dispersing the heat generating parts.

[0005] In RC-IGBT, the operation of IGBT and the operation of diode may interfere with each other, and the element characteristics of RC-IGBT may deteriorate. For example, when the diode is turned off, holes injected from the IGBT region at the boundary with the diode region may not be discharged, thereby increasing the reverse recovery current of the diode. If the reverse recovery current of the diode increases, the switching loss of the diode increases, and the switching loss of the RC-IGBT increases. Summary of the invention

[0006] A semiconductor device according to an embodiment of the present invention comprises a transistor region and a diode region, wherein the transistor region comprises: a semiconductor layer having a first surface and a second surface opposite to the first surface; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a second semiconductor region of a second conductivity type provided in the semiconductor layer and provided between the first semiconductor region and the first surface; a third semiconductor region of a first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first surface; a fourth semiconductor region of a second conductivity type and a fifth semiconductor region of a first conductivity type provided in the semiconductor layer and provided between the third semiconductor region and the first surface, and alternately arranged in a first direction parallel to the first surface; a sixth semiconductor region of a first conductivity type provided between the third semiconductor region and the fourth semiconductor region, wherein the first conductivity type impurity concentration is higher than the first conductivity type impurity concentration of the third semiconductor region, and the first conductivity type impurity concentration is lower than the first conductivity type impurity concentration of the fifth semiconductor region; a first trench provided on the first surface side of the semiconductor layer, extending in the first direction, repeatedly arranged in a second direction parallel to the first surface and perpendicular to the first direction, and alternately arranged with the first semiconductor region; The second semiconductor region, the third semiconductor region, the fourth semiconductor region and the fifth semiconductor region are in contact and separated from the sixth semiconductor region; a gate electrode is arranged in the first trench; a gate insulating film is arranged between the gate electrode and the third semiconductor region; a first electrode is arranged on the first surface side relative to the semiconductor layer, and has a first part, the bottom surface of the first part is in contact with the third semiconductor region, and the side surface of the first part is in contact with the fourth semiconductor region, the fifth semiconductor region and the sixth semiconductor region; and a second electrode is arranged on the second surface side relative to the semiconductor layer and in contact with the first semiconductor region, the diode region includes: the semiconductor layer; the second semiconductor region; a seventh semiconductor region of the second conductivity type is arranged in the semiconductor layer, arranged between the second semiconductor region and the second surface, and the second conductivity type impurity concentration is higher than the second conductivity type impurity concentration of the second semiconductor region; an eighth semiconductor region of the first conductivity type is arranged in the semiconductor layer, arranged between the second semiconductor region and the first surface; the first electrode is electrically connected to the eighth semiconductor region; and the second electrode is in contact with the seventh semiconductor region.

[0007] According to the present embodiment, it is possible to provide a semiconductor device including an RC-IGBT including an IGBT and a diode, and capable of reducing switching loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1It is a schematic diagram of the semiconductor device according to the first embodiment.

[0009] Figure 2 It is a schematic cross-sectional view of a part of the semiconductor device according to the first embodiment.

[0010] Figure 3 It is a schematic plan view of a part of the semiconductor device according to the first embodiment.

[0011] Figure 4 It is a schematic cross-sectional view of a part of the semiconductor device according to the first embodiment.

[0012] Figure 5 It is a schematic cross-sectional view of a part of a semiconductor device according to a comparative example.

[0013] Figure 6 It is a schematic top view of a part of a semiconductor device according to a comparative example.

[0014] Figure 7 It is a schematic cross-sectional view of a part of a semiconductor device according to a comparative example.

[0015] Figure 8 It is an explanatory diagram of a problem of a semiconductor device according to a comparative example.

[0016] Fig. 9 It is an explanatory diagram of the operation and effect of the semiconductor device according to the first embodiment.

[0017] Fig.10 It is an explanatory diagram of the operation and effect of the semiconductor device according to the first embodiment.

[0018] Fig.11 This is a schematic cross-sectional view of a portion of a semiconductor device according to a first modification of the first embodiment.

[0019] Fig.12 It is a schematic plan view of a part of a semiconductor device according to a first modification of the first embodiment.

[0020] Fig.13 This is a schematic cross-sectional view of a portion of a semiconductor device according to a first modification of the first embodiment.

[0021] Fig.14 It is a schematic cross-sectional view of a part of a semiconductor device according to a second modification of the first embodiment.

[0022] Fig.15 It is a schematic plan view of a part of a semiconductor device according to a second modification of the first embodiment.

[0023] Fig.16 It is a schematic cross-sectional view of a part of a semiconductor device according to a second modification of the first embodiment.

[0024] Fig.17 It is a schematic cross-sectional view of a part of the semiconductor device according to the second embodiment.

[0025] Fig.18 It is a schematic plan view of a part of the semiconductor device according to the second embodiment.

[0026] Fig.19 It is a schematic cross-sectional view of a part of the semiconductor device according to the second embodiment. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same reference numerals are given to the same or similar components, and the description of components that have been described once will be appropriately omitted.

[0028] In this specification, in the presence of n + Type, n-type, n - In the case of n-type marking, it means that the n-type impurity concentration is n + Type, n-type, n - In addition, in the presence of p + Type, p-type, p - In the case of a p-type mark, it means that the p-type impurity concentration is + Type, p-type, p - The order of type becomes lower.

[0029] In this specification, the n-type impurity concentration does not represent the actual n-type impurity concentration, but represents the effective n-type impurity concentration after compensation. Similarly, the p-type impurity concentration does not represent the actual p-type impurity concentration, but represents the effective p-type impurity concentration after compensation. For example, when the actual n-type impurity concentration is greater than the actual p-type impurity concentration, the concentration obtained by subtracting the p-type impurity concentration from the actual n-type impurity concentration is used as the n-type impurity concentration. The same is true for the p-type impurity concentration.

[0030] In this specification, the distribution and absolute value of the impurity concentration of a semiconductor region can be measured, for example, using Secondary Ion Mass Spectrometry (SIMS). In addition, the relative size relationship between the impurity concentrations of two semiconductor regions can be determined, for example, using Scanning Capacitance Microscopy (SCM). In addition, the distribution and absolute value of the impurity concentration can be measured, for example, using Spreading Resistance Analysis (SRA). In SCM and SRA, the relative size relationship and absolute value of the carrier concentration of the semiconductor region are determined. By assuming the activation rate of the impurity, the relative size relationship between the impurity concentrations of the two semiconductor regions, the distribution of the impurity concentrations, and the absolute value of the impurity concentrations can be determined based on the measurement results of SCM and SRA.

[0031] (First Embodiment)

[0032] A semiconductor device of a first embodiment has a transistor region and a diode region, wherein the transistor region includes: a semiconductor layer having a first surface and a second surface opposite to the first surface; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a second semiconductor region of a second conductivity type provided in the semiconductor layer and provided between the first semiconductor region and the first surface; a third semiconductor region of a first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first surface; a fourth semiconductor region of a second conductivity type and a fifth semiconductor region of a first conductivity type provided in the semiconductor layer and provided between the third semiconductor region and the first surface, and alternately arranged in a first direction parallel to the first surface; a sixth semiconductor region of a first conductivity type provided between the third semiconductor region and the fourth semiconductor region, wherein the first conductivity type impurity concentration is higher than the first conductivity type impurity concentration of the third semiconductor region and the first conductivity type impurity concentration is lower than the first conductivity type impurity concentration of the fifth semiconductor region; a first trench provided on the first surface side in the semiconductor layer, extending in the first direction, and extending in a second direction parallel to the first surface and perpendicular to the first direction. The diode region comprises: a semiconductor layer; a second semiconductor region; a seventh semiconductor region of the second conductivity type, which is arranged in the semiconductor layer and between the second semiconductor region and the second surface, and the second conductivity type impurity concentration is higher than the second conductivity type impurity concentration of the second semiconductor region; an eighth semiconductor region of the first conductivity type, which is arranged in the semiconductor layer and between the second semiconductor region and the first surface; the first electrode is electrically connected to the eighth semiconductor region; and the second electrode is in contact with the seventh semiconductor region.

[0033] The semiconductor device of the first embodiment is an RC-IGBT 100 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip. The RC-IGBT 100 has a trench gate IGBT having a gate electrode in a trench formed in a semiconductor layer. The following description will be given by taking the case where the first conductivity type is p-type and the second conductivity type is n-type as an example.

[0034] Figure 1 It is a schematic diagram of the semiconductor device according to the first embodiment.

[0035] Figure 2It is a schematic cross-sectional view of a part of the semiconductor device according to the first embodiment. Figure 2 yes Figure 1 AA' section.

[0036] Figure 3 It is a schematic plan view of a part of the semiconductor device according to the first embodiment. Figure 3 It is a top view of the first surface F1. Figure 2 yes Figure 3 AA' section.

[0037] Figure 4 It is a schematic cross-sectional view of a part of the semiconductor device according to the first embodiment. Figure 4 yes Figure 3 BB' cross section.

[0038] The semiconductor device of the first embodiment is an RC-IGBT 100. The RC-IGBT 100 includes a transistor region 101 and a diode region 102. The transistor region 101 operates as an IGBT, and the diode region 102 operates as a freewheeling diode.

[0039] The RC-IGBT 100 of the first embodiment has a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a gate electrode 16, a first conductive layer 18, a second conductive layer 20, a gate insulating film 22, a first insulating film 24, a second insulating film 26, an interlayer insulating layer 28 and a gate electrode pad 103.

[0040] The upper electrode 12 has a first trench contact portion 12 x (first portion).

[0041] In the semiconductor layer 10, there are provided a gate trench 31 (first trench), a first dummy trench 32 (second trench), a second dummy trench 33 (third trench), a collector region 41 (first semiconductor region), a drift region 42 (second semiconductor region), a base region 43 (third semiconductor region), an emitter region 44 (fourth semiconductor region), a unit contact region 45 (fifth semiconductor region), a resistance reduction region 46 (sixth semiconductor region), a barrier region 47 (tenth semiconductor region), a cathode region 51 (seventh semiconductor region), an anode region 52 (eighth semiconductor region) and a diode contact region 53 (ninth semiconductor region).

[0042] Semiconductor layer 10 has first surface F1 and second surface F2 facing first surface F1. First surface F1 and second surface F2 are, for example, substantially parallel to each other.

[0043] The semiconductor layer 10 is, for example, single crystal silicon and has a thickness of, for example, 40 μm or more and 700 μm or less.

[0044] In this specification, a direction parallel to the first surface F1 is referred to as a first direction. In addition, a direction parallel to the first surface F1 and orthogonal to the first direction is referred to as a second direction. In addition, in this specification, "depth" is defined as a distance in a direction toward the second surface F2 based on the first surface F1.

[0045] The transistor region 101 includes a semiconductor layer 10 , an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a gate electrode 16 , a first conductive layer 18 , a gate insulating film 22 , a first insulating film 24 , and an interlayer insulating layer 28 .

[0046] In the semiconductor layer 10 of the transistor region 101, there are provided a gate trench 31 (first trench), a first dummy trench 32 (second trench), a collector region 41 (first semiconductor region), a drift region 42 (second semiconductor region), a base region 43 (third semiconductor region), an emitter region 44 (fourth semiconductor region), a unit contact region 45 (fifth semiconductor region), a resistance reduction region 46 (sixth semiconductor region) and a barrier region 47 (tenth semiconductor region).

[0047] The upper electrode 12 is provided on the first surface F1 side of the semiconductor layer 10. The upper electrode 12 functions as an emitter electrode of the IGBT in the transistor region 101.

[0048] The upper electrode 12 has a first trench contact portion 12x. The first trench contact portion 12x is formed in a trench provided in the semiconductor layer 10. The first trench contact portion 12x extends in a first direction.

[0049] The bottom surface of the first trench contact portion 12x contacts the base region 43. The side surface of the first trench contact portion 12x contacts, for example, the base region 43, the emitter region 44, the cell contact region 45, and the resistance reduction region 46. The first trench contact portion 12x is electrically connected to the base region 43, the emitter region 44, the cell contact region 45, and the resistance reduction region 46.

[0050] The contact between the first trench contact 12x and the base region 43 is, for example, a Schottky contact. The contact between the first trench contact 12x and the emitter region 44 and the cell contact region 45 is, for example, an ohmic contact. The contact between the trench contact 12x and the resistance reduction region 46 is a Schottky contact or an ohmic contact. The contact between the trench contact 12x and the resistance reduction region 46 is preferably an ohmic contact.

[0051] The upper electrode 12 is, for example, a metal or a metal compound. The first trench contact portion 12x and the portion other than the first trench contact portion 12x are formed of, for example, the same material. The first trench contact portion 12x and the portion other than the first trench contact portion 12x may also be formed of different materials.

[0052] Lower electrode 14 is provided on the second surface F2 side of semiconductor layer 10. At least a portion of lower electrode 14 is in contact with second surface F2 of semiconductor layer 10. Lower electrode 14 functions as a collector of the IGBT in transistor region 101.

[0053] The lower electrode 14 is in contact with the collector region 41 in the transistor region 101. The lower electrode 14 is electrically connected to the collector region 41 in the transistor region 101.

[0054] The lower electrode 14 is made of, for example, metal or a metal compound.

[0055] The collector region 41 is p + The collector region 41 is in contact with the second surface F2. The collector region 41 is electrically connected to the lower electrode 14. The collector region 41 is in contact with the lower electrode 14. The collector region 41 becomes a source of holes when the IGBT is in the on state.

[0056] The collector region 41 contains p-type impurities. The p-type impurities are, for example, boron (B). The p-type impurity concentration of the collector region 41 is, for example, 1×10 18 cm -3 Above and 1×10 21 cm -3 the following.

[0057] The drift region 42 is n - The drift region 42 is provided between the collector region 41 and the first face F1.

[0058] The drift region 42 serves as a path for an on-current when the IGBT is in an on-state. The drift region 42 has a function of being depleted when the IGBT is in an off-state to maintain the withstand voltage of the IGBT.

[0059] The drift region 42 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the drift region 42 is, for example, 1×10 15 cm -3 Above and 1×10 18 cm -3 the following.

[0060] The base region 43 is p -The base region 43 is provided between the drift region 42 and the first face F1 . The base region 43 sandwiches the drift region 42 with the collector region 41 .

[0061] The depth of the base region 43 is, for example, 5 μm or less. In a region of the base region 43 facing the gate electrode 16 , an n-type inversion layer is formed when the IGBT is in an on state. The base region 43 functions as a channel region of the IGBT.

[0062] The base region 43 contains a p-type impurity. The p-type impurity is, for example, boron (B). The p-type impurity concentration of the base region 43 is, for example, 5×10 16 cm -3 Above and 5×10 17 cm -3 the following.

[0063] The emitter region 44 is n + The emitter region 44 is provided between the base region 43 and the first face F1. The emitter region 44 is in contact with the first face F1.

[0064] The emitter region 44 is in contact with the gate trench 31 and the first dummy trench 32. The emitter region 44 is in contact with the gate insulating film 22 and the first insulating film 24.

[0065] The emitter region 44 is in contact with the first trench contact portion 12x of the upper electrode 12. The emitter region 44 is electrically connected to the upper electrode 12. The emitter region 44 serves as a supply source of electrons when the IGBT is in an on state.

[0066] The emitter region 44 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the emitter region 44 is higher than the n-type impurity concentration of the drift region 42. The n-type impurity concentration of the emitter region 44 is, for example, 1×10 19 cm -3 Above and 1×10 21 cm -3 the following.

[0067] The cell contact region 45 is p + The cell contact region 45 is provided between the base region 43 and the first plane F1. The cell contact region 45 is in contact with the first plane F1.

[0068] The cell contact region 45 is in contact with the gate trench 31 and the first dummy trench 32. The cell contact region 45 is in contact with the gate insulating film 22 and the first insulating film 24.

[0069] The cell contact region 45 is in contact with the first trench contact portion 12 x of the upper electrode 12 . The cell contact region 45 is electrically connected to the upper electrode 12 .

[0070] The cell contact region 45 contains a p-type impurity. The p-type impurity is, for example, boron (B). The p-type impurity concentration of the cell contact region 45 is higher than the p-type impurity concentration of the base region 43. The p-type impurity concentration of the cell contact region 45 is, for example, 5×10 19 cm -3 Above and 1×10 21 cm -3 the following.

[0071] like Figure 3 As shown, emitter regions 44 and cell contact regions 45 are alternately arranged along the first direction on first plane F1. The width of emitter regions 44 in the first direction of first plane F1 is, for example, smaller than the width of cell contact regions 45 in the first direction of first plane F1.

[0072] The resistance reduction region 46 is a p-type semiconductor region. The resistance reduction region 46 is provided between the base region 43 and the emitter region 44. The resistance reduction region 46 is in contact with the base region 43 and the emitter region 44, for example.

[0073] The resistance reducing region 46 is, for example, provided between the base region 43 and the cell contact region 45. The resistance reducing region 46 is, for example, in contact with the base region 43 and the cell contact region 45. The resistance reducing region 46 extends, for example, along the first direction.

[0074] The resistance reduction region 46 is in contact with the first trench contact portion 12 x of the upper electrode 12 . The resistance reduction region 46 is in contact with the side surface of the first trench contact portion 12 x . The resistance reduction region 46 is electrically connected to the upper electrode 12 .

[0075] The resistance reduction region 46 is separated from the gate trench 31. The resistance reduction region 46 is separated from the gate insulating film 22. The resistance reduction region 46 is provided, for example, between the gate trench 31 and the first trench contact portion 12x. For example, the base region 43 is provided between the resistance reduction region 46 and the gate trench 31. The base region 43 between the resistance reduction region 46 and the gate trench 31 functions as a channel region of the IGBT.

[0076] The resistance reduction region 46 is in contact with the first dummy trench 32. The resistance reduction region 46 is in contact with the first insulating film 24.

[0077] The depth of the resistance reduction region 46 is shallower than the depth of the first trench contact 12 x .

[0078] The resistance reduction region 46 reduces the resistance of the lower part of the emitter region 44. The resistance reduction region 46 functions as a path for holes to be discharged to the upper electrode 12 during the IGBT's off operation. By providing the resistance reduction region 46, the operation of the parasitic npn transistor is suppressed, and the latch-up resistance of the RC-IGBT 100 is improved. In addition, the resistance reduction region 46 contacts the first dummy trench 32, whereby the hole current is discharged along the side wall of the first dummy trench 32, and thus the resistance reduction region 46 functions effectively. Therefore, compared with the case where the resistance reduction region 46 is not in contact with the first dummy trench 32, the latch-up resistance can be improved.

[0079] The resistance reduction region 46 contains a p-type impurity. The p-type impurity is, for example, boron (B). The p-type impurity concentration of the resistance reduction region 46 is higher than the p-type impurity concentration of the base region 43 and lower than the p-type impurity concentration of the cell contact region 45. The p-type impurity concentration of the resistance reduction region 46 is, for example, 5×10 17 cm -3 Above and 1×10 19 cm -3 the following.

[0080] The barrier region 47 is an n-type semiconductor region and is provided between the drift region 42 and the base region 43 .

[0081] The barrier region 47 has a function of promoting storage of carriers and reducing on-resistance when the IGBT is in an on-state.

[0082] The barrier region 47 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The concentration of the n-type impurities in the barrier region 47 is, for example, 5×10 15 cm -3 And 5×10 18 cm -3 the following.

[0083] The gate trench 31 is provided on the first surface F1 side of the semiconductor layer 10 . The gate trench 31 is a trench provided in the semiconductor layer 10 . The gate trench 31 is a part of the semiconductor layer 10 .

[0084] like Figure 3 As shown, the gate trench 31 extends in a first direction parallel to the first plane F1 at the first plane F1. The gate trench 31 has a stripe shape. A plurality of gate trenches 31 are repeatedly arranged in a second direction orthogonal to the first direction.

[0085] The gate trench 31 contacts the drift region 42, the barrier region 47, the base region 43, the emitter region 44, and the cell contact region 45. The gate trench 31 is separated from the resistance reduction region 46. This is because, when the resistance reduction region contacts the gate trench 31, the impurity concentration is higher than that of the base region 43, so the threshold is higher than the expected value, making it difficult to drive. The gate trench 31 penetrates the base region 43 and the barrier region 47 and reaches the drift region 42. The depth of the gate trench 31 is, for example, 8 μm or less.

[0086] The gate electrode 16 is provided in the gate trench 31 . The gate electrode 16 is, for example, a semiconductor or a metal. The gate electrode 16 is, for example, amorphous silicon or polysilicon containing n-type impurities or p-type impurities. The gate electrode 16 is electrically connected to the gate electrode pad 103 .

[0087] The gate insulating film 22 is provided between the gate electrode 16 and the semiconductor layer 10. The gate insulating film 22 is provided between the gate electrode 16 and the drift region 42, between the gate electrode 16 and the base region 43, between the gate electrode 16 and the emitter region 44, and between the gate electrode 16 and the cell contact region 45. The gate insulating film 22 is, for example, silicon oxide.

[0088] The first dummy trench 32 is provided on the first surface F1 side of the semiconductor layer 10 . The first dummy trench 32 is a trench provided in the semiconductor layer 10 . The first dummy trench 32 is a part of the semiconductor layer 10 .

[0089] like Figure 3 As shown, the first dummy trench 32 extends along a first direction parallel to the first surface F1 at the first surface F1. The first dummy trench 32 has a stripe shape. A plurality of first dummy trenches 32 are repeatedly arranged in a second direction orthogonal to the first direction. The first dummy trench 32 is provided between two adjacent gate trenches 31.

[0090] The first dummy trench 32 contacts the drift region 42, the barrier region 47, the base region 43, the emitter region 44, the cell contact region 45, and the resistance reduction region 46. The first dummy trench 32 penetrates the base region 43 and the barrier region 47 to reach the drift region 42. The depth of the first dummy trench 32 is, for example, 8 μm or less.

[0091] The first conductive layer 18 is disposed in the first dummy trench 32. The first conductive layer 18 is, for example, a semiconductor or a metal. The first conductive layer 18 is, for example, amorphous silicon or polysilicon containing n-type impurities or p-type impurities.

[0092] First conductive layer 18 is electrically connected to upper electrode 12, for example. First conductive layer 18 may be connected to an electrode other than upper electrode 12, and a voltage different from that of upper electrode 12 may be applied to first conductive layer 18. First conductive layer 18 may be electrically connected to gate electrode pad 103, for example.

[0093] The first insulating film 24 is provided between the first conductive layer 18 and the semiconductor layer 10. The first insulating film 24 is provided between the first conductive layer 18 and the drift region 42, between the first conductive layer 18 and the base region 43, between the first conductive layer 18 and the emitter region 44, between the first conductive layer 18 and the cell contact region 45, and between the first conductive layer 18 and the resistance reduction region 46. The first insulating film 24 is, for example, silicon oxide.

[0094] The interlayer insulating layer 28 is provided between the gate electrode 16 and the upper electrode 12. The interlayer insulating layer 28 electrically separates the gate electrode 16 from the upper electrode 12. For example, the first conductive layer 18 and the upper electrode 12 are electrically connected using an opening provided in the interlayer insulating layer 28. The interlayer insulating layer 28 is, for example, silicon oxide.

[0095] The diode region 102 includes a semiconductor layer 10 , an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a second conductive layer 20 , and a second insulating film 26 .

[0096] In the semiconductor layer 10 of the diode region 102, a second dummy trench 33 (third trench), a drift region 42 (second semiconductor region), a cathode region 51 (seventh semiconductor region), an anode region 52 (eighth semiconductor region) and a diode contact region 53 (ninth semiconductor region) are provided.

[0097] The upper electrode 12 functions as an anode electrode of the diode in the diode region 102. The upper electrode 12 is in contact with the anode region 52 and the diode contact region 53. The upper electrode 12 is electrically connected to the anode region 52 and the diode contact region 53.

[0098] The contact between the upper electrode 12 and the diode contact region 53 is, for example, an ohmic contact. In addition, the contact between the upper electrode 12 and the anode region 52 is, for example, a Schottky contact.

[0099] The upper electrode 12 is in contact with the anode region 52 on the first surface F1 . The position where the upper electrode 12 is in contact with the anode region 52 is shallower than the depth of the diode contact region 53 .

[0100] The lower electrode 14 functions as a cathode electrode of the diode in the diode region 102 . The lower electrode 14 is in contact with the cathode region 51 .

[0101] The cathode region 51 is n+ The cathode region 51 is in contact with the second surface F2. The cathode region 51 becomes a supply source of electrons when the diode is in the on state. The cathode region 51 is in contact with the lower electrode 14.

[0102] The drift region 42 is n - The drift region 42 is provided between the cathode region 51 and the first surface F1. The n-type impurity concentration of the drift region 42 is lower than the n-type impurity concentration of the cathode region 51.

[0103] The drift region 42 serves as a path for an on-current when the diode is in an on-state.

[0104] The anode region 52 is a p-type semiconductor region. The anode region 52 is provided between the drift region 42 and the first surface F1 . The anode region 52 sandwiches the drift region 42 with the cathode region 51 .

[0105] The anode region 52 serves as a source of holes when the diode is in an on state.

[0106] The diode contact region 53 is p + The diode contact region 53 is provided between the anode region 52 and the first surface F1.

[0107] The diode contact region 53 is in contact with the upper electrode 12. The diode contact region 53 is electrically connected to the upper electrode 12.

[0108] The p-type impurity concentration of the diode contact region 53 is higher than the p-type impurity concentration of the anode region 52 .

[0109] The second dummy trench 33 is provided on the first surface F1 side of the semiconductor layer 10 . The second dummy trench 33 is a trench provided in the semiconductor layer 10 . The second dummy trench 33 is a part of the semiconductor layer 10 .

[0110] like Figure 3 As shown, the second dummy trench 33 extends along a first direction parallel to the first plane F1 at the first plane F1. The second dummy trench 33 has a stripe shape. A plurality of second dummy trenches 33 are repeatedly arranged in a second direction orthogonal to the first direction.

[0111] The second dummy trench 33 contacts the drift region 42, the anode region 52, and the diode contact region 53. The second dummy trench 33 penetrates the anode region 52 and reaches the drift region 42. The depth of the second dummy trench 33 is, for example, 8 μm or less.

[0112] The second conductive layer 20 is disposed in the second dummy trench 33. The second conductive layer 20 is, for example, a semiconductor or a metal. The second conductive layer 20 is, for example, amorphous silicon or polysilicon containing n-type impurities or p-type impurities.

[0113] The second conductive layer 20 is electrically connected to, for example, the upper electrode 12. The second conductive layer 20 may be connected to an electrode other than the upper electrode 12, and a voltage different from that of the upper electrode 12 may be applied to the second conductive layer 20.

[0114] The second insulating film 26 is provided between the second conductive layer 20 and the semiconductor layer 10. The second insulating film 26 is provided between the second conductive layer 20 and the drift region 42, between the second conductive layer 20 and the anode region 52, and between the second conductive layer 20 and the diode contact region 53. The second insulating film 26 is in contact with the drift region 42, the anode region 52, and the diode contact region 53. The second insulating film 26 is, for example, silicon oxide.

[0115] The interlayer insulating layer 28 is provided between the second conductive layer 20 and the upper electrode 12. For example, the second conductive layer 20 and the upper electrode 12 are electrically connected using an opening provided in the interlayer insulating layer 28.

[0116] The gate electrode pad 103 is provided on the first surface F1 side of the semiconductor layer 10. The gate electrode pad 103 is electrically connected to the gate electrode 16. The gate electrode pad 103 and the gate electrode 16 are connected by, for example, a metal wire (not shown).

[0117] A gate voltage is applied to the gate electrode pad 103 .

[0118] Next, the operation and effects of the semiconductor device according to the first embodiment will be described.

[0119] The RC-IGBT 100 of the first embodiment can achieve both reduction in switching loss and improvement in latch-up tolerance. The RC-IGBT 100 has a first trench contact portion 12x and a resistance reduction region 46 in a transistor region 101. Moreover, the bottom surface of the first trench contact portion 12x is in contact with the base region 43. In particular, the RC-IGBT 100 can achieve both reduction in switching loss and improvement in latch-up tolerance by having the above-mentioned structure. This will be described in detail below.

[0120] Figure 5 It is a schematic cross-sectional view of a part of a semiconductor device according to a comparative example. Figure 5 yes Figure 6 XX' section. Figure 5 The first embodiment Figure 2 The corresponding figure.

[0121] Figure 6 It is a schematic top view of a part of a semiconductor device according to a comparative example. Figure 6 It is a top view of the first surface F1. Figure 6 The first embodiment Figure 3 The corresponding figure.

[0122] Figure 7 It is a schematic cross-sectional view of a part of a semiconductor device according to a comparative example. Figure 7 yes Figure 6 YY' section. Figure 7 The first embodiment Figure 4 The corresponding figure.

[0123] The semiconductor device of the comparative example is an RC-IGBT 900. The RC-IGBT 900 is different from the RC-IGBT 100 of the first embodiment in that it does not have the resistance reduction region 46 and in that it provides the p-type region 55.

[0124] The p-type region 55 is a p-type semiconductor region. The p-type region 55 is provided between the base region 43 and the first trench contact portion 12 x. The p-type region 55 is in contact with the bottom surface of the first trench contact portion 12 x.

[0125] The p-type impurity concentration of the p-type region 55 is higher than the p-type impurity concentration of the base region 43. The contact between the first trench contact portion 12x and the p-type region 55 is, for example, an ohmic contact.

[0126] The RC-IGBT 900 of the comparative example has a p-type region 55 in contact with the bottom surface of the first trench contact portion 12x. Since the p-type region 55 is provided, the discharge of holes from the p-type region 55 to the upper electrode 12 is promoted during the turn-off operation of the IGBT. Therefore, the operation of the parasitic npn transistor in the transistor region is suppressed. Therefore, the latch-up tolerance of the RC-IGBT 900 is improved.

[0127] Figure 8 It is an explanatory diagram of a problem of a semiconductor device according to a comparative example. Figure 8 is with Figure 5 The corresponding figure. Figure 8 This is a diagram showing the flow of holes when the diode operates stably.

[0128] like Figure 8 As shown, in the transistor region 101 close to the boundary with the diode region 102, when the diode is operating stably, the amount of holes injected from the base region 43 into the drift region 42 is large. Therefore, when the diode is operating stably, the amount of holes injected from the transistor region 101 into the drift region 42 of the diode region 102 increases.

[0129] It is considered that the reason why the amount of holes injected into the transistor region 101 of the RC-IGBT 900 of the comparative example becomes large is that the amount of holes injected from the p-type region 55 at the bottom of the first trench contact 12 x is large.

[0130] Fig. 9It is an explanatory diagram of the operation and effect of the semiconductor device according to the first embodiment. Fig. 9 is with Figure 2 The corresponding figure. Fig. 9 This is a diagram showing the flow of holes when the diode operates stably.

[0131] like Fig. 9 As shown, the amount of holes injected into the transistor region 101 near the boundary with the diode region 102 is smaller than that in the comparative example. The RC-IGBT 100 of the first embodiment does not have the p-type region 55 at the bottom of the first trench contact 12x. Therefore, it can be considered that this is because the injection of holes from the bottom of the first trench contact 12x does not occur.

[0132] Furthermore, in the RC-IGBT 100 of the first embodiment, during diode stable operation, electrons pass through the contact surface between the bottom surface of the first trench contact portion 12x of the Schottky contact and the base region 43 and are discharged to the upper electrode 12. Therefore, it is considered that injection of holes from the base region 43 into the drift region 42 is suppressed.

[0133] Fig.10 It is an explanatory diagram of the operation and effect of the semiconductor device according to the first embodiment. Fig.10 It is a diagram showing the current characteristics of the diodes of the RC-IGBT 100 of the first embodiment and the RC-IGBT 900 of the comparative example.

[0134] When the diode is in stable operation, if the amount of holes injected from the transistor region 101 close to the boundary with the diode region 102 into the diode region 102 is large, the amount of holes to be discharged to the upper electrode 12 during the diode cutoff operation increases. If the amount of holes to be discharged from the upper electrode 12 increases, the reverse recovery current of the diode increases. If the reverse recovery current of the diode increases, the switching loss of the diode increases.

[0135] The amount of holes injected from the transistor region 101 to the diode region 102 during the diode stabilization operation of the RC-IGBT 100 of the first embodiment is smaller than that of the RC-IGBT 900 of the comparative example. Fig.10 As shown, the reverse recovery current of the diode of the RC-IGBT 100 of the first embodiment is smaller than that of the comparative example RC-IGBT 900. Therefore, the switching loss of the diode of the RC-IGBT 100 of the first embodiment is smaller.

[0136] The RC-IGBT 100 of the first embodiment does not have the p-type region 55 at the bottom of the first trench contact 12x. However, the RC-IGBT 100 has the p-type resistance reduction region 46 between the base region 43 and the emitter region 44. The p-type resistance reduction region 46 is in contact with the side surface of the first trench contact 12x.

[0137] The RC-IGBT 100 of the first embodiment has the resistance reduction region 46 in contact with the side surface of the first trench contact portion 12x, and thus, when the IGBT is turned off, the discharge of holes from the resistance reduction region 46 to the upper electrode 12 is promoted. Therefore, the operation of the parasitic npn transistor in the transistor region 101 is suppressed. Therefore, the latch-up tolerance of the RC-IGBT 100 is improved.

[0138] As described above, according to the RC-IGBT 100 of the first embodiment, it is possible to achieve both reduction in switching loss and improvement in latch-up tolerance.

[0139] From the viewpoint of promoting the discharge of holes from the resistance reduction region 46 to the upper electrode 12, the p-type impurity concentration of the resistance reduction region 46 is preferably high. The p-type impurity concentration of the resistance reduction region 46 is higher than the p-type impurity concentration of the base region 43. The p-type impurity concentration of the resistance reduction region 46 is preferably 5×10 17 cm -3 More preferably, 1×10 18 cm -3 More preferably, 5×10 18 cm -3 above.

[0140] From the viewpoint of stabilizing the threshold voltage of the IGBT, the p-type impurity concentration of the resistance reduction region 46 close to the channel region of the IGBT is preferably low. The p-type impurity concentration of the resistance reduction region 46 is lower than the p-type impurity concentration of the cell contact region 45. The p-type impurity concentration of the resistance reduction region 46 is preferably 1×10 19 cm -3 the following.

[0141] From the viewpoint of facilitating the formation of the resistance reduction region 46, it is preferable to provide the first dummy trench 32 in contact with the resistance reduction region 46. The width of the resistance reduction region 46 in the second direction can be increased, and the formation of the resistance reduction region 46 becomes easier.

[0142] From the viewpoint of improving latch-up resistance, it is preferable to have the first dummy trench 32. In particular, the first conductive layer 18 in the first dummy trench 32 is electrically connected to the upper electrode 12, so that holes easily flow along the side of the first dummy trench 32 during the IGBT's off operation. Therefore, the discharge of holes from the resistance reduction region 46 to the upper electrode 12 is promoted. Therefore, the latch-up resistance of the RC-IGBT 100 is improved.

[0143] From the viewpoint of improving latch-up resistance, it is preferred that the width of the emitter region 44 in the first direction is small. From the viewpoint of improving latch-up resistance, it is preferred that the width of the emitter region 44 in the first direction at the first surface F1 is smaller than the width of the cell contact region 45 in the first direction at the first surface F1. In addition, the width of the emitter region 44 and the width of the cell contact region 45 can be adjusted to adjust the mutual conductance, thereby improving the short-circuit resistance.

[0144] From the viewpoint of promoting the discharge of electrons to the upper electrode 12 and suppressing the injection of holes into the drift region 42 during stable diode operation, the base region 43 is preferably in contact with the side surface of the first trench contact portion 12 x .

[0145] In addition, Figure 1 In the example, the transistor region 101 and the diode region 102 are each one, but the transistor region 101 and the diode region 102 may be divided into a plurality of regions and arranged alternately. By dividing into a plurality of regions, the heat generation of the IGBT and the diode can be uniformed.

[0146] (First Modification)

[0147] The semiconductor device according to the first modification of the first embodiment is different from the semiconductor device according to the first embodiment in that the diode region further includes a tenth semiconductor region between the second semiconductor region and the eighth semiconductor region.

[0148] Fig.11 This is a schematic cross-sectional view of a portion of a semiconductor device according to a first modification of the first embodiment. Fig.11 yes Fig.12 CC' section. Fig.11 The first embodiment Figure 2 The corresponding figure.

[0149] Fig.12 It is a schematic plan view of a part of a semiconductor device according to a first modification of the first embodiment. Fig.12 It is a top view of the first surface F1. Fig.12 The first embodiment Figure 3 The corresponding figure.

[0150] Fig.13This is a schematic cross-sectional view of a portion of a semiconductor device according to a first modification of the first embodiment. Fig.13 yes Fig.12 DD' section. Fig.13 The first embodiment Figure 4 The corresponding figure.

[0151] The semiconductor device according to the first modification of the first embodiment is an RC-IGBT 110. The RC-IGBT 110 is different from the RC-IGBT 100 according to the first embodiment in that the diode region 102 includes a barrier region 47.

[0152] The barrier region 47 is an n-type semiconductor region and is provided between the drift region 42 and the anode region 52 .

[0153] The barrier region 47 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The concentration of the n-type impurities in the barrier region 47 is, for example, 5×10 15 cm -3 And 5×10 18 cm -3 the following.

[0154] The barrier region 47 has a function of suppressing the injection of holes into the drift region 42 when the diode is in the on state. Therefore, when the diode is turned off, the amount of holes to be discharged to the upper electrode 12 decreases. The amount of holes to be discharged from the upper electrode 12 decreases, and the reverse recovery current of the diode decreases. If the reverse recovery current of the diode decreases, the switching loss of the diode decreases.

[0155] Therefore, according to the RC-IGBT 110 of the first modified example of the first embodiment, the switching loss is further reduced.

[0156] (Second Modification)

[0157] The semiconductor device of the second variant of the first embodiment is different from the semiconductor device of the first embodiment in that the diode region further includes an eleventh semiconductor region of the first conductivity type, the first conductivity type impurity concentration of the eleventh semiconductor region of the first conductivity type is higher than the first conductivity type impurity concentration of the eighth semiconductor region, the first electrode of the diode region includes a second part, the side surface of the second part is in contact with the eighth semiconductor region, the bottom surface of the second part is in contact with the eleventh semiconductor region, and the eleventh semiconductor region is arranged between the eighth semiconductor region and the second part.

[0158] Fig.14 It is a schematic cross-sectional view of a part of a semiconductor device according to a second modification of the first embodiment. Fig.14 yes Fig.15 EE' section. Fig.14The first embodiment Figure 2 The corresponding figure.

[0159] Fig.15 It is a schematic plan view of a part of a semiconductor device according to a second modification of the first embodiment. Fig.15 It is a top view of the first surface F1. Fig.15 The first embodiment Figure 3 The corresponding figure.

[0160] Fig.16 It is a schematic cross-sectional view of a part of a semiconductor device according to a second modification of the first embodiment. Fig.16 yes Fig.15 FF' cross section. Fig.16 The first embodiment Figure 4 The corresponding figure.

[0161] The semiconductor device of the second variation of the first embodiment is an RC-IGBT 120. The RC-IGBT 120 is different from the RC-IGBT 100 of the first embodiment in that the diode region 102 includes a trench bottom p-type region 56 (eleventh semiconductor region), and the upper electrode 12 of the diode region 102 has a second trench contact portion 12y (second portion).

[0162] The second trench contact portion 12y is formed in a trench provided in the semiconductor layer 10. The second trench contact portion 12y extends along the first direction.

[0163] The bottom surface of the second trench contact portion 12y contacts the trench bottom p-type region 56. The side surface of the second trench contact portion 12y contacts the anode region 52. The second trench contact portion 12y is electrically connected to the trench bottom p-type region 56 and the anode region 52.

[0164] The trench bottom p-type region 56 is a p-type semiconductor region. The trench bottom p-type region 56 is provided between the anode region 52 and the second trench contact portion 12y. The trench bottom p-type region 56 is in contact with the second trench contact portion 12y.

[0165] The p-type impurity concentration of the trench bottom p-type region 56 is higher than the p-type impurity concentration of the anode region 52. The contact between the second trench contact portion 12y and the trench bottom p-type region 56 is, for example, an ohmic contact.

[0166] According to the RC-IGBT 120 of the second modification of the first embodiment, for example, the first trench contact portion 12 x of the transistor region 101 and the second trench contact portion 12 y of the diode region 102 can be manufactured by a common process.

[0167] As described above, according to the first embodiment and the modified example, a semiconductor device capable of achieving both reduction in switching loss and improvement in latch-up tolerance can be provided.

[0168] (Second Embodiment)

[0169] The semiconductor device of the second embodiment is different from the semiconductor device of the first embodiment in that the transistor region does not have a second trench. Hereinafter, a part of the description of the same contents as the first embodiment may be omitted.

[0170] The semiconductor device of the second embodiment is an RC-IGBT 200 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip. The RC-IGBT 200 has a trench gate IGBT having a gate electrode in a trench formed in a semiconductor layer. The following description will be given by taking the case where the first conductivity type is p-type and the second conductivity type is n-type as an example.

[0171] Fig.17 It is a schematic cross-sectional view of a part of the semiconductor device according to the second embodiment. Fig.17 yes Fig.18 GG' cross section. Fig.17 The first embodiment Figure 2 The corresponding figure.

[0172] Fig.18 It is a schematic plan view of a part of the semiconductor device according to the second embodiment. Fig.18 It is a top view of the first surface F1. Fig.18 The first embodiment Figure 3 The corresponding figure.

[0173] Fig.19 It is a schematic cross-sectional view of a part of the semiconductor device according to the second embodiment. Fig.19 yes Fig.18 HH' cross section. Fig.19 The first embodiment Figure 4 The corresponding figure.

[0174] The semiconductor device according to the second embodiment is an RC-IGBT 200 . The RC-IGBT 200 includes a transistor region 101 and a diode region 102 .

[0175] The transistor region 101 operates as an IGBT, and the diode region 102 operates as a freewheeling diode.

[0176] The RC-IGBT 200 of the second embodiment includes a semiconductor layer 10 , an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a gate electrode 16 , a second conductive layer 20 , a gate insulating film 22 , a second insulating film 26 , an interlayer insulating layer 28 , and a gate electrode pad 103 .

[0177] The upper electrode 12 has a first trench contact portion 12 x (first portion).

[0178] In the semiconductor layer 10, there are provided a gate trench 31 (first trench), a second dummy trench 33 (third trench), a collector region 41 (first semiconductor region), a drift region 42 (second semiconductor region), a base region 43 (third semiconductor region), an emitter region 44 (fourth semiconductor region), a unit contact region 45 (fifth semiconductor region), a resistance reduction region 46 (sixth semiconductor region), a barrier region 47 (tenth semiconductor region), a cathode region 51 (seventh semiconductor region), an anode region 52 (eighth semiconductor region) and a diode contact region 53 (ninth semiconductor region).

[0179] The semiconductor device according to the second embodiment can achieve both reduction in switching loss and improvement in latch-up tolerance, similarly to the RC-IGBT 100 according to the first embodiment.

[0180] In addition, the semiconductor device of the second embodiment has a higher occupancy rate of the gate trench 31 in the transistor region 101 of the RC-IGBT 200 than the RC-IGBT 100 of the first embodiment. Therefore, for example, the RC-IGBT 200 can have a lower on-resistance and a higher on-current than the RC-IGBT 100 of the first embodiment.

[0181] As described above, according to the second embodiment, it is possible to provide a semiconductor device capable of achieving both reduction in switching loss and improvement in latch-up tolerance.

[0182] In the first and second embodiments, the semiconductor layer is described as an example of single crystal silicon, but the semiconductor layer is not limited to single crystal silicon and may be other single crystal semiconductors such as single crystal silicon carbide.

[0183] In the first and second embodiments, the case where the first conductivity type is p-type and the second conductivity type is n-type is described as an example, but the first conductivity type may be n-type and the second conductivity type may be p-type.

[0184] In the first and second embodiments, the case where the second dummy trench 33 is provided in the diode region 102 is described as an example. However, the second dummy trench 33 may not be provided in the diode region 102 .

[0185] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the main purpose of the invention. For example, the constituent elements of one embodiment can also be replaced or changed to constituent elements of other embodiments. These embodiments and their variations are included in the scope and main purpose of the invention, and are included in the invention described in the claims and the scope of their equivalents.

[0186] Description of symbols

[0187] 10 Semiconductor layer

[0188] 12 Upper electrode (first electrode)

[0189] 12x first trench contact (first part)

[0190] 12y Second trench contact portion (second portion)

[0191] 14. Lower electrode (second electrode)

[0192] 16. Gate electrode

[0193] 18 first conductive layer

[0194] 20 Second conductive layer

[0195] 22 Gate insulating film

[0196] 24 First insulating film

[0197] 26 Second insulating film

[0198] 28 Interlayer insulation layer

[0199] 31 Gate trench (first trench)

[0200] 32 first dummy groove (second groove)

[0201] 33 Second dummy groove (third groove)

[0202] 41 Collector region (first semiconductor region)

[0203] 42 drift region (second semiconductor region)

[0204] 43 Base region (third semiconductor region)

[0205] 44 emitter region (fourth semiconductor region)

[0206] 45 Cell contact region (fifth semiconductor region)

[0207] 46 Resistance reduction region (sixth semiconductor region)

[0208] 47 Barrier region (tenth semiconductor region)

[0209] 51 cathode region (seventh semiconductor region)

[0210] 52 Anode region (eighth semiconductor region)

[0211] 53 diode contact region (ninth semiconductor region)

[0212] 56 Trench bottom p-type region (eleventh semiconductor region)

[0213] 100RC-IGBT (Semiconductor device)

[0214] 101 Transistor Area

[0215] 102 diode area

[0216] 103 Gate electrode pad

[0217] 110RC-IGBT (Semiconductor device)

[0218] 120RC-IGBT (Semiconductor device)

[0219] 200RC-IGBT (Semiconductor device)

[0220] F1 First side

[0221] F2 Second page

Claims

1. A semiconductor device, wherein: The semiconductor device has a transistor region and a diode region. The transistor region comprises: A semiconductor layer having a first surface and a second surface opposite to the first surface; A first semiconductor region of a first conductivity type, disposed in the semiconductor layer; A second semiconductor region of a second conductivity type, disposed in the semiconductor layer and between the first semiconductor region and the first surface; A third semiconductor region of the first conductivity type, disposed in the semiconductor layer and between the second semiconductor region and the first surface; A fourth semiconductor region of the second conductivity type and a fifth semiconductor region of the first conductivity type are provided in the semiconductor layer, provided between the third semiconductor region and the first surface, and alternately arranged in a first direction parallel to the first surface; A sixth semiconductor region of the first conductivity type, disposed between the third semiconductor region and the fourth semiconductor region, having a first conductivity type impurity concentration higher than that of the third semiconductor region, and a first conductivity type impurity concentration lower than that of the fifth semiconductor region; A first trench is provided on the first surface side of the semiconductor layer, extends in the first direction, is repeatedly arranged in a second direction parallel to the first surface and perpendicular to the first direction, contacts the second semiconductor region, the third semiconductor region, the fourth semiconductor region and the fifth semiconductor region, and is separated from the sixth semiconductor region; A gate electrode, disposed in the first trench; a gate insulating film disposed between the gate electrode and the third semiconductor region; a first electrode disposed on the first surface side relative to the semiconductor layer, and having a first portion, a bottom surface of the first portion being in contact with the third semiconductor region, and a side surface of the first portion being in contact with the fourth semiconductor region, the fifth semiconductor region, and the sixth semiconductor region; as well as A second electrode is provided on the second surface side relative to the semiconductor layer and is in contact with the first semiconductor region. The diode region comprises: the semiconductor layer; the second semiconductor region; A seventh semiconductor region of the second conductivity type, disposed in the semiconductor layer and between the second semiconductor region and the second surface, having a second conductivity type impurity concentration higher than that of the second conductivity type impurity in the second semiconductor region; An eighth semiconductor region of the first conductivity type, disposed in the semiconductor layer and between the second semiconductor region and the first surface; The first electrode is electrically connected to the eighth semiconductor region; as well as The second electrode is in contact with the seventh semiconductor region.

2. The semiconductor device according to claim 1, wherein The sixth semiconductor region extends along the first direction, and the fifth semiconductor region is provided between the sixth semiconductor region and the first surface.

3. The semiconductor device according to claim 1, wherein The sixth semiconductor region is disposed between the first trench and the first portion.

4. The semiconductor device according to claim 1, wherein The transistor region further comprises: A second trench is provided on the first surface side of the semiconductor layer, is provided between two adjacent first trenches, extends in the first direction, and contacts the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, and the sixth semiconductor region; A first conductive layer is disposed in the second groove; as well as A first insulating film is provided between the first conductive layer and the third semiconductor region.

5. The semiconductor device according to claim 4, wherein: The first conductive layer is electrically connected to the first electrode.

6. The semiconductor device according to claim 1, wherein A width of the fourth semiconductor region in the first direction is smaller than a width of the fifth semiconductor region in the first direction.

7. The semiconductor device according to claim 1, wherein The diode region also includes a ninth semiconductor region of the first conductivity type, which is arranged in the semiconductor layer, between the eighth semiconductor region and the first surface, and has a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the eighth semiconductor region, and the first electrode is in contact with the ninth semiconductor region.

8. The semiconductor device according to claim 1, wherein The transistor region further includes a tenth semiconductor region of the second conductivity type, which is disposed between the second semiconductor region and the third semiconductor region and has a second conductivity type impurity concentration higher than that of the second semiconductor region.

9. The semiconductor device according to claim 8, wherein: The diode region further includes the tenth semiconductor region between the second semiconductor region and the eighth semiconductor region.

10. The semiconductor device according to claim 1, wherein The diode region further includes an eleventh semiconductor region of the first conductivity type, wherein the first conductivity type impurity concentration of the eleventh semiconductor region of the first conductivity type is higher than the first conductivity type impurity concentration of the eighth semiconductor region, The first electrode of the diode region includes a second portion, a side surface of the second portion contacts the eighth semiconductor region, and a bottom surface of the second portion contacts the eleventh semiconductor region. The eleventh semiconductor region is provided between the eighth semiconductor region and the second portion.

11. The semiconductor device according to claim 1, wherein The diode region further comprises: a third trench provided on the first surface side of the semiconductor layer, extending in the first direction and contacting the second semiconductor region and the eighth semiconductor region; A second conductive layer is disposed in the third groove; as well as A second insulating film is provided between the second conductive layer and the eighth semiconductor region.

12. The semiconductor device according to claim 11, wherein The second conductive layer is electrically connected to the first electrode.

13. The semiconductor device according to claim 1, wherein A side surface of the first portion is in contact with the third semiconductor region.

14. The semiconductor device according to claim 1, wherein The depth of the sixth semiconductor region is shallower than the depth of the first portion.

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