Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, which adopts n-type ions of which the atomic weight is greater than that of Ge to replace phosphorus ions injected in an nMOS (n-channel metal oxide semiconductor) region source and drain and ions injected in a pre-amorphization manner in the prior art, so that an n-type source and drain injection region in an amorphous silicon state can be formed, the pre-amorphization injection in the prior art is omitted, the process is simplified, and the manufacturing cost is reduced. The process cost is reduced. Compared with pre-amorphization injection of Ge and C plasmas in the prior art, injection of the n-type ions with the atomic weight larger than that of Ge is more beneficial to increase of multiple crystal grain intersection points, the crystal phase transition temperature of cobalt silicide in an nMOS region can be reduced, and on the basis that the thermal stability of a pMOS region is not sacrificed, the crystal phase transition temperature of the cobalt silicide in the nMOS region can be reduced. The method is compatible with the requirement difference of the nMOS region and the pMOS region on the formation of the cobalt silicide and the heat treatment temperature of the cobalt silicide in the phase conversion stage from the high resistance to the low resistance, avoids the problem caused by the requirement difference, and can improve the resistance of the device. And the annealing activation process after the subsequent source-drain ion implantation is carried out after the cobalt silicide is formed, so that the performance of the device can be further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] When the feature size of the integrated circuit manufacturing process is reduced to below deep submicron, the feature size of the transistor gate, source, drain active area and contact hole continues to shrink, resulting in the continuous increase of the active area series resistance of the device and the contact resistance of the contact hole, thus affecting the speed of the circuit.

[0003] In order to reduce the sheet resistance of polysilicon gates and active regions and the contact resistance of contact holes, metal silicide process technology has been developed and widely used in integrated circuit manufacturing processes.

[0004] Cobalt silicide (Co-Salicide, also known as cobalt silicide, can be abbreviated as CoSi) has the advantages of good thermal stability and low resistance. It is currently the best choice for products that require high-temperature processes. The general process node of CoSi is 0.25μm-65nm. As the feature size of the device is further reduced, the difficulty of CoSi transforming from a high-resistance phase to a low-resistance phase is gradually increasing. For this reason, in the current CoSi process, the industry usually adds a pre-amorphization ion implantation (PAI) process before depositing the metal Co to improve the difficulty of CoSi transforming from a high-resistance phase to a low-resistance phase caused by the reduction in size. The process of this process is as follows:

[0005] First, please refer to Figure 1 In (A), after defining a pMOS region and an nMOS region on a substrate 300 by a device isolation structure 301, a gate oxide layer 302 and a gate 303 are formed by a gate process, and a spacer 304 is further formed by a spacer process;

[0006] Afterwards, please refer to Figure 1 In (A), an S / D IMP process is performed, i.e., the pMOS region is masked and n-type ions such as phosphorus P are used to perform source and drain ion implantation on the nMOS region to form an n-type source and drain implantation region 305n, and the nMOS region is masked and p-type ions such as boron B are used to perform source and drain ion implantation on the pMOS region to form a p-type source and drain implantation region 305p;

[0007] Next, please refer to Figure 1In (B), spike thermal annealing (spike) and laser spike annealing (LSA) are performed to anneal and activate the ions injected into the n-type source and drain injection region 305n and the p-type source and drain injection region 305p. The injected ions will diffuse laterally and longitudinally, thereby optimizing the morphology and doping uniformity of the n-type source and drain injection region 305n and the p-type source and drain injection region 305p.

[0008] Next, please refer to Figure 1 In (B), the silicide barrier layers 306 required for the nMOS region and the pMOS region are formed by processes such as material deposition, photolithography, and etching;

[0009] Then, please refer to Figure 1 In (B), under the masking effect of the silicide barrier layer, the nMOS region and the pMOS region are subjected to pre-amorphization ion implantation (i.e., PAI implantation). The ions implanted by PAI are usually elements such as Ge and C. Thus, the atoms in the lattice can be displaced by the ions implanted by PAI, so that the crystal is transformed into amorphous, which can reduce the subsequent CoSi crystal phase transition temperature;

[0010] Next, please refer to Figure 1 In (C), metal Co is deposited and two rapid thermal processes (RTP) are performed successively. During the thermal process, the amorphous layer generated by PAI implantation can reduce the CoSi crystal phase transition temperature, thereby forming a CoSi with lower resistance in the exposed area of ​​the silicide barrier layer 306 after further removing the unreacted Co.

[0011] Afterwards, a contact hole etch stop layer may be deposited (not in Figure 1 ), and then proceed to the subsequent metal connection (forming contact plugs and metal interconnects) and other processes.

[0012] The above process has the following disadvantages:

[0013] (1) Due to the presence of Ge, C and other elements injected by PAI, when two rapid thermal processes are performed to simultaneously form CoSi in the nMOS region and the pMOS region, the nMOS region and the pMOS region actually have different process temperature requirements for RTP. Usually, the RTP temperature (i.e., the temperature for high-resistance to low-resistance phase transition) required by the nMOS region is higher than that required by the pMOS region. When the requirements of the nMOS region are met, the pMOS region is prone to excessively high temperatures, resulting in defects such as Co clusters, thereby destroying the uniformity and profile of the CoSi formed on the substrate and increasing the pMOS region temperature. The resistance (Rs) of CoSi formed in the MOS region is because Ge / C elements are usually implanted together with phosphorus P during source-drain ion implantation in the nMOS region. PAI implantation causes the Ge / C elements to increase again. The presence of a large amount of Ge / C elements causes high temperature to easily cause Co clusters. When the needs of the pMOS region are met, defects such as insufficient phase transition of CoSi from high resistance to low resistance due to low temperature will appear in the nMOS region, which will also destroy the consistency and morphology of CoSi formed on the substrate, increase the resistance (Rs) of CoSi formed in the nMOS region, and thus limit the improvement of device performance.

[0014] (2) Since NiSi is prone to defects such as clusters under high temperature conditions, the process temperature of subsequent metal connection processes is usually limited to no more than 650°C. This cannot meet the needs of some products that still require some high-temperature processes after the formation of metal silicide, and has a narrow scope of application.

[0015] (3) The additional PAI injection step increases process complexity and cost.

[0016] (4) The ions injected into the S / D regions of the pMOS and nMOS regions have been activated by annealing before the deposition of the silicide barrier layer. When they undergo two RTPs to form CoSi, the ions in the previously activated n-type source / drain injection region 305n and p-type source / drain injection region 305p will diffuse again, thereby causing device performance degradation. Summary of the invention

[0017] The object of the present invention is to provide a method for manufacturing a semiconductor device, which can simplify the process, improve the overall consistency and morphology of the formed CoSi, and reduce the resistance of the CoSi.

[0018] To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0019] Providing a substrate having an nMOS region and a pMOS region, and forming gates on the nMOS region and the pMOS region;

[0020] Masking the pMOS region and performing n-type ion implantation, wherein the n-type ions include n-type ions with an atomic weight greater than Ge, so as to form n-type source and drain implantation regions in an amorphous silicon state in the substrate on both sides of the gate of the nMOS region, and masking the nMOS region and performing p-type ion implantation, so as to form p-type source and drain implantation regions in the substrate on both sides of the gate of the pMOS region;

[0021] Forming a silicide barrier layer on the substrate of the nMOS region and the pMOS region, wherein the silicide barrier layer exposes at least a portion of the surface of the n-type source-drain implantation region, at least a portion of the surface of the p-type source-drain implantation region, and at least a portion of the surface of the top of each gate;

[0022] Depositing metal cobalt and performing two different rapid thermal processes in succession to form cobalt silicide on the exposed surfaces of the n-type source and drain injection regions, the p-type source and drain injection regions and each of the gates, and simultaneously transforming the high resistance phase of the cobalt silicide into a low resistance phase;

[0023] conformally depositing a contact hole etch stop layer on the cobalt silicide;

[0024] A spike thermal annealing process and a laser spike annealing process are used to perform heat treatment respectively to activate the n-type ions in the n-type source and drain injection region and the p-type ions in the p-type source and drain injection region.

[0025] Optionally, the n-type ions having an atomic weight greater than that of Ge include at least one of As and Sb.

[0026] Optionally, the implantation energy of the n-type ions with an atomic weight greater than Ge is 12kev to 16kev, and the doping concentration is 2e+15cm -2 ~3e+15cm -2 .

[0027] Optionally, the temperature range of the spike thermal annealing process is 1040°C to 1060°C, and the temperature range of the laser spike annealing process is 1100°C to 1200°C.

[0028] Optionally, the thickness of the contact hole etch stop layer is

[0029] Optionally, the manufacturing method further comprises forming at least one contact plug and at least one metal interconnection line by a metal connection process, wherein each of the contact plugs penetrates the contact hole etching stop layer from top to bottom, and the bottom is electrically in contact with the cobalt silicide in the corresponding area, and the top is electrically in contact with the corresponding metal interconnection line;

[0030] Wherein, the temperature of the metal connection process is higher than 650°C.

[0031] Optionally, during n-type ion implantation, at least one impurity ion of Ge, C, F, and N is implanted into the substrate on both sides of the gate of the nMOS region together with the n-type ions with an atomic weight greater than Ge by common ion implantation.

[0032] Optionally, the p-type ions include at least one of B, BF2, Ga, and In.

[0033] Optionally, when performing p-type ion implantation, at least one impurity ion of Ge, C, F, N, and P is implanted into the substrate on both sides of the gate of the pMOS region together with the p-type ions by common ion implantation.

[0034] Optionally, after forming gates on the nMOS region and the pMOS region and before performing n-type ion implantation and p-type ion implantation, it also includes: forming sidewalls on the side walls of each of the gates; or, after transforming the high-resistance phase of the cobalt silicide into a low-resistance phase and before conformally depositing a contact hole etch stop layer on the cobalt silicide, it also includes: removing unreacted metal and further removing the silicide barrier layer.

[0035] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0036] 1. Using n-type ions with an atomic weight greater than Ge to perform source and drain injection in the nMOS region instead of using phosphorus P to perform source and drain injection in the nMOS region in the prior art can not only form an n-type source and drain injection region in an amorphous silicon (i.e., α-Si) state in the nMOS region, but also save the pre-amorphization injection (PAI) before depositing Co in the prior art, without adding a mask (also called a mask), simplifying the process and reducing the process cost.

[0037] 2. The injection of n-type ions (such as As, Sb, etc.) with an atomic weight greater than Ge can not only form amorphous silicon in the n-type source and drain injection region, but also, compared with the pre-amorphization injection of ions such as Ge and C in the prior art that are not compatible with Co, Si, and CoSi and thus easily produce CoSi cluster defects, is more conducive to increasing multiple grain intersections in the n-type source and drain injection region (because of the larger atomic weight), making it easier for silicon Si and cobalt Co to react to form CoSi, that is, the temperature required for the formation of CoSi is lower, and the crystal phase transition temperature of the formed CoSi is lower. At the same time, the process of pre-amorphization injection of Ge, C, etc. ions in the pMOS region is also omitted, so that the thermal stability of CoSi in the pMOS region can be reduced without sacrificing the thermal stability of CoSi in the pMOS region. The invention discloses a method for improving the thermal stability of the nMOS region by reducing the crystal phase transformation temperature of the CoSi in the nMOS region during the transformation from the high resistance phase to the low resistance phase, thereby making the heat treatment temperatures of the pMOS region and the nMOS region basically consistent when forming CoSi and transforming the crystal phase of the formed CoSi, and not easily generating Co clusters, thereby achieving compatibility between the nMOS region and the pMOS region in terms of the formation of CoSi and the heat treatment temperature difference in the transformation stage of CoSi from the high resistance phase to the low resistance phase, avoiding the problems of poor consistency and morphology of CoSi and excessively high resistance of CoSi caused by the difference in requirements in the prior art, and improving the device resistance at the same heat treatment temperature.

[0038] 3. The annealing activation process after the source and drain ion implantation is adjusted to after the contact hole etch stop layer is deposited. This not only activates the source and drain ion implantations in the nMOS region and the pMOS region at the same time, but also allows the CoSi to be annealed more times at the same time. Moreover, the spike thermal annealing (spike) process and the laser spike annealing (LSA) process have a short heating time. While further improving the degree of transformation from the high-resistance phase to the low-resistance phase of CoSi, they will not cause Co clustering and will not increase the damage to the uniformity and profile of CoSi. Therefore, compared with the prior art, the resistance (Rs) of the formed CoSi can be reduced, which is beneficial to the improvement of device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0040] Figure 1 The present invention is a schematic cross-sectional diagram of a device structure in an existing method for manufacturing a semiconductor device.

[0041] Figure 2 The figure is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0042] Figure 3 It is a schematic cross-sectional view of a device structure in a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0045] Please refer to Figure 2 An embodiment of the present invention provides a method for manufacturing a semiconductor device, which comprises the following steps:

[0046] S1, providing a substrate having an nMOS region and a pMOS region, and forming gates on the nMOS region and the pMOS region;

[0047] S2, masking the pMOS region and performing n-type ion implantation, wherein the n-type ions include n-type ions with an atomic weight greater than Ge, so as to form n-type source and drain implantation regions in an amorphous silicon state in the substrate on both sides of the gate of the nMOS region, and masking the nMOS region and performing p-type ion implantation, so as to form p-type source and drain implantation regions in the substrate on both sides of the gate of the pMOS region;

[0048] S3, forming a silicide barrier layer on the substrate of the nMOS region and the pMOS region, wherein the silicide barrier layer exposes at least a portion of the surface of the n-type source and drain implantation region, at least a portion of the surface of the p-type source and drain implantation region, and at least a portion of the surface of the top of each gate;

[0049] S4, depositing metal cobalt and performing two different rapid thermal processes in succession to form cobalt silicide on the exposed surfaces of the n-type source and drain injection regions, the p-type source and drain injection regions and each of the gates, and simultaneously transforming the high resistance phase of the cobalt silicide into a low resistance phase;

[0050] S5, conformally depositing a contact hole etch stop layer on the cobalt silicide and the silicide barrier layer;

[0051] S6, performing heat treatment using a spike thermal annealing process and a laser spike annealing process respectively to activate the n-type ions in the n-type source and drain injection region and the p-type ions in the p-type source and drain injection region.

[0052] Please refer to Figure 3 In step (A), in step S1, first, a substrate 100 is provided. The material of the substrate 100 can be any suitable semiconductor material such as silicon (Si), silicon germanium (GeSi), silicon carbide (SiC) or silicon on insulator (SOI). A device isolation structure 101 can be formed in the substrate 100 by any suitable device isolation process such as a shallow trench isolation process or a local field oxygen isolation process, and then the corresponding nMOS region and pMOS region are defined. Before or after the formation of the device isolation structure 101, a corresponding ion implantation process can also be performed. A corresponding n-type well (not shown) or p-type well (not shown) is formed in the substrate 100 of the nMOS region or the pMOS region by a process; then, a gate oxide layer 102 is synchronously formed on the substrate 100 of the nMOS region and the pMOS region by any suitable process such as thermal oxidation or chemical vapor deposition, and polysilicon is further deposited on the gate oxide layer 102 and gate lithography and etching are performed, thereby forming corresponding polysilicon gates 103 on the nMOS region and the pMOS region simultaneously; then, a sidewall spacer 104 is formed on the sidewall of the polysilicon gate 103 by a sidewall spacer process.

[0053] Please refer to Figure 3 (A) and (B) in step S2, the pMOS region may be masked first and n-type ion implantation may be performed, and then the nMOS region may be masked and p-type ion implantation may be performed; or the nMOS region may be masked first and p-type ion implantation may be performed, and then the pMOS region may be masked and n-type ion implantation may be performed.

[0054] As an example, the process in step S2 is as follows:

[0055] First, please refer to Figure 3In (A), a patterned photoresist 200 is formed by first coating a photoresist and developing the photoresist with the aid of a mask for forming a source / drain of an nMOS device (ie, an nMOS S / D mask).

[0056] Then, using the patterned photoresist 200, the polysilicon gate 103 and the sidewall 104 of the nMOS region as masks, the substrate 100 of the nMOS region is implanted with source and drain ions using n-type ions (i.e., the nMOS region is implanted with n-type ions), so as to form n-type source and drain implantation regions 105n in the substrate 100 on both sides of the polysilicon gate 103 of the nMOS region. The n-type ions implanted with the source and drain ions contain n-type ions with an atomic weight greater than that of Ge, and are usually heavily doped, so that the lattice of the substrate 100 at that location is destroyed, so that the n-type source and drain implantation regions 105n are in an amorphous silicon (α-Si) state. The n-type ions with an atomic weight greater than Ge actually replace the conventional phosphorus P ions used for source and drain injection in the nMOS region in the prior art and the Ge, C ions and other ions used for pre-amorphization injection before depositing Co in the prior art. Since their atomic weight is greater than Ge, their injection can help increase the multiple grain intersections in the n-type source and drain injection region 105n, and the degree of amorphization and uniformity are better, which is conducive to reducing the CoSi crystal phase transition temperature in the subsequent step S3. Optionally, the n-type ions with an atomic weight greater than Ge include at least one of arsenic As (arsenic) and Sb (antimony). For example, the n-type ions with an atomic weight greater than Ge are As.

[0057] Optionally, when the patterned photoresist 200, the polysilicon gate 103 and the sidewall 104 of the nMOS region are used as masks and the substrate 100 of the nMOS region is implanted with source and drain ions using n-type ions, impurity ions of at least one of Ge (germanium), C (carbon), F (fluorine), and N (nitrogen) are implanted together with n-type ions having an atomic weight greater than Ge into the substrate 100 on both sides of the polysilicon gate 103 of the nMOS region using a common ion implantation method. The implantation of at least one of the impurity ions of Ge, C, F, and N can subsequently play a role in inhibiting the diffusion of doping elements during annealing, improving the activation rate of doping elements, reducing the barrier lowering effect (DIBL) introduced by the drain end, adjusting the final depth and profile of the junction at the n-type source and drain implantation region 105n, and improving device reliability and extending the service life of the device.

[0058] Next, the patterned photoresist 200 is removed by a suitable stripping process, and then a patterned photoresist 201 is formed by coating the photoresist and developing the photoresist with the aid of a mask for forming a source and drain of a pMOS device (ie, a pMOS S / D mask).

[0059] Then, using the patterned photoresist 201, the polysilicon gate 103 and the sidewall 104 of the pMOS region as masks, p-type ions are used to perform source and drain ion implantation on the substrate 100 of the pMOS region (i.e., p-type ion implantation is performed on the pMOS region), so as to form p-type source and drain implantation regions 105p in the substrate 100 on both sides of the polysilicon gate 103 of the pMOS region. The p-type ions of the source and drain ion implantation include B (boron), BF 2 At least one of Ge, C, F, N, and P (phosphorus) is used as the substrate 100. By controlling the implantation dose, implantation energy and other process parameters of these p-type ions, these p-type ions can be controlled to cause the substrate 100 to produce a sufficient degree of amorphization after being implanted into the substrate 100, so as to meet the requirements of CoSi formation and phase transformation on the pMOS region. Optionally, when the patterned photoresist 201, the polysilicon gate 103 and the sidewall 104 of the pMOS region are used as masks, and the substrate 100 of the pMOS region is implanted with p-type ions for source and drain ion implantation, at least one impurity ion of Ge, C, F, N, and P (phosphorus) is implanted into the substrate 100 on both sides of the gate of the pMOS region together with the p-type ions by common ion implantation. The injection of at least one of the impurity ions of Ge, C, F, N, and P can subsequently inhibit the diffusion of the doping elements during the annealing process, increase the activation rate of the doping elements, reduce the barrier lowering effect (DIBL) introduced by the drain end, adjust the final depth and profile of the p-type source-drain injection region 105p junction, improve device reliability, and extend the service life of the device.

[0060] It should be understood that in this step, the injection of n-type ions with an atomic weight greater than Ge actually replaces the conventional phosphorus P ions used for source and drain injection in the nMOS region in the prior art and the Ge, C ions used in the pre-amorphization injection before depositing Co in the prior art. Therefore, by controlling the injection dose, injection energy, and injection type of n-type ions with an atomic weight greater than Ge and other process parameters, the injected n-type ions with an atomic weight greater than Ge can be controlled to meet the source and drain performance requirements of the original nMOS region and the amorphization degree requirements achieved by the pre-amorphization injection. Among them, the n-type ions with an atomic weight greater than Ge can be heavily doped, and while the n-type ions with an atomic weight greater than Ge are used for source and drain injection into the nMOS region, the injection dose and other parameters of the other ions injected together can remain unchanged relative to the prior art. Optionally, the injection energy of the n-type ions with an atomic weight greater than Ge is 12kev~16kev, and the doping concentration is 2e+15cm -2 ~3e+15cm -2Since the n-type ions with an atomic weight greater than that of Ge have a larger atomic weight, their implantation will destroy the lattice of the substrate 100 at that location, which helps to increase the multiple grain intersections in the n-type source and drain implantation region 105n, so that the n-type source and drain implantation region 105n presents a sufficiently amorphous silicon (α-Si) state, which is beneficial to reduce the CoSi crystal phase transition temperature on the n-type source and drain implantation region 105n in the subsequent step S4.

[0061] Please refer to Figure 3 In (C), in step S3, a silicide area block (SAB) material deposition, photolithography, and etching process are performed to form a silicide blocking layer 106, which exposes at least a portion of the top surface of each polysilicon gate 103 and at least a portion of the top surface of the n-type source and drain implantation region 105n and at least a portion of the top surface of the p-type source and drain implantation region 105p. Specifically, first, a silicide barrier layer 106 (for example, a material such as silicon oxide, silicon nitride or silicon oxynitride) can be deposited by any suitable process such as chemical vapor deposition; then, a patterned photoresist layer (not shown) is formed on the silicide barrier layer 106 by a photolithography process, the purpose of which is to limit the area where the silicide barrier layer 106 needs to be retained (that is, the area where cobalt silicide does not need to be formed); then, the silicide barrier layer 106 is etched by any suitable etching process such as dry etching using the patterned photoresist layer as a mask, and the remaining silicide barrier layer 106 can expose at least a portion of the top surface of the polysilicon gate 103 and at least a portion of the top surface of the n-type source and drain injection region 105n and at least a portion of the top surface of the p-type source and drain injection region 105p, and mask the sidewalls and other surfaces of each sidewall 104, in preparation for the next step of forming cobalt silicide; then, the patterned photoresist layer is removed by any suitable stripping process such as wet etching. Therefore, when cobalt silicide is subsequently formed on the n-type source-drain implantation region 105 n and the p-type source-drain implantation region 105 p , cobalt silicide is also formed on the top surface of each polysilicon gate 103 .

[0062] In other embodiments of the present invention, according to device performance and design requirements, the silicide barrier layer 106 remaining after etching not only masks the sidewalls and other surfaces of the sidewall 104, but also masks the top surface of the polysilicon gate 103. Therefore, when cobalt silicide is subsequently formed on the n-type source and drain injection region 105n and the p-type source and drain injection region 105p, cobalt silicide will not be formed on the top surface of the polysilicon gate 103.

[0063] In step S4, first, refer to Figure 3In (D), metal Co 107 is deposited by any suitable process such as sputtering deposition, and the surfaces of the n-type source and drain implantation region 105n, the p-type source and drain implantation region 105p and the polysilicon gate 103 exposed by the silicide barrier layer 106 are in direct contact with the metal Co 107; then, please refer to Figure 3 In (E), through the first rapid thermal processing (RTP) process such as rapid thermal annealing, the metal Co 107 reacts with the silicon in the n-type source and drain implantation region 105n, the p-type source and drain implantation region 105p and the surface of the polysilicon gate 103 exposed by the silicide barrier layer 106 to form a high-resistance cobalt silicide (CoSi) 108. This process consumes less silicon in the n-type source and drain implantation region 105n, the p-type source and drain implantation region 105p and the polysilicon gate 103, and will not reduce the device performance; then, please refer to Figure 3 In (E), a second rapid thermal processing (RTP) process such as a second rapid thermal annealing process is performed, and the temperature of the second rapid thermal processing (RTP) process can be higher than the temperature of the first rapid thermal processing (RTP) process, so that the high-resistance cobalt silicide in the cobalt silicide layer 108 is converted into a low-resistance cobalt silicide (for example, the high-resistance CoSi 2 Phase transformation to low-resistance CoSi phase or Co 2 Four phases).

[0064] In step S4, the n-type source / drain implantation region 105n in the nMOS region and the polysilicon gate 103 both have multiple grain intersections due to the presence of n-type ions with atomic weight greater than Ge. Therefore, when the cobalt silicide 108 on the top surface of the n-type source / drain implantation region 105n in the nMOS region and the polysilicon gate 103 is transformed from a high-resistance phase to a low-resistance phase (for example, from a high-resistance CoSi 2 Phase transformation to low-resistance CoSi phase or Co 2 The crystal phase transition temperature of the cobalt silicide 108 (Si phase) is lowered compared with the prior art, which is conducive to the formation of more low-resistance cobalt silicide phases at the same crystal phase transition temperature as the pMOS region, thereby reducing the resistance Rs of the n-type source and drain injection region 105n in the nMOS region and the cobalt silicide 108 on the polysilicon gate 103.

[0065] Moreover, in the two rapid thermal treatment processes for forming the cobalt silicide 108, since n-type ions (such as As, Sb, etc.) with atomic weight greater than Ge replace the Ge, C and other ions implanted in the prior art for pre-amorphization, during the transformation of CoSi from a high-resistance phase to a low-resistance phase in the nMOS region, the nMOS region is not prone to Co clustering due to the presence of excessive Ge, C and other ions. Therefore, the uniformity and profile of the cobalt silicide 108 formed in the nMOS region are better than those of the prior art, that is, the resistance (Rs) of the formed cobalt silicide 108 can be further reduced in the nMOS region, which is beneficial to the improvement of the performance of the nMOS device.

[0066] In addition, the p-type ion implantation in the pMOS region is different from the n-type ion implantation in the nMOS region. In the case of not performing the subsequent annealing activation in S6, there is no need to introduce additional Ge / C in the pMOS region for pre-amorphization as in the prior art. Instead, the p-type ions implanted can cause substrate amorphization and the cobalt silicide 108 required in the pMOS region in the prior art has a low temperature for transformation from a high resistance phase to a low resistance phase. Therefore, in step S4, the heat treatment temperatures of the nMOS region and the pMOS region for the formation of CoSi and the transformation of CoSi from a high resistance phase to a low resistance phase can be adjusted to be substantially the same, thereby not sacrificing the thermal stability of CoSi in the pMOS region. On the basis of the heat treatment temperature, the nMOS region and the pMOS region can form the required cobalt silicide 108 together, and under this heat treatment temperature, Co clusters are not easy to be generated in the pMOS region, so the uniformity and profile of the cobalt silicide 108 formed in the pMOS region will not be destroyed. Compared with the prior art, the resistance (Rs) of the cobalt silicide 108 formed in the pMOS region can be further reduced, which is beneficial to the improvement of the performance of the pMOS device.

[0067] In summary, since the nMOS region uses n-type ions with an atomic weight greater than Ge (such as As, Sb, etc.) for source and drain injection, the process of performing PAI injection in the nMOS region and the pMOS region together in the prior art is eliminated, and the difference in the requirements for the formation of CoSi and the heat treatment temperature of CoSi in the stage of transformation from a high-resistance phase to a low-resistance phase in the nMOS region and the pMOS region is compatible, thereby avoiding the problems of poor CoSi consistency and morphology and excessive CoSi resistance caused by the difference in requirements in the prior art, and the device resistance can be improved at the same heat treatment temperature.

[0068] As an example, in this step S4, due to the presence of n-type ions with an atomic weight greater than Ge (such as As, Sb, etc.), the temperature range of the two rapid thermal treatment processes is 400°C to 800°C, among which it is particularly suitable for products requiring high-temperature processes. Cobalt silicide has the advantages of good thermal stability and low resistance. It is formed after being treated with n-type ions with an atomic weight greater than Ge. It is particularly suitable for products requiring high-temperature processes and can also be further used in the manufacture of small-sized products.

[0069] For further information, please refer to Figure 3 In (E), after the cobalt silicide 108 is formed, the metal Co 107 that has not reacted with silicon can be removed by wet etching to prevent the remaining metal Co 107 from bridging and causing a circuit short circuit.

[0070] Please refer to Figure 3 In (F), in step S5, the silicide barrier layer 106 can be firstly removed by any suitable process such as wet etching, and then the contact hole etch stop layer 109 is deposited by a process such as chemical vapor deposition. The thickness of the contact hole etch stop layer 109 is relatively thin, and conformally covers the device surface originally covered by the cobalt silicide 108 and the silicide barrier layer 106. The material of the contact hole etch stop layer 109 can be any suitable material, such as silicon oxide, silicon nitride or silicon oxynitride, and can be a single layer film or a structure formed by stacking multiple layers of films.

[0071] As an example, the thickness of the contact hole etching stop layer 109 is

[0072] In other embodiments of the present invention, according to device performance and design requirements, the silicide barrier layer 106 may be retained before depositing the contact hole etch stop layer 109 , so that the contact hole etch stop layer 109 is deposited on the silicide barrier layer 106 and the cobalt silicide 108 .

[0073] Please refer to Figure 3 In step (F), in step S6(, a spike annealing process may be firstly adopted and then a laser spike annealing process may be adopted to perform annealing treatment to anneal and activate the doping elements such as n-type ions injected into the n-type source and drain injection region 105n and the doping elements such as p-type ions injected into the p-type source and drain injection region 105p, thereby forming the source and drain regions 105n' required for the corresponding nMOS tube on both sides of the polysilicon gate 103 in the nMOS region, and forming the source and drain regions 105p' required for the corresponding pMOS tube on both sides of the polysilicon gate 103 in the pMOS region.

[0074] In this embodiment, since n-type ions with larger atomic weight such as As are used in step S2 to replace phosphorus P ions in the prior art for source and drain implantation in the nMOS region, a shallower junction depth can be formed under the same implantation energy conditions, which is beneficial to improving device performance.

[0075] As an example, the temperature range of the spike thermal annealing process is 1040°C to 1060°C, and the temperature range of the laser spike annealing process is 1100°C to 1200°C, which can realize the activation of n-type ions and p-type ions, reduce the diffusion of corresponding doped ions in the n-type source and drain injection region 105n and the p-type source and drain injection region 105p, and eliminate the amorphization and lattice damage in the n-type source and drain injection region 105n and the p-type source and drain injection region 105p. At the same time, the cobalt silicide 108 on the nMOS region and the pMOS region can be annealed again to increase the effect of the cobalt silicide 108 transforming from a high-resistance phase to a low-resistance phase. Therefore, compared with the prior art, the resistance (Rs) of the formed cobalt silicide 108 can be reduced, which is beneficial to the improvement of device performance.

[0076] In addition, compared with the prior art, step S6 for activating n-type ions and p-type ions for source and drain injection is placed after the two rapid thermal treatment steps for forming cobalt silicide 108 (i.e., step S4). This can effectively solve the problem of device performance degradation caused by re-diffusion at the source and drain of the MOS region during the two rapid thermal treatments for forming cobalt silicide 108 in the prior art, thereby ensuring device performance.

[0077] In this step, the contact hole etching stop layer 109 can prevent the cobalt silicide 108 from being oxidized.

[0078] After step S6, subsequent processes such as metal gate replacement process and metal connection process can be continued to complete the manufacture of the semiconductor device. These subsequent processes can allow the process temperature to be higher than 650°C, and will not be limited to a temperature higher than 650°C due to the Co cluster problem as in the prior art, and can meet the needs of some products that still require some high-temperature processes after forming CoSi, and have a wider range of applications.

[0079] As an example, after completing step S6 (i.e., after annealing to activate the n-type ions injected into the n-type source and drain injection region 105n and the p-type source and drain injection region 105p), the manufacturing method further includes depositing an interlayer dielectric layer (not shown) and further forming at least one contact plug (not shown) and at least one metal interconnection line (not shown) through a metal connection process (including a contact hole process, a metal interconnection process, etc.), wherein each of the contact plugs penetrates the interlayer dielectric layer and the contact hole etching stop layer from top to bottom, and the bottom is electrically in contact with the cobalt silicide 108 in the corresponding area, and the top is electrically in contact with the corresponding metal interconnection line. The temperature of the process for depositing the interlayer dielectric layer and the metal connection process is allowed to be higher than 650°C. In addition, the above-mentioned process for depositing the interlayer dielectric layer and the metal connection process are conventional technologies in the art and will not be repeated here.

[0080] It has been found through testing that the technical solution of the present invention, under the condition that other conditions remain unchanged, uses n-type ions such as As with an atomic weight greater than Ge to replace the phosphorus P ions in the source and drain ion implantation stage of the nMOS region in the prior art, and adjusts the process of annealing and activating the n-type ions injected into the nMOS region and the p-type ions injected into the pMOS region to after the formation and phase transformation of the cobalt silicide 108. This not only effectively activates the injected n-type ions and p-type ions, but also reduces the source and drain resistance Rs by 18% to 34% (the degree of activation is inversely proportional to the resistance value, while the degree of diffusion is proportional to the resistance value. Therefore, it can be seen that the use of the present invention results in better activation effect and less diffusion).

[0081] In addition, the resistance of cobalt silicide can be effectively reduced. After testing, the resistance Rs of the cobalt silicide of the test structure (testkey) that is most difficult to phase transform is reduced by 35% to 42%. This shows that the technical solution of the present invention can break through the limitation of the existing cobalt silicide process node of 0.25μm to 65nm, and can make the Co silicide process still have application value at smaller process nodes.

[0082] In summary, the method for manufacturing a semiconductor device provided by the present invention can use n-type ions with an atomic weight greater than Ge to replace phosphorus P in the prior art for source and drain injection in the nMOS region on the basis that other doping elements that need to be injected at the same time as source and drain injection and are used to improve device performance can remain unchanged (such as Ge and C used to improve DBIL in NMOS and PMOS, etc.), which can not only form an n-type source and drain injection region in an amorphous silicon (i.e., α-Si) state in the nMOS region, but also save the pre-amorphization injection before depositing Co in the prior art, without increasing the mask (also known as a mask), simplifying the process and reducing the process cost. In addition, the injection of n-type ions (such as As, Sb, etc.) with an atomic weight greater than Ge can not only form amorphous silicon in the n-type source and drain injection region, but also, compared with the pre-amorphization injection of ions such as Ge and C in the prior art that are not compatible with Co, Si, and CoSi and thus easily produce CoSi cluster defects, is more conducive to increasing multiple grain intersections in the n-type source and drain injection region (because of the larger atomic weight), making the process of silicon Si and cobalt Co reacting to form CoSi easier, that is, the temperature required for forming CoSi is lower, and the crystal phase transition temperature of the formed CoSi is lower. At the same time, the process of pre-amorphization injection of Ge, C, etc. ions in the pMOS region is also omitted, so that the thermal stability of CoSi in the pMOS region can be maintained without sacrificing the thermal stability of CoSi in the pMOS region. On the basis of the stability of the semiconductor device, the crystal phase transformation temperature of CoSi in the nMOS region during the transformation from the high-resistance phase to the low-resistance phase is reduced, and Co clusters are not easily generated, so that the nMOS region and the pMOS region can achieve the compatibility of the demand gap for the formation of CoSi and the heat treatment temperature of the transformation stage of CoSi from the high-resistance phase to the low-resistance phase, avoiding the problems of poor consistency and morphology of CoSi and excessive resistance of CoSi caused by the demand gap in the prior art, and improving the device resistance at the same heat treatment temperature. In addition, the annealing activation process after the source and drain ion implantation is carried out after the formation of cobalt silicide, which can not only anneal the cobalt silicide again and improve the effect of cobalt silicide from the high-resistance phase to the low-resistance phase, but also avoid the problem of re-diffusion of activated source and drain ions and deterioration of device performance caused by the heat treatment process of cobalt silicide formation, compared with the scheme of performing source and drain ion thermal annealing to complete activation before forming metal silicide in the prior art.

[0083] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate having an nMOS region and a pMOS region, and forming gates on the nMOS region and the pMOS region; Masking the pMOS region and performing n-type ion implantation, wherein the n-type ions include n-type ions with an atomic weight greater than Ge, so as to form n-type source and drain implantation regions in an amorphous silicon state in the substrate on both sides of the gate of the nMOS region, and masking the nMOS region and performing p-type ion implantation, so as to form p-type source and drain implantation regions in the substrate on both sides of the gate of the pMOS region; Forming a silicide barrier layer on the substrate of the nMOS region and the pMOS region, wherein the silicide barrier layer exposes at least a portion of the surface of the n-type source-drain implantation region, at least a portion of the surface of the p-type source-drain implantation region, and at least a portion of the surface of the top of each gate; Depositing metal cobalt and performing two different rapid thermal processes in succession to form cobalt silicide on the exposed surfaces of the n-type source and drain injection regions, the p-type source and drain injection regions and each of the gates, and simultaneously transforming the high resistance phase of the cobalt silicide into a low resistance phase; conformally depositing a contact hole etch stop layer on the cobalt silicide; A spike thermal annealing process and a laser spike annealing process are used to perform heat treatment respectively to activate the n-type ions in the n-type source-drain injection region and the p-type ions in the p-type source-drain injection region.

2. The manufacturing method according to claim 1, characterized in that The n-type ions having an atomic weight greater than that of Ge include at least one of As and Sb.

3. The manufacturing method according to claim 1, characterized in that: The implantation energy of the n-type ions with an atomic weight greater than that of Ge is 12kev to 16kev, and the doping concentration is 2e+15cm -2 ~3e+15cm -2 .

4. The manufacturing method according to claim 1, characterized in that: The temperature range of the spike thermal annealing process is 1040°C to 1060°C, and the temperature range of the laser spike annealing process is 1100°C to 1200°C.

5. The manufacturing method according to claim 1, characterized in that: The thickness of the contact hole etching stop layer is 6. The manufacturing method according to claim 1, characterized in that: The method further includes forming at least one contact plug and at least one metal interconnection line by a metal connection process, wherein each of the contact plugs penetrates the contact hole etching stop layer from top to bottom, and the bottom is electrically in contact with the cobalt silicide in the corresponding area, and the top is electrically in contact with the corresponding metal interconnection line; Wherein, the temperature of the metal connection process is higher than 650°C.

7. The manufacturing method according to claim 1, characterized in that: When performing n-type ion implantation, at least one impurity ion of Ge, C, F, and N is implanted into the substrate on both sides of the gate of the nMOS region together with the n-type ions with an atomic weight greater than Ge by common ion implantation.

8. The manufacturing method according to claim 1, characterized in that: The p-type ions include at least one of B, BF2, Ga, and In.

9. The manufacturing method according to claim 8, characterized in that: When performing p-type ion implantation, at least one impurity ion of Ge, C, F, N, and P is implanted into the substrate on both sides of the gate of the pMOS region together with the p-type ions by common ion implantation.

10. The production method according to any one of claims 1 to 9, characterized in that: After forming gates on the nMOS region and the pMOS region and before performing n-type ion implantation and p-type ion implantation, it also includes: forming sidewalls on the side walls of each of the gates; or, after transforming the high-resistance phase of the cobalt silicide into a low-resistance phase and before conformally depositing a contact hole etch stop layer on the cobalt silicide, it also includes: removing unreacted metal and further removing the silicide barrier layer.

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