Complementary field effect transistor device and forming method thereof

Abstract

A complementary field effect transistor (CFET) device includes: a fin; a first channel region disposed vertically over the fin; a second channel region disposed vertically over the first channel region; the isolation structure is located between the first channel region and the second channel region; a first etch stop layer (ESL) on a lower surface of the isolation structure; the second ESL is located on the upper surface of the isolation structure, and the first ESL, the second ESL, the first channel region and the second channel region are made of the same semiconductor material; first source / drain regions at opposite ends of the first channel region; a second source / drain region at opposite ends of the second channel region; a dielectric structure at opposite ends of the isolation structure and vertically disposed between the first source / drain region and the second source / drain region; the first gate structure is located around the first channel region; and a second gate structure around the second channel region. The embodiment of the application also relates to a method of forming a complementary field effect transistor (CFET) device.

Description

Technical Field

[0001] Embodiments of the present application relate to complementary field effect transistor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that should be addressed.

[0004] Recently, vertically stacked transistor devices, such as complementary field effect transistor (CFET) devices, have provided a promising new architecture that achieves improved integration density by forming nanostructured field effect transistors (FETs) stacked vertically above a substrate. Various aspects of this new architecture need to be studied and improved to achieve better device performance. Summary of the invention

[0005] Some embodiments of the present application provide a method for forming a complementary field effect transistor (CFET) device, the method comprising: forming a nanostructure above a fin, wherein the nanostructure comprises: a lower nanostructure comprising a first pseudo material layer interlaced with a first semiconductor material layer; an upper nanostructure located above the lower nanostructure and comprising the first pseudo material layer interlaced with the first semiconductor material layer; a second pseudo material located between the lower nanostructure and the upper nanostructure; a first etch stop layer (ESL) located between the lower nanostructure and the second pseudo material; and a second etch stop layer (ESL). an etch stop layer between the upper nanostructure and the second dummy material; forming a dummy gate structure above a first portion of the nanostructure; forming a source / drain opening adjacent to the dummy gate structure and extending through the nanostructure; after forming the source / drain opening, selectively removing the second dummy material from the nanostructure to form a gap between the first etch stop layer and the second etch stop layer; filling the gap with an isolation structure; and after filling the gap, sequentially forming a first source / drain region, a dielectric structure, and a second source / drain region in the source / drain opening.

[0006] Other embodiments of the present application provide a complementary field effect transistor (CFET) device, comprising: a fin; a first plurality of channel regions vertically arranged above the fin; a second plurality of channel regions vertically arranged above the first plurality of channel regions; an isolation structure located between the first plurality of channel regions and the second plurality of channel regions; a first etch stop layer (ESL) located on a lower surface of the isolation structure facing the fin; a second etch stop layer located on an upper surface of the isolation structure away from the fin, wherein the first etch stop layer, the second etch stop layer, the first plurality of channel regions and the second plurality of channel regions are the same semiconductor material; a first source / drain region located at opposite ends of the first plurality of channel regions; a second source / drain region located at opposite ends of the second plurality of channel regions; a dielectric structure located at opposite ends of the isolation structure and vertically arranged between the first source / drain region and the second source / drain region; a first gate structure located around the first plurality of channel regions; and a second gate structure located around the second plurality of channel regions.

[0007] Some other embodiments of the present application provide a complementary field effect transistor (CFET) device, comprising: a substrate; a fin protruding above the substrate; a first channel region vertically stacked above the fin; a second channel region vertically stacked above the first channel region; an isolation structure located between the first channel region and the second channel region; a first gate structure located around the first channel region; a second gate structure located around the second channel region; a first etch stop layer (ESL) extending along a lower surface of the isolation structure facing the substrate; a second etch stop layer extending along an upper surface of the isolation structure away from the substrate, wherein the first channel region, the second channel region, the The first etch stop layer and the second etch stop layer are semiconductor materials; a first interface layer is embedded in the first etch stop layer between the isolation structure and the first gate structure; a second interface layer is embedded in the second etch stop layer between the isolation structure and the second gate structure, wherein the first interface layer and the second interface layer are oxides of the semiconductor material; a first source / drain region is located at opposite ends of the first channel region; a second source / drain region is located at opposite ends of the second channel region; and a dielectric structure is located at opposite ends of the isolation structure, wherein the dielectric structure separates the first source / drain region and the second source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0009] Figure 1 An example of a complementary field effect transistor (CFET) schematic in a three-dimensional view is shown in accordance with some embodiments.

[0010] Figures 2 to 10 , Fig.11A , Fig. 11B and Fig.12 are various views of a CFET device at various stages of fabrication according to an embodiment.

[0011] Fig.13 is a cross-sectional view of a CFET device according to another embodiment.

[0012] Fig.14 is a cross-sectional view of a CFET device according to another embodiment.

[0013] Fig.15 is a cross-sectional view of a CFET device according to another embodiment.

[0014] Fig.16A and Fig. 16B is a cross-sectional view of a CFET device according to another embodiment.

[0015] Fig.17 is a cross-sectional view of a CFET device according to another embodiment.

[0016] Fig.18 is a cross-sectional view of a CFET device according to yet another embodiment.

[0017] Figures 19 to 26 , Fig.27A , Fig.27B and Fig.28 is a cross-sectional view of a CFET device at various manufacturing stages according to an embodiment.

[0018] Fig.29A and Fig.29B is a cross-sectional view of a CFET device according to another embodiment.

[0019] Fig. 30A and Fig. 30B is a cross-sectional view of a CFET device according to another embodiment.

[0020] Fig.31A and Fig.31B is a cross-sectional view of a CFET device according to another embodiment.

[0021] Fig.32A and Fig.32B is a cross-sectional view of a CFET device according to another embodiment.

[0022] Fig.33A and Fig.33B is a cross-sectional view of a CFET device according to yet another embodiment.

[0023] Fig.34 is a flow chart of a method of forming a CFET device according to some embodiments. DETAILED DESCRIPTION

[0024] The following disclosure provides many different embodiments or examples for realizing different features of the embodiments of the present disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. Throughout the discussion, unless otherwise stated, the same or similar reference numerals in different figures refer to the same or similar elements formed by the same or similar materials using the same or similar formation methods.

[0025] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0026] According to various embodiments, a CFET is formed. The disclosed method allows various shapes and structures of an isolation structure for the CFET, the isolation structure being disposed between the upper nanostructure and the lower nanostructure of the CFET. The various shapes and structures allow the CFET to meet different design goals and performance requirements.

[0027] Figure 1 An example of a CFET schematic according to some embodiments is shown. Figure 1 It is a three-dimensional view, in which some components of the CFET are omitted for clarity of illustration.

[0028] The CFET includes a plurality of vertically stacked nanostructure FETs (e.g., nanowire FETs, nanosheet FETs, multi-bridge channel (MBC) FETs, nanoribbon FETs, gate-all-around (GAA) FETs, etc.). For example, the CFET may include a lower nanostructure FET of a first device type (e.g., n-type / p-type) and an upper nanostructure FET of a second device type (e.g., p-type / n-type) opposite to the first device type. Specifically, the CFET may include a lower PMOS transistor and an upper NMOS transistor, or the CFET may include a lower NMOS transistor and an upper PMOS transistor. It should be noted that the structure of the CFET also allows nanostructure FETs of the same device type to be stacked vertically to form a semiconductor device. Therefore, the term CFET is used herein as a general term to refer to the vertical stacking nature of a device structure, and is not limited to vertically stacked transistors of opposite device types. Each of the nanostructure FETs includes a semiconductor nanostructure 66 (including a lower semiconductor nanostructure 66L and an upper semiconductor nanostructure 66U), wherein the semiconductor nanostructure 66 is used as a channel region (also referred to as a channel layer, a semiconductor channel region, or a semiconductor channel layer) for the nanostructure FET. The semiconductor nanostructure 66 may be a nanosheet, a nanowire, etc. The lower semiconductor nanostructure 66L is used for the lower nanostructure FET, and the upper semiconductor nanostructure 66U is used for the upper nanostructure FET. Nanostructure isolation materials ( Figure 1 Not explicitly shown, see Fig.12 100 in the figure) to separate and electrically isolate the upper semiconductor nanostructure 66U from the lower semiconductor nanostructure 66L. For simplicity, the semiconductor nanostructure may also be referred to as a nanostructure hereinafter.

[0029] The gate dielectric 132 is along the top surface, sidewalls and bottom surface of the semiconductor nanostructure 66. The gate electrode 134 (including the lower gate electrode 134L and the upper gate electrode 134U) is located above the gate dielectric 132 and around the semiconductor nanostructure 66. The source / drain region 108 (including the lower epitaxial source / drain region 108L and the upper epitaxial source / drain region 108U) is disposed at opposite sides of the gate dielectric 132 and the gate electrode 134. The source / drain region 108 may refer to a source or a drain, which may be referred to individually or collectively depending on the context. Isolation features may be formed to separate the desired source / drain region 108 and / or the desired gate electrode 134. For example, the lower gate electrode 134L may be optionally separated from the upper gate electrode 134U by an isolation layer. Alternatively, the lower gate electrode 134L may be coupled to the upper gate electrode 134U. In addition, the upper epitaxial source / drain region 108U can be separated from the lower epitaxial source / drain region 108L by one or more dielectric layers. The isolation features between the channel region, gate, and source / drain regions allow vertically stacked transistors, thereby improving device density. Due to the vertical stacking nature of the CFET, this schematic may also be referred to as a stacked transistor or a folded transistor.

[0030] Figure 1 Reference cross sections used in later figures are also shown. Cross section AA' is parallel to the longitudinal axis of the semiconductor nanostructure 66 of the CFET and in the direction of current flow, for example, between the source / drain regions 108 of the CFET. Cross section BB' is perpendicular to cross section AA' and along the longitudinal axis of the gate electrode 134 of the CFET. Cross section CC' is parallel to cross section BB' and extends through the source / drain regions 108 of the CFET. For clarity, subsequent figures refer to these reference cross sections.

[0031] Figures 2 to 10 , Fig.11A , Fig. 11B and Fig.12 1 are various views (eg, three-dimensional views, cross-sectional views) of a CFET device 300 at various stages of fabrication according to an embodiment. Figure 2 , Figure 3 and Figure 4 is shown with Figure 1 Similar 3D views of the 3D view. Figures 5 to 10 , Fig.11A and Fig.12 shows along with Figure 1 A cross-sectional view of a cross section similar to the reference cross section AA'. Fig. 11B shows along with Figure 1 Throughout the discussion herein, figures with the same reference numerals but different letters (e.g., Fig.11A and Fig. 11B) shows different views (e.g., along different cross-sections) of the same semiconductor device at the same processing stage.

[0032] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. An insulating layer is provided on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0033] A multilayer stack 52 is formed over the substrate 50. The multilayer stack 52 includes dummy layers 54 (including a first dummy layer 54A and a second dummy layer 54B) and semiconductor layers 56 (including a lower semiconductor layer 56L and an upper semiconductor layer 56U). A subset of the lower semiconductor layer 56L and the first dummy layer 54A is disposed below the second dummy layer 54B and is interlaced with each other (e.g., forming an alternating layer pattern). Another subset of the upper semiconductor layer 56U and the first dummy layer 54A is disposed above the second dummy layer 54B and is interlaced with each other. Figure 2 In the example of the second dummy layer 54B, the second dummy layer 54B contacts the first dummy layer 54A immediately above it, and contacts the first dummy layer 54A immediately below it. As described in more detail later, the dummy layer 54 will be removed, and the semiconductor layer 56 will be patterned to form the channel region of the CFET. Specifically, the lower semiconductor layer 56L will be patterned to form the channel region of the lower nanostructure FET of the CFET, and the upper semiconductor layer 56U will be patterned to form the channel region of the upper nanostructure FET of the CFET.

[0034] The multilayer stack 52 is shown to include six dummy layers 54 and four semiconductor layers 56. It should be understood that the multilayer stack 52 may include any number of dummy layers 54 and semiconductor layers 56. Each layer of the multilayer stack 52 may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), and the like.

[0035] The first dummy layer 54A is formed of a first semiconductor material, and the second dummy layer 54B is formed of a second semiconductor material. The first semiconductor material and the second semiconductor material can be selected from candidate semiconductor materials of the substrate 50. The semiconductor materials of the first dummy layer 54A and the second dummy layer 54B will be described in more detail later. The first semiconductor material and the second semiconductor material have high etching selectivity to each other. Therefore, in subsequent processing, the material of the second dummy layer 54B can be removed at a faster rate than the material of the first dummy layer 54A.

[0036] The semiconductor layer 56 (including the lower semiconductor layer 56L and the upper semiconductor layer 56U) is formed of one or more semiconductor materials. The semiconductor material can be selected from the candidate semiconductor material of the substrate 50. In some embodiments, the semiconductor layer 56 is formed of a IV-V group material or a III-V group material. The lower semiconductor layer 56L and the upper semiconductor layer 56U can be formed of the same semiconductor material, or can be formed of different semiconductor materials. In some embodiments, the lower semiconductor layer 56L and the upper semiconductor layer 56U are both formed of semiconductor materials suitable for p-type devices and n-type devices, such as silicon. In some embodiments, the lower semiconductor layer 56L is formed of a semiconductor material suitable for a p-type device, such as germanium or silicon germanium, and the upper semiconductor layer 56U is formed of a semiconductor material suitable for an n-type device, such as silicon or carbon-doped silicon. The semiconductor material of the semiconductor layer 56 will be described in more detail later. The semiconductor material of the semiconductor layer 56 has a high etching selectivity to the semiconductor material of the dummy layer 54. Therefore, in subsequent processing, the material of the dummy layer 54 can be removed at a faster rate than the material of the semiconductor layer 56.

[0037] Some layers of the multilayer stack 52 may be thicker than other layers of the multilayer stack 52. The thickness of the second dummy layer 54B may be different from (e.g., greater than or less than) the thickness of each of the first dummy layers 54A. In some embodiments, the second dummy layer 54B has a large thickness, such as a thickness greater than each of the first dummy layers 54A. Forming the second dummy layer 54B to a large thickness allows the second dummy layer 54B to be more easily removed in subsequent processing. In addition, the thickness of each of the semiconductor layers 56 may be different from (e.g., greater than or less than) the thickness of each of the first dummy layer 54A and / or the second dummy layer 54B. In some embodiments, each of the semiconductor layers 56 may be thicker than each of the dummy layers 54.

[0038] In some embodiments, the first dummy layer 54A is formed of silicon germanium having a first germanium atomic percentage, and the second dummy layer 54B is formed of silicon germanium having a second germanium atomic percentage higher than the first germanium atomic percentage. The difference between the second germanium atomic percentage and the first germanium atomic percentage can be higher than, for example, about 10% or 30%, and can be in a range between about 30% and about 70%. The higher germanium atomic percentage allows the second dummy layer 54B to be etched at a faster rate than the first dummy layer 54A, and allows the second dummy layer 54B to be completely removed during a subsequent etching process, as discussed below.

[0039] exist Figure 3 In the embodiment of the present invention, a fin 62 is formed in the substrate 50, and nanostructures 64, 66 (including a first pseudo-nanostructure 64A, a second pseudo-nanostructure 64B, a lower semiconductor nanostructure 66L, and an upper semiconductor nanostructure 66U) are formed in the multilayer stack 52. In some embodiments, nanostructures 64, 66 and fins 62 can be formed in the multilayer stack 52 and the substrate 50, respectively, by etching grooves in the multilayer stack 52 and the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic. The formation of nanostructures 64, 66 by etching the multilayer stack 52 can define a first pseudo-nanostructure 64A from the first pseudo-layer 54A, a second pseudo-nanostructure 64B from the second pseudo-layer 54B, a lower semiconductor nanostructure 66L from the lower semiconductor layer 56L, and an upper semiconductor nanostructure 66U from the upper semiconductor layer 56U. The first pseudo nanostructure 64A and the second pseudo nanostructure 64B may also be collectively referred to as pseudo nanostructure 64. The lower semiconductor nanostructure 66L and the upper semiconductor nanostructure 66U may also be collectively referred to as semiconductor nanostructure 66. The nanostructures below the second pseudo nanostructure 64B (e.g., 64A and 66L) may be collectively referred to as lower nanostructures 65L, and the nanostructures above the second pseudo nanostructure 64B (e.g., 64A and 66U) may be collectively referred to as upper nanostructures 65U. Figure 3 In the example of FIG. 5 , each of the second nanostructures 64B is interposed between the lower nanostructure 65L and the upper nanostructure 65U.

[0040] As described in more detail later, the pseudo nanostructure 64 will be removed to form the channel region of the CFET. Specifically, the lower semiconductor nanostructure 66L will be used as the channel region of the lower nanostructure FET for the CFET. In addition, the upper semiconductor nanostructure 66U will be used as the channel region of the upper nanostructure FET for the CFET. Subsequently, the second pseudo nanostructure 64B will be replaced with an isolation structure. The isolation structure can define the boundary of the lower nanostructure FET and the upper nanostructure FET.

[0041] The fin 62 and the nanostructures 64, 66 can be patterned by any suitable method. For example, the fin 62 and the nanostructures 64, 66 can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a spacing that is less than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 62 and the nanostructures 64, 66. In some embodiments, the mask (or other layer) may remain on the nanostructures 64, 66.

[0042] Although the fin 62 and each of the nanostructures 64, 66 are shown as having a constant width throughout, in other embodiments, the fin 62 and / or the nanostructures 64, 66 may have tapered sidewalls such that the width of each of the fin 62 and / or the nanostructures 64, 66 continuously increases in a direction toward the substrate 50. In such embodiments, each of the nanostructures 64, 66 may have a different width and be trapezoidal in a cross-sectional view.

[0043] exist Figure 4 In the embodiment, an isolation region 70 adjacent to the fin 62 is formed. The isolation region 70 can be formed by depositing an insulating material over the substrate 50, the fin 62 and the nanostructures 64, 66 and between adjacent fins 62. The insulating material can be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In some embodiments, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be implemented. In an embodiment, the insulating material is formed so that excess insulating material covers the nanostructures 64, 66. Although the insulating material is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) can first be formed along the surface of the substrate 50, the fin 62 and the nanostructures 64, 66. Thereafter, a filling material such as one of the previously described insulating materials can be formed over the liner.

[0044] A removal process is then applied to the insulating material to remove excess insulating material above the nanostructures 64, 66. In some embodiments, a planarization process may be utilized, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The planarization process exposes the nanostructures 64, 66 so that the top surfaces of the nanostructures 64, 66 and the insulating material are flush after the planarization process is completed.

[0045] The insulating material is then recessed to form the isolation region 70. The insulating material is recessed so that the upper portion of the fin 62 protrudes from between adjacent isolation regions 70. In addition, the top surface of the isolation region 70 can have a flat surface (as shown), a convex surface, a concave surface (such as a depression), or a combination thereof. The top surface of the isolation region 70 can be formed to be flat, convex and / or concave by appropriate etching. The isolation region 70 can be recessed using an etching process, such as an etching process that is selective to the insulating material (e.g., selectively etching the insulating material at a faster rate than the material of the fin 62 and the nanostructures 64, 66). For example, oxide removal (using, for example, dilute hydrofluoric (dHF) acid) can be used.

[0046] exist Figure 4 In the embodiment of the present invention, a pseudo dielectric layer 72 is formed on the fin 62 and / or the nanostructure 64, 66. The pseudo dielectric layer 72 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to an acceptable technique. A pseudo gate layer 74 is formed above the pseudo dielectric layer 72, and a mask layer 76 is formed above the pseudo gate layer 74. The pseudo gate layer 74 may be deposited above the pseudo dielectric layer 72, and then planarized such as by CMP. The mask layer 76 may be deposited above the pseudo gate layer 74. The pseudo gate layer 74 may be a conductive or non-conductive material, and may be selected from a group including amorphous silicon, polycrystalline silicon (poly silicon), polycrystalline silicon germanium (poly-SiGe), etc. The pseudo gate layer 74 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The pseudo gate layer 74 may be formed by other materials having high etching selectivity to insulating materials. The mask layer 76 may include, for example, silicon nitride, silicon oxynitride, etc. In the illustrated embodiment, the dummy dielectric layer 72 covers the isolation region 70 such that the dummy dielectric layer 72 extends between the dummy gate layer 74 and the isolation region 70. In another embodiment, the dummy dielectric layer 72 covers only the fins 62 and / or the nanostructures 64,66.

[0047] Next, in Figure 5In the embodiment of the present invention, the mask layer 76 is patterned using acceptable photolithography and etching techniques to form a mask 86. The pattern of the mask 86 is then transferred to the dummy gate layer 74 and to the dummy dielectric layer 72 to form a dummy gate 84 and a dummy dielectric 82, respectively. The dummy gate 84 and the dummy dielectric 82 are collectively referred to as a dummy gate stack 85. The dummy gate 84 covers the corresponding channel region of the nanostructures 64 and 66. The pattern of the mask 86 can be used to physically separate each of the dummy gates 84 from the adjacent dummy gates 84. The dummy gate 84 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the corresponding fin 62. After patterning, the mask 86 can be optionally removed, such as by any acceptable etching technique.

[0048] exist Figure 5 In the embodiment of the present invention, a gate spacer 90 is formed above the nanostructures 64, 66 and on the exposed sidewalls of the mask 86 (if present), the pseudo gate 84 and the pseudo dielectric 82. The gate spacer 90 can be formed by conformal formation of one or more dielectric materials and subsequent etching of the dielectric material. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, etc., which may be formed by deposition processes such as CVD, ALD, etc. Other dielectric materials formed by any acceptable process may be used. Any acceptable etching process, such as dry etching, may be implemented to pattern the dielectric material. The etching may be anisotropic. The dielectric material (when etching) has a portion remaining on the sidewall of the pseudo gate 84 (thus forming the gate spacer 90). The fin spacer may also be formed as part of forming the gate spacer 90.

[0049] Source / drain recesses 94 (also referred to as source / drain openings) are formed in the nanostructures 64, 66 and the fins 62. An epitaxial source / drain region will subsequently be formed in the source / drain recesses 94. The source / drain recesses 94 may extend through the nanostructures 64, 66 and into the fins 62. The fins 62 may be etched so that the bottom surface of the source / drain recesses 94 is disposed above, below, or flush with the top surface of the isolation region 70. The source / drain recesses 94 may be formed by etching the nanostructures 64, 66 and the substrate 50 using an anisotropic etching process (such as RIE, NBE, etc.). During the etching process for forming the source / drain recesses 94, the gate spacers 90 and the dummy gates 84 mask portions of the nanostructures 64, 66 and the fins 62. Each layer of the nanostructures 64, 66 and the fins 62 may be etched using a single etching process or multiple etching processes. After the source / drain recesses 94 reach a desired depth, a timed etching process may be used to stop the etching of the source / drain recesses 94 .

[0050] Next, in Figure 6In some embodiments, a selective etching process is performed using an etchant that is selective to the material of the second pseudo nanostructure 64B (e.g., has a higher etching rate to the material of the second pseudo nanostructure 64B), thereby completely removing the second pseudo nanostructure 64B without substantially corroding other materials of the NFET device. In an exemplary embodiment, the selective etching process is an isotropic etching process. In some embodiments in which the second pseudo nanostructure 64B is formed of germanium or silicon germanium with a high atomic percentage of germanium, the first pseudo nanostructure 64A is formed of silicon germanium with a low atomic percentage of germanium, and the semiconductor nanostructure 66 is formed of silicon without germanium, the selective etching process may include a dry etching process using chlorine gas (with or without plasma). Because the pseudo gate stack 85 wraps around the sidewalls of the semiconductor nanostructures 66 and 64 (see Figure 4 ), so the dummy gate stack 85 can support the upper nanostructure 65U so that the upper nanostructure 65U does not collapse when the second dummy nanostructure 64B is removed. After removing the second dummy nanostructure 64B, a gap 95 (e.g., an empty space) is formed between the upper nanostructure 65U and the lower nanostructure 65L.

[0051] Next, in Figure 7 in Figure 6 A dielectric material 100' is formed (e.g., conformally) above the CEFT device. The dielectric material 100' is formed to line the bottom and sidewalls of the source / drain recess 94 and fill the gap 95. In some embodiments, the dielectric material 100' is a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, aluminum oxide, hafnium oxide, zirconium oxide, etc., combinations thereof, or multilayers thereof. The dielectric material 100' may be a single layer of material, or may include multiple sublayers, such as having a double-layer structure or a triple-layer structure. Suitable formation methods, such as CVD, PVD, ALD, etc., may be implemented to form the dielectric material 100'. As an example, the thickness of the dielectric layer 100' may be between about 2 nm and about 20 nm.

[0052] Next, in Figure 8 In the embodiment of the present invention, an etching process is performed to remove the portion of the dielectric material 100' disposed outside the gap 95. The etching process can be anisotropic (e.g., an anisotropic plasma etching process), but a suitable isotropic etching process can also be used. After the etching process, the remaining portion of the dielectric material 100' located inside the gap 95 forms the isolation structure 100 (also referred to as a dielectric isolation structure). Figure 8In the example of FIG. 1 , the sidewalls of isolation structure 100 are straight and flush with the sidewalls of nanostructures 64 and 66. In other embodiments, the sidewalls of isolation structure 100 may be curved (e.g., concave or convex) and may not be aligned with the sidewalls of nanostructures 64 and 66. These and other variations are fully intended to be included within the scope of the disclosed embodiments.

[0053] Next, in Fig. 9 , forming an internal spacer 98. Forming the internal spacer 98 may include an etching process that laterally etches the first pseudo nanostructure 64A. The etching process may be isotropic and may be selective to the material of the first pseudo nanostructure 64A, so that the first pseudo nanostructure 64A is etched at a faster rate than the semiconductor nanostructure 66. Although the sidewalls of the pseudo nanostructure 64A are shown as being straight after etching, the sidewalls may be concave or convex.

[0054] The internal spacer 98 is formed on the sidewall of the recessed first pseudo nanostructure 64A. As described in more detail later, a source / drain region will be formed in the source / drain groove 94, and the first pseudo nanostructure 64A will be replaced with a corresponding gate structure. The internal spacer 98 serves as an isolation component between the subsequently formed source / drain region and the subsequently formed gate structure. In addition, the internal spacer 98 can be used to prevent damage to the subsequently formed source / drain region by a subsequent etching process (such as an etching process for forming a gate structure). On the other hand, the isolation structure 100 is used to isolate the upper semiconductor nanostructure 66U (collectively) from the lower semiconductor nanostructure 66L (collectively). In addition, the isolation structure 100 can define the boundary of the lower nanostructure FET and the upper nanostructure FET.

[0055] The internal spacer 98 can be formed by conformally depositing an insulating material in the source / drain recess 94 and on the sidewalls of the recessed first pseudo nanostructure 64A and then etching the insulating material. The insulating material can be a hard dielectric material, for example, a carbon-containing dielectric material, such as silicon oxycarbonitride, silicon oxycarbide, etc. The insulating material can be formed by a deposition process, such as ALD, CVD, etc. The etching of the insulating material can be anisotropic or isotropic. The insulating material (when etched) has a portion remaining along the sidewalls of the (recessed) first pseudo nanostructure 64A (thus forming the internal spacer 98).

[0056] Next, in Fig.10, a lower epitaxial source / drain region 108L and an upper epitaxial source / drain region 108U are formed. The lower epitaxial source / drain region 108L is formed in the lower portion of the source / drain recess 94. The lower epitaxial source / drain region 108L contacts the lower semiconductor nanostructure 66L and does not contact the upper semiconductor nanostructure 66U. The internal spacer 98 electrically insulates the lower epitaxial source / drain region 108L from the dummy nanostructure 64A, which will be replaced with a replacement gate in a subsequent process.

[0057] The lower epitaxial source / drain region 108L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 108L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon doped with n-type dopants such as phosphorus, arsenic, etc. When the lower epitaxial source / drain region 108L is a p-type source / drain region, the corresponding material may include silicon or silicon germanium doped with p-type dopants such as boron, indium, etc. The lower epitaxial source / drain region 108L may be in-situ doped and may or may not be implanted with the corresponding p-type or n-type dopant. During the epitaxy of the lower epitaxial source / drain region 108L, the upper semiconductor nanostructure 66U may be masked to prevent undesired epitaxial growth on the upper semiconductor nanostructure 66U. After growing the lower epitaxial source / drain regions 108L, the mask over the upper semiconductor nanostructures 66U may then be removed.

[0058] As a result of the epitaxial process used to form lower epitaxial source / drain regions 108L, the upper surface of lower epitaxial source / drain regions 108L has facets that extend laterally outward beyond the sidewalls of nanostructures 64 and 66. In some embodiments, adjacent lower epitaxial source / drain regions 108L remain separated after the epitaxial process is completed. In other embodiments, these facets cause adjacent lower epitaxial source / drain regions 108L of the same FET to merge.

[0059] A first contact etch stop layer (CESL) 112 and a first interlayer dielectric (ILD) 114 are formed over the lower epitaxial source / drain regions 108L. The first CESL 112 may be formed of a dielectric material having a high etch selectivity relative to the etching of the first ILD 114, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which may be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 114 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 114 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0060] The formation process may include depositing a conformal CESL layer, depositing a material for the first ILD 114, and a subsequent planarization process and then an etch back process. In some embodiments, the first ILD 114 is first etched, leaving the first CESL 112 unetched. An anisotropic etching process is then performed to remove the portion of the first CESL 112 that is above the recessed first ILD 114. After recessing, the sidewalls of the upper semiconductor nanostructure 66U are exposed. The first ILD 114 and the first CESL 112 may be collectively referred to as a dielectric structure 113 after recessing. In the illustrated embodiment, the dielectric structure 113 extends along the sidewalls of the isolation structure 100, along the sidewalls of the inner spacer 98U1 (e.g., the inner spacer 98 located above the isolation structure 100 and contacting the isolation structure 100), and along the sidewalls of the inner spacer 98L1 (e.g., the inner spacer 98 located below the isolation structure 100 and contacting the isolation structure 100). Along Fig.10 In the vertical direction, each dielectric structure 113 is disposed below the upper surface of the inner spacer 98U1 and above the lower surface of the inner spacer 98L1.

[0061] An upper epitaxial source / drain region 108U is then formed in the upper portion of the source / drain recess 94. The upper epitaxial source / drain region 108U may be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 66U. The material of the upper epitaxial source / drain region 108U may be selected from the same candidate material group used to form the lower epitaxial source / drain region 108L, depending on the desired conductivity type of the upper epitaxial source / drain region 108U. The conductivity type of the upper epitaxial source / drain region 108U may be opposite to the conductivity type of the lower epitaxial source / drain region 108L. For example, the upper epitaxial source / drain region 108U may be doped opposite to the lower epitaxial source / drain region 108L. The upper epitaxial source / drain region 108U may be in-situ doped with n-type or p-type dopants and / or may be implanted with n-type or p-type dopants. Adjacent upper epitaxial source / drain regions 108U may remain separated after the epitaxial process, or may merge. As discussed above, the lower nanostructure FET and the upper nanostructure FET of the CFET device may be the same device type (e.g., n-type or p-type), or may be different device types.

[0062] After forming the upper epitaxial source / drain regions 108U, the second CESL 122 and the second ILD 124 are formed. The materials and formation methods may be similar to those of the first CESL 112 and the first ILD 114, respectively, and are not discussed in detail herein. The formation process may include: depositing layers for the second CESL 122 and the second ILD 124; and performing a planarization process to remove excess portions of the corresponding layers. After the planarization process, the top surfaces of the second ILD 124, the second CESL 122, the gate spacer 90, and the mask 86 are coplanar (within process variations). The planarization process may leave the mask 86 unremoved (as shown), or the mask 86 may be removed, in which case the top surface of the second ILD 124 is flush with the top surface of the dummy gate stack 85.

[0063] Next, in FIG. 11A to FIG. 11BIn the replacement gate process, the dummy gate stack 85 is replaced by the replacement gate structure. For example, the mask 86 is removed by a CMP process (if it has not been removed). Next, the dummy gate stack 85 is removed in one or more etching steps, thereby forming a groove between the gate spacers 90. In some embodiments, the dummy gate 84 and the dummy dielectric 82 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the material of the dummy gate 84. Each portion of the groove exposes the nanostructure 64, 66 and / or is located above the portion of the nanostructure 64, 66, which is used as a channel region in the resulting device. The portion of the nanostructure 64, 66 used as the channel region is arranged between adjacent pairs of the lower epitaxial source / drain region 108L or between adjacent pairs of the upper epitaxial source / drain region 108U. During removal, when etching the dummy gate 84, the dummy dielectric 82 can be used as an etch stop layer. Then, after removing the dummy gate 84, the dummy dielectric 82 can be removed.

[0064] The remaining portion of the first pseudo nanostructure 64A is then removed to form an opening in the region between the semiconductor nanostructures 66. The remaining portion of the first pseudo nanostructure 64A can be removed by any acceptable etching process that selectively etches the material of the first pseudo nanostructure 64A at a faster rate than the material of the semiconductor nanostructure 66, the internal spacer 98, and the isolation structure 100. The etching can be isotropic. For example, when the first pseudo nanostructure 64A is formed of silicon germanium, the semiconductor nanostructure 66 is formed of silicon, the internal spacer 98 is formed of silicon oxynitride, and the isolation structure 100 is formed of silicon oxynitride, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In some embodiments, a trimming process (not shown separately) is performed to reduce the thickness of the exposed portion of the semiconductor nanostructure 66 and to enlarge the opening 128.

[0065] Fig. 11B Shows Fig.11A CFET device 300, but along Figure 1 The cross section B-B'. Fig. 11B As shown in , isolation structure 100 and nanostructure 66 have the same width W. Isolation structure 100 has a height H1, and nanostructure 66 has a height H2. Height H1 is greater than height H2, which in some embodiments can provide better isolation between nanostructures 66U and 66L and can accommodate greater process variation in the thickness of dielectric structure 113. In other embodiments, height H1 is equal to or less than height H2. Height H1 can be between about 5 nm and about 30 nm, and height H2 can be between about 3 nm and about 10 nm.

[0066] Next, an interface layer 68 is formed at the outer surface of the nanostructure 66. In some embodiments, the interface layer 68 is formed of an oxide of a II-VI material or an oxide of a IV material. In the illustrated embodiment, the interface layer 68 is an oxide of the material of the nanostructure 66 and is formed by an oxidation process (e.g., a thermal oxidation process). In other words, the interface layer 68 is formed by converting (e.g., oxidizing) the outer portion of the nanostructure 66 into an oxide (e.g., silicon oxide) of the material (e.g., silicon) of the nanostructure 66. Therefore, in the illustrated embodiment, the interface layer 68 is not formed on, for example, the isolation structure 100 and the isolation region 70. As an example, the thickness of the interface layer 68 can be between about 0.5 nm and about 2 nm.

[0067] exist Fig. 11B In the cross-sectional view of FIG. 1 , the interface layer 68 surrounds (eg, surrounds) the nanostructure 66, and no interface layer 68 is formed on the isolation structure 100. Fig.11A , no interface layer 68 is formed at the surface of the end portion 66A of the nanostructure 66, which is disposed between the vertically adjacent inner spacers 98. This is because the end portion 66A is not exposed to the opening 128 and is therefore not oxidized by the oxidation process.

[0068] Still reference Fig.11A and Fig. 11B Next, a gate dielectric layer 132 (also referred to as a gate dielectric) is formed (e.g., conformally) over the interface layer 68 and along the sidewalls of the isolation structure 100, such that the gate dielectric layer 132 conformally lines the recesses between the gate spacers 90 and lines the openings between the nanostructures 66. Specifically, the gate dielectric layer 132 is formed on the top surface of the fin 62; along the top surface, sidewalls, and bottom surface of the semiconductor nanostructure 66 (on the interface layer 68); along the top surface, sidewalls, and bottom surface of the isolation structure 100; and along the sidewalls of the gate spacers 90. The gate dielectric layer 132 wraps around all (e.g., four) sides of the semiconductor nanostructure 66 and the isolation structure 100. The gate dielectric layer 132 may also be formed on the top surfaces of the second ILD 124 and the gate spacers 90, and may be formed on the sidewalls of the fin 62 (e.g., in an embodiment where the top surface of the isolation region 70 is below the top surface of the fin 62).

[0069] The gate dielectric layer 132 may include an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, a combination thereof, a multilayer thereof, etc. The gate dielectric layer 132 may include a high dielectric constant (high-k) material having a k value greater than about 7.0, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and a combination thereof. The formation method of the gate dielectric layer 132 may include molecular beam deposition (MBD), ALD, PECVD, etc. As an example, the thickness of the gate dielectric layer 132 may be between about 1 nm and about 5 nm.

[0070] Next, a lower gate electrode 134L is formed on the gate dielectric 132 around the lower semiconductor nanostructure 66L. For example, the lower gate electrode 134L wraps around the lower semiconductor nanostructure 66L. The lower gate electrode 134L can be formed of a metal-containing material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multilayers thereof, etc. Although a single-layer gate electrode is shown, the lower gate electrode 134L can include any number of work function adjustment layers, any number of barrier layers, any number of glue layers, and gate fill materials (e.g., metals or metal-containing materials).

[0071] The lower gate electrode 134L is formed of a material suitable for the device type of the lower nanostructure FET. For example, the lower gate electrode 134L may include one or more work function adjustment layers formed of a material suitable for the device type of the lower nanostructure FET. In some embodiments, the lower gate electrode 134L includes an n-type work function adjustment layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, and the like. In some embodiments, the lower gate electrode 134L includes a p-type work function adjustment layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, and the like. Additionally or alternatively, the lower gate electrode 134L may include a dipole-inducing element suitable for the device type of the lower nanostructure FET. Acceptable dipole-inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0072] The lower gate electrode 134L may be formed by conformally depositing one or more gate electrode layers and then recessing the gate electrode layers. Any acceptable etching process, such as dry etching, wet etching, etc., or a combination thereof, may be implemented to recess the gate electrode layers. The etching may be isotropic. Etching the lower gate electrode 134L may expose the upper semiconductor nanostructure 66U.

[0073] In some embodiments, an isolation layer ( Fig.11A and Fig. 11B Not shown, see e.g. Fig.13136 in the figure). The isolation layer serves as an isolation member between the lower gate electrode 134L and the subsequently formed upper gate electrode 134U. The isolation layer can be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, combinations thereof, etc.) and then recessing the dielectric material to expose the upper semiconductor nanostructure 66U.

[0074] Next, an upper gate electrode 134U is formed on the isolation layer (if present) described above or on the lower gate electrode 134L. The upper gate electrode 134U is disposed between the upper semiconductor nanostructures 66U and wraps the upper semiconductor nanostructures 66U. The upper gate electrode 134U can be formed of the same candidate material and candidate process used to form the lower gate electrode 134L. The upper gate electrode 134U is formed of a material suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 134U may include one or more work function adjustment layers formed of a material suitable for the device type of the upper nanostructure FET. Although a single-layer gate electrode 134U is shown, the upper gate electrode 134U may include any number of work function adjustment layers, any number of barrier layers, any number of glue layers, and gate fill materials.

[0075] In addition, a removal process is performed to make the top surfaces of the upper gate electrode 134U and the second ILD 124 flush. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be used as a removal process. After the planarization process, the top surfaces of the upper gate electrode 134U, the gate dielectric 132, the second ILD 124, and the gate spacer 90 are substantially coplanar (within process variations). Each corresponding pair of the gate dielectric 132 and the gate electrode 134 (including the upper gate electrode 134U and / or the lower gate electrode 134L) may be collectively referred to as a "gate structure" 133 (including an upper gate structure 133U and a lower gate structure 133L). Each gate structure 133 (which may also be referred to as a replacement gate structure or a metal gate structure) extends along multiple sides (e.g., top surface, sidewalls, and bottom surface) of the channel region of the semiconductor nanostructure 66. The lower gate electrode 134L may also extend along the sidewalls and / or top surface of the fin 62.

[0076] exist Fig. 11B In the example, no isolation layer is formed, and the upper gate electrode 134U and the lower gate electrode 134L are in direct contact. Fig. 11B The dashed line 135 in FIG. 1 (which is disposed between the upper and lower surfaces of the isolation structure 100) serves as a conceptual demarcation between the upper gate electrode 134U and the lower gate electrode 134L, and it should be understood that the gate fill material may extend continuously without an interface from the upper gate electrode 134U to the lower gate electrode 134L. It should be noted that the isolation layer (if formed) is not Fig.11AIn the cross section, therefore Fig.11A Not visible in the cross section.

[0077] Next, in Fig.12 In the embodiment of the present invention, a gate mask 138 is formed over the gate structure 133. The formation process may include: recessing the gate structure 133; filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride, etc.; and performing a planarization process to remove excess portions of the dielectric material located over the second ILD 124.

[0078] Next, an etch stop layer (ESL) 104 and a third ILD 106 are formed over the second ILD 124 and the gate mask 138. In some embodiments, the ESL 104 may include a dielectric material having a high etch selectivity relative to the etching of the third ILD 106, such as aluminum oxide, aluminum nitride, silicon oxycarbide, etc. The third ILD 106 may be formed using flowable CVD, ALD, etc., and the material may include PSG, BSG, BPSG, USG, etc., which may be deposited by any suitable method, such as CVD, PECVD, etc.

[0079] Next, source / drain contact openings are formed to extend through the ESL 104, the third ILD 106, the second ILD 124, and the second CESL 122 to expose the upper epitaxial source / drain region 108U. Similarly, a gate contact opening is formed to extend through the ESL 104, the third ILD 106, and the gate mask 138 to expose the upper gate electrode 134U. Next, a silicide region 99 is formed on the upper epitaxial source / drain region 108U, and a source / drain contact plug 119 is formed on the silicide region 99 to be electrically coupled to the upper epitaxial source / drain region 108U. In addition, a gate contact plug 118 is formed in the gate contact opening to be electrically coupled to the upper gate electrode 134U.

[0080] In some embodiments, the silicide region 99 is formed by: depositing a metal (such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof) that can react with a semiconductor material (e.g., silicon, germanium) to form a silicide or germanide region over the upper epitaxial source / drain region 108U; and then performing a thermal annealing process to form the silicide region 99. The unreacted portion of the deposited metal is then removed, for example, by an etching process. Although region 99 is referred to as a silicide region, region 99 may also be a germanide region or a silicon germanide region (e.g., a region including silicide and germanide).

[0081] The source / drain contact plugs 119 and the gate contact plugs 118 can be formed by filling the source / drain contact openings and the gate contact openings with a conductive material such as tungsten, but other suitable materials such as aluminum, copper, tungsten nitride, ruthenium, silver, gold, rhodium, molybdenum, nickel, cobalt, cadmium, zinc, alloys thereof, combinations thereof, etc. can be optionally utilized. A planarization process such as CMP can be performed to remove excess portions of the conductive material disposed outside the source / drain contact openings and the gate contact openings. The layers of the CFET device 300 disposed between the upper portion of the fin 62 and the third ILD 106 are collectively referred to as device layers 142 of the CFET device.

[0082] Next, a front side interconnect structure 120 is formed on the device layer 142. The front side interconnect structure 120 includes a dielectric layer 116 and a layer of conductive features 92 located in the dielectric layer 116. The dielectric layer 116 may include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 116 may also include a passivation layer formed of a non-low-k and dense dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, etc., or a combination thereof, on top of the low-k dielectric material. The dielectric layer 116 may also include a polymer layer.

[0083] Conductive component 92 may include conductive wires and conductive vias, which may be formed using, for example, a damascene process. Conductive component 92 may include metal wires and metal vias, which may include a diffusion barrier layer and a copper-containing material above the diffusion barrier layer. Aluminum pads electrically connected to the metal wires and metal vias may also exist above the metal wires and metal vias. Depending on how the corresponding tube core is packaged, the top surface components in conductive component 92 may include bonding pads, metal pillars, solder areas, etc. In some embodiments, contacts to lower gate structure 133L and lower epitaxial source / drain region 108L may be made through the back side of device layer 142 (e.g., the side opposite to front side interconnect structure 120).

[0084] Fig.13 1 is a cross-sectional view of a CFET device 300A according to another embodiment. The CFET device 300A is similar to the CFET device 300, but has an isolation layer 136 formed between the lower gate electrode 134L and the upper gate electrode 134U. The cross-sectional view of the CFET device 300A along the section AA' is similar to Fig.12The isolation layer 136 is the same or similar, so it is not repeated. As discussed above, the isolation layer 136 can be formed after forming the lower gate electrode 134L and before forming the upper gate electrode 134U. The isolation layer 136 can be formed by: conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, combinations thereof, etc.) on the lower gate electrode 134L; and then recessing the dielectric material to expose the upper semiconductor nanostructure 66U. In the illustrated embodiment, the isolation layer 136 is located between the upper surface and the lower surface of the isolation structure 100. The isolation layer 136 electrically isolates the upper gate electrode 134U from the lower gate electrode 134L, and allows the upper gate electrode 134U and the lower gate electrode 134L to be controlled by different gate control voltages.

[0085] Additional embodiments are discussed below. The CFET devices of the additional embodiments can be formed by modifying the processing steps used for the manufacture of the CFET device 300. After reading the disclosed embodiments, those skilled in the art will be able to easily modify the processing steps used for the manufacture of the CFET device 300 to form the CFET devices of the additional embodiments. It should be noted that for each of the subsequent embodiments discussed, as will be readily understood by those skilled in the art, the isolation layer 136 (if present) between the lower gate electrode 134L and the upper gate electrode 134U can be removed to represent another embodiment.

[0086] Fig.14 3 is a cross-sectional view of a CFET device 300B according to another embodiment. The CFET device 300B is similar to the CFET device 300A, but the isolation structure 100 is wider than the nanostructure 66. In some embodiments, the first dummy nanostructure 64A is removed to release the nanostructure 66 (see Fig.11A and Fig. 11B ), a trimming process (e.g., an etching process) is performed to reduce the size (e.g., width and / or height) of the nanostructure 66. The trimming process increases the spacing between adjacent nanostructures 66, which advantageously makes it easier to form subsequent material layers (e.g., gate dielectrics, work function layers, and gate fill materials) between the nanostructures 66. Because the trimming process selectively etches the nanostructures 66, the isolation structure 100 is about 1 nm to about 5 nm wider than the nanostructures 66 on each side. In other words, the lateral offset D between the sidewalls of the isolation structure 100 and the corresponding sidewalls (e.g., proximal sidewalls) of the nanostructure 66 is between about 1 nm and about 5 nm. A cross-sectional view of the CFET device 300B along section AA' is similar to Fig.12 The CFET device 300 is the same or similar to that in the embodiment of the present invention and thus will not be repeated.

[0087] Fig.15is a cross-sectional view of a CFET device 300C according to another embodiment. The CFET device 300C is similar to the CFET device 300A, but has a seam 103 (eg, an air gap or spacer) in each of the isolation structures 100. The seam 103 is formed in Figure 7 When the dielectric material 100' does not completely fill the gap 95 between the upper nanostructure 65U and the lower nanostructure 65L, for example, because it is difficult to fill the gap 95 having a small height. The cross-sectional view of the CFET device 300C along the section AA' is similar to Fig.12 The CFET device 300 in FIG. 1 is shown in FIG. 1 , but has a seam 103 in the isolation structure 100 .

[0088] Fig.16A and Fig. 16B is a cross-sectional view of a CFET device 300D according to another embodiment. The CFET device 300D is similar to the CFET device 300A, but the isolation structure 100 is formed of two different materials (eg, 100A and 100B).

[0089] In some embodiments, to form the isolation structure 100 of the CFET device 300D, Figure 7 In the process of , a first dielectric material 100A is formed to line the source / drain grooves 94 and the gap 95. The first dielectric material 100A is formed using a material with better etching resistance (e.g., silicon nitride), and can also serve as an adhesion layer for the second dielectric material 100B formed subsequently. The first dielectric material 100A does not completely fill the gap 95, but only partially fills the gap 95, wherein the central area of ​​the gap 95 is not filled. As an example, the thickness of the first dielectric material 100A can be between about 1nm and 10nm. Next, a second dielectric material 100B is formed to fill the remaining portion of the gap 95 left by the first dielectric material 100A. The second dielectric material 100B is formed using a material with better fluidity, such as silicon oxide formed by a FVCD process. As an example, the thickness of the second dielectric material 100B can be between about 2nm and 10nm. The double-layer structure for the isolation structure 100 reliably avoids or reduces seams in the isolation structure 100 (see, for example Fig.15 103) appears. Fig.16A and Fig. 16B As shown in , the first dielectric material 100A surrounds (eg, surrounds) the second dielectric material 100B and contacts the gate dielectric layer 132 .

[0090] Fig.17 is a cross-sectional view of a CFET device 300E according to another embodiment. The CFET device 300E is similar to the CFET device 300, but the isolation structure 100 has Fig.17. In particular, the end portions of each isolation structure 100 (e.g., the portions located between and contacting the internal spacers 98) are thicker than the center portions of the isolation structure 100 (e.g., the portions located between and contacting the gate dielectric layer 132). The dumbbell shape may be the result of etching the center portion of the isolation structure 100 during an etching process to remove the first pseudo-nanostructure 64 to release the nanostructure 66 and / or an etching process to trim the nanostructure 66. In an embodiment, the end portions of the isolation structure 100 may be a total of about 2 nm to about 10 nm thicker than the center portion of the isolation structure 100, such that the vertical offset between the upper surface (or lower surface) of the end portion of the isolation structure 100 and the upper surface (or lower surface) of the center portion of the isolation structure 100 is between about 1 nm and about 5 nm. A cross-sectional view of the CFET device 300E along section BB' is similar to Fig. 11B The CFET device 300 is the same or similar to that in the embodiment, and the details are not repeated here.

[0091] Fig.18 is a cross-sectional view of a CFET device 300F according to yet another embodiment. CFET device 300F is similar to CFET device 300, but isolation structure 100 has a drum shape with a curved upper surface and a curved lower surface. In particular, the end portion of each isolation structure 100 (e.g., the portion located between and in contact with the internal spacers 98) is thicker than the center portion of isolation structure 100 (e.g., the portion located between and in contact with the gate dielectric layer 132). In some embodiments, in Figure 6 In the process of removing the second pseudo nanostructure 64B, the etching process performed to remove the second pseudo nanostructure 64B may also remove some portions of the first pseudo nanostructure 64A. For example, the corner portions of the first pseudo nanostructure 64A that contact the second pseudo nanostructure 64B are removed more than the center portion of the first pseudo nanostructure 64A, thereby producing a drum shape of the isolation structure 100 after filling the gap 95. The cross-sectional view of the CFET device 300F along the section BB' is similar to Fig. 11B The CFET device 300 is the same or similar to that in the embodiment, and the details are not repeated here.

[0092] Figures 19 to 26 , Fig.27A , Fig.27B and Fig.284 is a diagram of a CFET device 400 according to an embodiment at various stages of manufacturing (e.g., a three-dimensional view, a cross-sectional view). The CFET device 400 is similar to the CFET device 300, but has an etch stop layer 56E formed above and below the second pseudo layer 54B in the multilayer stack 52, so that in subsequent processing, each of the formed second pseudo nanostructures 64B is sandwiched between two ESLs 66E. The details are discussed below. It should be noted that for simplicity, the following discussion of the CFET device 400 focuses on the differences between the manufacturing processes of the CFET device 400 and the CFET device 300, while the processing steps common to the CFET devices 400 and 300 may be briefly mentioned or omitted.

[0093] Fig.19 A cross-sectional view of a multilayer stack 52 is shown, similar to Figure 2 5B, but has etch stop layers (ESL) 56E formed above and below the second dummy layer 54B in the multilayer stack 52. In other words, the second dummy layer 54B is sandwiched between the etch stop layers 56E.

[0094] In some embodiments, etch stop layer 56E is formed of the same material as semiconductor layer 56 using the same or similar formation method. In the illustrated embodiment, etch stop layer 56E is formed to be thinner than dummy layer 54 and semiconductor layer 56. For example, etch stop layer 56E may have a thickness of 20%, 10%, or less of the thickness of dummy layer 54 (or semiconductor layer 56).

[0095] Fig. 20 The patterning process for forming fins 62, nanostructures 66 and 64 is shown (see FIG. Figure 3 ) and after forming dummy dielectric layer 72, dummy gate layer 74, and mask layer 76. After the patterning process, patterned dummy layer 54 forms nanostructure 64, patterned semiconductor layer 56 forms nanostructure 66, and patterned ESL 56E forms ESL 66E.

[0096] Next, in Fig.21 In the embodiment, a dummy gate 84 and a dummy dielectric 82 are formed by patterning the dummy gate layer 74 and the dummy dielectric layer 72, respectively. A gate spacer 90 is formed along the sidewalls of the dummy gate 84 and the dummy dielectric 82. Next, source / drain grooves 94 are formed.

[0097] Next, in Fig. 22, the second pseudo-nanostructure 64B is removed by a selective etching process. It should be noted that the ESL 66E protects (e.g., shields) the pseudo-nanostructure 64A adjacent to the second pseudo-nanostructure 64B during the selective etching process, thereby reducing or avoiding unintentional etching of the pseudo-nanostructure 64A. Therefore, the ESL 66E helps maintain the target size of the gap 95, which in turn determines the size of the isolation structure 100 formed subsequently.

[0098] Next, in Fig.23 In the embodiment of the present invention, dielectric material 110 ′ is formed to fill gaps 95 between ESL 66E and to line sidewalls and bottoms of source / drain recesses 94 .

[0099] Next, in Fig.24 In the embodiment, an etching process is performed to remove the portion of the dielectric material 110' located outside the gap 95, and the remaining portion of the dielectric material 110' forms the isolation structure 100, which is sandwiched between the ESLs 66E.

[0100] Next, in Fig.25 In the embodiment, the inner spacer 98 is formed by replacing the end portion of the first dummy nanostructure 64 exposed to the source / drain recess 94 .

[0101] Next, in Fig.26 In the process, a lower epitaxial source / drain region 108L, a first CESL 112 , a first ILD 114 , an upper epitaxial source / drain region 108U, a second CESL 122 , and a second ILD 124 are sequentially formed in the source / drain recess 94 .

[0102] Next, in Fig.27A and Fig.27B In the embodiment of the present invention, the dummy gate 84 and the dummy dielectric 82 are removed, and then the first dummy nanostructure 64A is removed to release the nanostructure 66, thereby forming the channel region of the CFET device. It should be noted that after removing the first dummy nanostructure 64A, the end portion 66EA of the ESL 66E (the portion that contacts the inner spacer 98 and extends along the inner spacer 98) is not exposed to the opening between the nanostructures 66, while the central portion 66EB of the ESL 66E is exposed to the opening between the nanostructures 66.

[0103] Next, an interface layer 68 is formed by, for example, converting the outer portions of the nanostructures 66 into oxide (e.g., silicon oxide) using an oxidation process. It should be noted that in the illustrated embodiment, the ESL 66E is formed of the same material as the nanostructures 66, and therefore, the outer portions of the ESL 66E exposed to the openings between the nanostructures 66 are also converted into the interface layer 68 (e.g., silicon oxide) by the oxidation process. Fig.29A and Fig.29B In the example of FIG. 1 , an inner portion of ESL 66E (e.g., a portion contacting isolation structure 100) is not oxidized and remains as the semiconductor material (e.g., silicon) of nanostructure 66. In particular, end portion 66EA of ESL 66E disposed between and contacting vertically adjacent inner spacers 98 is not oxidized. In contrast, central portion 66EB of ESL 66E is exposed to opening 128, and thus, an outer portion (e.g., an outer sub-layer) of central portion 66EB is converted to interface layer 68.

[0104] exist Fig.27B In the embodiment, the interface layer 68 on each of the nanostructures 66 surrounds the nanostructure 66 and has a rectangular ring shape. In contrast, the interface layer 68 is disposed only on the upper and lower surfaces of the isolation structure and has a U-shape. The U-shaped interface layer 68 on the upper surface (or lower surface) of each isolation structure 100 extends along the upper surface and sidewalls of the remaining portion (e.g., the inner portion) of the ESL 66E.

[0105] Next, in Fig.28 , a gate mask 138 is formed over the gate structure 133. ESL 104 and third ILD 106 are formed over the gate mask 138 and the second ILD 124. Source / drain contact plugs 119 and gate contact plugs 118 are formed to be electrically coupled to the upper epitaxial source / drain region 108U and the upper gate electrode 134U, respectively. A silicide region 99 may be formed between the upper epitaxial source / drain region 108U and the source / drain contact plug 119. Next, a front-side interconnect structure 120 is formed on the device layer 142.

[0106] Fig.29A and Fig.29B 1 is a cross-sectional view of a CFET device 400A according to another embodiment. The CFET device 400A is similar to the CFET device 400, but has an isolation layer 136 formed between the upper gate electrode 134U and the lower gate electrode 134L. The isolation layer 136 may be formed using the same or similar formation method as Fig.14 The isolation layer 136 in FIG. 1 is formed of the same or similar material, and the details are not repeated here.

[0107] Additional embodiments are discussed below. The CFET devices of the additional embodiments can be formed by modifying the processing steps used for the manufacture of the CFET device 400. After reading the disclosed embodiments, those skilled in the art will be able to easily modify the processing steps used for the manufacture of the CFET device 400 to form the CFET devices of the additional embodiments. It should be noted that for each of the subsequent embodiments discussed, as will be readily understood by those skilled in the art, the isolation layer 136 (if present) between the lower gate electrode 134L and the upper gate electrode 134U can be removed to represent another embodiment.

[0108] Fig. 30A and Fig. 30B 4 is a cross-sectional view of a CFET device 400B according to another embodiment. CFET device 400B is similar to CFET device 400A, but the central portion 66EB of ESL 66E is completely oxidized into the interface layer 68. It should be noted that Fig. 30A As shown in FIG, the end portion 66EA of the ESL 66E remains unoxidized. Due to the complete oxidation of the central portion 66EB, Fig. 30B In the embodiment, the interface layer 68 on the upper surface (or lower surface) of each isolation structure 100 has a rectangular shape, and no unoxidized ESL 66E exists between the interface layer 68 and the isolation structure 100 .

[0109] Fig.31A and Fig.31B 4 is a cross-sectional view of a CFET device 400C according to another embodiment. The CFET device 400C is similar to the CFET device 400A, but no interfacial layer 68 is formed on the isolation structure 100. In some embodiments, Fig.27A and Fig.27B In the process of removing the first pseudo nanostructure 64A, the etching process performed to remove the first pseudo nanostructure 64A also removes (e.g., completely removes) the central portion 66EB of the ESL 66E because the central portion 66EB is exposed to the opening between the nanostructures 66. Therefore, no interface layer 68 is formed on the isolation structure 100. It should be noted that Fig.31A As shown in , end portion 66EA of ESL 66E remains because end portion 66EA is not exposed to the openings between nanostructures 66 and thus is not removed or oxidized. Fig.31B In the cross-sectional view, Fig.31B A cross section across the middle of isolation structure 100 is shown without interfacial layer 68 formed on isolation structure 100 .

[0110] Fig.32A and Fig.32B4 is a cross-sectional view of a CFET device 400D according to another embodiment. The CFET device 400D is similar to the CFET device 400A, but the degree of oxidation of the ESL 66E on the upper and lower surfaces of the isolation structure 100 is different. Fig.32A and Fig.32B In the example of , the central portion 66EB of the ESL 66E disposed on the lower surface of the isolation structure 100 is completely oxidized and becomes the interface layer 68, while the central portion 66EB of the ESL 66E disposed on the upper surface of the isolation structure 100 is partially oxidized (e.g., only the outer portion is oxidized). Fig.32B In the cross-sectional view of FIG. 1 , the interface layer 68B on the upper surface of each isolation structure 100 has a U shape and extends along the upper surface and sidewalls of the remaining inner portion of the central portion 66EB of the ESL 66E. In contrast, the interface layer 68B on the lower surface of each isolation structure 100 has a rectangular shape and extends along the upper surface and sidewalls of the remaining inner portion of the central portion 66EB of the ESL 66E. Fig.32B In the embodiment shown in FIG. 1 , no ESL 66E exists between the interface layer 68 and the isolation structure 100 .

[0111] Fig.33A and Fig.33B 4 is a cross-sectional view of a CFET device 400E according to yet another embodiment. The CFET device 400E is similar to the CFET device 400A, but the degree of oxidation of the ESL 66E on the upper and lower surfaces of the isolation structure is different. Fig.33A and Fig.33B In the example of , the central portion 66EB of the ESL 66E disposed on the upper surface of the isolation structure 100 is completely oxidized and becomes the interface layer 68, while the central portion 66EB of the ESL 66E disposed on the lower surface of the isolation structure 100 is partially oxidized (e.g., only the outer portion is oxidized). Fig.33B In the cross-sectional view of FIG. 1 , the interface layer 68B on the lower surface of each isolation structure 100 has a U shape and extends along the upper surface and sidewalls of the remaining inner portion of the central portion 66EB of the ESL 66E. In contrast, the interface layer 68B on the upper surface of each isolation structure 100 has a rectangular shape and extends along the upper surface and sidewalls of the remaining inner portion of the central portion 66EB of the ESL 66E. Fig.33B In the embodiment shown in FIG. 1 , no ESL 66E exists between the interface layer 68 and the isolation structure 100 .

[0112] Embodiments can achieve advantages. The disclosed method allows various shapes and structures for isolation structure 100 to meet different design goals and performance requirements. For example, by using an etch-resistant outer layer and a flowable inner layer, a double-layer structure for isolation structure 100 avoids or reduces seams in the isolation structure while still achieving the desired physical properties for the isolation structure. The double-layer structure also provides more adjustment parameters to adjust the dielectric constant of the isolation structure. As another example, by using ESL 66E on both sides of the second pseudo-nanostructure 64B, when the second pseudo-nanostructure 64B is removed, the first pseudo-nanostructure 64A is protected from undesirable etching, thereby maintaining the desired size for the gap 95, which in turn ensures that the isolation structure 100 formed in the gap 95 has a target size to achieve performance goals.

[0113] Fig.34 is a flow chart of a method 1000 of forming a CFET device according to some embodiments. It should be understood that Fig.34 The embodiment methods shown in are merely examples of many possible embodiment methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the following may be added, removed, replaced, rearranged, or repeated: Fig.34 The steps shown in .

[0114] refer to Fig.34 In block 1010, a nanostructure is formed over the fin, wherein the nanostructure includes: a lower nanostructure including a first dummy material layer interlaced with a first semiconductor material layer; an upper nanostructure located over the lower nanostructure and including a first dummy material layer interlaced with the first semiconductor material layer; a second dummy material located between the lower nanostructure and the upper nanostructure; a first etch stop layer (ESL) located between the lower nanostructure and the second dummy material; and a second ESL located between the upper nanostructure and the second dummy material. In block 1020, a dummy gate structure is formed over a first portion of the nanostructure. In block 1030, a source / drain opening is formed adjacent to the dummy gate structure and extending through the nanostructure. In block 1040, after forming the source / drain opening, the second dummy material is selectively removed from the nanostructure to form a gap between the first ESL and the second ESL. In block 1050, the gap is filled with an isolation structure. In block 1060 , after filling the gap, a first source / drain region, a dielectric structure, and a second source / drain region are sequentially formed in the source / drain openings.

[0115] In an embodiment, a method of forming a complementary field effect transistor (CFET) device includes forming a nanostructure above a fin, wherein the nanostructure includes: a lower nanostructure including a first dummy material layer interlaced with a first semiconductor material layer; an upper nanostructure located above the lower nanostructure and including a first dummy material layer interlaced with the first semiconductor material layer; a second dummy material located between the lower nanostructure and the upper nanostructure; a first etch stop layer (ESL) located between the lower nanostructure and the second dummy material; and a second ESL located between the upper nanostructure and the second dummy material. The method also includes: forming a dummy gate structure above a first portion of the nanostructure; forming a source / drain opening adjacent to the dummy gate structure and extending through the nanostructure; after forming the source / drain opening, selectively removing the second dummy material from the nanostructure to form a gap between the first ESL and the second ESL; filling the gap with an isolation structure; and after filling the gap, sequentially forming a first source / drain region, a dielectric structure, and a second source / drain region in the source / drain opening. In an embodiment, the first ESL, the second ESL and the first semiconductor material are formed of the same semiconductor material, wherein the first ESL and the second ESL are formed to be thinner than the first semiconductor material layer of the nanostructure. In an embodiment, the first dummy material and the second dummy material are formed of semiconductor materials having different components. In an embodiment, the method further comprises, after filling the gap and before sequentially forming: replacing the end portion of the first dummy material of the nanostructure exposed by the source / drain opening with an internal spacer, wherein, after filling the gap, the dielectric structure extends along the sidewall of the isolation structure, along the first sidewall of the first internal spacer and along the second sidewall of the second internal spacer, wherein the first internal spacer is located below the isolation structure and contacts the first ESL, and the second internal spacer is located above the isolation structure and contacts the second ESL, wherein the dielectric structure is disposed between an upper surface of the second internal spacer away from the fin and a lower surface of the first internal spacer facing the fin. In an embodiment, the method further comprises, after forming the second source / drain region: removing the dummy gate structure to expose the first portion of the nanostructure; after removing the dummy gate structure, selectively removing the first dummy material from the first portion of the nanostructure, wherein after selectively removing the first dummy material, the first semiconductor material in the upper nanostructure and the lower nanostructure of the first portion of the nanostructure respectively forms an upper channel region and a lower channel region of the CFET device; performing an oxidation process to convert at least an outer portion of the upper channel region, an outer portion of the lower channel region, an outer portion of the second ESL, and an outer portion of the first ESL into an interfacial layer; and after performing the oxidation process, forming a first gate structure around the lower channel region and forming a second gate structure around the upper channel region. In an embodiment, an inner portion of at least one of the first ESL and the ESL remains as a semiconductor material after the oxidation process.In an embodiment, the method further includes forming an isolation layer between the first gate structure and the second gate structure.

[0116] In an embodiment, a complementary field effect transistor (CFET) device includes: a fin; a first plurality of channel regions vertically disposed above the fin; a second plurality of channel regions vertically disposed above the first plurality of channel regions; an isolation structure located between the first plurality of channel regions and the second plurality of channel regions; a first etch stop layer (ESL) located on a lower surface of the isolation structure facing the fin; a second ESL located on an upper surface of the isolation structure away from the fin, wherein the first ESL, the second ESL, the first plurality of channel regions, and the second plurality of channel regions are the same semiconductor material; a first source / drain region located at opposite ends of the first plurality of channel regions; a second source / drain region located at opposite ends of the second plurality of channel regions; a dielectric structure located at opposite ends of the isolation structure and vertically disposed between the first source / drain region and the second source / drain region; a first gate structure located around the first plurality of channel regions; and a second gate structure located around the second plurality of channel regions. In an embodiment, the first ESL and the second ESL are thinner than the first plurality of channel regions and the second plurality of channel regions. In an embodiment, the CFET device further comprises: a first internal spacer laterally disposed between the first gate structure and the first source / drain region; and a second internal spacer laterally disposed between the second gate structure and the second source / drain region. In an embodiment, the dielectric structure contacts the sidewalls of the isolation structure, the sidewalls of the first ESL, the sidewalls of the second ESL, the sidewalls of the uppermost first internal spacer, and the sidewalls of the lowermost second internal spacer, and extends along the sidewalls of the isolation structure, the sidewalls of the first ESL, the sidewalls of the second ESL, the sidewalls of the uppermost first internal spacer, and the sidewalls of the lowermost second internal spacer. In an embodiment, the upper surface of the dielectric structure away from the fin is closer to the fin than the lowermost surface of the second plurality of channel regions facing the fin, wherein the lower surface of the dielectric structure facing the fin is farther from the fin than the uppermost surface of the first plurality of channel regions away from the fin. In an embodiment, the CFET device further comprises: a first interface layer embedded in a first ESL between the isolation structure and the first gate structure; and a second interface layer embedded in a second ESL between the isolation structure and the second gate structure, wherein the first interface layer and the second interface layer are oxides of the semiconductor material of the first ESL. In an embodiment, an end portion of the isolation structure contacts the dielectric structure, wherein a middle portion of the isolation structure is laterally disposed between the end portions of the isolation structure, wherein a first portion of the first ESL extends along the end portion of the isolation structure, and a second portion of the first ESL extends along the middle portion of the isolation structure, wherein the first portion of the first ESL is thicker than the second portion of the ESL. In an embodiment, in a cross section along a longitudinal direction of the first plurality of channel regions, the first interface layer has the same thickness as the first ESL, or the second interface layer has the same thickness as the second ESL.In an embodiment, in a cross section along a longitudinal direction of the first plurality of channel regions, the first interface layer has a smaller thickness than the first ESL, or the second interface layer has a smaller thickness than the second ESL.

[0117] In an embodiment, a complementary field effect transistor (CFET) device includes: a substrate; a fin protruding above the substrate; a first channel region vertically stacked above the fin; a second channel region vertically stacked above the first channel region; an isolation structure located between the first channel region and the second channel region; a first gate structure located around the first channel region; a second gate structure located around the second channel region; a first etch stop layer (ESL) extending along a lower surface of the isolation structure facing the substrate; a second ESL extending along an upper surface of the isolation structure away from the substrate, wherein the first channel region, the second channel region, The first ESL and the second ESL are semiconductor materials; a first interface layer embedded in the first ESL between the isolation structure and the first gate structure; a second interface layer embedded in the second ESL between the isolation structure and the second gate structure, wherein the first interface layer and the second interface layer are oxides of the semiconductor material; a first source / drain region located at opposite ends of the first channel region; a second source / drain region located at opposite ends of the second channel region; and a dielectric structure located at opposite ends of the isolation structure, wherein the dielectric structure separates the first source / drain region and the second source / drain region. In an embodiment, in a cross section along a direction perpendicular to the longitudinal direction of the first channel region, the first of the first interface layer and the second interface layer has a U-shape. In an embodiment, in a cross section, the second of the first interface layer and the second interface layer has a rectangular shape. In an embodiment, in a cross section along a direction perpendicular to the longitudinal direction of the first channel region, the first of the first interface layer and the second interface layer has a rectangular shape.

[0118] Some embodiments of the present application provide a method for forming a complementary field effect transistor (CFET) device, the method comprising: forming a nanostructure above a fin, wherein the nanostructure comprises: a lower nanostructure comprising a first pseudo material layer interlaced with a first semiconductor material layer; an upper nanostructure located above the lower nanostructure and comprising the first pseudo material layer interlaced with the first semiconductor material layer; a second pseudo material located between the lower nanostructure and the upper nanostructure; a first etch stop layer (ESL) located between the lower nanostructure and the second pseudo material; and a second etch stop layer (ESL). an etch stop layer between the upper nanostructure and the second dummy material; forming a dummy gate structure above a first portion of the nanostructure; forming a source / drain opening adjacent to the dummy gate structure and extending through the nanostructure; after forming the source / drain opening, selectively removing the second dummy material from the nanostructure to form a gap between the first etch stop layer and the second etch stop layer; filling the gap with an isolation structure; and after filling the gap, sequentially forming a first source / drain region, a dielectric structure, and a second source / drain region in the source / drain opening.

[0119] In some embodiments, the first etch stop layer, the second etch stop layer, and the first semiconductor material are formed of the same semiconductor material, wherein the first etch stop layer and the second etch stop layer are formed to be thinner than the first semiconductor material layer of the nanostructure. In some embodiments, the first dummy material and the second dummy material are formed of semiconductor materials having different compositions. In some embodiments, the method further comprises, after filling the gap and before sequentially forming: replacing the end portion of the first dummy material of the nanostructure exposed by the source / drain opening with an internal spacer, wherein after filling the gap, the dielectric structure extends along the sidewall of the isolation structure, along the first sidewall of the first internal spacer, and along the second sidewall of the second internal spacer, wherein the first internal spacer is located below the isolation structure and contacts the first etch stop layer, and the second internal spacer is located above the isolation structure and contacts the second etch stop layer, wherein the dielectric structure is disposed between an upper surface of the second internal spacer away from the fin and a lower surface of the first internal spacer facing the fin. In some embodiments, the method further comprises, after forming the second source / drain region: removing the dummy gate structure to expose the first portion of the nanostructure; after removing the dummy gate structure, selectively removing the first dummy material from the first portion of the nanostructure, wherein after selectively removing the first dummy material, the first semiconductor material in the upper nanostructure and the lower nanostructure of the first portion of the nanostructure respectively forms an upper channel region and a lower channel region of the complementary field effect transistor device; performing an oxidation process to convert at least an outer portion of the upper channel region, an outer portion of the lower channel region, an outer portion of the second etch stop layer, and an outer portion of the first etch stop layer into an interface layer; and after performing the oxidation process, forming a first gate structure around the lower channel region and forming a second gate structure around the upper channel region. In some embodiments, an inner portion of at least one of the first etch stop layer and the etch stop layer remains as the semiconductor material after the oxidation process. In some embodiments, the method further comprises: forming an isolation layer between the first gate structure and the second gate structure.

[0120] Other embodiments of the present application provide a complementary field effect transistor (CFET) device, comprising: a fin; a first plurality of channel regions vertically arranged above the fin; a second plurality of channel regions vertically arranged above the first plurality of channel regions; an isolation structure located between the first plurality of channel regions and the second plurality of channel regions; a first etch stop layer (ESL) located on a lower surface of the isolation structure facing the fin; a second etch stop layer located on an upper surface of the isolation structure away from the fin, wherein the first etch stop layer, the second etch stop layer, the first plurality of channel regions and the second plurality of channel regions are the same semiconductor material; a first source / drain region located at opposite ends of the first plurality of channel regions; a second source / drain region located at opposite ends of the second plurality of channel regions; a dielectric structure located at opposite ends of the isolation structure and vertically arranged between the first source / drain region and the second source / drain region; a first gate structure located around the first plurality of channel regions; and a second gate structure located around the second plurality of channel regions.

[0121] In some embodiments, the first etch stop layer and the second etch stop layer are thinner than the first plurality of channel regions and the second plurality of channel regions. In some embodiments, the complementary field effect transistor device further comprises: a first internal spacer disposed laterally between the first gate structure and the first source / drain region; and a second internal spacer disposed laterally between the second gate structure and the second source / drain region. In some embodiments, the dielectric structure contacts the sidewalls of the isolation structure, the sidewalls of the first etch stop layer, the sidewalls of the second etch stop layer, the sidewalls of the uppermost first internal spacer, and the sidewalls of the lowermost second internal spacer, and extends along the sidewalls of the isolation structure, the sidewalls of the first etch stop layer, the sidewalls of the second etch stop layer, the sidewalls of the uppermost first internal spacer, and the sidewalls of the lowermost second internal spacer. In some embodiments, the upper surface of the dielectric structure away from the fin is closer to the fin than the lowermost surface of the second plurality of channel regions facing the fin, wherein the lower surface of the dielectric structure facing the fin is farther from the fin than the uppermost surface of the first plurality of channel regions away from the fin. In some embodiments, the complementary field effect transistor device further comprises: a first interface layer embedded in the first etch stop layer between the isolation structure and the first gate structure; and a second interface layer embedded in the second etch stop layer between the isolation structure and the second gate structure, wherein the first interface layer and the second interface layer are oxides of the semiconductor material of the first etch stop layer. In some embodiments, an end portion of the isolation structure contacts the dielectric structure, wherein a middle portion of the isolation structure is laterally disposed between the end portions of the isolation structure, wherein a first portion of the first etch stop layer extends along the end portion of the isolation structure, and a second portion of the first etch stop layer extends along the middle portion of the isolation structure, wherein the first portion of the first etch stop layer is thicker than the second portion of the etch stop layer. In some embodiments, in a cross section along a longitudinal direction of the first plurality of channel regions, the first interface layer has the same thickness as the first etch stop layer, or the second interface layer has the same thickness as the second etch stop layer. In some embodiments, in a cross section along a longitudinal direction of the first plurality of channel regions, the first interface layer has a smaller thickness than the first etch stop layer, or the second interface layer has a smaller thickness than the second etch stop layer.

[0122] Some other embodiments of the present application provide a complementary field effect transistor (CFET) device, comprising: a substrate; a fin protruding above the substrate; a first channel region vertically stacked above the fin; a second channel region vertically stacked above the first channel region; an isolation structure located between the first channel region and the second channel region; a first gate structure located around the first channel region; a second gate structure located around the second channel region; a first etch stop layer (ESL) extending along a lower surface of the isolation structure facing the substrate; a second etch stop layer extending along an upper surface of the isolation structure away from the substrate, wherein the first channel region, the second channel region, the The first etch stop layer and the second etch stop layer are semiconductor materials; a first interface layer is embedded in the first etch stop layer between the isolation structure and the first gate structure; a second interface layer is embedded in the second etch stop layer between the isolation structure and the second gate structure, wherein the first interface layer and the second interface layer are oxides of the semiconductor material; a first source / drain region is located at opposite ends of the first channel region; a second source / drain region is located at opposite ends of the second channel region; and a dielectric structure is located at opposite ends of the isolation structure, wherein the dielectric structure separates the first source / drain region and the second source / drain region.

[0123] In some embodiments, in a cross section along a direction perpendicular to the longitudinal direction of the first channel region, the first of the first interface layer and the second interface layer has a U-shape. In some embodiments, in the cross section, the second of the first interface layer and the second interface layer has a rectangular shape. In some embodiments, in a cross section along a direction perpendicular to the longitudinal direction of the first channel region, the first of the first interface layer and the second interface layer has a rectangular shape.

[0124] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method of forming a complementary field effect transistor device, the method comprising: A nanostructure is formed above the fin, wherein the nanostructure comprises: a lower nanostructure comprising a first dummy material layer interleaved with a first semiconductor material layer; an upper nanostructure located above the lower nanostructure and comprising the first dummy material layer interlaced with the first semiconductor material layer; a second dummy material disposed between the lower nanostructure and the upper nanostructure; a first etch stop layer disposed between the lower nanostructure and the second dummy material; and a second etch stop layer disposed between the upper nanostructure and the second dummy material; and forming a dummy gate structure over the first portion of the nanostructure; forming a source / drain opening adjacent to the dummy gate structure and extending through the nanostructure; After forming the source / drain openings, selectively removing the second dummy material from the nanostructure to form a gap between the first etch stop layer and the second etch stop layer; filling the gap with an isolation structure; and After filling the gap, a first source / drain region, a dielectric structure, and a second source / drain region are sequentially formed in the source / drain opening.

2. The method according to claim 1, wherein: The first etch stop layer, the second etch stop layer, and the first semiconductor material are formed of the same semiconductor material, wherein the first etch stop layer and the second etch stop layer are formed to be thinner than the first semiconductor material layer of the nanostructure.

3. The method according to claim 2, wherein: The first dummy material and the second dummy material are formed of semiconductor materials having different compositions.

4. The method of claim 2, further comprising, after filling the gap and before sequentially forming: replacing end portions of the first dummy material of the nanostructure exposed by the source / drain opening with internal spacers, wherein After filling the gap, the dielectric structure extends along the sidewalls of the isolation structure, along the first sidewalls of the first internal spacer, and along the second sidewalls of the second internal spacer, wherein the first internal spacer is located below the isolation structure and contacts the first etch stop layer, and the second internal spacer is located above the isolation structure and contacts the second etch stop layer, wherein the dielectric structure is arranged between an upper surface of the second internal spacer away from the fin and a lower surface of the first internal spacer facing the fin.

5. The method according to claim 2, further comprising, after forming the second source / drain region: removing the dummy gate structure to expose the first portion of the nanostructure; After removing the dummy gate structure, selectively removing the first dummy material from the first portion of the nanostructure, wherein: After selectively removing the first dummy material, the first semiconductor material in the upper nanostructure and the lower nanostructure of the first portion of the nanostructure forms an upper channel region and a lower channel region of the complementary field effect transistor device, respectively; performing an oxidation process to convert at least an outer portion of the upper channel region, an outer portion of the lower channel region, an outer portion of the second etch stop layer, and an outer portion of the first etch stop layer into an interface layer; as well as After performing the oxidation process, a first gate structure is formed around the lower channel region, and a second gate structure is formed around the upper channel region.

6. The method according to claim 5, wherein: The first etch stop layer and an inner portion of at least one of the etch stop layers remain as the semiconductor material after the oxidation process.

7. The method according to claim 5, further comprising: An isolation layer is formed between the first gate structure and the second gate structure.

8. A complementary field effect transistor device, comprising: fin; a first plurality of channel regions disposed vertically above the fins; a second plurality of channel regions disposed vertically above the first plurality of channel regions; an isolation structure located between the first plurality of channel regions and the second plurality of channel regions; a first etch stop layer located on a lower surface of the isolation structure facing the fin; a second etch stop layer located on an upper surface of the isolation structure away from the fin, wherein the first etch stop layer, the second etch stop layer, the first plurality of channel regions, and the second plurality of channel regions are the same semiconductor material; first source / drain regions located at opposite ends of the first plurality of channel regions; second source / drain regions located at opposite ends of the second plurality of channel regions; a dielectric structure located at opposite ends of the isolation structure and vertically disposed between the first source / drain region and the second source / drain region; a first gate structure disposed around the first plurality of channel regions; and The second gate structure is located around the second plurality of channel regions.

9. The complementary field effect transistor device according to claim 8, wherein: The first etch stop layer and the second etch stop layer are thinner than the first plurality of channel regions and the second plurality of channel regions.

10. A complementary field effect transistor device, comprising: substrate; a fin protruding above the substrate; a first channel region vertically stacked above the fin; a second channel region vertically stacked above the first channel region; an isolation structure, located between the first channel region and the second channel region; A first gate structure, located around the first channel region; a second gate structure, located around the second channel region; a first etch stop layer extending along a lower surface of the isolation structure facing the substrate; a second etch stop layer extending along an upper surface of the isolation structure away from the substrate, wherein the first channel region, the second channel region, the first etch stop layer and the second etch stop layer are semiconductor materials; a first interface layer embedded in the first etch stop layer between the isolation structure and the first gate structure; a second interface layer embedded in the second etch stop layer between the isolation structure and the second gate structure, wherein the first interface layer and the second interface layer are oxides of the semiconductor material; a first source / drain region located at opposite ends of the first channel region; a second source / drain region located at opposite ends of the second channel region; and A dielectric structure is located at opposite ends of the isolation structure, wherein the dielectric structure separates the first source / drain region and the second source / drain region.

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