CCD output node structure capable of suppressing charge backflow noise and manufacturing method thereof

Abstract

The invention provides a CCD output node structure capable of suppressing charge backflow noise and a manufacturing method thereof. The structure comprises a substrate; the signal transfer channel is arranged on one side of the substrate; the plurality of charge transfer gate electrodes are arranged on one side, deviating from the substrate, of the signal transfer channel at intervals; the output direct current gate electrodes are arranged on the side edges of the charge transfer gate electrodes side by side; the first injection region and the second injection region are respectively arranged between the output direct current gate electrode and the substrate; the output node is arranged on one side, far away from the signal transfer channel, of the first injection region and the second injection region; the reset transistor is arranged on one side, far away from the first injection region and the second injection region, of the output node; the gate dielectric layer is arranged on one side, deviating from the substrate, of the signal transfer channel; according to the invention, a potential barrier structure for suppressing charge backflow is formed, and backflow noise can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the field of photoelectric detection, and in particular to a CCD output node structure capable of suppressing charge reflux noise and a manufacturing method thereof. Background Art

[0002] When the CCD image sensor is working, the signal charge collected by the photosensitive pixel is transferred to the output node through the horizontal shift register, where the signal charge is converted into a voltage signal and output by the on-chip output amplifier. In this process, the integrity of the output node for receiving the signal charge has a direct impact on the performance of the device. If the charge transferred to the output node flows back, this part of the backflow charge will form additional backflow noise, thereby increasing the noise level of the device. Summary of the invention

[0003] In view of the above problems existing in the prior art, the present invention proposes a CCD output node structure and a manufacturing method thereof that can suppress charge reflux noise, mainly to solve the problem that the existing CCD device has a high noise level and is difficult to meet the requirements of high-precision application scenarios.

[0004] In order to achieve the above-mentioned purpose and other purposes, the technical solution adopted by the present invention is as follows.

[0005] The present application provides a CCD output node structure capable of suppressing charge reflux noise, the structure comprising: a substrate; a signal transfer channel, which is arranged on one side of the substrate; a plurality of charge transfer gate electrodes, which are arranged at intervals on the side of the signal transfer channel away from the substrate; an output DC gate electrode, which is arranged side by side on the sides of the plurality of charge transfer gate electrodes; a first injection region and a second injection region, which are respectively arranged between the output DC gate electrode and the substrate, so that the injection concentrations of the signal transfer channel, the first injection region and the second injection region form a gradient; an output node, which is arranged on the side of the first injection region and the second injection region away from the signal transfer channel; a reset transistor, which is arranged on the side of the output node away from the first injection region and the second injection region, so as to extract the charge collected in the output node during reset; and a gate dielectric layer, which is arranged on the side of the signal transfer channel away from the substrate, so as to isolate the charge transfer gate electrode, the output DC gate electrode and the transistor gate electrode of the reset transistor from the channel of the corresponding region.

[0006] In one embodiment of the present application, the reset transistor includes: a transistor gate electrode, which is arranged on a side of the output node away from the first injection region and the second injection region; a transistor channel region, which is arranged below the transistor gate electrode and in contact with the output node, and the diameter of the transistor channel region gradually increases in a direction away from the output node; and a transistor drain region, which is connected to a side of the transistor channel region away from the output node.

[0007] In one embodiment of the present application, a charge collection region is formed on a side of the output node facing away from the substrate by ion implantation, and the charges transferred by the signal transfer channel are stored in the charge collection region, wherein the injection concentration of the charge collection region is higher than the injection concentration of the first injection region and the second injection region.

[0008] In one embodiment of the present application, a signal collection region is formed in a side of the transistor drain region facing away from the substrate by ion implantation, and the implantation concentration of the signal collection region is higher than that of the transistor drain region and the transistor channel region.

[0009] In one embodiment of the present application, the first injection region is located between the second injection region and the signal transfer channel, and the injection concentration of the second injection region is higher than the injection concentration of the first injection region, and the injection concentration of the first injection region is higher than the doping concentration of the signal transfer channel.

[0010] In an embodiment of the present application, the transistor channel region adopts a trumpet-shaped structure.

[0011] In one embodiment of the present application, the substrate is doped with P type, and the signal transfer channel, the first injection region, the second injection region, the output node, the charge collection region, the transistor channel region, the transistor drain region and the signal collection region are all doped with N type.

[0012] The present application also provides a method for manufacturing a CCD output node structure capable of suppressing charge reflux noise, the method comprising: providing a substrate; manufacturing a signal transfer channel, which is arranged on one side of the substrate; manufacturing a plurality of charge transfer gate electrodes, which are arranged at intervals on the side of the signal transfer channel away from the substrate; manufacturing a gate dielectric layer; manufacturing an output DC gate electrode, which is arranged side by side on the sides of the plurality of charge transfer gate electrodes; manufacturing a first injection region and a second injection region, which are respectively arranged between the output DC gate electrode and the substrate, so that the injection concentrations of the signal transfer channel, the first injection region and the second injection region form a gradient; manufacturing an output node, which is arranged on the side of the first injection region and the second injection region away from the signal transfer channel; manufacturing a reset transistor, which is arranged on the side of the output node away from the first injection region and the second injection region, so as to extract the charge collected in the output node during reset; wherein the gate dielectric layer is arranged on the side of the signal transfer channel away from the substrate, so as to isolate the charge transfer gate electrode, the output DC gate electrode and the transistor gate electrode of the reset transistor from the channel of the corresponding region.

[0013] As described above, the CCD output node structure capable of suppressing charge reflux noise and the manufacturing method thereof proposed in the present application have the following beneficial effects.

[0014] The present application forms a multi-barrier gradient by setting two injection regions with different concentrations in the output DC gate electrode, preventing the charge from flowing back from the output node to the model transfer channel of the horizontal shift register, thereby suppressing the reflux noise and improving the device precision. By designing the channel region of the reset transistor to be a narrow front and wide back structure, the charge can be prevented from flowing back from the drain region of the reset transistor to the output node, further reducing the reflux noise, so that the CCD device can be applied to scenes with high precision requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Schematic diagram of a top view of a CCD output node structure capable of suppressing charge reflux noise in an embodiment of the present application.

[0016] Figure 2 FIG. 1 is a cross-sectional schematic diagram of a CCD output node structure along line AA′ capable of suppressing charge backflow noise in an embodiment of the present application.

[0017] Description of Figure Numbers:

[0018] 1-signal transfer channel; 2-charge transfer gate electrode; 3-output DC gate electrode; 4-first injection region; 5-second injection region; 6-output node; 7-charge collection region; 8-transistor gate electrode; 9-transistor channel region; 10-transistor drain region; 11-signal collection region; 12-gate dielectric layer; 13-substrate. DETAILED DESCRIPTION

[0019] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0020] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0021] The inventors have found that:

[0022] When the CCD image sensor is working, the signal charge collected by the photosensitive pixel is transferred to the output node through the horizontal shift register, where the signal charge is converted into a voltage signal and output by the on-chip output amplifier. In this process, the integrity of the signal charge received by the output node has a direct impact on the performance of the device. If the charge transferred to the output node generates a reflux phenomenon, this part of the reflux charge will form additional reflux noise, thereby increasing the noise level of the device. Usually, the noise generated by the reflux charge is about 2-3e-. For conventional CCDs, the readout noise level of the device is generally dozens of electrons. The noise caused by this part of the reflux charge accounts for a small proportion and can be basically ignored. However, for scientific-grade CCDs with higher requirements for noise levels, the readout noise is about a few electrons. At this time, the contribution of the noise caused by the reflux charge to the total readout noise cannot be ignored. Therefore, for scientific-grade CCDs, it is necessary to more strictly control the reflux charge of the output node to ensure its requirements for extremely low readout noise.

[0023] Based on the shortcomings of existing CCD devices, the present application proposes a CCD output node structure and a manufacturing method thereof that can suppress charge reflux noise. The technical solution of the present application is described in detail below in conjunction with specific embodiments.

[0024] See also Figure 1 and Figure 2 , Figure 1 Schematic diagram of a top view of a CCD output node structure capable of suppressing charge reflux noise in one embodiment of the present application. Figure 2FIG. 1 is a cross-sectional diagram of a CCD output node structure along line AA' that can suppress charge reflux noise in one embodiment of the present application. Figure 1 Combination Figure 2 It can be seen that the CCD output node structure capable of suppressing charge reflux noise provided by the embodiment of the present application comprises: a substrate 13; a signal transfer channel 1, which is arranged on one side of the substrate 13; a plurality of charge transfer gate electrodes 2, which are arranged at intervals on the side of the signal transfer channel 1 away from the substrate 13; an output DC gate electrode 3, which is arranged side by side on the sides of the plurality of charge transfer gate electrodes 2; a first injection region 4 and a second injection region 5, which are respectively arranged between the output DC gate electrode 3 and the substrate 13, so that the injection of the signal transfer channel 1, the first injection region 4 and the second injection region 5 An output node 6 is arranged on a side of the first injection region 4 and the second injection region 5 away from the signal transfer channel 1; a reset transistor is arranged on a side of the output node 6 away from the first injection region 4 and the second injection region 5 to extract the charge collected in the output node 6 during reset; a gate dielectric layer 12 is arranged on a side of the signal transfer channel 1 away from the substrate 13 to isolate the charge transfer gate electrode 2, the output DC gate electrode 3 and the transistor gate electrode 8 of the reset transistor from the channel of the corresponding area.

[0025] In one embodiment, the reset transistor includes: the reset transistor includes: a transistor gate electrode 8, which is arranged on the side of the output node 6 away from the first injection area 4 and the second injection area 5; a transistor channel area 9, which is arranged below the transistor gate electrode 8 and contacts the output node 6, and the diameter of the transistor channel area 9 gradually increases in the direction away from the output node 6; a transistor drain area 10, which is connected to the side of the transistor channel area 9 away from the output node 6. Specifically, the diameter of the transistor channel area 9 close to the output node 6 is smaller than the diameter close to the transistor drain area 10. The reset transistor here can be a MOS tube. In one embodiment, the transistor channel area 9 can be designed as a trumpet-shaped structure, which will not affect the charge in the process of the charge entering the transistor drain area 10 from the output node 6, and in the process of the charge moving from the transistor drain area 10 to the output node 6, the structure with a gradually reduced diameter can effectively suppress the charge reflux, thereby reducing the charge reflux noise from the drain area to the output node 6.

[0026] In one embodiment, a charge collection region 7 is formed on the side of the output node 6 facing away from the substrate 13 by ion implantation, and the charges transferred by the signal transfer channel 1 are stored in the charge collection region 7, wherein the injection concentration of the charge collection region 7 is higher than the injection concentrations of the first injection region 4 and the second injection region 5.

[0027] In one embodiment, a signal collection region 11 is formed in a side of the transistor drain region 10 facing away from the substrate 13 by ion implantation, and the implantation concentration of the signal collection region 11 is higher than that of the transistor drain region 10 and the transistor channel region 9 .

[0028] In one embodiment, the first injection region 4 is located between the second injection region 5 and the signal transfer channel 1, and the injection concentration of the second injection region 5 is higher than the injection concentration of the first injection region 4, and the injection concentration of the first injection region 4 is higher than the doping concentration of the signal transfer channel 1. Since the injection concentration of the charge collection region 7 is higher than that of the second injection region 5, the injection concentrations of the charge collection region 7, the second injection region 5, the first injection region 4 and the signal transfer channel 1 form a gradient distribution, thereby forming a multi-level barrier structure, which can effectively prevent the charge in the output node 6 from flowing back to the signal transfer channel 1, thereby reducing the reflux noise on this path.

[0029] In one embodiment, the substrate 13 is doped with P type, and the signal transfer channel 1, the first injection region 4, the second injection region 5, the output node 6, the charge collection region 7, the transistor channel region 9, the transistor drain region 10 and the signal collection region 11 are all doped with N type.

[0030] Specifically, the CCD output structure includes: a signal transfer channel 1 of a horizontal shift register CCD, which can be doped with N type at a concentration of N-; a charge transfer gate electrode 2 of the horizontal shift register; an output DC gate electrode 3 of the horizontal shift register; a first injection region 4 below the output DC gate electrode, which can be doped with N type at a concentration of N; a second injection region 5 below the output DC gate electrode, which can be doped with N type at a concentration of N+; an output node 6, which can be doped with N type at a concentration of N-; a charge collection region 7 of the output node, which can be doped with N type at a concentration of N++; a gate electrode of a reset MOS tube (i.e., a transistor gate electrode) 8; a reset MOS tube channel region (i.e., a transistor channel region) 9, which can be doped with N type at a concentration of N-; a reset MOS tube drain region (i.e., a transistor drain region) 10, which can be doped with N type at a concentration of N-; a signal collection region 11 of the reset MOS tube drain, which can be doped with N type at a concentration of N++; a gate dielectric layer 12; and a silicon substrate 13, which is p-type doped).

[0031] When the CCD is working, by applying high and low clock pulse levels to the charge transfer gate electrode 2 of the horizontal shift register, the signal charge is driven to flow in the horizontal shift register CCD signal transfer channel 1 through the output DC gate area 3, the first injection area 4, and the second injection area 5 to the output node 6, and then collected in the output node charge collection area 7. The collected signal charge is detected by the output amplifier of the CCD and converted into a voltage signal for reading. After the signal detection is completed, the gate electrode 8 of the reset MOS tube is turned on, and the signal charge flows into the reset MOS tube drain area 10 through the reset MOS tube channel area 9 and is drawn away in the reset MOS tube drain signal collection area 11, thereby realizing the clearing of the signal charge of the output node 6, waiting for the arrival of the next signal charge, thereby completing a signal reading and reset.

[0032] In the above process, charge reflux occurs in two places. First, when the signal charge is transferred from the horizontal shift register to the output node 6 through the output DC gate electrode 3, the signal flows back from the output node 6 to the CCD signal transfer channel 1 of the horizontal shift register. Under normal circumstances, by adjusting the voltage of the output DC gate electrode, a potential barrier is formed between the horizontal shift register signal transfer channel 1 and the output node 6 to prevent the signal charge from flowing back to the horizontal shift register. However, if the operating voltage of the output DC gate electrode 3 is not properly set, or the process fluctuates, the potential barrier under the output DC gate electrode 3 will not be able to completely prevent the charge from flowing back from the output node 6 to the CCD signal transfer channel 1 of the horizontal shift register, which makes the requirements for the operating voltage and process stability higher. The embodiment of the present application is designed with two injection regions under the output DC gate electrode, with injection concentrations of N and N+ respectively, forming a concentration difference gradient structure of N-, N, N+ and N++ together with the injection concentration N- of the horizontal shift register CCD signal transfer channel 1 and the injection concentration N++ of the charge collection region 7 of the output node 6, thereby forming a natural multi-layer potential barrier gradient between the horizontal shift register CCD signal transfer channel 1 and the output node 6, rather than relying solely on the control of the output DC gate voltage to prevent charge reflux.

[0033] Second, in the process of signal charge being extracted from the output node 6 to the reset MOS tube drain signal collection area 11 through the reset MOS tube, the signal charge flows back from the reset MOS tube to the output node 6. In the embodiment of the present application, the reset MOS tube channel area 9 is designed to be a trumpet-shaped structure, with a smaller opening on the side adjacent to the output node 6 and a larger opening on the side adjacent to the reset MOS tube drain area 10. When the signal charge passes through the reset MOS tube channel area 9, it flows from the area with a smaller opening to the area with a larger opening, and will not affect the flow of the signal charge in the normal flow direction of the charge. When the charge flows back, it flows from the larger opening to the smaller opening. This structure can suppress the reverse flow of the charge.

[0034] In one embodiment, the present application also provides a method for manufacturing a CCD output node structure that can suppress charge reflux noise, the method comprising: providing a substrate; manufacturing a signal transfer channel, which is arranged on one side of the substrate; manufacturing a plurality of charge transfer gate electrodes, which are arranged at intervals on the side of the signal transfer channel away from the substrate; manufacturing a gate dielectric layer; manufacturing an output DC gate electrode, which is arranged side by side on the sides of the plurality of charge transfer gate electrodes; manufacturing a first injection region and a second injection region, which are respectively arranged between the output DC gate electrode and the substrate, so that the injection concentrations of the signal transfer channel, the first injection region and the second injection region form a gradient; manufacturing an output node, which is arranged on the side of the first injection region and the second injection region away from the signal transfer channel; manufacturing a reset transistor, which is arranged on the side of the output node away from the first injection region and the second injection region, so as to extract the charge collected in the output node during reset; wherein the gate dielectric layer is arranged on the side of the signal transfer channel away from the substrate to isolate the charge transfer gate electrode, the output DC gate electrode and the transistor gate electrode of the reset transistor from the channel of the corresponding region.

[0035] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A CCD output node structure capable of suppressing charge reflux noise, characterized in that: The structure comprises: substrate; A signal transfer channel, which is arranged on one side of the substrate; A plurality of charge transfer gate electrodes are arranged at intervals on a side of the signal transfer channel away from the substrate; An output DC gate electrode, which is arranged side by side on the sides of the plurality of charge transfer gate electrodes; A first injection region and a second injection region, which are respectively arranged between the output DC gate electrode and the substrate, so that the injection concentrations of the signal transfer channel, the first injection region and the second injection region form a gradient; an output node, which is arranged on a side of the first injection region and the second injection region away from the signal transfer channel; a reset transistor, which is arranged at a side of the output node away from the first injection region and the second injection region, so as to extract the charge collected in the output node during resetting; A gate dielectric layer is arranged on a side of the signal transfer channel away from the substrate to isolate the charge transfer gate electrode, the output DC gate electrode and the transistor gate electrode of the reset transistor from the channel in the corresponding area.

2. The CCD output node structure capable of suppressing charge reflux noise according to claim 1, characterized in that: The reset transistor comprises: a transistor gate electrode, which is arranged on a side of the output node away from the first injection region and the second injection region; a transistor channel region, which is disposed below the transistor gate electrode and in contact with the output node, wherein a diameter of the transistor channel region gradually increases in a direction away from the output node; A transistor drain region is connected to a side of the transistor channel region facing away from the output node.

3. The CCD output node structure capable of suppressing charge reflux noise according to claim 2, characterized in that: A charge collection region is formed on a side of the output node away from the substrate by ion implantation, and charges transferred by the signal transfer channel are stored in the charge collection region, wherein the injection concentration of the charge collection region is higher than that of the first injection region and the second injection region.

4. The CCD output node structure capable of suppressing charge reflux noise according to claim 3, characterized in that: A signal collection region is formed in a side of the transistor drain region away from the substrate by ion implantation, and the implantation concentration of the signal collection region is higher than that of the transistor drain region and the transistor channel region.

5. The CCD output node structure capable of suppressing charge reflux noise according to claim 3, characterized in that: The first injection region is located between the second injection region and the signal transfer channel, and the injection concentration of the second injection region is higher than the injection concentration of the first injection region, and the injection concentration of the first injection region is higher than the doping concentration of the signal transfer channel.

6. The CCD output node structure capable of suppressing charge reflux noise according to claim 2, characterized in that: The transistor channel region adopts a trumpet-shaped structure.

7. The CCD output node structure capable of suppressing charge reflux noise according to claim 5, characterized in that: The substrate is doped with P type, and the signal transfer channel, the first injection region, the second injection region, the output node, the charge collection region, the transistor channel region, the transistor drain region and the signal collection region are all doped with N type.

8. A method for manufacturing a CCD output node structure capable of suppressing charge reflux noise, characterized in that: The method comprises: providing a substrate; Making a signal transfer channel, which is arranged on one side of the substrate; Making a plurality of charge transfer gate electrodes, which are arranged at intervals on a side of the signal transfer channel away from the substrate; manufacturing a gate dielectric layer; Making an output DC gate electrode, which is arranged side by side on the sides of the plurality of charge transfer gate electrodes; Making a first injection region and a second injection region, which are respectively arranged between the output DC gate electrode and the substrate, so that the injection concentrations of the signal transfer channel, the first injection region and the second injection region form a gradient; Making an output node, which is arranged on a side of the first injection region and the second injection region away from the signal transfer channel; A reset transistor is manufactured and arranged on a side of the output node away from the first injection region and the second injection region to extract the charge collected in the output node during reset; wherein a gate dielectric layer is arranged on a side of the signal transfer channel away from the substrate to isolate the charge transfer gate electrode, the output DC gate electrode and the transistor gate electrode of the reset transistor from the channel of the corresponding area.

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