TOPCon battery and preparation method thereof

Abstract

The invention provides a TOPCon battery and a preparation method thereof, and relates to the technical field of batteries, and the preparation method of the battery comprises the following steps: preparing a first intermediate sample; wherein the first intermediate sample comprises a silicon wafer, a front surface structure and a back surface structure; wherein the front surface structure comprises a doped monocrystalline silicon layer, a second silicon dioxide layer, a second AlOx layer and a second silicon nitride layer which are sequentially stacked on the front surface of the silicon wafer; carrying out annealing treatment on the first intermediate sample to obtain a second intermediate sample; wherein the temperature of the annealing treatment is 750 to 900 DEG C; and performing subsequent treatment on the second intermediate sample to obtain the TOPCon battery. By adopting the method provided by the invention, the purpose of reducing the ultraviolet induced degradation of the TOPCon battery can be achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of batteries, and in particular to a TOPCon battery and a preparation method thereof. Background Art

[0002] TOPCon (Tunnel Oxide Passivation Contact) cell stands for tunneling oxide passivation contact cell. Its core lies in the ultra-thin tunneling oxide layer and doped polysilicon layer on the back. The tunneling oxide layer and the doped polysilicon layer together form a passivation contact structure, which can effectively reduce carrier recombination, making the TOPCon cell have higher photoelectric conversion efficiency and good stability.

[0003] However, the current TOPCon cells have the problem of UVID (Ultraviolet Induced Degradation). The generation of the UVID problem is mainly related to the material properties and structure of the TOPCon cells. On the one hand, specific materials in the battery will undergo chemical changes under ultraviolet irradiation, causing the battery performance to deteriorate; on the other hand, the structural design of the battery will also affect its resistance to ultraviolet rays. The existing technology mainly improves the anti-UVID effect of the battery by increasing the refractive index of silicon nitride (>2.3), adding a cutoff film or adding a light conversion film. Although this technical means has alleviated the UVID problem of TOPCon cells to a certain extent, it is still necessary to further reduce the ultraviolet induced attenuation of TOPCon cells. Summary of the invention

[0004] The problem solved by the present invention is: how to further reduce the ultraviolet induced attenuation of the TOPCon battery.

[0005] In order to solve the above problems, the present invention provides a method for preparing a TOPCon battery, comprising:

[0006] Step S1, preparing a first intermediate sample; wherein the first intermediate sample comprises a silicon wafer, a front structure and a back structure; wherein the front structure comprises a doped single crystal silicon layer, a second silicon oxide layer, a second AlO layer, which are sequentially stacked on the front of the silicon wafer x layer and a second silicon nitride layer;

[0007] Step S2, annealing the first intermediate sample to obtain a second intermediate sample; wherein the annealing temperature is 750-900° C.;

[0008] Step S3: performing subsequent processing on the second intermediate sample to obtain a TOPCon battery.

[0009] Optionally, in step S1, the backside structure includes a tunneling oxide layer, a doped polysilicon layer and a first silicon nitride layer stacked in sequence on the backside of the silicon wafer;

[0010] Or the back structure comprises a tunneling oxide layer (3), a doped polysilicon layer (4), a first silicon oxide layer, a first AlO layer, which are sequentially stacked on the back of the silicon wafer (1) x layer and a first silicon nitride layer (5).

[0011] Optionally, in step S2, the annealing treatment time is 10-150s.

[0012] Optionally, in step S1, the second AlO x The thickness of the layer is 2-15 nm.

[0013] Optionally, in step S1, the second AlO x The thickness of the layer is 9-15 nm.

[0014] Optionally, the thickness of the first silicon nitride layer and the second silicon nitride layer are both 40-150 nm.

[0015] Optionally, in step S3, the subsequent processing of the second intermediate sample includes: after preparing an electrode on the second intermediate sample, sequentially performing a sintering treatment and a hydrogen passivation recovery treatment.

[0016] Optionally, in step S3, the sintering temperature is 700-720°C.

[0017] Optionally, in step S3, the hydrogen passivation recovery treatment includes at least one of light injection treatment, electrical injection treatment and annealing treatment.

[0018] The present invention also provides a TOPCon battery, which is prepared by the preparation method of the TOPCon battery as described above.

[0019] Compared with the prior art, the present invention can improve the thickness (1.5-2.5nm) and quality of the second silicon oxide layer obtained on the light-receiving surface of the TOPCon cell by adding a relatively high temperature (750-900°C) annealing process before the sintering process, which is beneficial to improve the negative charge density and silicon-hydrogen bond concentration at the interface between aluminum oxide and silicon, thereby improving the stability of the aluminum oxide and silicon nitride stack on the light-receiving surface of the TOPCon cell under ultraviolet irradiation, and achieving the purpose of reducing the ultraviolet induced attenuation of the TOPCon cell. In addition, the high temperature annealing process in the present invention can be achieved by a mesh belt furnace or a roller furnace, which can be better compatible with the production line. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1Schematic diagram of the process of preparing a TOPCon battery in an embodiment of the present invention;

[0021] Figure 2 This is one of the structural schematic diagrams of the first intermediate sample in an embodiment of the present invention;

[0022] Figure 3 This is a second structural schematic diagram of the first intermediate sample in an embodiment of the present invention;

[0023] Figure 4 The attenuation of the open circuit voltage of the TOPCon cells prepared in Examples 1-2 and Examples 4-6 under different ultraviolet light conditions is compared;

[0024] Figure 5 This is a comparison diagram of negative fixed charges of the TOPCon cells prepared in Example 2, Examples 4-5 and Comparative Example 5 after UV15 irradiation;

[0025] Figure 6 This is a comparison chart of the ultraviolet attenuation of the TOPCon cells prepared in Examples 1-3 and Comparative Examples 1-3 after UV60 irradiation.

[0026] Description of reference numerals:

[0027] 1. Silicon wafer; 2. Doped single crystal silicon layer; 3. Tunneling oxide layer; 4. Doped polysilicon layer; 5. First silicon nitride layer; 6. Second AlO x layer; 7, second silicon nitride layer; 8, second silicon oxide layer; 9, first silicon oxide layer; 10, first AlO x layer. DETAILED DESCRIPTION

[0028] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be interpreted as being limited to the embodiments described herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are only for exemplary purposes and are not intended to limit the scope of protection of the present invention.

[0029] Unless otherwise defined, all technical and scientific terms used in this application have the same meanings as those commonly understood by those skilled in the art to which this application belongs; the terms used in the specification of this application are only for the purpose of describing specific implementation methods and are not intended to limit this application;

[0030] The term "including" and its variations used in this article are open inclusions, that is, "including but not limited to"; the term "based on" is "based at least in part on"; the term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment"; the term "some embodiments" means "at least some embodiments"; the term "optionally" means "optional embodiments". The relevant definitions of other terms will be given in the following description. It should be noted that the concepts of "first" and "second" mentioned in the present invention are used to distinguish different objects, rather than to describe a specific order or a primary and secondary relationship. In addition, the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, the meaning of "multiple" is two or more.

[0031] Studies have shown that the increase in negative charge density and silicon-hydrogen bond concentration at the interface between aluminum oxide and silicon can effectively suppress the UV-induced degradation of TOPCon cells. However, during the preparation of existing TOPCon cells, a thin layer of silicon oxide is usually formed at the interface between silicon and aluminum oxide. The quality and thickness of the silicon oxide layer determine the increase in negative charge density and silicon-hydrogen bond concentration at the interface between aluminum oxide and silicon.

[0032] Based on the above considerations, if Figure 1 As shown, a method for preparing a TOPCon battery provided in an embodiment of the present invention includes:

[0033] Step S1, preparing a first intermediate sample; wherein the first intermediate sample comprises a silicon wafer 1, a front structure and a back structure; wherein the front structure comprises a doped single crystal silicon layer 2, a second silicon oxide layer 8, an AlO layer 9 and a second silicon oxide layer 11 which are sequentially stacked on the front of the silicon wafer 1; x layer 6 and a second silicon nitride layer 7;

[0034] Step S2, annealing the first intermediate sample to obtain a second intermediate sample; wherein the annealing temperature is 750-900° C.;

[0035] Step S3: performing subsequent processing on the second intermediate sample to obtain a TOPCon battery.

[0036] The embodiment of the present invention can increase the thickness (1.5-2.5nm) and quality of the second silicon oxide layer obtained on the light-receiving surface of the TOPCon cell by adding a relatively high temperature (750-900°C) annealing process before the sintering process step, which is beneficial to increase the negative charge density and silicon-hydrogen bond concentration at the interface between aluminum oxide and silicon, thereby improving the stability of the aluminum oxide and silicon nitride stack on the light-receiving surface of the TOPCon cell under ultraviolet irradiation, thereby achieving the purpose of reducing the ultraviolet induced attenuation of the TOPCon cell. In addition, the high-temperature annealing process in the embodiment of the present invention can be implemented by a mesh belt furnace or a roller furnace, which can be better compatible with the production line.

[0037] It should be noted that the method of the present invention is also applicable to the preparation of TOPCon cells with other light-receiving surfaces containing an aluminum oxide layer and a silicon nitride layer. Therefore, the use of the method of the present invention in the preparation of TOPCon cells with the above-mentioned structure also falls within the scope of protection of the present application.

[0038] In some embodiments of the present invention, illustratively, Figure 2 As shown, in the step S1, the back structure includes a tunneling oxide layer 3, a doped polysilicon layer 4 and a first silicon nitride layer 5 which are sequentially stacked on the back of the silicon wafer 1. Exemplarily, in this embodiment, the method for preparing the first intermediate sample includes: cleaning the silicon wafer 1 and then performing double-sided texturing, performing boron diffusion on the front side of the silicon wafer 1 to form a doped single crystal silicon layer 2, preparing a front passivation anti-reflection layer on the surface of the doped single crystal silicon layer 2, and sequentially preparing a tunneling oxide layer 3, a doped polysilicon layer 4 and a back passivation anti-reflection layer on the back side of the silicon wafer 1 to obtain a first intermediate sample, such as Figure 2 As shown; wherein the front passivation anti-reflection layer includes a second silicon oxide layer 8, a second AlO x layer 6 and a second silicon nitride layer 7 .

[0039] In some embodiments of the present invention, illustratively, Figure 3 As shown, the back structure includes a tunneling oxide layer 3, a doped polysilicon layer 4, a first silicon oxide layer 9, a first AlO layer 12, and the like which are sequentially stacked on the back of the silicon wafer 1. x layer 10 and the first silicon nitride layer 5

[0040] In some embodiments of the present invention, in step S2, the annealing treatment time is 10-150 seconds. In this embodiment, the purpose of reducing the ultraviolet induced decay of the TOPCon cell can be achieved in a shorter time, which is beneficial to improving production efficiency.

[0041] In some embodiments of the present invention, in step S1, the second AlO x The thickness of the layer 6 is 2-15 nm. Preferably, in step S1, the second AlOx The thickness of the second AlO layer is 9-15 nm. x The thickness of the layer is about 5 nm. In this embodiment, an annealing step is added before the sintering step to make the second AlO x The thickness of layer 6 is relatively large, which is beneficial to further reduce the UV-induced degradation of the TOPCon cell.

[0042] In some embodiments of the present invention, the thickness of the first silicon nitride layer 5 and the second silicon nitride layer 7 are both 40-150 nm.

[0043] In some embodiments of the present invention, in step S3, the subsequent processing of the second intermediate sample includes: after preparing an electrode on the second intermediate sample, sequentially performing a sintering treatment and a hydrogen passivation recovery treatment.

[0044] In some embodiments of the present invention, in step S3, the temperature of the sintering treatment is 700-720°C.

[0045] In some embodiments of the present invention, in step S3, the hydrogen passivation recovery treatment includes at least one of a light injection treatment, an electrical injection treatment, and an annealing treatment.

[0046] In some embodiments of the present invention, in step S3, the hydrogen passivation recovery treatment is a light injection treatment, and the temperature of the light injection treatment is 200-700°C.

[0047] In some embodiments of the present invention, in step S1 , the tunnel oxide layer 3 is made of silicon dioxide.

[0048] The embodiment of the present invention further provides a TOPCon battery, which is manufactured using the above-mentioned method for manufacturing the TOPCon battery.

[0049] The present invention is further described below in conjunction with specific embodiments.

[0050] Example 1

[0051] A1. After cleaning the N-type silicon wafer, double-sided texturing is performed, and then boron is diffused on the front side of the N-type silicon wafer to form a boron-doped single-crystalline silicon layer. The boron-doped single-crystalline silicon layer and the N-type silicon wafer form a PN junction; wherein the thickness of the N-type silicon wafer is 130μm.

[0052] A2. Silicon dioxide and phosphorus-doped amorphous silicon are sequentially deposited on the back side of an N-type silicon wafer, and annealed to convert the phosphorus-doped amorphous silicon into phosphorus-doped polysilicon, and the silicon dioxide and phosphorus-doped polysilicon coated on the front side of the N-type silicon wafer are removed, thereby obtaining a tunneling oxide layer (made of silicon dioxide) and a phosphorus-doped polysilicon layer on the back side of the N-type silicon wafer; silicon nitride is deposited on the surface of the phosphorus-doped polysilicon layer to obtain a first silicon nitride layer; wherein the thickness of the tunneling oxide layer is 1.5 nm, the thickness of the phosphorus-doped polysilicon layer is 120 nm, and the thickness of the first silicon nitride layer is 80 nm.

[0053] A3. Depositing Al on the surface of the boron-doped single crystal silicon layer 2 O 3 , get Al 2 O 3 layer, in which the boron-doped single crystal silicon layer and Al 2 O 3 The layers will react to form a silicon oxide layer to obtain a second silicon oxide layer; 2 O 3 Silicon nitride is deposited on the surface of the layer to obtain a second silicon nitride layer, thereby preparing a first intermediate sample; wherein, Al 2 O 3 The thickness of the layer is 5 nm and the thickness of the second silicon nitride layer is 80 nm.

[0054] A4. Annealing the first intermediate sample to obtain a second intermediate sample; wherein the annealing temperature is 750° C. and the time is 2 min.

[0055] A5. After preparing the electrode on the second intermediate sample by screen printing, sintering treatment and light injection treatment are carried out in sequence to obtain a TOPCon battery; wherein the sintering treatment temperature is 720°C, the light injection treatment temperature is 550°C, and in the final TOPCon battery, the thickness of the second silicon oxide layer is 1.5-2.5nm.

[0056] Example 2

[0057] The difference from Example 1 is that in step A4, the temperature of the annealing treatment is 800°C.

[0058] Example 3

[0059] The difference from Example 1 is that in step A3, Al 2 O 3 The thickness of the layer is 15 nm, and the temperature of the annealing treatment in step A4 is 800°C.

[0060] Example 4

[0061] The difference from Example 1 is that in step A4, the temperature of the annealing treatment is 770°C.

[0062] Example 5

[0063] The difference from Example 1 is that in step A4, the temperature of the annealing treatment is 790°C.

[0064] Example 6

[0065] The difference from Example 1 is that in step A4, the temperature of the annealing treatment is 850°C.

[0066] Example 7

[0067] The difference from Example 1 is that in step A4, the temperature of the annealing treatment is 900°C.

[0068] Comparative Example 1

[0069] B1. After cleaning the N-type silicon wafer, double-sided texturing is performed, and then boron is diffused on the front side of the N-type silicon wafer to form a boron-doped single-crystalline silicon layer. The boron-doped single-crystalline silicon layer and the N-type silicon wafer form a PN junction; wherein the thickness of the N-type silicon wafer is 130 μm.

[0070] B2. Silicon dioxide and phosphorus-doped amorphous silicon are sequentially deposited on the back side of an N-type silicon wafer, and annealed to convert the phosphorus-doped amorphous silicon into phosphorus-doped polysilicon, and the silicon dioxide and phosphorus-doped polysilicon coated on the front side of the N-type silicon wafer are removed, thereby obtaining a tunneling oxide layer (made of silicon dioxide) and a phosphorus-doped polysilicon layer on the back side of the N-type silicon wafer; silicon nitride is deposited on the surface of the phosphorus-doped polysilicon layer to obtain a first silicon nitride layer; wherein the thickness of the tunneling oxide layer is 1.5 nm, the thickness of the phosphorus-doped polysilicon layer is 120 nm, and the thickness of the first silicon nitride layer is 80 nm.

[0071] B3. Depositing Al on the surface of the boron-doped single crystal silicon layer 2 O 3 , get Al 2 O 3 layer, in which the boron-doped single crystal silicon layer and Al 2 O 3 The layers will react to form a silicon oxide layer to obtain a second silicon oxide layer; 2 O 3 Silicon nitride is deposited on the surface of the layer to obtain a second silicon nitride layer, thereby preparing a first intermediate sample; wherein, Al 2 O 3 The thickness of the layer is 10 nm and the thickness of the second silicon nitride layer is 80 nm.

[0072] B4. After preparing the electrode on the first intermediate sample by screen printing, sintering treatment and light injection treatment are carried out in sequence to obtain a TOPCon battery; wherein the sintering treatment temperature is 720°C, and the light injection treatment temperature is 550°C; in the final TOPCon battery, the thickness of the second silicon oxide layer is 1.5-2.5nm.

[0073] Comparative Example 2

[0074] The difference from Comparative Example 1 is that in step B3, Al 2 O 3 The thickness of the layer is 15 nm.

[0075] Comparative Example 3

[0076] The difference from Comparative Example 1 is that in step B3, Al 2 O 3 The thickness of the layer is 5 nm.

[0077] Comparative Example 4

[0078] The difference from Example 1 is that in step A4, the temperature of the annealing treatment is 650°C.

[0079] Comparative Example 5

[0080] The difference from Example 1 is that in step A4, the temperature of the annealing treatment is 700°C.

[0081] Experimental example

[0082] The attenuation of the open circuit voltage of the TOPCon cells prepared in Examples 1-2 and Examples 4-6 under different UV conditions is shown in FIG. Figure 4 ,from Figure 4 It can be seen that the UV-induced attenuation of the open circuit voltage of the TOPCon battery prepared in Example 6 is the smallest. 2 O 3 When the layer thickness is 5 nm and the annealing temperature is 850 °C, the UV-induced degradation of the TOPCon cell is minimal.

[0083] It should be noted that Figure 4 "750℃" corresponds to Example 1, "800℃" corresponds to Example 2, "770℃" corresponds to Example 4, "790℃" corresponds to Example 5, and "850℃" corresponds to Example 6. UV0 efficiency decay refers to the data of TOPCon battery without ultraviolet light irradiation, and UV5 efficiency decay refers to the data of TOPCon battery at 5KWh / m 2 UV10 efficiency degradation refers to the data of TOPCon battery under ultraviolet irradiation of 10KWh / m 2UV15 efficiency degradation refers to the efficiency degradation of TOPCon battery under 15KWh / m 2 Data under UV exposure.

[0084] The negative fixed charge (Qf) of the TOPCon cells prepared in Example 2, Examples 4-5 and Comparative Example 5 after UV15 irradiation was tested, and the results are shown in Figure 5 ,from Figure 5 It can be seen that the TOPCon battery prepared in Example 2 has more negative fixed charge (Qf) after UV15 irradiation, indicating better passivation effect and better resistance to ultraviolet radiation.

[0085] It should be noted that UV15 irradiation refers to the TOPCon solar cell at 15KWh / m 2 irradiated under ultraviolet light. Figure 5 , "700°C" corresponds to Example 5, "800°C" corresponds to Example 2, "770°C" corresponds to Example 4, and "790°C" corresponds to Example 5.

[0086] The TOPCon cells prepared in Examples 1-3, Example 7 and Comparative Examples 1-4 were subjected to performance tests and UV attenuation tests. The results are shown in Tables 1 and Figure 6 As can be seen from Table 1, compared with Comparative Examples 1-4, the efficiency attenuation of the TOPCon cells prepared in Examples 1-3 and Example 7 is smaller under ultraviolet irradiation, indicating that the ultraviolet induced attenuation of the efficiency of the TOPCon cells prepared in Examples 1-3 and Example 7 is smaller; compared with Examples 1-2 and Example 7, the ultraviolet induced attenuation of the efficiency of the TOPCon cells prepared in Example 3 is smaller, which shows that when the annealing step is added before the sintering step, when Al 2 O 3 When the thickness of the layer is large, the UV-induced attenuation of the TOPCon cell efficiency can be further reduced, indicating that in this application, the annealing treatment and the increase of Al 2 O 3 The two technical means of layer thickness have a synergistic effect in reducing the UV-induced degradation of TOPCon cells.

[0087] It should be noted that in Table 1, UV60 efficiency degradation refers to the TOPCon battery at 60KWh / m 2 The efficiency decay under ultraviolet light, V oc is the open circuit voltage of the TOPCon battery, I sc is the short-circuit current of the TOPCon battery, and η is the efficiency of the TOPCon battery. Figure 6In the figure, "750℃-5nm" corresponds to Example 1, "800℃-5nm" corresponds to Example 2, "800℃-15nm" corresponds to Example 3, "0℃-5nm" corresponds to Example 3, "0℃-10nm" corresponds to Example 1, and "0℃-15nm" corresponds to Example 2.

[0088] Table 1

[0089]

[0090] Although the present invention is disclosed as above, the protection scope of the present invention is not limited thereto. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention, and these changes and modifications will fall within the protection scope of the present invention.

Claims

1. A method for preparing a TOPCon battery, characterized in that: include: Step S1, preparing a first intermediate sample; wherein the first intermediate sample comprises a silicon wafer (1), a front structure and a back structure; wherein the front structure comprises a doped single crystal silicon layer (2), a second silicon oxide layer (8), a second AlO layer, and a second silicon oxide layer (9) which are sequentially stacked on the front of the silicon wafer (1). x layer (6) and a second silicon nitride layer (7); Step S2, annealing the first intermediate sample to obtain a second intermediate sample; wherein the annealing temperature is 750-900° C.; Step S3: performing subsequent processing on the second intermediate sample to obtain a TOPCon battery.

2. The method for preparing a TOPCon battery according to claim 1, characterized in that: In the step S1, the backside structure comprises a tunneling oxide layer (3), a doped polysilicon layer (4) and a first silicon nitride layer (5) which are sequentially stacked on the backside of the silicon wafer (1); Or the back structure comprises a tunneling oxide layer (3), a doped polysilicon layer (4), a first silicon oxide layer (9), a first AlO x layer (10) and a first silicon nitride layer (5).

3. The method for preparing a TOPCon battery according to claim 1, characterized in that: In the step S2, the annealing treatment time is 10-150s.

4. The method for preparing a TOPCon battery according to claim 1, characterized in that: In the step S1, the second AlO x The thickness of layer (6) is 2-15 nm.

5. The method for preparing a TOPCon battery according to claim 4, characterized in that: In the step S1, the second AlO x The thickness of layer (6) is 9-15 nm.

6. The method for preparing a TOPCon battery according to claim 2, characterized in that: The thickness of the first silicon nitride layer (5) and the second silicon nitride layer (7) are both 40-150 nm.

7. The method for preparing a TOPCon battery according to claim 1, characterized in that: In the step S3, the subsequent processing of the second intermediate sample includes: after preparing an electrode on the second intermediate sample, sequentially performing a sintering process and a hydrogen passivation recovery process.

8. The method for preparing a TOPCon battery according to claim 7, characterized in that: In the step S3, the temperature of the sintering treatment is 700-720°C.

9. The method for preparing a TOPCon battery according to claim 7, characterized in that: In the step S3, the hydrogen passivation recovery treatment includes at least one of a light injection treatment, an electrical injection treatment and an annealing treatment.

10. A TOPCon battery, characterized in that: The TOPCon battery is prepared by the preparation method of any one of claims 1 to 9.

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