Semiconductor device package having exposed heat dissipation

Abstract

A semiconductor device package includes an interconnect structure having a first surface with at least one die thereon and a second surface opposite the first surface and configured to be coupled to an external device. A protection structure on a first surface of the interconnect structure exposes a heat dissipation surface facing away from the interconnect structure in one or more directions. Related devices and methods of manufacture are also discussed.

Description

[0001] Priority claim

[0002] This application claims priority to U.S. patent application No. 17 / 849,206, filed on June 24, 2022, the disclosure of which is hereby incorporated by reference herein. Technical Field

[0003] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device package. Background Art

[0004] Power semiconductor devices such as power amplifiers are used in a variety of applications, such as base stations for wireless communication systems, multi-stage and multi-path amplifiers (e.g., Doherty amplifiers), etc. The signal amplified by the power amplifier typically includes a signal having a modulated carrier having a frequency in the megahertz (MHz) to gigahertz (GHz) range. For example, circuits requiring high power handling capabilities while operating at high frequencies such as the R-band (0.5-1 GHz), S-band (3 GHz), X-band (10 GHz), Ku-band (12-18 GHz), K-band (18-27 GHz), Ka-band (27-40 GHz), and V-band (40-75 GHz) have become increasingly common. In particular, there is now a high demand for RF transistor amplifiers for amplifying radio frequency ("RF") signals having frequencies of, for example, 500 MHz and higher (including microwave frequencies).

[0005] Many power amplifier designs use semiconductor switching devices as amplifying devices. Examples of these switching devices include power transistor devices such as MOSFET (metal oxide semiconductor field effect transistor), DMOS (double diffused metal oxide semiconductor) transistor, HEMT (high electron mobility transistor), MESFET (metal semiconductor field effect transistor), LDMOS (laterally diffused metal oxide semiconductor) transistor, etc. The power amplifier may also include passive matching networks at the input nodes and output nodes of the active power transistor devices.

[0006] Transistor devices are typically formed as semiconductor integrated circuit chips. Transistor devices can be implemented, for example, in silicon, or using wide bandgap semiconductor materials (i.e., having a bandgap greater than 1.40 eV), such as silicon carbide ("SiC") and group III nitride materials. As used herein, the term "group III nitride" refers to those semiconductor compounds formed between nitrogen and group III elements in the periodic table, typically aluminum (Al), gallium (Ga) and / or indium (In). The term also refers to ternary and quaternary compounds, such as AlGaN and AlInGaN. These compounds have an empirical formula in which one mole of nitrogen is combined with a total of one mole of group III elements.

[0007] Silicon-based RF transistor amplifiers can often be implemented using LDMOS transistors and are able to exhibit high levels of linearity with relatively inexpensive manufacturing. Group III-nitride-based RF amplifiers can often be implemented using HEMTs, primarily for applications requiring high power and / or high frequency operation where LDMOS transistor amplifiers may have inherent performance limitations.

[0008] An RF transistor amplifier may include one or more amplifier stages, each of which is typically implemented as a transistor amplifier. To increase output power and current handling capability, an RF transistor amplifier is typically implemented in a "unit cell" configuration, in which a large number of individual "unit cell" transistors are electrically connected (e.g., in parallel). An RF transistor amplifier may be implemented as a single integrated circuit chip or "die," or may include multiple dies. A die or chip may include a small piece of semiconductor material or other substrate in which electronic circuit elements are fabricated. For example, multiple individual power transistor devices may be formed on a relatively large semiconductor substrate (e.g., by growing epitaxial layers thereon, doping selected regions with dopants, forming insulating layers and metal layers thereon, etc.), and the completed structure may then be cut (e.g., by sawing or cutting operations) into multiple individual dies. When multiple RF transistor amplifier dies are used, they may be connected in series and / or in parallel.

[0009] RF transistor amplifiers typically include matching circuits, such as impedance matching circuits, designed to improve impedance matching between active transistor dies (e.g., including MOSFET, HEMT, LDMOS, etc.) and transmission lines connected thereto for RF signals at fundamental operating frequencies, and harmonic termination circuits designed to at least partially terminate harmonic products, such as second-order and third-order harmonic products, that may be generated during device operation. Termination of harmonic products also affects the generation of intermodulation distortion products.

[0010] (One or more) RF amplifier transistor dies and impedance matching circuits and harmonic termination circuits can be enclosed in a device package. Integrated circuit packaging can refer to encapsulating one or more dies in a supporting housing or package (e.g., an overmold or open cavity package) that protects the die from physical damage and / or corrosion and supports electrical contacts for connection to external circuits. The input and output impedance matching circuits in an integrated circuit device package typically include an LC network that provides at least a portion of an impedance matching circuit configured to match the impedance of the active transistor die to a fixed value. The package can include electrical leads to electrically connect the RF amplifier to external circuit elements, such as input and output RF transmission lines and a bias voltage source.

[0011] Some conventional methods of assembling RF power devices may involve assembling transistor dies and some matching network components in a ceramic or overmolded package on a laminate or flange. The transistor die, capacitors, and input / output leads may be interconnected with wires, such as gold wires and / or aluminum wires. The wire-bonding-based connections of some conventional semiconductor device packages may introduce or cause several problems. For example, as the operating frequency increases (e.g., above about 5 GHz), the parasitic effects of wire bonding may cause variability in inductance, thereby affecting the design and / or effectiveness of the matching circuit. This wire-bonding-based assembly process may also be slow and sequential (e.g., one package is bonded at a time), and the assembly cost may be high (e.g., due to the cost of gold wires and expensive wire bonding machines). Summary of the invention

[0012] According to some embodiments, a semiconductor device package includes an interconnect structure having a first surface and a second surface, the first surface having at least one die thereon, the second surface being opposite to the first surface and configured to be mounted on an external device or otherwise coupled to an external device. A protective structure is provided on the first surface of the interconnect structure. The protective structure exposes a heat dissipation surface. The heat dissipation surface may face away from the interconnect structure in one or more directions.

[0013] In some embodiments, the heat dissipation surface may be an outwardly facing surface of at least one die, or a thermally conductive member and / or protective member thereon.

[0014] In some embodiments, the protection structure includes at least one opening therein that exposes the heat dissipation surface.

[0015] In some embodiments, the heat dissipation surface includes a surface of the at least one die opposite the interconnect structure.

[0016] In some embodiments, the heat dissipation surface includes a thermally conductive member on a surface of the at least one die opposite the interconnect structure.

[0017] In some embodiments, the thermally conductive member further includes one or more support structures coupled to the interconnect structure.

[0018] In some embodiments, the surface of the protective structure includes at least one opening therein that exposes the thermally conductive member.

[0019] In some embodiments, a surface of the protection structure includes at least one opening therein exposing a surface of the at least one die opposite the interconnect structure, and the thermally conductive member is located on the surface of the protection structure.

[0020] In some embodiments, at least one die includes a first surface facing the interconnect structure and respective terminals electrically connected to the conductive pattern thereof in a flip-chip configuration.

[0021] In some embodiments, at least one die includes one or more transistors having a gate connection, a source connection, or a drain connection coupled to a respective terminal.

[0022] In some embodiments, at least one die includes one or more passive electrical components.

[0023] In some embodiments, the corresponding terminal includes a conductive bump or a conductive pillar structure.

[0024] In some embodiments, the second surface of the interconnect structure includes input and output connections for the semiconductor device package.

[0025] In some embodiments, the protective structure comprises a molded structure.

[0026] In some embodiments, the protective structure includes a cover member.

[0027] In some embodiments, the cover member is positioned over the at least one die, and the heat dissipation surface comprises a surface of the cover member opposite the at least one die.

[0028] In some embodiments, the heat dissipation surface is coupled or configured to be coupled to an external cooling device.

[0029] According to some embodiments, a semiconductor device package includes an interconnect structure including a conductive pattern therein and / or thereon. The interconnect structure has a first surface and a second surface, the second surface being opposite to the first surface and being configured to be mounted on an external device or otherwise coupled to an external device. At least one die is provided on the first surface of the interconnect structure. The at least one die includes a corresponding terminal facing the first surface and electrically connected to the conductive pattern in a flip-chip configuration. A heat dissipation surface is located on at least one die. The heat dissipation surface faces away from the interconnect structure in one or more directions. For example, the heat dissipation surface can be an outwardly facing surface of at least one die, or a thermally conductive member and / or protective member thereon.

[0030] In some embodiments, the heat dissipation surface includes a surface of the at least one die opposite the interconnect structure.

[0031] In some embodiments, the heat dissipation surface includes a thermally conductive member on a surface of the at least one die opposite the interconnect structure.

[0032] In some embodiments, a protection structure is disposed on the first surface of the interconnect structure, and the protection structure exposes a heat dissipation surface, for example, a heat dissipation surface opposite to the interconnect structure.

[0033] In some embodiments, the protective structure includes a molded structure having at least one opening therein exposing the heat dissipation surface.

[0034] In some embodiments, the protection structure includes a cover member on the at least one die, and the heat dissipation surface includes a surface of the cover member opposite the at least one die.

[0035] In some embodiments, the heat dissipation surface is coupled or configured to be coupled to an external cooling device.

[0036] According to some embodiments, a method for manufacturing a semiconductor device package includes providing an interconnect structure including a first surface and a second surface, the first surface having at least one tube core thereon, the second surface being opposite to the first surface and configured to be mounted on an external device or otherwise coupled to an external device. A corresponding terminal of the at least one tube core is electrically connected to a conductive pattern of the interconnect structure. A protection structure is formed on the first surface of the interconnect structure to provide a heat dissipation surface exposed thereby.

[0037] In some embodiments, forming the protection structure includes forming the protection structure having at least one opening therein that exposes the heat sink surface.

[0038] In some embodiments, the protective structure comprises a molded structure.

[0039] In some embodiments, forming the protection structure includes a film assisted molding process, wherein the film covers the heat dissipation surface during forming the molded structure.

[0040] In some embodiments, forming the protection structure includes a laser ablation process that removes portions of the molding structure from the heat sink surface.

[0041] In some embodiments, forming the protection structure includes a mechanical grinding process that removes portions of the molding structure from the heat sink surface.

[0042] In some embodiments, the heat dissipation surface includes a surface of at least one die, such as a surface opposite the interconnect structure.

[0043] In some embodiments, the heat dissipation surface includes a thermally conductive member on a surface of at least one die, such as a surface opposite the interconnect structure.

[0044] In some embodiments, a thermally conductive member is attached to the surface of at least one die prior to forming the protection structure.

[0045] In some embodiments, after forming the protection structure, a thermally conductive member is attached to the surface of the at least one die.

[0046] In some embodiments, the protection structure includes a cover member on the at least one die, and the heat dissipation surface includes a surface of the cover member opposite the at least one die.

[0047] In some embodiments, the second surface is mounted on an external device, and / or an external cooling device is provided on the heat dissipation surface.

[0048] In some embodiments, at least one die is a Group III-nitride based material.

[0049] In some embodiments, the operating frequency of the RF transistor amplifier is in the R-band, S-band, X-band, Ku-band, K-band, Ka-band and / or V-band.

[0050] For those skilled in the art, other devices, apparatuses and / or methods according to some embodiments will be clear after reviewing the following drawings and detailed description. In addition to any and all combinations of the above embodiments, all such additional embodiments are also intended to be included in this specification, belong to the scope of the present invention, and be protected by the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 is a schematic cross-sectional view of a conventional semiconductor device package mounted on an external device.

[0052] Figure 2A and Figure 2Bis a schematic cross-sectional view of a semiconductor device package including an exposed heat dissipation surface according to some embodiments of the present disclosure mounted on an external device.

[0053] Figure 3A is a schematic plan view showing a top metallization structure of a power semiconductor device according to some embodiments of the present disclosure, which is shown by way of example using a high electron mobility transistor.

[0054] Figure 3B It is along Figure 3A A schematic cross-sectional view taken along line BB' of Figure 3A The structure of a unit cell transistor.

[0055] Figure 4A is a schematic cross-sectional view of a semiconductor device package including a non-active or back surface of a semiconductor die as an exposed heat sink surface according to some embodiments of the present disclosure.

[0056] Figure 4B Shows Figure 4A Top and bottom perspective views of a semiconductor device package.

[0057] Figure 5A is a schematic cross-sectional view of a semiconductor device package including a thermally conductive member as an exposed heat dissipation surface according to some embodiments of the present disclosure.

[0058] Figure 5B Shows Figure 5A Top and bottom perspective views of a semiconductor device package.

[0059] Figure 5C is a schematic cross-sectional view of a semiconductor device package including a thermally conductive member with an integrated clip or support structure as an exposed heat dissipation surface according to some embodiments of the present disclosure.

[0060] Fig. 6A is a schematic cross-sectional view of a semiconductor device package including a thermally conductive member as an exposed heat dissipation surface according to further embodiments of the present disclosure.

[0061] Figure 6B Shows Fig. 6A Top and bottom perspective views of a semiconductor device package.

[0062] Figure 6C is a schematic cross-sectional view of a semiconductor device package including a thermally conductive member having a plurality of integrated clips or support structures as an exposed heat dissipation surface according to some embodiments of the present disclosure.

[0063] Fig.6Dis a schematic cross-sectional view of a semiconductor device package including a plurality of thermally conductive members as exposed heat dissipation surfaces according to some embodiments of the present disclosure.

[0064] Fig. 7A , Figure 7B and Figure 7C is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device package using a film assisted molding process to expose a heat dissipation surface according to some embodiments of the present disclosure.

[0065] Fig. 8A and Figure 8B is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device package using a backside grinding process to expose a heat dissipation surface according to some embodiments of the present disclosure.

[0066] Fig.9A and Fig. 9B is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device package using a laser ablation process to expose a heat dissipation surface according to some embodiments of the present disclosure.

[0067] Fig. 10A is a plan view, and Fig. 10B is a cross-sectional view illustrating a method of manufacturing a semiconductor device package by forming a thermally conductive member on an inactive surface or a back surface of a semiconductor die before forming a molding structure thereon according to some embodiments of the present disclosure.

[0068] Fig.11A is a plan view, and Fig. 11B , Fig. 11C and Fig.11D is a cross-sectional view illustrating a method of manufacturing a semiconductor device package by forming a thermally conductive member thereon after forming a molding structure on an inactive surface or a back surface of a semiconductor die according to some embodiments of the present disclosure.

[0069] Fig.12 is a schematic cross-sectional view of a semiconductor device package including a thermally conductive lid member as an exposed heat dissipation surface according to some embodiments of the present disclosure.

[0070] Fig.13 is a schematic cross-sectional view of a semiconductor device package including a thermally conductive member as a heat dissipation surface exposed by a cover member according to some embodiments of the present disclosure.

[0071] Fig.14 is a schematic cross-sectional view of a semiconductor device package including a thermally conductive member as a heat dissipation surface supported by a side wall of a cover member according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0072] In the following detailed description, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it will be appreciated by those skilled in the art that the present disclosure can be practiced without these specific details. In some cases, well-known methods, processes, components, and circuits are not described in detail to avoid confusing the present disclosure. It is intended that all embodiments disclosed herein can be implemented individually or combined in any manner and / or combination. Aspects described with respect to an embodiment may be incorporated into different embodiments, although not specifically described relative thereto. That is, all embodiments and / or features of any embodiment may be combined in any manner and / or combination.

[0073] Figure 1 is a schematic cross-sectional view of a conventional semiconductor device package 1 mounted on an external device 2, such as a customer circuit board or other application (illustrated as a printed circuit board (PCB) or motherboard 3, which includes a heat sink or chassis 4 opposite the package 1). In particular, Figure 1 A heat conduction path 9 in a conventional massive multiple-input multiple-output (mMIMO) power amplifier 11 is illustrated.

[0074] like Figure 1 As shown in , a semiconductor device package 1 includes a semiconductor die 10 mounted on an interconnect structure 5. The semiconductor die 10 may include a semiconductor structure (e.g., a structure based on silicon, Group III nitrides, and / or silicon carbide) that defines a transistor unit cell therein. The interconnect structure 5 may be a PCB or laminate structure that includes a conductive pattern located therein or thereon. Wire bonding connections 14 electrically connect terminals of the die 10 (which are located on a "front" surface or active surface of the die adjacent to a conductive path) to the conductive pattern of the interconnect structure 5, and the wire bonding connections are covered or otherwise protected by a molding structure 40. The "back" surface or non-active surface of the die 10 is mounted on a conductive member of the interconnect structure 5, such as by a thermally conductive adhesive. Heat generated by the die 10 may be dissipated by thermal conduction or a thermally conductive path 9 to cool the power amplifier 11. In Figure 1 In the power amplifier 11 of FIG. 1 , a heat conduction path 9 is implemented through the bottom of the package 1 , to the circuit board 3 (which, in the example shown, includes an array of through-holes 6 extending therethrough), to the heat sink 4 , and out of the power amplifier 11 .

[0075] As described above, the wire-bonding-based connections of some conventional semiconductor device packages may introduce or cause several problems. For example, as the operating frequency increases (e.g., above 5 to 6 GHz), the parasitic effects of the wire bonds may cause variability in inductance, thereby affecting the design and / or effectiveness of the matching network. In addition, during operation, high levels of heat may be generated within the (one or more) semiconductor die. If the (one or more) die becomes too hot, the performance of the amplifier (e.g., output power, efficiency, linearity, gain, etc.) may deteriorate and / or the (one or more) die may be damaged. In addition, the array of through holes in the external device (which can be used for heat conduction) may impose limitations on the functionality of the external device. For example, due to Figure 1 The through hole array 6 provides a heat conduction path 9 through the external device 2 , and the bottom surface of the external device 2 may not be available for implementing other features (such as an array antenna).

[0076] Some embodiments of the present invention may stem from such a recognition that a flip chip configuration can help alleviate the above-mentioned problems and other problems. As used herein, "flip chip" may refer to a configuration in which a pad or terminal of a transistor die or other circuit components are electrically connected by a conductive bump or column rather than by wire bonding. For example, a transistor die may have one or more gate terminals, a drain terminal, and a source terminal, which are located on the same side or surface of the adjacent active conductive channel of the transistor die (also referred to herein as the active surface of the die), which is opposite to the non-active surface of the die (also referred to herein as the back surface). The terminal can be implemented by a conductive column (e.g., a copper column) and / or a conductive bump (e.g., a solder bump). The die can be "flipped" onto the underlying interconnect structure (i.e., the active surface of the die faces the interconnect structure, and the opposite non-active surface of the die faces the interconnect structure), so that one or more terminals on the active surface are electrically connected to the conductive pattern of the interconnect structure.

[0077] Thus, bond wires may not be required for the gate and drain connections, which can reduce the amount of inductance present in the circuit, thereby reducing parasitics associated with packaging and connections. Additionally, providing terminals for electrical connections at the front surface of the die for mounting in a flip chip configuration can allow thermal conduction paths away from external circuit boards or other devices or applications.

[0078] More generally, embodiments of the present invention relate to packaging techniques for semiconductor dies (e.g., silicon (Si), silicon carbide (SiC), or gallium nitride (GaN) on SiC transistor dies and / or dies including passive electrical components) that provide a thermal conduction path by exposing or otherwise providing a heat dissipation surface (e.g., a non-active surface of or a thermally conductive member on one or more semiconductor dies) at a "top" side of the package (i.e., as opposed to the side of the package that provides an interface for mounting on or otherwise coupling to an external device or application (also referred to as the bottom side of the package)). The heat dissipation surface can be used to conduct heat (through the top of the package) to a cooling solution (such as a heat sink). In some embodiments, the bottom of the semiconductor device package can be configured or optimized to achieve electrical performance, such as reducing or minimizing impedance. In some embodiments, the die(s) can be mounted in a flip-chip configuration on an interconnect structure (e.g., a single or multi-layer laminate or PCB including conductive patterns therein and / or thereon).

[0079] The interconnect structure including (one or more) dies thereon can provide a semiconductor device package, wherein the bottom side of the package (which can be provided by the bottom surface of the interconnect structure) is configured to be coupled to an external device, such as a PCB or other customer application. The top side of the package (which can include one or more exposed heat dissipation surfaces HD described herein) can also be configured to be coupled to an external device, such as a heat sink or heat spreader or other external cooling solution in a customer application. As used herein, the term "coupled" can refer to physical mounting and / or electrical connection. Thus, an element coupled to another element can be mechanically, thermally and / or electrically coupled to the other element.

[0080] Figure 2A and Figure 2B is a schematic cross-sectional view of semiconductor device packages 200a and 200b including exposed heat dissipation surfaces HD, mounted on an external device or application 2, 2', shown as a circuit board 3, 3' with one or more heat sinks or chassis 4, 4', according to some embodiments of the present disclosure. In particular, Figure 2A and Figure 2B Thermal conduction paths 209 , 209 b in example power amplifiers 211 a and 211 b (eg, mMIMO amplifiers) are illustrated.

[0081] like Figure 2A-2BAs shown in , semiconductor device packages 200a, 200b respectively include one or more semiconductor dies 110 mounted on an interconnect structure 105. (One or more) semiconductor dies 110 may include a semiconductor structure (e.g., a structure based on Si, SiC and / or GaN) that defines a transistor unit cell therein. The interconnect structure 105 may be a single-layer or multi-layer laminate, such as a printed circuit board (PCB) or a redistribution layer (RDL) laminate structure, wherein the conductive pattern 107 is implemented as a conductive trace and / or through-hole in or on a substrate of the PCB or RDL laminate structure. The interconnect structure 105 may also be a metal or ceramic structure (e.g., a low-temperature ceramic, such as LTCC) that includes a conductive pattern 107 and / or an insulating layer or pattern therein or thereon. Terminals of the semiconductor die 110 (e.g., gate terminals, drain terminals, and / or source terminals, illustrated as conductive bumps or pillar structures 222, 224, and / or 226) are adjacent to a front or active surface of the die 110 and are electrically connected to a conductive pattern of the interconnect structure 105 at a first surface of the interconnect structure 105 in a flip-chip configuration.

[0082] The interconnect structure 105 also includes an opposing second surface that is configured to be mounted on or otherwise coupled to an external device 2, 2', also referred to herein as an external device mounting interface or a package mounting interface. Figure 2A and Figure 2B In the example of the present invention, the interconnect structure 105 includes a conductive pad 115 that provides input and output package terminals or leads (referred to herein as package connections) on the second surface. The input and output package connections 115 (e.g., on the second surface of the interconnect structure 105) are configured to electrically connect the semiconductor packages 200a, 200b to the external devices 2, 2'. In any of the embodiments described herein, the package connections 115 can be configured for land grid array (LGA) or ball grid array (BGA) connections.

[0083] The molded structure (or other protective structure, such as a cover member) 240 covers or otherwise protects the die(s) 110 and the interconnect structure 105. The protective structure 240 may cover or otherwise extend over the die(s) and the interconnect structure 105. For example, the protective structure 240 may be a dispensed and cured encapsulant or compound, such as a plastic or plastic polymer compound, formed to encapsulate one or more surfaces of the die(s) 110 and the interconnect structure 105, thereby providing environmental protection for the packages 200a, 200b. As another example, the protective structure 240 may be a ceramic or other cover member that provides environmental protection for the packages 200a, 200b. The protective structure 240 may be opposite to an external device mounting interface, which in some embodiments is provided by a second surface of the interconnect structure 105.

[0084] The protection structure 240 is formed or otherwise configured to expose one or more heat dissipation surfaces HD opposite to the interconnect structure 105. Figure 2A In the embodiment of the present invention, the back surface or inactive surface of the die 110 provides a first heat dissipation surface HD exposed by the protective structure 240, and the thermally conductive member 260 on the inactive surface of the die 110 provides a second heat dissipation surface. The thermally conductive member 260 can be a thermally conductive material such as a metal flange (e.g., a copper coin) exposed by the protective structure 240 or otherwise provided at the top side of the package 200a. Figure 2B In the embodiment, the back surface or inactive surface of the die 110 provides a heat dissipation surface HD exposed by the protection structure 240. In other embodiments, the protection structure 240 itself can be thermally conductive (e.g., a thermally conductive lid member) and provide an exposed heat dissipation surface HD. More generally, the protection structure 240 can provide one or more heat dissipation surfaces HD that are exposed away from the interconnect structure 105 in one or more directions (e.g., through an opening in the protection member or otherwise exposed facing outward).

[0085] The heat generated by the die 110 may be dissipated via one or more thermal conduction or heat dissipation paths 109, 109' defined by or otherwise provided by the exposed heat dissipation surface(s) HD. Figure 2AA power amplifier configuration 211a is illustrated in which a semiconductor device package 200a is configured to provide "top" side cooling via thermal conduction or heat conduction paths 209 provided by a first heat dissipation surface HD (a non-active surface of the die 110 that is exposed by the protective structure 240 opposite the interconnect structure 105), a second heat dissipation surface HD (a surface of the thermally conductive member 260 that is opposite the interconnect structure 105), and a heat sink 4 on the heat dissipation surface HD at the top of the semiconductor package 200a. Thus, the bottom of the semiconductor package 200a (e.g., including the second or bottom surface of the interconnect structure 105) can be configured or optimized to achieve electrical performance, such as reducing or minimizing impedance. In addition, by routing the heat conduction paths 209 away from the external device 2, the external device 2 can be configured to provide additional functionality (e.g., at the back side of the PCB 3). For example, at Figure 2A In the embodiment of the present invention, an antenna array 7 is provided on the back side of the PCB 3. Other features providing additional functionality may also be included in or on the PCB 3 by routing the heat conduction path 209 away from the PCB 3 and eliminating associated structures therein that might otherwise be required for heat conduction (such as the through-hole array 6 in the power amplifier 11).

[0086] Figure 2B An alternative power amplifier configuration 211b is illustrated in which the semiconductor device package 200b is configured to provide double-sided cooling at both the top and bottom of the package 200b. Figure 2B As shown in , a first thermal conduction path 209 is provided by a heat dissipation surface HD (a non-active surface of the die 110) that is exposed by the protection structure 240 and coupled to a first heat sink 4' at the top of the amplifier 211b through a thermal interface material (TIM) 265. The TIM 265 can be any thermally conductive material, including a thermal tape or adhesive, that provides an interface with the heat dissipation surface(s) HD described herein. A second thermal conduction path 209b is provided by conductive posts or bumps 222, 224, 226 located at the active surface of the die 110 that are coupled to a conductive pattern or via 107 extending through the interconnect structure, a thermally conductive flange 6' in the PCB 3', and a second heat sink 4' located at the bottom of the amplifier 211b.

[0087] Figure 3A is a schematic plan view illustrating a top metallization structure of a semiconductor die 110 according to some embodiments of the present disclosure, which is shown by way of example of a high electron mobility transistor (HEMT) die. Figure 3B It is along Figure 3A A schematic cross-sectional view taken along line BB' shows Figure 3AAlthough described herein by way of example with reference to a HEMT, it should be understood that embodiments of the present disclosure are not limited to any particular transistor type and may include, for example, metal oxide semiconductor field effect transistor (MOSFET) embodiments, such as laterally diffused MOSFET (LDMOS) embodiments.

[0088] like Figure 3A and Figure 3B As shown in , the transistor device or die 110 may include a plurality of transistor unit cells or structures 100 connected in parallel to device terminals or electrodes (e.g., input terminals, output terminals, and ground terminals). For example, each of the gate contacts 152, drain contacts 154, and source contacts 156 may extend in a first direction (e.g., an X direction) to define gate "fingers", drain "fingers", and / or source "fingers", which may be connected by one or more corresponding busses (e.g., by gate buses and drain buses adjacent to the upper surface or active surface 136A of the semiconductor structure 190). In particular, the gate fingers 152 are electrically connected to a common gate manifold 142, and the drain fingers 154 are electrically connected to a common drain manifold 144. The gate manifold or bus 142 is electrically connected to a gate terminal 222, which may be implemented as one or more conductive bumps or pillars, and the drain manifold or bus 144 is electrically connected to a drain terminal 224, which may be implemented as one or more conductive bumps or pillars. The source fingers 156 are electrically connected to a source terminal 226, which may be implemented by one or more conductive bumps or pillars.

[0089] exist Figure 3A1 , gate fingers 152, drain fingers 154, and source fingers 156 extend parallel to each other, wherein the gate fingers 152 extend from the gate bus 142 in a first direction, and the drain fingers 154 extend from the drain bus 144 in a direction opposite to the first direction. Each gate finger 152 can be positioned between the drain finger 154 and the source finger 156 to define the unit cell 100. The gate fingers 152, drain fingers 154, and source fingers 156 (and the connection bus) can respectively define a portion of the gate connection electrode, the drain connection electrode, and the source connection electrode of the device, as defined by the top side metallization structure 140. Since the gate fingers 152 are electrically connected to the common gate bus 142, the drain fingers 154 are electrically connected to the common drain bus 144, and the source fingers 156 are electrically connected together, it can be seen that the unit cell transistors 100 are electrically connected together in parallel. One of the device's terminals (eg, source terminal 226 connected to source contact(s) 156 ) may be configured to be coupled to a reference signal, such as, for example, electrical ground.

[0090] like Figure 3B As shown in , semiconductor die 110 may be formed on a substrate 132 such as, for example, a SiC, Si or sapphire substrate, which in some embodiments may include a back surface or inactive surface 132A providing a heat dissipation surface HD. Figure 3B In the unit cell structure 100, a channel layer 134 is formed on a substrate 132. A barrier layer 136 is formed on the channel layer 134 opposite to the substrate 132. The channel layer 134 may include, for example, gallium nitride (GaN), and the barrier layer 126 may include, for example, aluminum gallium nitride (AlGaN). The channel layer 134 and the barrier layer 136 may together form a semiconductor layer structure 190 on the substrate 132. A source contact 156 and a drain contact 154 are formed on an upper surface of the barrier layer 136 and are laterally spaced apart from each other. The source contact 156 and the drain contact 154 may form an ohmic contact to the barrier layer 136.

[0091] A gate contact 152 is formed on the upper surface of the barrier layer 126 between the source contact 156 and the drain contact 154. When the HEMT device 110 is biased to be in its conducting or "on" state, a two-dimensional electron gas (2DEG) layer is formed at the junction between the channel layer 134 and the barrier layer 136. The 2DEG layer acts as a highly conductive layer that allows current to flow between the source and drain regions of the device, respectively, located below the source contact 156 and the drain contact 154. The source contact 156 can be coupled to a reference signal, such as, for example, a ground voltage.

[0092] In some embodiments, one or more insulating layers 150 may directly contact an upper surface of semiconductor structure 190 (e.g., contacting upper surface 136A of barrier layer 136). One or more insulating layers 150 may serve as a passivation layer for device 110. In some embodiments, additional metal contacts (not shown) may be provided to contact gate contact 152, drain contact 154, and / or source contact 156. For example, conductive pillar structures (e.g., copper pillars) may protrude from an active or front surface 112 of device 110 to provide electrical connections between gate contact 152, drain contact 154, and / or source contact 156 and an external device or module, such as external devices 2, 2' described herein. Figure 3A The dielectric layer is not shown in the figure to isolate the various conductive elements of the top side metallization structure 140 from each other to simplify the drawing. It should be appreciated that Figure 3A and Figure 3B (and other figures) are highly simplified diagrams, and actual semiconductor devices may include many more unit cells and various circuit systems and elements that are not shown in the simplified diagrams herein.

[0093] Figure 4A is a schematic cross-sectional view of a semiconductor device package 400 including a non-active surface or back surface of the semiconductor die 110 as an exposed heat dissipation surface according to some embodiments of the present disclosure. Figure 4B Shows Figure 4A 4A and 4B are top and bottom perspective views of a semiconductor device package 400.

[0094] like Figure 4A and Figure 4B As shown in , semiconductor device package 400 includes one or more semiconductor dies 110 on interconnect structure 105. (One or more) semiconductor dies 110 may include semiconductor structures (e.g., Si, SiC and / or GaN-based structures) that define a plurality of transistors having respective terminals (e.g., gate, drain and / or source terminals 222, 224 and / or 226) and conductive channels adjacent to their active surfaces in some embodiments. In some embodiments, one or more DC blocking capacitors may be integrated with the transistors.

[0095] The interconnect structure 105 includes a conductive pattern 107 therein and / or thereon. As described above, the interconnect structure 105 can be a single-layer or multi-layer laminate, such as a PCB or RDL laminate structure, in which the conductive pattern 107 is implemented as a conductive trace and / or through hole therein. The conductive pattern 107 is electrically connected to the corresponding terminals 222, 224, 226 of the (one or more) tube cores 110 adjacent to the first surface of the interconnect structure 105. The second surface of the interconnect structure 105 opposite to the first surface having the (one or more) tube cores 110 thereon provides an interface configured to be mounted on an external device, such as a circuit board or other application, or otherwise coupled to the external device. In some embodiments, the input lead or connection 115A and the output lead or connection 115B of the package 400 and the ground lead or connection 115G (collectively referred to as the connection 115) can be provided on the second surface of the interconnect structure 105. In example package 400, interconnect structure 105 is a multi-layer laminate including conductive pattern 107, which may be fabricated using semiconductor processing techniques, for example, by depositing conductive and insulating layers and / or patterns on a substrate and by forming vias and conductive wiring patterns within the structure.

[0096] The package 400 may also include various passive electrical components, which may include resistors, inductors, and / or capacitors implemented as discrete devices (e.g., surface mount devices (SMDs), integrated passive devices (IPDs) having thin film substrates such as silicon, alumina, or glass) and / or by elements integrated into an interconnect structure (e.g., spiral inductors, laminate-based transmission lines, etc.). The passive electrical components may be configured, for example, to provide impedance matching and / or harmonic termination circuits, and may be coupled to a respective gate terminal 222, drain terminal 224, or source terminal 226 of the transistor die(s) 110 (e.g., between the respective terminal 222, 224, or 226 and an input, output, or ground connection 115). As shown in FIG. Figure 4A As shown in , the die 130 including one or more passive electrical components is implemented in a flip chip configuration, wherein the corresponding terminals face the interconnect structure and are electrically connected to the conductive pattern. Therefore, as used herein, the term "die" can refer to an active component die 110 (e.g., a transistor die) or a passive component die 130 (e.g., a capacitor chip or an IPD). Additionally or alternatively, in some embodiments, the conductive pattern 107 of the interconnect structure 105 can define one or more passive electrical components (shown by way of example with reference to an embedded spiral inductor).

[0097] The die(s) 110 are mounted on the first surface of the interconnect structure 105 in a flip chip configuration (with underfill material 121 therebetween), with the respective terminals 222, 224, and / or 226 on the active surface of the die(s) 110 facing the interconnect structure 105 for electrical connection with the conductive pattern 107. The inactive surface of the die(s) 110 faces away from the interconnect structure 105. The passive electrical component die(s) 130 are similarly mounted on the first surface of the interconnect structure 105 in a flip chip configuration, with the back surface facing away from the interconnect structure 105.

[0098] The protective structure 240, in this example a mold structure, provides environmental protection for the die(s) 110, 130 on the first surface of the interconnect structure 105. For example, the mold structure 240 may be formed of a dispensed and cured encapsulant or compound, such as a plastic or plastic polymer compound, that encapsulates or otherwise covers the die(s) 110, 130 and one or more surfaces of the interconnect structure 105.

[0099] In the semiconductor device package 400, the inactive surfaces of the transistor die(s) 110 provide corresponding heat dissipation surfaces HD, which are exposed by the protective structure 240 or are otherwise free of the protective structure 240. The back surfaces of the passive electrical component die(s) 130 may also provide corresponding heat dissipation surfaces HD, which are exposed by the molding structure 240 or are otherwise free of the molding structure 240. The thermally conductive spacers 131 may be provided on the back surfaces of the passive electrical component die(s) 130 (and / or on the inactive surfaces of the transistor die(s) 110) to account for the height differences between the dies(s) 110 and 130, so that the corresponding heat dissipation surfaces HD may have similar heights or may be substantially coplanar. In some embodiments, more than one surface of the corresponding die(s) 110, 130 may be exposed by the protective structure 240 or be free of the protective structure 240, for example, to face away from the interconnect structure 105 in one or more directions.

[0100] The heat dissipation surface(s) HD may define one or more thermal conduction paths 209 configured to conduct heat away from the interconnect structure 105 and the external device mounting interface in one or more directions, thereby providing top-side cooling for the package 400. In some embodiments, a TIM 265 may be provided on one or more of the exposed heat dissipation surfaces HD, e.g., for attachment to an external device or heat sink.

[0101] Figure 4A and Figure 4BThe heat dissipation surface(s) HD of the package 400 may be recessed, may protrude, or may be substantially coplanar with the surface of the protection structure 240 opposite to the interconnect structure 105. ... Figure 7A-7C , Figure 8A-B or Figure 9A-9B Any of the fabrication methods described are exposed by the protective structure 240 or are free of the protective structure 240 .

[0102] Figure 5A is a schematic cross-sectional view of a semiconductor device package 500 including a thermally conductive member 260 on an inactive or back surface of a semiconductor die 110 for providing an enlarged exposed heat dissipation surface HD according to some embodiments of the present disclosure. Figure 5B Shows Figure 5A 1 and 2 are top and bottom perspective views of a semiconductor device package 500 . Figure 5C is a schematic cross-sectional view of a semiconductor device package 500' according to some embodiments of the present disclosure, the semiconductor device package 500' comprising a thermally conductive member 260 on an inactive surface or back surface of a semiconductor die 110 for providing an enlarged exposed heat dissipation surface HD, wherein the thermally conductive member 260 comprises an integrated clip or support structure 261.

[0103] like Figure 5A , Figure 5B and Figure 5C As shown in FIG. 5 , semiconductor device packages 500, 500′ include one or more semiconductor dies 110 on an interconnect structure 105, and various passive electrical components, which may be implemented by discrete devices or dies 130 (e.g., SMD, IPD, etc.) and / or elements formed by conductive patterns 107 or otherwise integrated in the interconnect structure 105. The interconnect structure 105, its conductive patterns 107, and the dies 110, 130 mounted thereon may be implemented in a manner similar to that described above with reference to FIG. Figure 4A and Figure 4B The protective structure 240 (in this example, a molding structure) provides environmental protection for the die(s) 110 , 130 on the first surface of the interconnect structure 105 , similar to the molding structure 240 of the package 400 .

[0104] In the semiconductor device packages 500, 500', at least one thermally conductive member 260 is provided on the inactive surface of the die(s) 110 as a heat dissipation surface HD exposed by the protection structure 240. For example, the thermally conductive member 260 may be attached to the surface of the die(s) 110 using solder, conductive nanoparticles (e.g., silver nanoparticles), or other thermally conductive paste or adhesive material 111. The back surface of the passive electrical component(s) die(s) 130 may also provide a corresponding heat dissipation surface HD that may be coupled to the thermally conductive member 260, for example by extending the thermally conductive member 260 laterally above the component(s) 130, and using thermally conductive spacers 131 to account for height differences between the die(s) 110 and the component(s) 130.

[0105] The semiconductor device package 500' also includes at least one clip or support structure 261 extending between the first surface of the interconnect structure 105 and the thermally conductive member 260 to provide mechanical support and / or maintain the thermally conductive member 260 substantially parallel to the top and bottom surfaces of the package 500'. In some embodiments, the (one or more) clips or support structures 261 may include the same thermally conductive material as the thermally conductive member 260 and may extend integrally from the thermally conductive member 260, and in some cases may provide (one or more) additional thermal conduction paths away from the interconnect structure 105. In other embodiments, the (one or more) clips or support structures 261 may be separate and / or thermally insulating structures that are mechanically coupled to the thermally conductive member 260, such as using an adhesive.

[0106] The heat dissipation surfaces HD of the packages 500, 500' may define an enlarged heat conduction path 209' relative to the heat conduction path 209 of the package 400, and similarly be configured to conduct heat away from the interconnect structure 105 and the external device mounting interface in one or more directions, thereby providing top-side cooling for the packages 500, 500'. In some embodiments, a TIM 265 may be provided on one or more of the exposed heat dissipation surfaces HD, e.g., for attachment to an external device or heat sink. Figure 5A , Figure 5B and Figure 5C The heat dissipation surface HD of the package 500, 500' may be recessed, may protrude, or may be substantially coplanar with the surface of the protection structure 240 opposite to the interconnect structure 105. The heat dissipation surface HD in the package 500, 500' may be used as described herein. Figure 7A-7C , Figure 8A-B or Figure 9A-9B Any of the fabrication methods described are exposed by the protective structure 240 or are free of the protective structure 240 .

[0107] Fig. 6Ais a schematic cross-sectional view of a semiconductor device package 600 according to further embodiments of the present disclosure, the semiconductor device package 600 including a thermally conductive member 260 ′ on an inactive or back surface of a die 110 , 130 for providing an exposed heat dissipation surface HD extending the length and / or width of the package 600 . Figure 6B Shows Fig. 6A 6 are top and bottom perspective views of a semiconductor device package 600. Figure 6C is a schematic cross-sectional view of a semiconductor device package 600' according to some embodiments of the present disclosure, the semiconductor device package 600' comprising a thermally conductive member 260' on an inactive surface or back surface of a die 110, 130 for providing an exposed heat dissipation surface HD extending to the length and / or width of the package 600', wherein the thermally conductive member 260' comprises a plurality of integrated clips or support structures 261. Fig.6D is a schematic cross-sectional view of a semiconductor device package 600 ″ including a plurality of thermally conductive members 260 ″ on respective inactive or back surfaces of the dies 110 , 130 for providing an exposed heat dissipation surface HD according to some embodiments of the present disclosure.

[0108] like Fig. 6A , Figure 6B , Figure 6C and Fig.6D As shown in FIG. 1 , semiconductor device packages 600, 600′, 600″ each include one or more semiconductor dies 110 on an interconnect structure 105, and various passive electrical components, which may be implemented by discrete devices or dies 130 (e.g., SMD, IPD, etc.) and / or elements formed by conductive patterns 107 or otherwise integrated in the interconnect structure 105. The interconnect structure 105, its conductive patterns 107, and the dies 110, 130 mounted thereon may be implemented in a manner similar to that described above with reference to FIG. Figure 4A and Figure 4B The protection structure 240 (in this example, a molding structure) provides environmental protection for the die(s) 110 , 130 on the first surface of the interconnect structure 105 , similar to the molding structure 240 of the package 400 .

[0109] In the semiconductor device packages 600, 600', 600", at least one thermally conductive member 260', 260" is provided on a non-active surface of the die(s) 110, 130 that is a heat dissipation surface HD exposed by the protection structure 240 (e.g., using solder or other thermally conductive adhesive material 111). The semiconductor device package 600' also includes a plurality of clips or support structures 261 extending between the first surface of the interconnect structure 105 and the thermally conductive member 260' to provide mechanical support. In some embodiments, the clips or support structures 261 may include the same thermally conductive material as the thermally conductive member 260' and may extend integrally from the thermally conductive member 260'. In other embodiments, the clips or support structures 261 may be separate and / or a thermally insulating structure mechanically coupled to the thermally conductive member 260', for example, using an adhesive. The semiconductor device package 600" also includes a plurality of thermally conductive members 260" located on the respective non-active surfaces or back surfaces of the die 110, 130. The back surface of the passive electrical component die(s) 130 may be coupled to the thermally conductive members 260 ′, 260 ″, for example using thermally conductive spacers 131 thereon, to account for height differences between the die(s) 110 , 130 .

[0110] More generally, the thermally conductive member may include a single thermally conductive member 260' or a plurality of thermally conductive members 260", which may contact one, some, or all of the dies 110, 130 in the package 600, 600', 600". The heat dissipation surface(s) HD may extend upwardly in one or more dimensions up to the entirety of the top surface of the package 600, 600', 600", to define one or more thermally conductive paths 209", which are enlarged relative to the thermally conductive paths 209' of the package 500, 500' and are similarly configured to conduct heat away from the interconnect structure 105 and external device mounting interfaces in one or more directions to provide top-side cooling for the package 600, 600'.

[0111] In some embodiments, a TIM 265 may be provided on one or more of the exposed heat dissipation surfaces HD, for example, for attachment to an external device or heat sink. Fig. 6A , Figure 6B , Figure 6C and Fig.6D The heat dissipation surface HD may be stacked on the surface of the protection structure 240 opposite to the interconnect structure 105. The heat dissipation surface HD in the package 600, 600', 600'' may be used as described herein. Figure 7A-7C , Figure 8A-B or Figure 9A-9BAny of the manufacturing methods described are exposed by the protective structure 240 or are free of the protective structure 240. Before or after forming the protective structure 240, the protective structure 240 may be formed using the method described herein. Figure 10A-10B and Figures 11A-11D Any of the fabrication methods described attach the thermally conductive member(s) 260 ′, 260 ″ to the inactive surface of the die(s) 110 , 130 opposite the interconnect structure 105 .

[0112] In addition, although FIG. 5A to FIG. 6D 1 and 2. The transistor die 110 is illustrated as including gate, source, and drain terminals 222, 224, and 226 on the same surface, but it will be understood that in any of the packages 500, 500'', 600, 600', 600'', one or more terminals of the transistor die 110, at least one of the gate terminal 222, the source terminal 226, or the drain terminal 224, may be provided on different or opposite surfaces of the die 110 via one or more conductive via structures extending through the die 110. For example, in some embodiments, the source terminal 226 may be provided on the opposite side of the die 110 from the gate terminal 222 and the drain terminal 224 on the active surface (i.e., on the non-active surface), and may be grounded or otherwise electrically connected to the thermally conductive member 260, 260', 260''. That is, in some embodiments, the thermally conductive member 260, 260', 260'' may provide both a heat dissipation function and an electrical isolation function.

[0113] Fig. 7A , Figure 7B and Figure 7C is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device package 700 according to some embodiments of the present disclosure, the method using a film assisted molding process to provide a protection structure 240 exposing one or more heat dissipation surfaces HD.

[0114] like Fig. 7AAs shown in , a molding apparatus 705 including an upper mold chase 710 and a lower mold chase 720 is opened, and one or more interconnect structures 105 (which in this example each include one or more semiconductor dies 110 and / or 130 mounted on a first surface thereof in a flip-chip manner, some of which have thermally conductive members 260 stacked thereon) are loaded into the mold chases 710, 720. For example, a plurality of interconnect structures 105 may be physically connected in strips or arrays and may be placed (automatically or manually) into the mold chases 710, 720, and may be clamped or otherwise secured in the lower mold chase 720, such as by vacuum. The upper mold chase 710 includes a film or tape material 730 loaded therein. The film or tape material 730 is pulled toward the upper mold frame 710 , such as by a vacuum, so that the film or tape material 730 can conformally extend along the inner surface of the upper mold frame 710 .

[0115] like Figure 7B As shown in , the molding apparatus 705 is closed by clamping the upper mold frame 710 and the lower mold frame 720 together so that the adhesive surface of the film or tape material 730 is pressed against or otherwise in contact with the corresponding surface of the tube core 110, 130 and / or the thermally conductive member 260 opposite the interconnect structure 105. Figure 7B In the example of FIG. 1 , the interconnect structure 105 includes some dies 110 having thermally conductive members 260 on their inactive surfaces, and other dies 110 without thermally conductive members 260. Thus, the film or tape material 730 contacts the inactive surfaces of one or more dies 110, and contacts the thermally conductive members 260 on other of the dies 110. The dies 110 having and not having the thermally conductive members 260 on their inactive surfaces may extend from the first surface of the interconnect structure 105 to substantially the same height, or to different heights.

[0116] The film or tape material 730 may have a thickness and / or compressibility configured to at least partially compensate for variations in height of the components 110, 130, and / or 260. For example, the film or tape material 730 may be configured to compensate for or allow for a tolerance of about 20 μm to 50 μm in height variations among the components 110, 130, and / or 260. In some embodiments, the height variations among the components 110, 130, and / or 260 may be less than about 20 μm, for example, about 5 μm to 15 μm. In some embodiments, the film or tape material 730 may have a thickness of about 50 μm to 100 μm.

[0117] With the molding apparatus 705 closed and the film or tape material 730 contacting the upper surface of the components 110, 130, and / or 260 opposite the interconnect structure 105, a molding compound (e.g., a plastic or polymer compound) is pressed or otherwise introduced into the molding frame to form the protective structure 240. The molding compound covers the first surface of the interconnect structure 150 and the side surfaces of the components 110, 130, and / or 260 thereon. The upper surfaces of the components 110, 130, and / or 260 are covered by the film or tape material 730, which prevents the molding compound from forming thereon.

[0118] Therefore, if Figure 7C As shown in , when removed from the molding apparatus 705, the semiconductor device package 700 includes one or more heat dissipation surfaces HD that are exposed by the protective structure 240 (here, the molding compound) opposite the interconnect structure 105 or are otherwise free of the protective structure 240. In the package 700, the heat dissipation surfaces HD include the surfaces of the die 110, 130 or the thermally conductive members 260 thereon that are exposed by the protective structure 240, for example, the surface opposite the interconnect structure 105. The second surface or bottom surface of the interconnect structure 105 includes the input leads or connections 115A and the output leads or connections 115B and the ground leads or connections 115G of the package 700, or is otherwise configured to be mounted on an external device, such as on a circuit board or other customer application.

[0119] 7A to 7C The film-assisted molding process shown in can be advantageous because the protective structure 240 can be formed so that the heat dissipation surface HD (e.g., the surface of the die(s) 110, the passive component(s), or the thermally conductive member(s) 260) can be exposed without using mechanical force and without removing portions of the semiconductor material or metal material of the components 110, 130, and / or 260. In addition, the exposed heat dissipation surface HD of the components 110, 130, and / or 260 may not require post-plating for attachment to an external device, heat sink, or other customer application. However, 7A to 7C The film assisted molding process shown in may subject components 110 , 130 , and / or 260 to higher pressures or stresses (which may damage the flip chip connections) and may require expensive processing and molding equipment.

[0120] Fig. 8A and Figure 8B is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device package 800 according to some embodiments of the present disclosure, the method using a back grinding process to provide a protection structure 240 that exposes one or more heat dissipation surfaces HD.

[0121] like Fig. 8AAs shown in , the interconnect structure 105 includes one or more tube cores 110, 130 mounted on its first surface in a flip-chip manner. A thermally conductive sheet or panel 260p is attached to the corresponding surface of the tube core 110 and / or 130 opposite to the interconnect structure 105, for example, using a thermally conductive adhesive 111. The thermally conductive panel 260p can be a metal sheet (e.g., a copper (Cu) sheet) or other thermally conductive material, which is configured to be sliced ​​or otherwise singulated to define corresponding thermally conductive components 260, 260' as described herein. For example, the thermally conductive panel 260p may include a tie rod element 211, which physically connects the portions of the thermally conductive panel 260p and is configured to be cut to define corresponding thermally conductive components 260, 260'. The tie rod element 211 can be implemented by a notched portion of the panel 260p or a portion that is otherwise thinner than the rest of the panel 260p. The tie rod elements 211 may be defined by pre-etching portions of the thermally conductive face plate 260p. The pre-etching may define molded lock features 212 in the thermally conductive face plate 260p.

[0122] Still reference Fig. 8A A preliminary protection structure 240p (in this example, an encapsulation molding structure as described herein) is formed on a first surface of the interconnect structure 105, the dies 110, 130 mounted thereon in a flip-chip manner, and a thermally conductive panel 260p on the dies 110 and / or 130 opposite the interconnect structure 105. The preliminary protection structure 240p is formed to cover one or more surfaces of the dies 110, 130 and the interconnect structure 105 and the thermally conductive panel 260p, including the surface of the panel 260p opposite the interconnect structure 105. In some embodiments, the mold-lock features 212 in the thermally conductive panel 260p can improve adhesion and / or provide mechanical support between the thermally conductive panel 260p (and the resulting thermally conductive member 260) and the molding structure.

[0123] A mechanical lapping or polishing process (eg, using a rotary or other lapping device 805) is performed to remove portions of the preliminary protection structure 240p and expose a surface of the panel 260p, such as a surface opposite the interconnect structure 105, such as Figure 8B Thus, the exposed surface of the panel 260p defines one or more heat dissipation surfaces HD exposed by the protection structure 240 (defined by the remaining portion of the preliminary protection structure 240p). The panel 260p, the protection structure 240, and the underlying interconnect structure 105 may be sliced ​​or otherwise singulated (e.g., along Figure 8B) to define respective semiconductor device packages 800, each semiconductor device package 800 having a respective heat dissipation surface HD (defined by respective thermally conductive members 260 resulting from the singulation process) opposite to respective interconnect structures 105. The heat dissipation surface may extend upward in one or more dimensions to the entirety of the top surface of package 800, which may be similar to FIG. 6A to FIG. 6C In some embodiments, one or more side surfaces of the thermally conductive member 260 (eg, portions of the tie bar elements 211 exposed by the protection structure after singulation) may also provide corresponding heat dissipation surfaces HD.

[0124] Fig. 8A and Figure 8B The mechanical grinding or polishing process shown in for exposing the heat dissipation surface HD can be advantageous because the heat dissipation surface HD (e.g., the exposed surface of the thermally conductive member(s) 260) can be exposed in a relatively inexpensive manner and can be simultaneously flattened to provide a level surface HD even if there are imperfections or variations in the placement of the thermally conductive member(s) 260 (e.g., even if the member 260 is tilted, for example, due to variations in the height of the underlying component or die 110, 130 to which the member 260 is mounted). However, the mechanical grinding or polishing process may subject the components 110, 130 and / or 260p to higher pressure or stress (which may damage the flip chip connection), and / or may require post-plating for attachment to an external device, heat sink, or other customer application.

[0125] Fig.9A and Fig. 9B is a schematic cross-sectional view illustrating a method of manufacturing semiconductor device packages 900 a and 900 b according to some embodiments of the present disclosure, the method using a laser ablation process to provide a protection structure 240 that exposes one or more heat dissipation surfaces HD.

[0126] like Fig.9A and Fig. 9B As shown in , the interconnect structure 105 includes one or more active component semiconductor dies 110 mounted on a first surface thereof in a flip-chip manner. Although not shown, one or more passive electrical component dies 130 may be similarly flip-chip mounted on a first surface of the interconnect structure 105 adjacent to the die 110. A preliminary protection structure 240p (in this example, an encapsulation molding structure as described herein) is formed on one or more surfaces of the interconnect structure 105 and the semiconductor dies 110 (and / or passive electrical component dies) mounted thereon in a flip-chip manner. Fig.9A In FIG. 1 , a preliminary protection structure 240 p is formed on an inactive surface of the semiconductor die 110 opposite to the interconnect structure 105 . Fig. 9BIn the embodiment, a corresponding thermally conductive member 260 is provided on an inactive surface of the semiconductor die 110 opposite to the interconnect structure 105 , and a preliminary protection structure 240 p is formed on a surface of the thermally conductive member 260 opposite to the interconnect structure 105 .

[0127] A laser ablation process is performed (eg, using laser 905) to remove portions of preliminary protection structure 240p and expose the inactive surface of semiconductor die 110 ( Fig.9A ) and / or a surface of the thermally conductive member 260 opposite to the interconnect structure 105 ( Fig. 9B ), thereby defining semiconductor device packages 900a and 900b, wherein respective heat dissipation surfaces HD are exposed by the protection structure 240 (defined by the remaining portion of the preliminary protection structure 240p) and face away from the interconnect structure 105 in one or more directions. Fig.9A The package 900a can be similar to FIG. 4A to FIG. 4B The package is 400, while Fig. 9B The package 900b can be similar to FIG. 5A to FIG. 5C Package 500, 500'.

[0128] Fig.9A and Fig. 9B The laser ablation process shown in for exposing the heat dissipation surface HD can be advantageous because the heat dissipation surface HD (e.g., the surface of the semiconductor die 110, passive components, and / or thermally conductive member 260 opposite to the interconnect structure 105) can be locally exposed in a relatively small area of ​​the top surface of the package 900a, 900b without subjecting the semiconductor die 110, passive components, and / or thermally conductive member 260 to higher pressure or stress (which may damage the flip chip connection). However, due to the laser ablation process, the heat dissipation surface HD may be recessed relative to the (one or more) adjacent or surrounding surfaces 240s of the protection structure 240. The recess may define a step difference of less than about 20 microns, for example, about 1 to 15 microns, between the heat dissipation surface HD and the surrounding surface 240s. In some embodiments, the step difference may be less than a few hundred microns. A post-plating process may be performed to subsequently attach the heat dissipation surface HD to an external device, a heat sink, or other customer application.

[0129] Fig. 10A is a plan view, and Fig. 10B is a cross-sectional view illustrating a method of manufacturing a semiconductor device package 1000 according to some embodiments of the present disclosure. Fig. 10A and Fig. 10B The method shown in forms a thermally conductive member 260 on an inactive surface or back surface of the semiconductor die 110 (or a passive electrical component) before forming the protection structure 240 of the package 1000 .

[0130] like Fig. 10A and Fig. 10B As shown in , the interconnect structures 105 each include one or more semiconductor dies 110 (and / or passive electrical components; not shown) mounted on a first surface of the interconnect structure 105 in a flip-chip manner. Multiple interconnect structures 105 can be physically connected into a strip or array 1005. A thermally conductive sheet or panel 260p is attached to the corresponding surface of the component or die 110 opposite to the interconnect structure 105, for example, using a thermally conductive adhesive 111. The thermally conductive panel 260p can be a metal sheet (e.g., a copper (Cu) sheet) or other thermally conductive material, which includes a tie rod element 211 that physically connects the portions of the thermally conductive panel 260p. The tie rod 211 is configured to be cut to be sliced ​​or otherwise singulated to define a corresponding thermally conductive member 260.

[0131] The protective structure 240 is formed to expose the surface of the thermally conductive panel 260p opposite to the interconnect structure 105. In particular, the protective structure 240 (shown as a molded structure in this example) is formed on the first surface of the interconnect structure 105 and on the side surfaces of the semiconductor die 110 (and / or passive electrical components) mounted thereon, but is not formed on the surface of the semiconductor die 110 (and / or passive electrical components) covered by the panel 260p. In some embodiments, a portion of the protective structure 240 may be formed on the surface of the thermally conductive panel 260p opposite to the die 110, and a portion of the protective structure 240 may be removed (e.g., using Fig. 8A and Figure 8B Mechanical grinding or polishing process or Fig.9A and Fig. 9B A laser ablation process) is performed to expose the surface of the panel 260p opposite to the interconnect structure 105.

[0132] Thus, the surface of the panel 260p defines one or more heat dissipation surfaces HD exposed by the protection structure 240, such as one or more heat dissipation surfaces HD opposite the interconnect structure 105. The panel 260p, the protection structure 240, and the underlying interconnect structure 105 may be sliced ​​or otherwise singulated (e.g., along the Fig. 10B ) to define a corresponding semiconductor device package 1000, each semiconductor device package 1000 having a corresponding heat dissipation surface HD (defined by a corresponding thermally conductive member 260 produced by the singulation process) opposite to the corresponding interconnect structure 105. The heat dissipation surface HD may extend upward in one or more dimensions to the entirety of the top surface of the package 1000, similar to FIG. 6A to FIG. 6C Package 600, 600'.

[0133] Fig.11A is a plan view, and Fig. 11B , Fig. 11C and Fig.11Dis a cross-sectional view illustrating a method of manufacturing a semiconductor device package 1100 according to some embodiments of the present disclosure. FIG. 11A to FIG. 11D The method shown in , after forming the protection structure 240 of the package 1000 , forms a thermally conductive member 260 on an inactive surface or back surface of the semiconductor die 110 (or a passive electrical component).

[0134] like Fig.11A and Fig. 11B As shown in , the interconnect structures 105 each include one or more semiconductor dies 110 (and / or passive electrical components; not shown) mounted on a first surface of the interconnect structure 105 in a flip-chip manner. A plurality of interconnect structures 105 may be physically connected into a strip or array 1105. A preliminary protection structure 240p (in this example, an encapsulation molding structure as described herein) is formed on one or more surfaces of the interconnect structure 105 and on the back surface (e.g., non-active surface) and side surfaces of the semiconductor die 110 (and / or passive electrical components) mounted thereon in a flip-chip manner. A laser ablation process is performed using a laser 905 to remove portions of the preliminary protection structure 240p and expose the non-active surface of the semiconductor die 110 (and / or passive electrical components) as a heat dissipation surface HD. Due to the laser ablation process, the heat dissipation surface HD may be recessed relative to the adjacent or surrounding surface(s) 240s of the protection structure 240.

[0135] like Fig. 11C As shown in FIG, a metal or other attachment layer 1111 is deposited (e.g., by sputtering) on ​​the surface 240s of the protection structure 240 and on the exposed heat dissipation surface HD. The metal or other attachment layer 1111 may be configured to increase adhesion to the surface 240s of the protection structure 240 and the exposed heat dissipation surface HD of the semiconductor die 110 (and / or passive electrical components).

[0136] like Fig.11D As shown in , a thermally conductive adhesive material 111 (e.g., solder, conductive nanoparticles (e.g., silver nanoparticles), or other thermally conductive paste or adhesive material) is formed on an attachment layer 1111, and a thermally conductive panel 260p is attached to a surface 240s of a protection structure 240 and a corresponding heat dissipation surface HD of a semiconductor die 110 (and / or a passive electrical component). The thermally conductive panel 260p may be a metal sheet (e.g., a Cu sheet) or other thermally conductive material, which includes pre-etched saw streets or tie bar elements 211 that physically connect portions of the thermally conductive panel 260p. The tie bars 211 are configured to be cut to be sliced ​​or otherwise singulated to define corresponding thermally conductive members 260.

[0137] Thus, the surface of the panel 260p defines one or more heat dissipation surfaces HD exposed by the protection structure 240, such as one or more heat dissipation surfaces HD opposite the interconnect structure 105. The panel 260p, the protection structure 240, and the underlying interconnect structure 105 may be sliced ​​or otherwise singulated (e.g., along Fig.11D ) to define corresponding semiconductor device packages 1100, each semiconductor device package 1100 having a corresponding heat dissipation surface HD (defined by a corresponding thermally conductive member 260 produced by the singulation process) opposite to the corresponding interconnect structure 105. The heat dissipation surface HD may extend upward in one or more dimensions to the entirety of the top surface of the package 1100, similar to FIG. 6A to FIG. 6C Package 600, 600'.

[0138] Fig.12 , Fig.13 and Fig.14 1 is a schematic cross-sectional view of semiconductor device packages 1200 , 1300 , and 1400 including a protection structure implemented by cover members 240 ′, 240 ″, 240 ′″ that expose or otherwise provide a heat dissipation surface HD according to some embodiments of the present disclosure.

[0139] like Fig.12 , Fig.13 and Fig.14 As shown in FIG. 1 , semiconductor device packages 1200, 1300, and 1400 respectively include one or more semiconductor dies 110 on an interconnect structure 105, and various passive electrical components, which may be implemented by discrete devices or dies 130 (e.g., SMD, IPD, etc.) and / or by elements formed by conductive patterns 107 or otherwise integrated in the interconnect structure 105. The interconnect structure 105, its conductive patterns 107, and the dies 110 and 130 mounted thereon may be implemented in a manner similar to that described in reference to FIG. Figure 4A and 4B The package 400 is configured, oriented and electrically connected in the manner described.

[0140] and 4A to 11DCompared to the package shown in the embodiments of 1200, 1300, 1400 including the molding structure for environmental protection as described above, the semiconductor device packages 1200, 1300, 1400 include a protective structure 240', 240", 240''' implemented as a cover member for environmental protection. The protective structure 240', 240", 240''' may be formed of ceramic or other materials and is configured to enclose (one or more) dies 110, 130 located on the first surface of the interconnect structure 105 in an open cavity. In some embodiments, the protective structure 240', 240", 240''' may be formed of a material having at least a certain thermal conductivity and may thus be used as a heat dissipation surface HD. The protective structure 240', 240", 240''' may be fixed to one or more surfaces of the interconnect structure 105 using an adhesive.

[0141] In the semiconductor device packages 1200, 1300, 1400, at least one thermally conductive member 260 is provided on an inactive surface of the die(s) 110, such as opposite the interconnect structure 105. For example, the thermally conductive member 260 may be attached to the surface of the die(s) 110 using solder, conductive nanoparticles (e.g., silver nanoparticles), or other thermally conductive paste or adhesive material 111. The back surface of the passive electrical component(s) die(s) 130 may also provide a corresponding heat dissipation surface HD that may be coupled to the thermally conductive member 260, such as by extending the thermally conductive member 260 laterally over the die(s) 130 and using thermally conductive spacers 131 thereon to account for height differences between the die(s) 110 and the component(s) 130. Although not shown, one or more clips or support structures (e.g., 261) may extend between the first surface of the interconnect structure 105 and the thermally conductive member 260 to provide mechanical support to the thermally conductive member 260.

[0142] exist Fig.12In an example of the embodiment of the present invention, one or more surfaces of the thermally conductive member 260 are in physical contact with the protective structure 240'. The protective structure 240' can be a protective cover member formed of a ceramic or other material having sufficient thermal conductivity to transfer heat from the surface of the thermally conductive member 260 to one or more thermally conductive paths 309 configured to conduct heat away from the interconnect structure 105 in one or more directions. Thus, the protective structure 240' not only encloses the components or dies 110, 130 on the interconnect structure 105 in an open cavity, but also itself provides one or more heat dissipation surfaces HD configured to conduct heat in one or more directions opposite to or away from the external device mounting interface on the bottom surface of the interconnect structure 105, thereby providing top-side cooling for the package 1200. That is, the thermally conductive member 260 is not exposed by the protective member 240', but can sufficiently spread the heat from the dies 110, 130 for dissipation, even in embodiments where the protective member 240' itself does not provide high thermal conductivity.

[0143] exist Fig.13 In the example of the cover member 240", the cover member 240" includes an opening therein that is spatially aligned with a surface of the thermally conductive member 260. For example, the opening in the protective structure 240" can provide a cavity sized to receive or otherwise expose a surface of the thermally conductive member 260 opposite the interconnect structure 105. Thus, the surface of the thermally conductive member 260 provides a heat dissipation surface HD opposite the interconnect structure 105 that is exposed by the protective structure 240". Fig.13 The heat dissipation surface HD may be recessed, may protrude, or may be substantially coplanar with a surface of the protection structure 240″ opposite the interconnect structure 105. Thus, the heat dissipation surface HD may define a heat conduction path 309′ configured to conduct heat away from the interconnect structure 105 and the external device mounting interface in one or more directions, thereby providing top-side cooling for the package 1300.

[0144] exist Fig.14In the example of , the outwardly facing surface(s) of the thermally conductive member 260 also provide one or more heat dissipation surfaces HD that are opposite or otherwise facing away from the interconnect structure 105 in one or more directions, and are mechanically supported by portions of the protective structure 240''' to enclose the components or die 110, 130 in the open cavity. In particular, the protective structure 240''' extends around the periphery of the die 110, 130 to define the side walls or side surfaces of the package 1400. The thermally conductive member 260 extends upward in one or more dimensions to the entirety of the top surface of the package 1400, thereby both defining the heat dissipation surface HD and providing environmental protection for the die 110, 130. The heat dissipation surface HD defines a thermal conduction path 309'' that is enlarged relative to the path of the package 1300, but is similarly configured to conduct heat away from the interconnect structure 105 and the external device mounting interface in one or more directions, thereby providing top-side cooling for the package 1400. In . Fig.13 and 14 In some embodiments, the protection structure 240 ″ and / or 240 ′″ may not need to be thermally conductive and may be formed of a thermally insulating material.

[0145] Thus, embodiments of the present disclosure provide semiconductor device packages having one or more heat dissipation surfaces that are opposite or otherwise facing away from a package mounting interface in one or more directions, thereby allowing one or more heat conduction paths in a direction opposite or otherwise facing away from an external device (e.g., a circuit board or other customer application). Such top-side cooling can reduce complexity requirements for the external device or application, such as by removing the requirement for vias or other heat conduction paths through the external device. In addition, embodiments of the present disclosure can also provide improved thermal capacity, such as by establishing a heat conduction path that is separate or independent from an electrical ground path (e.g., by providing a source terminal on the front surface of the transistor die and providing (one or more) heat conduction paths by coupling the back surface of the transistor die to a thermally conductive member), which otherwise may be difficult or impossible to achieve without a flip-chip interconnect scheme as described herein.

[0146] Embodiments of the present disclosure may be used for mMIMO or other lower power / lower frequency products, but may also be used for higher power / higher frequency RF power products that may benefit from a flip chip configuration and top side cooling. For example, some embodiments of the present disclosure may be used for high power RF transistors for cellular or aerospace and defense (A&D) applications, such as 20W or higher average output power RF transistors for 5G base station applications at 3.5GHz and above. Embodiments of the present disclosure may also allow for lower cost products that are configured to operate at higher frequencies. Although embodiments of the present disclosure have been described herein with reference to specific HEMT structures, the present disclosure should not be construed as limited to such structures, and the present disclosure may be applied to form many different transistor structures, such as pHEMTs (including GaAs / AlGaAs pHEMTs) and / or GaN MESFETs.

[0147] Various embodiments have been described herein with reference to the accompanying drawings in which example embodiments are shown. However, these embodiments may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete and to fully convey the inventive concept to those skilled in the art. Various modifications to the example embodiments and the general principles and features described herein will be clear. In the accompanying drawings, the sizes and relative sizes of layers and regions are not shown to scale and may be exaggerated in some cases for clarity.

[0148] It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0149] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "a kind of" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "comprise", "comprises", "includes" and / or "comprising" specify the presence of the features, integers, steps, operations, elements and / or parts when used herein, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups thereof.

[0150] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and unless explicitly defined as such herein, are not interpreted in an idealized or overly formal sense.

[0151] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on another element," "attached to another element," or "extending onto another element," it can be directly on the other element or intervening elements may also be present. Conversely, when an element is referred to as being "directly on another element," "directly attached to another element," or "extending directly onto another element," there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0152] Relative terms such as "below" or "above" or "up" or "lower" or "top" or "bottom" or "horizontal" or "lateral" or "vertical" may be used to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0153] Embodiments of the present invention are described herein with reference to cross-sectional views of schematic diagrams of idealized embodiments (and intermediate structures) of the present invention. For clarity, the thickness of the layers and regions in the figures may be exaggerated. In addition, deviations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, embodiments of the present invention should not be interpreted as being limited to the specific shapes of the regions shown herein, but should include shape deviations, for example, caused by manufacturing. Elements illustrated by dotted lines may be optional in the illustrated embodiments.

[0154] The same reference numerals refer to the same elements throughout. Therefore, the same or similar reference numerals may be described with reference to other drawings, even if they are neither mentioned nor described in the corresponding drawings. Moreover, elements not represented by reference numerals may be described with reference to other drawings.

[0155] In the drawings and specification, typical embodiments of the invention have been disclosed, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the appended claims.

Claims

1. A semiconductor device package, comprising: an interconnect structure including a first surface having at least one die thereon and a second surface, the first surface being opposite the first surface and configured to be coupled to an external device; A protection structure is located on the first surface of the interconnect structure, wherein the protection structure exposes a heat dissipation surface. 2 . The semiconductor device package of claim 1 , wherein the protection structure includes at least one opening therein exposing the heat dissipation surface. 3 . The semiconductor device package of claim 2 , wherein the heat dissipation surface comprises a surface of the at least one die. 4 . The semiconductor device package of claim 1 , wherein the heat dissipation surface comprises a thermally conductive member on a surface of the at least one die. 5 . The semiconductor device package of claim 4 , wherein the thermally conductive member further comprises one or more support structures coupled to the interconnect structure. 6 . The semiconductor device package of claim 4 , wherein a surface of the protection structure includes at least one opening therein exposing the thermally conductive member.

7. The semiconductor device package of claim 4, wherein a surface of the protection structure includes at least one opening therein, the at least one opening exposing a surface of the at least one die opposite to the interconnect structure, and the thermally conductive member is located on the surface of the protection structure.

8. A semiconductor device package as claimed in any preceding claim, wherein the at least one die comprises respective terminals facing the first surface of the interconnect structure and electrically connected to the conductive pattern thereof in a flip chip configuration.

9. The semiconductor device package of claim 8, wherein the at least one die comprises one or more transistors having a gate connection, a source connection, or a drain connection coupled to a respective terminal.

10. The semiconductor device package of claim 8, wherein the at least one die comprises one or more passive electrical components. 11 . The semiconductor device package of claim 8 , wherein the corresponding terminal comprises a conductive bump or a conductive pillar structure.

12. The semiconductor device package of any preceding claim, wherein the second surface of the interconnect structure comprises input and output connections for the semiconductor device package.

13. The semiconductor device package according to any one of claims 1 to 12, wherein the protection structure comprises a molding structure.

14. The semiconductor device package of any one of claims 12, wherein the protection structure comprises a cover member.

15. The semiconductor device package of claim 14, wherein the cover member is located on the at least one die, and the heat dissipation surface comprises a surface of the cover member opposite the at least one die.

16. A semiconductor device package, comprising: an interconnect structure including a conductive pattern therein and / or thereon, the interconnect structure including a first surface and a second surface, the second surface being opposite to the first surface and configured to be coupled to an external device; at least one die on the first surface of the interconnect structure, the at least one die including respective terminals facing the first surface and electrically connected to the conductive pattern in a flip-chip configuration; as well as A heat dissipation surface is located on the at least one die and faces away from the interconnect structure in one or more directions.

17. The semiconductor device package of claim 16, wherein the heat dissipation surface comprises a surface of the at least one die.

18. The semiconductor device package of claim 16, wherein the heat dissipation surface comprises a thermally conductive member on a surface of the at least one die.

19. The semiconductor device package according to claim 16, further comprising: A protection structure is located on the first surface of the interconnect structure, wherein the protection structure exposes the heat dissipation surface. 20 . The semiconductor device package of claim 19 , wherein the protection structure comprises a mold structure having at least one opening therein exposing the heat dissipation surface.

21. The semiconductor device package of claim 19, wherein the protection structure comprises a cover member located on the at least one die, and the heat dissipation surface comprises a surface of the cover member opposite the at least one die.

22. A method for manufacturing a semiconductor device package, the method comprising: providing an interconnect structure comprising a first surface having at least one die thereon and a second surface, the first surface being opposite to the first surface and configured to be coupled to an external device, wherein respective terminals of the at least one die are electrically connected to conductive patterns of the interconnect structure; as well as A protection structure is formed on the first surface of the interconnect structure to provide a heat dissipation surface exposed thereby.

23. The method of claim 22, wherein forming the protection structure comprises forming a protection structure having at least one opening therein exposing the heat sink surface.

24. The method of claim 23, wherein the protective structure comprises a molded structure.

25. The method of claim 24, wherein forming the protection structure comprises a film assisted molding process, wherein a film covers the heat dissipation surface during forming the molding structure.

26. The method of claim 24, wherein forming the protection structure comprises a laser ablation process that removes portions of the molding structure from the heat sink surface.

27. The method of claim 24, wherein forming the protection structure comprises a mechanical grinding process that removes portions of the molding structure from the heat sink surface.

28. The method of claim 23, wherein the heat dissipation surface comprises a surface of the at least one die.

29. The method of claim 22, wherein the heat dissipation surface comprises a thermally conductive member on a surface of the at least one die.

30. The method of claim 29, further comprising attaching the thermally conductive member to the surface of the at least one die prior to forming the protection structure.

31. The method of claim 29, further comprising attaching the thermally conductive member to the surface of the at least one die after forming the protection structure.

32. The method of claim 22 or 23, wherein the protection structure comprises a cover member positioned over the at least one die, and the heat dissipation surface comprises a surface of the cover member opposite the at least one die.

33. The semiconductor device package of any one of claims 1 to 15, wherein the heat dissipation surface is coupled or configured to be coupled to an external cooling device.

34. A semiconductor device package as claimed in any one of claims 16 to 21, wherein the heat dissipation surface is coupled or configured to be coupled to an external cooling device.

35. The method of any one of claims 22 to 32, further comprising: mounting the second surface on the external device; and / or An external cooling device is arranged on the heat dissipation surface.

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