Error correction decoding device and error correction decoding method

Abstract

An error correction decoding device is configured to decode a multi-valued modulation symbol having a dimension of D and a number of bits per dimension of M (M is an integer of 2 or more) from each of D (D is an integer of 1 or more) pulse amplitude modulation symbols. An error correction decoding device is provided with: a soft decision unit (1) that acquires each pulse amplitude modulation symbol from a communication symbol sequence in which D pulse amplitude modulation symbols are arranged, calculates, on the basis of each pulse amplitude modulation symbol, a positive or negative first hard decision bit indicating the logarithmic posterior probability ratio of each of M bits included in a multi-valued modulation symbol, and outputs the calculated first hard decision bit to a second hard decision bit that indicates the logarithmic posterior probability ratio of each of the M bits included in the multi-valued modulation symbol; calculating an absolute value of each logarithmic posterior probability ratio as a first reliability; and an exclusive-OR calculation unit (2) that calculates the exclusive-OR of the D * M first hard decision bits calculated by the soft decision unit (1). Furthermore, the error correction decoding device is provided with: a reliability selection unit (3) which compares the D * M first reliability degrees calculated by the soft decision unit (1) with each other, selects one first reliability degree from among the D * M first reliability degrees on the basis of the result of the comparison, and outputs the one first reliability degree as a second reliability degree; and a soft decision error correction decoding unit (4) that performs soft decision error correction decoding on the result of the exclusive OR operation performed by the exclusive OR operation unit (2) and the second reliability.

Description

Technical Field

[0001] The present disclosure relates to an error correction decoding device and an error correction decoding method. Background Art

[0002] There is an error correction decoding device that decodes D (D is an integer greater than 1) pulse amplitude modulation symbols into multi-value modulation symbols with D dimensions and M (M is an integer greater than 2) bits per dimension (for example, refer to non-patent document 1).

[0003] The error correction decoding device includes a soft decision unit that performs soft decisions on D pulse amplitude modulation symbols to calculate hard decision bits indicating whether a logarithmic posterior probability ratio of each bit included in a multi-value modulation symbol of dimension D is positive or negative.

[0004] When the pulse amplitude modulation symbol is quantized by N bits in each dimension, the number of coordinates after quantization on the receiving side is 2^N^D. For example, if N=6 and D=4, the number of coordinates is 2^6^4=16,777,216.

[0005] Prior art literature

[0006] Non-patent literature

[0007] Non-patent literature 1: T. Kakizaki et al., "Low-complexity Channel-polarized Multilevel Coding for Probabilistic Amplitude Shaping," Proc. OFC 2022, W3H.4. Summary of the invention

[0008] Problems to be solved by the invention

[0009] In the error correction decoding device disclosed in Non-Patent Document 1, as the dimension D increases, the soft decision unit needs to perform more calculations on the hard decision bits and the reliability. As a result, it may take a long time for the soft decision unit to decode the multi-value modulation symbol.

[0010] If the soft decision unit has a lookup table that has 2^N^D address spaces and can store hard decision bits and reliability corresponding to the value of the pulse amplitude modulation symbol of dimension D, the hard decision bits and reliability corresponding to the value of the pulse amplitude modulation symbol can be obtained respectively. However, the larger the dimension, the larger the address space of the lookup table. Therefore, depending on the dimension D, the soft decision unit may not be able to install the lookup table.

[0011] The present disclosure is made to solve the above-mentioned problems, and its purpose is to obtain an error correction decoding device that can suppress the increase in calculation processing of the first hard decision bits and reliability associated with the increase in dimension compared with the error correction decoding device disclosed in Non-Patent Document 1.

[0012] Means for solving problems

[0013] The error correction decoding device disclosed in the present invention is an error correction decoding device that decodes each pulse amplitude modulation symbol among D pulse amplitude modulation symbols into a multi-value modulation symbol with a dimension of D and a number of bits of each dimension of M, wherein D is an integer greater than 1 and M is an integer greater than 2. The error correction decoding device comprises: a soft decision unit that obtains each pulse amplitude modulation symbol from a communication symbol sequence in which the D pulse amplitude modulation symbols are arranged, calculates a first hard decision bit indicating the positive or negative of a logarithmic posterior probability ratio of each of the M bits included in the multi-value modulation symbol based on each pulse amplitude modulation symbol, and calculates the absolute value of each logarithmic posterior probability ratio as a first reliability; and an exclusive-OR operation unit that operates an exclusive-OR of the D×M first hard decision bits calculated by the soft decision unit. In addition, the error correction decoding device has: a reliability selection unit, which compares the D×M first reliabilities calculated by the soft decision unit with each other, selects a first reliability from the D×M first reliabilities based on the comparison result, and outputs one first reliability as the second reliability; and a soft decision error correction decoding unit, which performs soft decision error correction decoding on the result of the XOR operation performed by the XOR operation unit and the second reliability.

[0014] Effects of the Invention

[0015] According to the present disclosure, compared with the error correction decoding device disclosed in Non-Patent Document 1, it is possible to suppress an increase in the calculation process of each of the first hard decision bits and the reliability associated with an increase in the number of dimensions. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a diagram showing the structure of the error correction decoding device according to the first embodiment.

[0017] Figure 2 This is a hardware configuration diagram showing the hardware of the error correction decoding device according to the first embodiment.

[0018] Figure 3 This is a hardware configuration diagram of a computer when the error correction decoding device is implemented by software, firmware, etc.

[0019] Figure 4 This is a flowchart showing an error correction decoding method as a processing procedure of an error correction decoding apparatus.

[0020] Figure 5 This is a structural diagram of another error correction decoding device according to embodiment 1.

[0021] Figure 6 This is a hardware configuration diagram showing the hardware of another error correction decoding device according to the first embodiment.

[0022] Figure 7 This is a structural diagram of yet another error correction decoding device according to embodiment 1. DETAILED DESCRIPTION

[0023] Hereinafter, in order to explain the present disclosure in more detail, a mode for implementing the present disclosure will be described with reference to the drawings.

[0024] Implementation Method 1

[0025] Figure 1 This is a diagram showing the structure of the error correction decoding device according to the first embodiment.

[0026] Figure 2 This is a hardware configuration diagram showing the hardware of the error correction decoding device according to the first embodiment.

[0027] Figure 1 The error correction decoding device shown is installed in, for example, a receiving device not shown in the figure. Figure 1 The error correction decoding device shown has a soft decision unit 1, an exclusive OR operation unit 2, a reliability selection unit 3, a soft decision error correction decoding unit 4, a pre-correction unit 5, a hard decision error correction decoding unit 6 and a probability shaping decoding unit 7.

[0028] The error correction decoding apparatus decodes each of D (D is an integer greater than or equal to 1) pulse amplitude modulation symbols into a multi-value modulation symbol having D dimensions and M (M is an integer greater than or equal to 2) bits per dimension.

[0029] The receiving device (not shown) has Figure 1 The error correction decoding device shown can correct bit errors generated in the communication path with the transmission device not shown.

[0030] The soft decision unit 1 is composed of, for example, Figure 2 The soft decision circuit 11 shown is implemented.

[0031] The soft decision unit 1 is based on the arrangement of D pulse amplitude modulation symbols Y1, Y2, ..., Y D Get each pulse amplitude modulation symbol Y from the communication symbol sequence j (j=1, ..., D). Pulse amplitude modulation symbol Y j is a one-dimensional pulse amplitude modulation symbol.

[0032] The soft decision unit 1 modulates the pulse amplitude symbol Y according to j Calculate the first hard decision bit H k , the first hard decision bit H kIndicates the positive or negative of the logarithmic posterior probability ratio of each of the M bits included in the multi-value modulation symbol. The soft decision unit 1 performs the following processing in D dimensions: j , calculate the M first hard decision bits H k Therefore, in H representing the first hard decision bit collected for D dimensions k In this example, k=1, 2,…, D×M.

[0033] The soft decision unit 1 calculates the absolute value of each logarithmic posterior probability ratio as the first reliability |L k |.

[0034] The soft decision unit 1 converts the first hard decision bit H k are output to the exclusive OR operation unit 2 and the pre-correction unit 5, respectively, and the first reliability |L k |Output to the reliability selection unit 3.

[0035] The XOR operation unit 2 is composed of, for example, Figure 2 The XOR operation circuit 12 shown is implemented.

[0036] The XOR operation unit 2 operates the D×M first hard decision bits H1 to H2 calculated by the soft decision unit 1. D×M XOR of .

[0037] The XOR operation unit 2 uses the XOR operation result as the second hard decision bit H d The signals are output to the soft decision error correction decoding unit 4 and the pre-correction unit 5 respectively.

[0038] The reliability selection unit 3 is composed of, for example, Figure 2 The reliability selection circuit 13 shown is implemented.

[0039] The reliability selection unit 3 selects the D×M first reliability levels |L1| to |L D×M | compare with each other, based on the comparison results, from D×M first reliability |L1| to |L D×M |Select a first reliability.

[0040] For example, the reliability selection unit 3 selects D×M first reliability levels |L1| to |L D×M Select the smallest first reliability |L k |.

[0041] The reliability selection unit 3 selects the first reliability |L k |As the second reliability|L d |Output to the soft decision error correction decoding unit 4.

[0042] Furthermore, the reliability selection unit 3 selects the first reliability |L kThe index k of | is output to the pre-correction unit 5 as a correction candidate index k′.

[0043] The soft decision error correction decoding unit 4 is composed of, for example, Figure 2 The soft decision error correction decoding circuit 14 shown is implemented.

[0044] The soft decision error correction decoding unit 4 obtains the second hard decision bit H from the exclusive OR operation unit 2. d , obtain the second reliability |L from the reliability selection unit 3 d |.

[0045] The soft decision error correction decoding unit 4 decodes the second hard decision bit H d and the second reliability |L d |Perform soft decision error correction decoding to generate the third hard decision bit H.

[0046] The soft-decision error correction decoding unit 4 outputs the third hard-decision bit H to the pre-correction unit 5 .

[0047] The pre-correction unit 5 is configured to Figure 2 This is achieved by the pre-correction circuit 15 shown.

[0048] The pre-correction unit 5 obtains the second hard decision bit H from the exclusive OR operation unit 2. d , obtain the third hard decision bit H from the soft decision error correction decoding unit 4.

[0049] Furthermore, the pre-correction unit 5 obtains the correction candidate index k′ from the reliability selection unit 3 .

[0050] If the second hard decision bit H d and the third hard decision bit H, the pre-correction unit 5 converts the D×M first hard decision bits H1 to H D×M As the 4th hard decision bit B cap k (k=1, 2, ..., D×M) is output to the hard decision error correction decoding unit 6. In the text of the specification, due to the electronic application, the symbol "^" cannot be added to the character "B". Therefore, it is marked as "B cap".

[0051] If the second hard decision bit H d Different from the third hard decision bit H, the pre-correction unit 5 uses D×M first hard decision bits H1 to H D×M In the example, the first hard decision bit H corresponding to the correction candidate index k' is k (k=k') is inverted. The first hard decision bit H corresponding to the corrected candidate index k' k (k=k') is the same as the second reliability |L d |The corresponding first hard decision bit H k .

[0052] The pre-correction unit 5 converts the inverted first hard decision bit H k’ As the 4th hard decision bit B cap k The pre-correction unit 5 outputs the D×M first hard decision bits H1 to H D×M The first hard decision bit H that is not inverted k Directly used as the 4th hard decision bit B cap k Output to the hard decision error correction decoding unit 6.

[0053] The hard decision error correction decoding unit 6 is composed of, for example, Figure 2 The hard decision error correction decoding circuit 16 is shown to be implemented.

[0054] The hard decision error correction decoding unit 6 decodes the D×M fourth hard decision bits B cap 1 to B cap outputted from the pre-correction unit 5. D×M Hard decision error correction decoding is performed to generate a second restored bit string as a bit string.

[0055] The probability shaping decoding unit 7 is composed of, for example, Figure 2 The probability shaping decoding circuit 17 shown is implemented.

[0056] The probability shaping decoding unit 7 obtains a first restored bit string by performing probability shaping decoding on the second restored bit string generated by the hard decision error correction decoding unit 6 .

[0057] Specifically, in the transmitting device, when the second bit sequence constituting the multi-value modulation symbol is a bit sequence obtained by probabilistically shaping the first bit sequence, the probabilistic shaping decoding unit 7 probabilistically shapes the second restored bit sequence to obtain the first restored bit sequence.

[0058] The probability shaping decoding unit 7 outputs the first restored bit sequence to, for example, a processing unit of a receiving device (not shown).

[0059] exist Figure 1 In the embodiment, it is assumed that the soft decision unit 1, the XOR operation unit 2, the reliability selection unit 3, the soft decision error correction decoding unit 4, the pre-correction unit 5, the hard decision error correction decoding unit 6 and the probability shaping decoding unit 7 as the constituent elements of the error correction decoding device are respectively Figure 2 That is, it is assumed that the error correction decoding device is implemented by a soft decision circuit 11, an XOR operation circuit 12, a reliability selection circuit 13, a soft decision error correction decoding circuit 14, a pre-correction circuit 15, a hard decision error correction decoding circuit 16 and a probability shaping decoding circuit 17.

[0060] The soft decision circuit 11, the XOR operation circuit 12, the reliability selection circuit 13, the soft decision error correction decoding circuit 14, the pre-correction circuit 15, the hard decision error correction decoding circuit 16 and the probability shaping decoding circuit 17 are respectively equivalent to, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array) or a circuit composed of a combination thereof.

[0061] The constituent elements of the error correction decoding device are not limited to being implemented by dedicated hardware, and the error correction decoding device may also be implemented by software, firmware, or a combination of software and firmware.

[0062] Software or firmware is stored as a program in the computer's memory. A computer refers to hardware that executes programs, such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a central processing unit, a processing unit, an arithmetic unit, a microprocessor, a microcomputer, a processor, or a DSP (Digital Signal Processor).

[0063] Figure 3 This is a hardware configuration diagram of a computer when the error correction decoding device is implemented by software, firmware, etc.

[0064] When the error correction decoding device is implemented by software or firmware, a program for causing a computer to execute the processing of the soft decision unit 1, the XOR operation unit 2, the reliability selection unit 3, the soft decision error correction decoding unit 4, the pre-correction unit 5, the hard decision error correction decoding unit 6, and the probability shaping decoding unit 7 is stored in the memory 21. Then, the processor 22 of the computer executes the program stored in the memory 21.

[0065] In addition, Figure 2 In FIG. 1 , an example is shown in which the constituent elements of the error correction decoding device are respectively implemented by dedicated hardware. Figure 3 In the example in which the error correction decoding device is implemented by software or firmware, etc., is shown. However, this is only an example, and some components of the error correction decoding device may be implemented by dedicated hardware, and the remaining components may be implemented by software or firmware, etc.

[0066] Next, explain Figure 1 The operation of the error correction decoding device shown.

[0067] Figure 4This is a flowchart showing an error correction decoding method as a processing procedure of an error correction decoding apparatus.

[0068] The soft decision unit 1 is based on the arrangement of D pulse amplitude modulation symbols Y1, Y2, ..., Y D Get each pulse amplitude modulation symbol Y from the communication symbol sequence j (j=1,…,D).

[0069] The soft decision unit 1 is as shown in the following equation (1), based on the one-dimensional pulse amplitude modulation symbol Y j , calculate the logarithmic posterior probability ratio L of each of the D×M bits contained in the multi-value modulation symbol c k i = 1, ..., M, M is an integer greater than 2. k = D(i-1) + j. Logarithmic posterior probability ratio L c k The computational process of is fixed and has nothing to do with the dimension D.

[0070]

[0071] In formula (1), Y is the pulse amplitude modulation symbol Y j y is a probability variable. y is D pulse amplitude modulation symbols Y1, Y2, ..., Y D Any one of the set Y. X is a Figure 1 The probability variable of the multi-value modulation symbol output by the error correction decoding device shown. X (x) is the probability that X=x. x is any one of the set X of multi-value modulation symbols.

[0072] i is used to identify 2 M When the multi-value modulation symbol is, for example, 8PAM (Pulse Amplitude Modulation), M=3.

[0073] q X，Y (x, y) is a decoding metric when X=x and Y=y. In a one-dimensional additive white Gaussian noise communication path, it is expressed as in equation (2). σ is the standard deviation of the noise.

[0074] "x∈X: bi=0" indicates the object of the summation. Specifically, when taking the summation about x, only the bit b indicated by the bit index i is added. i The object of the condition that is 0 is used as the object of the sum.

[0075] If there is a 2^N address space and a one-dimensional pulse amplitude modulation symbol Y is storedj The logarithmic posterior probability ratio L c k The soft decision unit 1 can obtain the pulse amplitude modulation symbol Y from the lookup table without performing the operation of formula (1). j The logarithmic posterior probability ratio L c k N is the one-dimensional pulse amplitude modulation symbol Y that is quantized after being affected by noise or distortion in the communication path. j The number of bits.

[0076] For example, when N=6, y is represented by 64 values. In this case, the address space of the LUT is 64.

[0077] In the error correction decoding device disclosed in non-patent document 1, when N=6, if D=2, y is represented by 4096 values. In this case, the address space of the LUT is 4096. In addition, when N=6, if D=4, y is represented by 16,777,216 values. In this case, the address space of the LUT is 16,777,216.

[0078] As can be seen from the difference in the address space of the LUT, the amount of calculation of equation (1) by the soft decision unit 1 is extremely small compared to the amount of calculation of the log-posteriori probability ratio by the soft decision unit of the error correction decoding device disclosed in Non-Patent Document 1.

[0079] Next, the soft decision unit 1 calculates the first hard decision bit H k , the first hard decision bit H k Indicates the bit b contained in the multi-value modulation symbol i The logarithmic posterior probability ratio L c k The positive and negative ( Figure 4 Step ST1).

[0080] The soft decision unit 1 is, for example, based on the logarithmic posterior probability ratio L c k If it is positive, the first hard decision bit H k Set to 0, the logarithmic posterior probability ratio L c k If it is negative, the first hard decision bit H k Set to 1.

[0081] The soft decision unit 1 converts the first hard decision bit H k The signals are output to the exclusive-OR operation unit 2 and the pre-correction unit 5 respectively.

[0082] The soft decision unit 1 calculates the absolute value of each logarithmic posterior probability ratio as the first reliability |L k |( Figure 4Step ST1).

[0083] Specifically, the soft decision unit 1 calculates the logarithmic posterior probability ratio L c k The absolute value of the first reliability |L k |.

[0084] The soft decision unit 1 determines the first reliability |L k |Output to the reliability selection unit 3.

[0085] XOR operation unit 2 obtains D×M first hard decision bits H1 to H2 from soft decision unit 1. D×M .

[0086] The exclusive OR operation unit 2 calculates D×M first hard decision bits H1 to H D×M XOR of ( Figure 4 Step ST2).

[0087] The XOR operation unit 2 uses the XOR operation result as the second hard decision bit H d The signals are output to the soft decision error correction decoding unit 4 and the pre-correction unit 5 respectively.

[0088] exist Figure 1 In the error correction decoding device shown in FIG. 1 , the XOR operation unit 2 calculates the second hard decision bit H d , and the second hard decision bit H d The second hard decision bit H can be output to the pre-correction unit 5. However, this is just an example, and the pre-correction unit 5 can also calculate the second hard decision bit H d .

[0089]

[0090] In formula (3), "mod 2" is a mathematical symbol representing a remainder.

[0091] The reliability selection unit 3 obtains D×M first reliability |L1| to |L1| from the soft decision unit 1. D×M |, and the first reliability |L1|~|L D×M |Compare with each other.

[0092] The reliability selection unit 3 selects D×M first reliability levels |L1| to |L D×M |Select a first reliability ( Figure 4 Step ST3).

[0093] For example, the reliability selection unit 3 selects D×M first reliability levels |L1| to |L D×M Select the smallest first reliability |L k |.

[0094] The reliability selection unit 3 selects the first reliability |L k |As the second reliability|L d |Output to the soft decision error correction decoding unit 4.

[0095] Here, the reliability selection unit 3 selects D×M first reliability levels |L1| to |L D×M Select the smallest first reliability |L k | is an example. However, this is just an example, and the reliability selection unit 3 may select D×M first reliability levels |L1| to |L D×M For example, select the second smallest first reliability |L k |.

[0096] The reliability selection unit 3 converts the selected first reliability |L k The index k of | is determined as the corrected candidate index k'.

[0097] The reliability selection unit 3 outputs the correction candidate index k′ to the pre-correction unit 5 .

[0098]

[0099] In formula (4), “arg min” represents the value assigned to |L k |The mathematical symbol for the minimum value of k.

[0100] The soft decision error correction decoding unit 4 obtains the second hard decision bit H from the exclusive OR operation unit 2. d , obtain the second reliability |L from the reliability selection unit 3 d |.

[0101] The soft decision error correction decoding unit 4 decodes the second hard decision bit H d and the second reliability |L d |Perform soft decision error correction decoding to generate the third hard decision bit H( Figure 4 Step ST4).

[0102] Specifically, the soft decision error correction decoding unit 4 decodes the second hard decision bit H d and the second reliability |L d The plurality of second log-posteriori probability ratios formed by the combination of | are collectively subjected to soft decision error correction decoding to generate a third hard decision bit H. The soft decision error correction decoding process itself is a well-known technique, and thus a detailed description thereof is omitted.

[0103] The soft-decision error correction decoding unit 4 outputs the third hard-decision bit H to the pre-correction unit 5 .

[0104] As the soft decision error correction code, for example, a low density parity check code or a turbo code is used. The code length of the soft decision error correction code is about several hundred bits to several tens of thousands of bits. As the resolution of each of the second logarithmic posterior probability ratios, for example, 8 values, 16 values, or 32 values ​​are assumed.

[0105] The pre-correction unit 5 obtains the second hard decision bit H from the exclusive OR operation unit 2. d , obtain the third hard decision bit H from the soft decision error correction decoding unit 4.

[0106] In addition, the pre-correction unit 5 obtains D×M first hard decision bits H1 to H2 from the soft decision unit 1. D×M , obtain the correction candidate index k' from the reliability selection unit 3.

[0107] The pre-correction unit 5 converts the second hard decision bit H d Compare with the third hard decision bit H.

[0108] If the second hard decision bit H d is the same as the third hard decision bit H, the pre-correction unit 5 changes the first hard decision bit H k (k=1, 2, ..., D×M) as the fourth hard decision bit B hat k The pre-correction unit 5 outputs the first hard decision bit H to the hard decision error correction decoding unit 6. k The first hard decision bit H is directly output to the hard decision error correction decoding unit 6 without causing any first hard decision bit H to be k Reversal.

[0109] If the second hard decision bit H d Different from the third hard decision bit H, the pre-correction unit 5 uses D×M first hard decision bits H k ~H D×M In the example, the first hard decision bit H corresponding to the correction candidate index k' is k Reverse Figure 4 Step ST5).

[0110] The pre-correction unit 5 converts the inverted first hard decision bit H k As the 4th hard decision bit B cap k (k=k′) is output to the hard decision error correction decoding unit 6.

[0111] In addition, the pre-correction unit 5 converts D×M first hard decision bits H1 to H D×M The first hard decision bit H in the uninverted k Directly used as the 4th hard decision bit B cap k Output to the hard decision error correction decoding unit 6.

[0112] The processing of the pre-correction unit 5 is expressed as shown in the following equations (5) to (6).

[0113]

[0114] The hard decision error correction decoding unit 6 obtains D×M fourth hard decision bits Bhat1 to Bhat from the pre-correction unit 5 D× M.

[0115] The hard decision error correction decoding unit 6 decodes D×M fourth hard decision bits Bhat 1 to Bhat D×M Perform hard decision error correction decoding to generate the second restored bit string ( Figure 4 Step ST6). The hard decision error correction decoding process itself is a well-known technique, so a detailed description thereof is omitted.

[0116] The hard decision error correction decoding unit 6 outputs the second restored bit string to the probability shaping decoding unit 7 .

[0117] As a hard decision error correction code, for example, a BCH code, a Staircase code, or a Zipper code can be used. The BCH code is disclosed, for example, in "R. Bose and D. Ray-Chaudhuri, "On a class of error correcting binary group codes," Information and Control, vol. 3, no. 1, pp. 68-79, March 1960". The Staircase code is disclosed, for example, in "BP Smith et al., "Staircase codes: FEC for 100 Gb / s OTN," J. Lightw. Technol., vol. 30, no. 1, pp. 110-117, Jan. 2012, doi: 10.1109 / JLT.2011.2175479". Zipper codes are disclosed, for example, in “AYSukmadji et al., “Zipper codes: Spatially-coupled product-like codes with iterative algebraic decoding,” Canadian Workshop on Information Theory (CWIT), Hamilton, ON, Canada, June 2019, pp. 1-6, doi: 10.1109 / CWIT.2019.8929906”.

[0118] The code length of the hard decision error correction code is, for example, several hundred bits to several hundred thousand bits.

[0119] By rearranging the bit positions before the hard decision error correction decoding unit 6 performs hard decision error correction decoding, the influence of continuous bit errors can be reduced.

[0120] The probability shaping decoding unit 7 obtains the second restored bit string from the hard decision error correction decoding unit 6 .

[0121] The probability shaping decoding unit 7 performs probability shaping decoding on the second restored bit string generated by the hard decision error correction decoding unit 6 to obtain the first restored bit string ( Figure 4 Step ST7).

[0122] The probability shaping decoding unit 7 outputs the first restored bit sequence to, for example, a processing unit of a receiving device (not shown).

[0123] In order to transmit, there are D pulse amplitude modulation symbols Y1, Y2, ..., Y D In a transmitting device for a communication symbol sequence, the probability of occurrence of a plurality of signal points is biased, and in a case where the second bit string constituting the multi-value modulation symbol is a bit string obtained by probabilistically shaping the first bit string, the probabilistic shaping decoding unit 7 performs probabilistic shaping decoding on the second restored bit string. Therefore, in the transmitting device, if the second bit string is not a bit string obtained by probabilistically shaping the first bit string, the probabilistic shaping decoding unit 7 does not perform probabilistic shaping decoding on the second restored bit string.

[0124] In the transmitting device, for example, when probability shaping coding is performed in a manner such that the probability distribution PX(x) of the multi-value modulation symbol is close to a discretized Gaussian distribution, the signal-to-noise ratio required to obtain the specified communication quality is reduced. Such a probability shaping coding process is disclosed in, for example, patent document (International Publication No. 2020 / 031257).

[0125] In the above-mentioned first embodiment, an error correction decoding device is constructed for decoding each of D (D is an integer greater than or equal to 1) pulse amplitude modulation symbols into a multi-value modulation symbol having a dimension of D and a bit number of M (M is an integer greater than or equal to 2) in each dimension. The error correction decoding device comprises: a soft decision unit 1, which obtains each pulse amplitude modulation symbol from a communication symbol sequence in which the D pulse amplitude modulation symbols are arranged, calculates a first hard decision bit indicating the positive or negative of a logarithmic posterior probability ratio of each of the M bits included in the multi-value modulation symbol based on each pulse amplitude modulation symbol, and calculates the absolute value of each logarithmic posterior probability ratio as a first reliability; and an exclusive-OR operation unit 2, which operates an exclusive-OR of the D×M first hard decision bits calculated by the soft decision unit 1. In addition, the error correction decoding device includes: a reliability selection unit 3 that compares the D×M first reliabilities calculated by the soft decision unit 1, selects one first reliability from the D×M first reliabilities based on the comparison result, and outputs the one first reliability as the second reliability; and a soft decision error correction decoding unit 4 that performs soft decision error correction decoding on the result of the XOR operation performed by the XOR operation unit 2 and the second reliability. Therefore, the error correction decoding device can suppress the increase in calculation processing of the first hard decision bit and the reliability associated with the increase in the dimension, compared with the error correction decoding device disclosed in non-patent document 1.

[0126] exist Figure 1 In the error correction decoding device shown, the soft decision unit 1 obtains each one-dimensional pulse amplitude modulation symbol from the communication symbol sequence in which D pulse amplitude modulation symbols are arranged. However, the number of bits representing the one-dimensional pulse amplitude modulation symbol is sometimes switched. In addition, the dimension of the pulse amplitude modulation symbol obtained by the soft decision unit 1 is sometimes switched.

[0127] When such switching is performed, the processing of each of the XOR operation unit 2, the reliability selection unit 3, the soft decision error correction decoding unit 4, the pre-correction unit 5, and the hard decision error correction decoding unit 6 is affected. However, the influence on each processing can be dealt with by, for example, switching the bit index i processed in equation (1) and the variable j for identifying the pulse amplitude modulation symbol.

[0128] In the soft decision unit 1, when there is a first hard decision bit H k The computationally irrelevant bit b i When Figure 5 As shown, the soft decision unit 1 will make the decision about the bit b i The logarithmic posterior probability ratio L c k The first reliability L' is output to the soft decision error correction decoding unit 8. Figure 5 FIG. 1 is a structural diagram of another error correction decoding device showing embodiment 1. Figure 5 In, with Figure 1The same reference numerals denote the same or corresponding parts, and thus description thereof will be omitted.

[0129] The soft decision error correction decoding unit 8 obtains the second hard decision bit H from the exclusive OR operation unit 2. d , obtain the second reliability |L from the reliability selection unit 3 d |.

[0130] The soft decision error correction decoding unit 4 decodes the second hard decision bit H d , Second reliability |L d | and the first reliability L' perform soft decision error correction decoding to generate the third hard decision bit H.

[0131] For example, Figure 6 As shown, the soft decision error correction decoding unit 8 is implemented by a soft decision error correction decoding circuit 18 .

[0132] Figure 6 FIG. 2 is a hardware configuration diagram showing the hardware of another error correction decoding device according to Embodiment 1. Figure 6 In, with Figure 2 The same reference numerals denote the same or corresponding parts, and thus description thereof will be omitted.

[0133] exist Figure 1 In the error correction decoding device shown in the figure, the hard decision error correction decoding unit 6 processes the D×M fourth hard decision bits B cap 1 to B cap outputted from the pre-correction unit 5. D×M The hard decision error correction decoding is performed to generate the second restored bit string. However, this is only an example, and the hard decision error correction decoding unit 6 may exclude the fourth hard decision bit B cap 1 to B cap outputted from the pre-correction unit 5 from the hard decision error correction decoding target. D×M part of.

[0134] In this case, if Figure 7 As shown, the hard decision error correction decoding unit 6 obtains the third hard decision bit H corresponding to the fourth hard decision bit to be excluded from the soft decision error correction decoding unit 4 instead of the fourth hard decision bit to be excluded. Figure 7 FIG. 1 is a structural diagram of another error correction decoding device according to Embodiment 1. Figure 7 In, with Figure 1 The same reference numerals designate the same or corresponding parts.

[0135] Furthermore, the hard decision error correction decoding unit 6 decodes the fourth hard decision bits B cap 1 to B cap D×M In the above, hard decision error correction decoding is performed on the fourth hard decision bit other than the fourth hard decision bit to be excluded and the third hard decision bit H corresponding to the fourth hard decision bit to be excluded, thereby generating a second restored bit string.

[0136] Furthermore, the present disclosure can modify any constituent elements of the embodiments or omit any constituent elements of the embodiments.

[0137] Industrial Applicability

[0138] The present disclosure is applicable to an error correction decoding device and an error correction decoding method.

[0139] Description of symbols

[0140] 1: soft decision unit; 2: XOR operation unit; 3: reliability selection unit; 4: soft decision error correction decoding unit; 5: pre-correction unit; 6: hard decision error correction decoding unit; 7: probability shaping decoding unit; 8: soft decision error correction decoding unit; 11: soft decision circuit; 12: XOR operation circuit; 13: reliability selection circuit; 14: soft decision error correction decoding circuit; 15: pre-correction circuit; 16: hard decision error correction decoding circuit; 17: probability shaping decoding circuit; 18: soft decision error correction decoding circuit; 21: memory; 22: processor.

Claims

1. An error correction decoding device, which decodes each pulse amplitude modulation symbol of D pulse amplitude modulation symbols into a multi-value modulation symbol with a dimension of D and a bit number of M in each dimension, wherein: D is an integer greater than 1, and M is an integer greater than 2, wherein the error correction decoding device has: a soft decision unit, which obtains each pulse amplitude modulation symbol from a communication symbol sequence in which the D pulse amplitude modulation symbols are arranged, calculates a first hard decision bit indicating the positive or negative of a logarithmic posterior probability ratio of each of the M bits included in the multi-value modulation symbol according to each pulse amplitude modulation symbol, and calculates the absolute value of each logarithmic posterior probability ratio as a first reliability; an XOR operation unit, which operates an XOR of the D×M first hard decision bits calculated by the soft decision unit; a reliability selection unit that compares the D×M first reliabilities calculated by the soft decision unit, selects one first reliability from the D×M first reliabilities based on a result of the comparison, and outputs the one first reliability as a second reliability; and A soft decision error correction decoding unit performs soft decision error correction decoding on a result of the exclusive OR operation performed by the exclusive OR operation unit and the second reliability.

2. The error correction decoding device according to claim 1, characterized in that: The reliability selection unit selects the smallest first reliability among the D×M first reliabilities based on the comparison result, and outputs the smallest first reliability as the second reliability.

3. The error correction decoding device according to claim 2, characterized in that: The error correction decoding device comprises a pre-correction unit. If the second hard decision bit indicating the result of the XOR operation performed by the XOR operation unit is the same as the third hard decision bit generated by the soft decision error correction decoding unit, the pre-correction unit outputs the D×M first hard decision bits calculated by the soft decision unit as fourth hard decision bits, If the second hard decision bit is different from the third hard decision bit, the pre-correction unit inverts the first hard decision bit corresponding to the second reliability among the D×M first hard decision bits, outputs the inverted first hard decision bit as the fourth hard decision bit, and outputs the first hard decision bits other than the first hard decision bit corresponding to the second reliability among the D×M first hard decision bits as the fourth hard decision bits.

4. The error correction decoding device according to claim 3, characterized in that: The error correction decoding device includes a hard decision error correction decoding unit that generates a bit sequence by performing hard decision error correction decoding on the D×M fourth hard decision bits output from the pre-correction unit.

5. The error correction decoding device according to claim 4, characterized in that: The error correction decoding device includes a probability shaping decoding unit that performs probability shaping decoding on the bit sequence generated by the hard decision error correction decoding unit.

6. An error correction decoding method, decoding each pulse amplitude modulation symbol in D pulse amplitude modulation symbols to obtain a multi-value modulation symbol with a dimension of D and a bit number of M in each dimension, wherein: D is an integer greater than 1, M is an integer greater than 2, and the error correction decoding method is characterized in that: The soft decision unit obtains each pulse amplitude modulation symbol from the communication symbol sequence in which the D pulse amplitude modulation symbols are arranged, calculates a first hard decision bit indicating the positive or negative of a logarithmic posterior probability ratio of each of the M bits included in the multi-value modulation symbol based on each pulse amplitude modulation symbol, and calculates the absolute value of each logarithmic posterior probability ratio as a first reliability. The XOR operation unit calculates the XOR of the D×M first hard decision bits calculated by the soft decision unit. The reliability selection unit compares the D×M first reliabilities calculated by the soft decision unit, selects one first reliability from the D×M first reliabilities based on the comparison result, and outputs the one first reliability as a second reliability. The soft decision error correction decoding unit performs soft decision error correction decoding on the result of the exclusive OR operation performed by the exclusive OR operation unit and the second reliability.

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