Array substrate and display device

Abstract

An array substrate is provided. The array substrate comprises a plurality of pixel driving circuits. Each of the plurality of pixel driving circuits includes a driving transistor (Td), a data write transistor, a compensation transistor, one or more reset transistors, and a storage capacitor (Cst). The array substrate further comprises a light shielding layer (LSL). An orthographic projection of the light shielding layer (LSL) on the substrate (BS) at least partially overlaps an orthographic projection of an active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, ACTd) of each of the driving transistor (Td), the data write transistor, the compensation transistor and the one or more reset transistors on the substrate (BS).

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Organic light emitting diode (OLED) display is one of the hot spots in the field of flat panel display research today. Unlike thin film transistor liquid crystal display (TFT-LCD) that uses a stable voltage to control brightness, OLED is driven by a driving current that needs to be kept constant to control illumination. The OLED display panel includes a plurality of pixel units, which are configured with a pixel driving circuit arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line of each row and a drain terminal connected to a data line of each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied to the driving transistor from the data line via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the invention

[0003] On the one hand, the present disclosure provides an array substrate, comprising a plurality of pixel driving circuits; wherein each of the plurality of pixel driving circuits comprises a driving transistor, a data writing transistor, a compensation transistor, one or more reset transistors and a storage capacitor; wherein the array substrate further comprises a light-shielding layer; wherein the orthographic projection of the light-shielding layer on the base substrate at least partially overlaps with the orthographic projection of the active layer of each of the driving transistor, the data writing transistor, the compensation transistor and the one or more reset transistors on the base substrate.

[0004] Optionally, the orthographic projection of the light shielding layer on the base substrate covers the orthographic projection of the active layer of each of the driving transistor, the data writing transistor, the compensation transistor and the one or more reset transistors on the base substrate.

[0005] Optionally, the light-shielding layer includes a plurality of first light-shielding lines; wherein the orthographic projection of each of the plurality of first light-shielding lines on the base substrate covers the orthographic projection of the active layer of the one or more reset transistors on the base substrate.

[0006] Optionally, the orthographic projection of the first shading line corresponding to the current row of the multiple first shading lines on the substrate covers the orthographic projection of the active layer of the first reset transistor in the pixel driving circuit of the current row and the active layer of the second reset transistor in the pixel driving circuit of the previous adjacent row on the substrate; and the orthographic projection of the first shading line corresponding to the next adjacent row of the multiple first shading lines on the substrate covers the orthographic projection of the active layer of the second reset transistor in the pixel driving circuit of the current row and the active layer of the first reset transistor in the pixel driving circuit of the next adjacent row on the substrate.

[0007] Optionally, the array substrate further includes a plurality of reset control signal lines; wherein the orthographic projections of the respective first shading light lines on the base substrate at least partially overlap with the orthographic projections of corresponding reset control signal lines among the plurality of reset control signal lines on the base substrate.

[0008] Optionally, the shading layer further includes a plurality of second shading lines; wherein the orthographic projection of each of the plurality of second shading lines on the base substrate covers the orthographic projection of the active layer of the data writing transistor and the active layer of the compensation transistor on the base substrate.

[0009] Optionally, the array substrate further comprises a plurality of gate lines; wherein an orthographic projection of each second light-shielding line on the base substrate at least partially overlaps with an orthographic projection of a corresponding gate line among the plurality of gate lines on the base substrate.

[0010] Optionally, the shading layer includes multiple first shading lines and multiple second shading lines; wherein, the second shading lines corresponding to the current row of the multiple second shading lines and the first shading lines corresponding to the next adjacent row of the multiple first shading lines are connected to each other in the peripheral area to form a ring structure.

[0011] Optionally, the light-shielding layer includes a plurality of first light-shielding lines and a plurality of second light-shielding lines; wherein the plurality of first light-shielding lines and the plurality of second light-shielding lines are connected to a gate scanning circuit, which is located in the peripheral area and is configured to provide a gate scanning signal.

[0012] Optionally, the light shielding layer includes a plurality of islands; wherein an orthographic projection of each of the plurality of islands on the base substrate at least partially overlaps with an orthographic projection of a first capacitor electrode of the storage capacitor on the base substrate.

[0013] Optionally, the array substrate also includes a plurality of voltage supply lines; wherein the light shielding layer also includes a plurality of extension portions; wherein the plurality of islands are separated from each other; wherein each of the plurality of extension portions extends away from a corresponding island among the plurality of islands; and wherein each of the extension portions is connected to a corresponding voltage supply line among the plurality of voltage supply lines.

[0014] Optionally, the light-shielding layer further includes a plurality of bridges; wherein adjacent islands among the plurality of islands are connected by corresponding bridges among the plurality of bridges.

[0015] Optionally, the array substrate further includes a plurality of voltage supply lines; wherein the light shielding layer further includes an extension portion extending away from one of the plurality of islands; wherein the extension portion is connected to one of the plurality of voltage supply lines.

[0016] Optionally, the array substrate includes a display area and a peripheral area; wherein the shading layer includes a plurality of third shading light lines located in the display area, a peripheral shading signal line located in the peripheral area, and a plurality of peripheral connecting lines located in the peripheral area; each of the plurality of third shading light lines includes a portion of the plurality of islands and a portion of the plurality of bridges; and each of the plurality of peripheral connecting lines connects the corresponding third shading light line with the peripheral shading signal line.

[0017] Optionally, the shading layer is an overall structure of an interconnected shading network extending over a plurality of sub-pixels; wherein the overall structure comprises a plurality of first islands, a plurality of second islands, a plurality of first bridges, a plurality of second bridges, a plurality of third bridges and a plurality of branches.

[0018] Optionally, the interconnected shading network includes multiple rows of islands; wherein each row of islands in the multiple rows of islands includes multiple first islands among the multiple first islands arranged along a direction substantially parallel to the first direction and multiple second islands among the multiple second islands arranged along a direction substantially parallel to the first direction; each first bridge among the multiple first bridges connects the first island among the multiple first islands in two adjacent rows and the second island among the multiple second islands; each second bridge among the multiple second bridges connects the first island among the multiple first islands in the same row and the second island among the multiple second islands; each third bridge among the multiple third bridges connects two adjacent first islands among the multiple first islands in the same row; and each branch among the multiple branches extends away from the corresponding first island among the multiple first islands.

[0019] Optionally, the orthographic projection of the corresponding first island on the substrate covers the orthographic projection of the active layer of the driving transistor on the substrate; the orthographic projection of each second island among the multiple second islands on the substrate covers the orthographic projection of the active layer of the compensation transistor on the substrate; the orthographic projection of each branch on the substrate covers the orthographic projection of the active layer of the data writing transistor on the substrate; and the orthographic projection of each first bridge on the substrate covers the orthographic projection of the active layer of the first reset transistor and the active layer of the second reset transistor on the substrate.

[0020] Optionally, the array substrate includes a display area and a peripheral area; wherein, in the peripheral area, the shading layer also includes a peripheral shading signal line and a plurality of peripheral connecting lines connecting the overall structure located in the display area with the peripheral shading signal line located in the peripheral area; wherein the interconnected shading network includes a plurality of rows of islands; each row of islands in the plurality of rows of islands includes a plurality of first islands among the plurality of first islands arranged along a direction substantially parallel to a first direction and a plurality of second islands among the plurality of second islands arranged along a direction substantially parallel to the first direction; and each of the plurality of peripheral connecting lines connects a corresponding row in the plurality of rows of islands with the peripheral shading signal line.

[0021] Optionally, the array substrate includes K reset signal lines, and the K reset signal lines are respectively configured to provide reset signals to reset transistors in K columns of pixel driving circuits of the array substrate; wherein the K reset signal lines include: a plurality of third reset signal lines, which are located in the (2k-1)th column in the K columns, K and k are positive integers, 1≤k≤(K / 2); and a plurality of fourth reset signal lines, which are located in the (2k)th column in the K columns; wherein each third reset signal line and each fourth reset signal line have different line patterns.

[0022] On the other hand, the present disclosure provides an array substrate, comprising a plurality of pixel driving circuits; wherein each of the plurality of pixel driving circuits comprises a driving transistor, a data writing transistor, a compensation transistor, one or more reset transistors and a storage capacitor; wherein the array substrate further comprises a light-shielding layer; wherein an orthographic projection of a first portion of the light-shielding layer on a substrate substrate at least partially overlaps with an orthographic projection of an active layer of the driving transistor on the substrate substrate; an orthographic projection of a second portion of the light-shielding layer on the substrate substrate at least partially overlaps with an orthographic projection of an active layer of the data writing transistor, the compensation transistor and at least one of the one or more reset transistors on the substrate substrate; and the first portion and the second portion are configured to be provided with different signals.

[0023] Optionally, the first part is configured to be provided with a constant voltage signal, and the second part is configured to be provided with a pulse signal.

[0024] Optionally, the first portion is configured to be provided with a voltage supply signal, and the second portion is configured to be provided with a gate scan signal.

[0025] Optionally, the first portion includes a plurality of third shading light lines; the second portion includes a plurality of first shading light lines and a plurality of second shading light lines; the plurality of first shading light lines and the plurality of second shading light lines are connected to a gate scanning circuit configured to provide a gate scanning signal; and the plurality of third shading light lines are connected to a signal line configured to provide a voltage supply signal.

[0026] Optionally, the array substrate also includes a plurality of voltage supply lines located in the display area of ​​the array substrate; wherein one voltage supply line among the plurality of voltage supply lines is connected to an extension of a corresponding third shading line among the plurality of third shading lines through a via; and the plurality of third shading lines are connected to the same voltage supply line among the plurality of voltage supply lines.

[0027] Optionally, the shading layer also includes a peripheral shading signal line located in a peripheral area of ​​the array substrate, and a plurality of peripheral connecting lines connecting the plurality of third shading lines located in the display area of ​​the array substrate and the peripheral shading signal line located in the peripheral area.

[0028] Optionally, the array substrate also includes a plurality of voltage supply lines located in the display area of ​​the array substrate; wherein one of the plurality of voltage supply lines is connected to an extension of a corresponding third shading line among the plurality of third shading lines through a via; the plurality of third shading lines are connected to the same voltage supply line among the plurality of voltage supply lines; and the shading layer also includes a peripheral shading signal line located in the peripheral area of ​​the array substrate, and a plurality of peripheral connecting lines connecting the plurality of third shading lines located in the display area of ​​the array substrate and the peripheral shading signal lines located in the peripheral area.

[0029] Optionally, the first part includes a plurality of islands separated from each other, and a plurality of extensions; the second part includes a plurality of first shading light lines and a plurality of second shading light lines; each of the plurality of extensions extends away from a corresponding island among the plurality of islands; wherein the array substrate also includes a plurality of voltage supply lines located in the display area of ​​the array substrate; and each of the plurality of voltage supply lines is connected to a corresponding extension through a via.

[0030] On the other hand, the present disclosure provides a display device, which includes the array substrate described herein, and one or more integrated circuits connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0032] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0033] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0034] Figure 2B is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0035] Figure 2C is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0036] Figure 3A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure.

[0037] Figure 3B It is shown Figure 3A Schematic diagram of the arrangement of multiple pixel driving circuits in a portion of an array substrate depicted in FIG.

[0038] Figure 3C It is shown Figure 3A Schematic diagram of the structure of a light shielding layer in a portion of an array substrate depicted in FIG.

[0039] Figure 3D It is shown Figure 3A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG.

[0040] Figure 3E It is shown Figure 3A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG.

[0041] Figure 3F It is shown Figure 3A A schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG.

[0042] Figure 3G It is shown Figure 3A A schematic diagram of the structure of an interlayer dielectric layer in a portion of an array substrate is depicted in FIG.

[0043] Figure 3H It is shown Figure 3A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG.

[0044] Figure 4A is along Figure 3A Cross-sectional view along line A-A'.

[0045] Figure 4B is along Figure 3A Cross-sectional view along line BB'.

[0046] Figure 4C is along Figure 3A Cross-sectional view along line C-C'.

[0047] Figure 4D is along Figure 3A Cross-sectional view along line D-D'.

[0048] Figure 4E is along Figure 3A Cross-sectional view along line E-E'.

[0049] Figure 5 It is shown Figure 3A Schematic diagram of the structure of a light shielding layer and a semiconductor material layer in a portion of an array substrate depicted in FIG.

[0050] Figure 6 It is shown Figure 3A Schematic diagram of the structure of a light shielding layer in a portion of an array substrate depicted in FIG.

[0051] Figure 7 It is shown Figure 3A A schematic diagram of the structure of a light shielding layer and a first conductive layer in a portion of an array substrate depicted in FIG.

[0052] Figure 8 The layout of the light shielding layer, the semiconductor material layer and the first conductive layer in a part of the array substrate in some embodiments of the present disclosure is shown.

[0053] Fig. 9 Shows Figure 8 Layout of a light shielding layer in a portion of an array substrate depicted in FIG.

[0054] Fig.10 A ring structure in some embodiments according to the present disclosure is shown, which is formed by second shading lines corresponding to a current row of a plurality of second shading lines and first shading lines corresponding to a next adjacent row of a plurality of first shading lines.

[0055] Fig.11 Id-Vg curves of some array substrates are shown.

[0056] Fig.12 The Wy-Lv correspondence of some array substrates is shown.

[0057] Fig.13A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure.

[0058] Fig. 13B It is shown Fig.13A Schematic diagram of the arrangement of multiple pixel driving circuits in a portion of an array substrate depicted in FIG.

[0059] Fig. 13C It is shown Fig.13A A schematic diagram of the structure of a light shielding layer in a portion of an array substrate depicted in FIG.

[0060] Fig.13D It is shown Fig.13A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG.

[0061] Fig.13E It is shown Fig.13A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG.

[0062] Fig.13F It is shown Fig.13A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG.

[0063] Fig.14 It is shown Fig.13A Schematic diagram of the structure of a light shielding layer and a semiconductor material layer in a portion of an array substrate depicted in FIG.

[0064] Fig.15 The layout of the light shielding layer in a portion of the array substrate in some embodiments of the present disclosure is shown.

[0065] Fig.16A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure.

[0066] Fig. 16B It is shown Fig.16A A schematic diagram of the structure of a light shielding layer in a portion of an array substrate depicted in FIG.

[0067] Fig. 16C It is shown Fig.16A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG.

[0068] Fig.16D It is shown Fig.16A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG.

[0069] Fig.16E It is shown Fig.16A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG.

[0070] Fig.17A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure.

[0071] Fig. 17B It is shown Fig.17A A schematic diagram of the structure of a light shielding layer in a portion of an array substrate depicted in FIG.

[0072] Fig. 17C It is shown Fig.17A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG.

[0073] Fig.17D It is shown Fig.17A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG.

[0074] Fig.17E It is shown Fig.17A A schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG.

[0075] Fig.17F It is shown Fig.17A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG.

[0076] Fig.18A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure.

[0077] Fig.18B It is shown Fig.18A A schematic diagram of the structure of a light shielding layer in a portion of an array substrate depicted in FIG.

[0078] Fig. 18C It is shown Fig.18A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG.

[0079] Fig.18D It is shown Fig.18A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate depicted in FIG.

[0080] Fig.18E It is shown Fig.18A Schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG.

[0081] Fig.18F It is shown Fig.18AA schematic diagram of the structure of the first signal line layer in a portion of an array substrate depicted in FIG.

[0082] Fig.19A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure.

[0083] Fig.19B It is shown Fig.19A A schematic diagram of the structure of a light shielding layer in a portion of an array substrate depicted in FIG.

[0084] Fig.19C It is shown Fig.19A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG.

[0085] Fig.19D It is shown Fig.19A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG.

[0086] Fig.19E It is shown Fig.19A A schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG.

[0087] Fig.19F It is shown Fig.19A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG. DETAILED DESCRIPTION

[0088] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0089] The present disclosure particularly provides an array substrate and a display device, which substantially overcome one or more problems caused by the limitations and shortcomings of the prior art. On the one hand, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of pixel drive circuits. Optionally, each of the plurality of pixel drive circuits includes a drive transistor, a data write transistor, a compensation transistor, one or more reset transistors and a storage capacitor. Optionally, the array substrate also includes a shading layer. Optionally, the orthographic projection of the shading layer on the substrate substrate at least partially overlaps with the orthographic projection of the active layer of each of the drive transistor, the data write transistor, the compensation transistor and the one or more reset transistors on the substrate substrate.

[0090] Various suitable pixel driving circuits can be used in the array substrate described in the present disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C and 8T2C. In some embodiments, each of the plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in the present disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0091] Figure 1 is a plan view of an array substrate in some embodiments of the present disclosure. Figure 1 , the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, for example, a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of voltage supply lines Vdd. Each sub-pixel is driven by a corresponding pixel driving circuit PDC to emit light. In one example, a high voltage signal is input to a corresponding pixel driving circuit PDC connected to an anode of the light-emitting element through each of a plurality of voltage supply lines Vdd; a low voltage signal is input to a cathode of the light-emitting element. The voltage difference between the high voltage signal (e.g., VDD signal) and the low voltage signal (e.g., VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0092] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2AIn some embodiments, each pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a reset control signal line rstN corresponding to a current level (or a current row) among a plurality of reset control signal lines, a first electrode connected to a first reset signal line Vint1N corresponding to a current level (or a current row) among a plurality of first reset signal lines, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding gate line among a plurality of gate lines GL, a first electrode connected to a corresponding data line among a plurality of data lines DL, and a second electrode connected to the first electrode of the driving transistor Td; a third transistor T3 having a gate connected to a corresponding gate line, a first electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second electrode connected to the second electrode of the driving transistor Td; a fourth transistor T4 having a gate connected to a corresponding light emitting control signal line among a plurality of light emitting control signal lines em, a first electrode connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the second transistor T2; a fifth transistor T5 having a gate connected to a corresponding light emitting control signal line, a first electrode connected to the second electrodes of the driving transistor Td and the third transistor T3, and a second electrode connected to the anode of the light emitting element LE; and a sixth transistor T6 having a gate connected to a corresponding reset control signal line rst(N+1) of a next adjacent stage (or a next adjacent row) among a plurality of reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2N of a current stage (or a current row) among a plurality of second reset signal lines, and a second electrode connected to the second electrode of the fifth transistor and the anode of the light emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the fourth transistor T4.

[0093] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a second transistor T2), a compensation transistor (e.g., a third transistor T3), two light emitting control transistors (e.g., a fourth transistor T4 and a fifth transistor T5), and two reset transistors (e.g., a first transistor T1 and a sixth transistor T6).

[0094] Figure 2B is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2BIn some embodiments, the third transistor T3 is a "dual-gate" transistor and the first transistor T1 is a "dual-gate" transistor. Optionally, in the "dual-gate" first transistor, the active layer of the first transistor crosses the corresponding reset control signal line twice (alternatively, the corresponding reset control signal line crosses the active layer of the first transistor T1 twice). Similarly, in the "dual-gate" third transistor, the active layer of the third transistor T3 crosses the corresponding first gate line of the plurality of first gate lines GL1 twice (alternatively, the corresponding gate line crosses the active layer of the third transistor T3 twice). The gate of the first transistor T1 is Figure 3D and Figure 5 D is marked as "G1", where the first transistor T1 is a "double-gate" transistor. The gate of the third transistor T3 is Figure 3D and Figure 5 In D, it is marked as "G3", where the third transistor T3 is a "dual-gate" transistor.

[0095] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3 and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1 and the first electrode of the third transistor T3. The second node N2 is connected to the second electrode of the fourth transistor T4, the second electrode of the second transistor T2, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the third transistor T3, and the first electrode of the fifth transistor T5. The fourth node N4 is connected to the second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6 and the anode of the light emitting element LE.

[0096] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, and the first terminal and the second terminal are connected to the active layer of the transistor. The direction of the current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Therefore, depending on the direction of the current flowing through the transistor, in one example, the first electrode is configured to receive an input signal, and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal, and the first electrode is configured to output an output signal.

[0097] Figure 2C is a timing diagram showing the operation of the pixel driving circuit in some embodiments according to the present disclosure. Figure 2A , Figure 2B and Figure 2CDuring one frame of image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light emitting sub-stage t3. In the initial sub-stage t0, a cut-off reset control signal is provided to the gate of the first transistor T1 through the current stage reset control signal line rstN to turn off the first transistor T1. In the initial sub-stage t0, the gate line GL is provided with a cut-off signal, so the second transistor T2 and the third transistor T3 are turned off.

[0098] In the reset sub-stage t1, the on-reset control signal is provided to the gate of the first transistor T1 through the current stage reset control signal line rstN to turn on the first transistor T1; to allow the initialization voltage signal from the current stage corresponding first reset signal line Vint1N to be transmitted from the first electrode of the first transistor T1 to the second electrode of the first transistor T1, and then to the first capacitor electrode Ce1 and the gate of the driving transistor Td. The gate of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from a corresponding voltage supply line in a plurality of voltage supply lines Vdd. As the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 increases, the first capacitor electrode Ce1 is charged in the reset sub-stage t1. In the reset sub-stage t1, the corresponding gate line in the plurality of gate lines GL is provided with a cut-off signal, so the second transistor T2 and the third transistor T3 are cut off. The corresponding light emitting control signal line in the plurality of light emitting control signal lines em is provided with a high voltage signal to cut off the fourth transistor T4 and the fifth transistor T5.

[0099] In the data writing sub-phase t2, the gate of the first transistor T1 is again provided with a cut-off reset control signal through the current level reset control signal line rstN to cut off the first transistor T1. The corresponding gate line in the plurality of gate lines GL is provided with a turn-on signal, so the second transistor T2 and the third transistor T3 are turned on. The second electrode of the driving transistor Td is connected to the second electrode of the third transistor T3. The gate of the driving transistor Td is electrically connected to the first electrode of the third transistor T3. Since the third transistor T3 is turned on in the data writing sub-phase t2, the gate of the driving transistor Td and the second electrode are connected and short-circuited, and only the PN junction between the gate and the first electrode of the driving transistor Td is effective, so that the driving transistor Td is in a diode connection mode. The second transistor T2 is turned on in the data writing sub-phase t2. The data voltage signal transmitted through the corresponding data line in the plurality of data lines DL is received by the first electrode of the second transistor T2, and then transmitted to the first electrode of the driving transistor Td, and the first electrode of the driving transistor Td is connected to the second electrode of the second transistor T2. The node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate of the driving transistor Td and the first electrode is effective, in the data writing sub-phase t2, the voltage level at the node N1 gradually rises to (Vdata+Vth), where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 is reduced to a relatively small value, the storage capacitor Cst is discharged. The corresponding light emitting control signal line among the plurality of light emitting control signal lines em is provided with a high voltage signal to turn off the fourth transistor T4 and the fifth transistor T5.

[0100] In the data writing sub-phase t2, a reset control signal is provided to the gate of the sixth transistor T6 through the reset control signal line rst(N+1) corresponding to the next adjacent stage to turn on the sixth transistor T6; to allow the initialization voltage signal from the second reset signal line Vint2N corresponding to the current stage to be transferred from the first electrode of the sixth transistor T6 to the second electrode of the sixth transistor T6; and then to the node N4. The anode of the light emitting element LE is initialized.

[0101] In the light-emitting sub-stage t3, the gate of the first transistor T1 is again provided with a cut-off reset control signal through the current stage reset control signal line rstN to cut off the first transistor T1. The corresponding gate line in the plurality of gate lines GL is provided with a cut-off signal, and the second transistor T2 and the third transistor T3 are cut off. The corresponding light-emitting control signal line in the plurality of light-emitting control signal lines em is provided with a low voltage signal to turn on the fourth transistor T4 and the fifth transistor T5. In the light-emitting sub-stage t3, the voltage level at the node N1 is maintained at (Vdata+Vth), and the driving transistor Td is turned on by the voltage level and operates in the saturation region. A path is formed through the fourth transistor T4, the driving transistor Td, and the fifth transistor T5 to the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at the node N3 connected to the second electrode of the driving transistor Td is equal to the light-emitting voltage of the light-emitting element LE.

[0102] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels include respective first sub-pixels, respective second sub-pixels, and respective third sub-pixels. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a S1-S2-S3 format repeating array, wherein S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, and S3 represents the corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, and C3 represents the corresponding third sub-pixel of the third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0103] In another example, the array of multiple sub-pixels includes a repeating array of the S1-S2-S3-S4 format, wherein S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, S3 represents the corresponding third sub-pixel, and S4 represents the corresponding fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C4 represents the corresponding fourth sub-pixel of the fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C2' represents the corresponding fourth sub-pixel of the second color. In another example, the C1-C2-C3-C2′ format is an RGBG format, wherein the corresponding first subpixel is a red subpixel, the corresponding second subpixel is a green subpixel, the corresponding third subpixel is a blue subpixel, and the corresponding fourth subpixel is a green subpixel.

[0104] In some embodiments, the minimum repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0105] In an alternative embodiment, the minimum repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0106] Figure 3A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure. Figure 3B It is shown Figure 3A Schematic diagram of the arrangement of multiple pixel driving circuits in a portion of an array substrate depicted in FIG. Figure 3C It is shown Figure 3A Schematic diagram of the structure of a light shielding layer in a portion of an array substrate depicted in FIG. Figure 3D It is shown Figure 3A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG. Figure 3E It is shown Figure 3A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG. Figure 3F It is shown Figure 3A A schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG. Figure 3G It is shown Figure 3A A schematic diagram of the structure of an interlayer dielectric layer in a portion of an array substrate is depicted in FIG. Figure 3H It is shown Figure 3A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG. Figure 4A is along Figure 3A Cross-sectional view along line A-A'. 3A to 3H and Figure 4A A portion of an array substrate having two pixel driving circuits (including PDC1 and PDC2) is depicted.

[0107] Reference FIG. 3A to FIG. 3H and Figure 4A In some embodiments, the array substrate includes: a base substrate BS; a light shielding layer LSL located on the base substrate BS; a buffer layer BUF, which is located on a side of the light shielding layer LSL away from the base substrate BS; a semiconductor material layer SML, which is located on a side of the buffer layer BUF away from the base substrate BS; a gate insulating layer GI, which is located on a side of the semiconductor material layer SML away from the base substrate BS; a first conductive layer CT1, which is located on a side of the gate insulating layer GI away from the semiconductor material layer SML; an insulating layer IN, which is located on a side of the first conductive layer away from the gate insulating layer GI; a second conductive layer CT2, which is located on a side of the insulating layer IN away from the first conductive layer CT1; an interlayer dielectric layer ILD, which is located on a side of the second conductive layer CT2 away from the insulating layer IN; a first signal line layer SL1, which is located on a side of the interlayer dielectric layer ILD away from the second conductive layer CT2; and a planarization layer PLN, which is located on a side of the first signal line layer SL1 away from the interlayer dielectric layer ILD.

[0108] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3C In some embodiments, the light shielding layer LSL includes a light shielding member LS. Various suitable materials and various suitable manufacturing methods can be used to manufacture the light shielding layer LSL. For example, a metal material can be deposited on a substrate by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable metal materials for manufacturing the light shielding layer LSL include, but are not limited to, aluminum, chromium, tungsten, titanium, tantalum, molybdenum, copper, and alloys or stacks containing them.

[0109] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3D , each pixel driving circuit is marked with a number, and the number represents the area corresponding to multiple transistors (including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a driving transistor Td) in each pixel driving circuit. Each pixel driving circuit is also marked with a number representing the component of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1 and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2 and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3 and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4 and a second electrode D4. The fifth transistor T5 includes an active layer ACT5, a first electrode S5 and a second electrode D5. The sixth transistor T6 includes an active layer ACT6, a first electrode S6 and a second electrode D6. The driving transistor Td includes an active layer ACTd, a first electrode Sd and a second electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit, the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer. In another example, the active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6 and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6 and Sd) and the second electrodes (D1, D2, D3, D4, D5, D6 and Dd) of the transistors (T1, T2, T3, T4, T5, T6 and Td) are located on the same layer.

[0110] As used herein, an active layer refers to a component of a transistor including at least a portion of a semiconductor material layer, the orthographic projection of which on the substrate substrate overlaps with the orthographic projection of the gate on the substrate substrate. A first electrode refers to a component of a transistor connected to one side of the active layer, and a second electrode refers to a component of a transistor connected to the other side of the active layer. In the context of a dual-gate transistor (e.g., a third transistor T3), an active layer refers to a component of a transistor including a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first portion and the second portion, wherein the orthographic projection of the first portion of the semiconductor material layer on the substrate substrate overlaps with the orthographic projection of the first gate on the substrate substrate, and the orthographic projection of the second portion of the semiconductor material layer on the substrate substrate overlaps with the orthographic projection of the second gate on the substrate substrate. In the context of a dual-gate transistor, a first electrode refers to a component of a transistor connected to a side of the first portion away from the third portion, and a second electrode refers to a component of a transistor connected to a side of the second portion away from the third portion.

[0111] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3E In some embodiments, the first conductive layer includes a plurality of gate lines GL, a plurality of reset control signal lines (including a current-stage corresponding reset control signal line rstN and a next-stage reset control signal line rst(N+1)), a plurality of light-emitting control signal lines em, and a first capacitor electrode Ce1 of a storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, and the like. Optionally, the plurality of gate lines GL, the plurality of reset control signal lines, the plurality of light-emitting control signal lines em, and the first capacitor electrode Ce1 are located in the same layer.

[0112] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when a plurality of gate lines GL and a first capacitor electrode Ce1 are formed due to one or more steps of the same patterning process performed in the same material layer, the plurality of gate lines GL and the first capacitor electrode Ce1 are located in the same layer. In another example, by simultaneously performing the steps of forming a plurality of gate lines GL and forming the first capacitor electrode Ce1, a plurality of gate lines GL and the first capacitor electrode Ce1 can be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in the cross-sectional view is the same.

[0113] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3F In some embodiments, the second conductive layer includes a plurality of first reset signal lines (including a first reset signal line Vint1N corresponding to the current level and a first reset signal line Vint1(N+1) corresponding to the next adjacent level), a plurality of second reset signal lines (including a second reset signal line Vint2N corresponding to the current level and a second reset signal line Vint2(N-1) corresponding to the previous adjacent level), an anti-interference block IPB, and a second capacitor electrode Ce2 of the storage capacitor Cst. The anti-interference block IPB can effectively reduce crosstalk, especially the vertical crosstalk between the N1 node and the adjacent data line. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, and the like. Optionally, the plurality of first reset signal lines, the plurality of second reset signal lines, the second capacitor electrode Ce2 and the anti-interference block IPB are located in the same layer.

[0114] Figure 3F A via extending through the interlayer dielectric layer ILD is depicted in FIG.

[0115] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3H In some embodiments, the first signal line layer includes a plurality of voltage supply lines Vdd, a node connection line Cln, a first initialization connection line Cli1, a second initialization connection line Cli2, a relay electrode RE, a data connection pad DCP, a plurality of third reset signal lines (including a corresponding third reset signal line VintA located in the (2k-1)th column in the K column) and a plurality of fourth reset signal lines (including a corresponding fourth reset signal line VintB located in the (2k)th column). The node connection line Cln connects the first capacitor electrode Ce1 and the first electrode of the third transistor T3 in the corresponding pixel driving circuit together.

[0116] As used herein, the terms "column (2k-1)" and "column (2k)" are used in the context of column K. The array substrate may or may not include additional columns before the first column in column K and / or additional columns after the last column in column K. In the context of the array substrate, the term "column (2k-1)" does not necessarily mean an odd column, and the term "column (2k)" does not necessarily mean an even column. In one example, the column (2k-1) is an odd column in the context of column K, but may be an even column in the context of the array substrate. In another example, the column (2k-1) is an odd column in the context of column K, and is also an odd column in the context of the array substrate. In one example, the column (2k) is an even column in the context of column K, but may be an odd column in the context of the array substrate. In another example, the column (2k) is an even column in the context of column K, and is also an even column in the context of the array substrate.

[0117] Optionally, the first initialization connection line Cli1 exists in the (2k)th column but not in the (2k-1)th column. Optionally, each third reset signal line VintA exists in the (2k-1)th column but not in the (2k)th column. In the (2k-1)th column, the transmission of the reset signal is not accomplished by a separate initialization connection line, but is provided by the corresponding third reset signal line VintA as an integral signal line extending throughout the (2k-1)th column. Therefore, the first initialization connection line Cli1 does not exist in the (2k-1)th column.

[0118] Optionally, the second initialization connection line Cli2 exists in the (2k-1)th column but not in the (2k)th column. Optionally, each fourth reset signal line VintB exists in the (2k)th column but not in the (2k-1)th column. In the (2k)th column, the transmission of the reset signal is not accomplished by a separate initialization connection line, but is provided by the corresponding fourth reset signal line VintB as an integral signal line extending throughout the (2k)th column. Therefore, the second initialization connection line Cli2 does not exist in the (2k)th column.

[0119] The corresponding third reset signal line VintA in the (2k-1)th column connects the corresponding first reset signal line among the plurality of first reset signal lines (for example, the corresponding first reset signal line Vint1N at the current stage) and the first electrode S1 of the first transistor T1 in the corresponding pixel driving circuit in the (2k-1)th column.

[0120] The first initialization connection line Cli1 in the (2k)th column connects a corresponding first reset signal line among a plurality of first reset signal lines (eg, the current stage corresponding first reset signal line Vint1N) and a first electrode S1 of a first transistor T1 in a corresponding pixel driving circuit in the (2k)th column.

[0121] The corresponding fourth reset signal line VintB in the (2k)th column connects the corresponding second reset signal line among the plurality of second reset signal lines (for example, the corresponding second reset signal line Vint2N at the current stage) and the first electrode S6 of the sixth transistor T6 in the corresponding pixel driving circuit in the (2k)th column.

[0122] The second initialization connection line Cli2 in the (2k-1)th column connects a corresponding second reset signal line among a plurality of second reset signal lines (eg, the current stage corresponding second reset signal line Vint2N) and a first electrode S6 of a sixth transistor T6 in a corresponding pixel driving circuit in the (2k-1)th column.

[0123] The relay electrode RE connects the first electrode S5 of the fifth transistor T5 in the corresponding pixel driving circuit to an anode contact pad in the corresponding pixel driving circuit, which in turn is connected to an anode in a corresponding light emitting element of a corresponding sub-pixel.

[0124] The data signal connection pad DCP connects each data line with the first electrode of the second transistor T2 in the corresponding pixel driving circuit.

[0125] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, a plurality of voltage supply lines Vdd, a plurality of third reset signal lines, a plurality of fourth reset signal lines, a node connection line Cln, a first initialization connection line Cli1, a second initialization connection line Cli2, a data connection pad DCP, and a relay electrode RE are located on the same layer.

[0126] Reference Figure 2A , Figure 2B , 3A to 3H ,and Figure 4AIn some embodiments, except for the hole region H in which a portion of the second capacitor electrode Ce2 does not exist, the orthographic projection of the second capacitor electrode Ce2 on the substrate substrate BS completely covers and exceeds the orthographic projection of the first capacitor electrode Ce1 on the substrate substrate BS. In some embodiments, the first signal line layer includes a node connection line Cln, which is located on a side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. Optionally, the node connection line Cln is located on the same layer as the plurality of voltage supply lines Vdd. Optionally, the array substrate further includes a first via v1 located in the hole region H and extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1. In some embodiments, the first capacitor electrode Ce1 is located on a side of the gate insulating layer GI away from the substrate substrate BS. Optionally, the array substrate further includes a first via v1 and a second via v2. The first via v1 is located in the hole region H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via hole v1, and is connected to the semiconductor material layer SML through the second via hole v2. Figure 4A As depicted, the node connection line Cln is connected to the second electrode D3 of the third transistor.

[0127] Reference Figure 2A , Figure 2B , 3A to 3H and Figure 4A , in some embodiments, the anti-interference block IPB is located at the same layer as the second capacitor electrode Ce2. Each of the multiple voltage supply lines Vdd is connected to the interference prevention block IPB through a third via v3. Optionally, the third via v3 extends through the interlayer dielectric layer ILD. Optionally, the orthographic projection of the anti-interference block IPB on the substrate substrate BS partially overlaps with the orthographic projection of the corresponding voltage supply line in the multiple voltage supply lines Vdd on the substrate substrate BS. Optionally, the orthographic projection of the anti-interference block IPB on the substrate substrate BS overlaps at least partially with the orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate substrate BS. In one example, the orthographic projection of the anti-interference block IPB on the substrate substrate BS overlaps at least partially with the orthographic projection of the two channel portions of the active layer ACT3 of the third transistor T3 on the substrate substrate BS. In another example, the orthographic projection of the anti-interference block IPB on the substrate substrate BS covers the orthographic projection of the two channel portions of the active layer ACT3 of the third transistor T3 on the substrate substrate BS.

[0128] Figure 4B is along Figure 3A Cross-sectional view of line BB' in FIG. Figure 4B as well as FIG. 3A to FIG. 3H , the corresponding third reset signal line VintA in the (2k-1)th column connects the corresponding first reset signal line among the multiple first reset signal lines (for example, the corresponding first reset signal line Vint1N of the current stage) to the source S1 of the first transistor T1 of the corresponding pixel driving circuit in the (2k-1)th column. The corresponding first reset signal line among the multiple first reset signal lines (for example, the corresponding first reset signal line Vint1N of the current stage) is configured to provide a reset signal to the source S1 of the first transistor T1 in the corresponding pixel driving circuit in the (2k-1)th column through the corresponding third reset signal line VintA in the (2k-1)th column. Optionally, the corresponding third reset signal line VintA in the (2k-1)th column is connected to the corresponding first reset signal line Vint1N of the current stage through a fourth via v4 extending through the interlayer dielectric layer ILD. Optionally, the corresponding third reset signal line VintA in the (2k-1)th column is connected to the source S1 of the first transistor T1 in the corresponding pixel driving circuit in the (2k-1)th column through a fifth via v5 extending through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI.

[0129] Figure 4C is along Figure 3A Cross-sectional view of line C-C' in FIG. Figure 4C as well as 3A to 3H , the second initialization connection line Cli2 in the (2k-1)th column connects the corresponding second reset signal line among the plurality of second reset signal lines (for example, the corresponding second reset signal line Vint2N of the current stage) to the source S6 of the sixth transistor T6 in the corresponding pixel driving circuit in the (2k-1)th column. The corresponding second reset signal line among the plurality of second reset signal lines (for example, the corresponding second reset signal line Vint2N of the current stage) is configured to provide a reset signal to the source S6 of the sixth transistor T6 in the corresponding pixel driving circuit in the (2k-1)th column through the second initialization connection line Cli2 in the (2k-1)th column. Optionally, the second initialization connection line Cli2 is connected to the corresponding second reset signal line Vint2N of the current stage through a sixth via v6 extending through the interlayer dielectric layer ILD. Optionally, the second initialization connection line Cli2 is connected to the source S6 of the sixth transistor T6 in the corresponding pixel driving circuit in the (2k-1)th column through a seventh via hole v7 extending through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI.

[0130] Figure 4D is along Figure 3A The cross-sectional view of the line D-D' in FIG. Figure 4D as well as 3A to 3H, the first initialization connection line Cli1 of the (2k)th column connects the corresponding first reset signal line among the plurality of first reset signal lines (for example, the corresponding first reset signal line Vint1N of the current stage) to the source S1 of the first transistor T1 in the corresponding pixel driving circuit of the (2k)th column. The corresponding first reset signal line among the plurality of first reset signal lines (for example, the corresponding first reset signal line Vint1N of the current stage) is configured to provide a reset signal to the source S1 of the first transistor T1 in the corresponding pixel driving circuit in the (2k)th column through the first initialization connection line Cli1 in the (2k)th column. Optionally, the first initialization connection line Cli1 in the (2k)th column is connected to the corresponding first reset signal line Vint1N of the current stage through an eighth via v8 extending through the interlayer dielectric layer ILD. Optionally, the first initialization connection line Cli1 in the (2k)th column is connected to the source S1 of the first transistor T1 in the corresponding pixel driving circuit in the (2k)th column through a ninth via v9 extending through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI.

[0131] Figure 4E is along Figure 3A The cross-sectional view of the line E-E' in FIG. Figure 4E as well as 3A to 3H , the fourth reset signal line VintB in the (2k)th column connects the corresponding second reset signal line among the plurality of second reset signal lines (for example, the corresponding second reset signal line Vint2N of the current stage) to the source S6 of the sixth transistor T6 in the corresponding pixel driving circuit in the 2kth column. The corresponding second reset signal line among the plurality of second reset signal lines (for example, the corresponding second reset signal line Vint2N of the current stage) is configured to provide a reset signal to the source S6 of the sixth transistor T6 in the corresponding pixel driving circuit in the (2k)th column through the corresponding fourth reset signal line VintB in the (2k)th column. Optionally, the corresponding fourth reset signal line VintB in the (2k)th column is connected to the corresponding second reset signal line Vint2N of the current stage through a tenth via v10 extending through the interlayer dielectric layer ILD. Optionally, the corresponding fourth reset signal line VintB in the (2k)th column is connected to the source S6 of the sixth transistor T6 in the corresponding pixel driving circuit in the (2k)th column through an eleventh via v11 extending through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI.

[0132] Reference 3A to 3H as well as FIG. 4A to FIG. 4EIn each pixel driving circuit, in some embodiments, a corresponding gate line among the multiple gate lines GL includes a main portion MP extending along an extension direction of the corresponding gate line, and a gate protrusion GP protruding away from the main portion MP (for example, along a direction from a corresponding gate line of a current level among the multiple gate lines GL toward a corresponding reset control signal line rstN of the current level).

[0133] In some embodiments, as described above, the third transistor T3 is a dual-gate transistor. In some embodiments, the gate protrusion GP is one of the dual gates in the third transistor T3. Figure 4A , an orthographic projection of the gate protrusion GP on the substrate BS at least partially overlaps with an orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate BS.

[0134] In some embodiments, in each column of pixel driving circuits, the total number of pixel driving circuits (or the total number of sub-pixels) is P. In at least one corresponding column of pixel driving circuits, the ratio of the total number of reset signal lines extending along the second direction DR2 and passing through the P pixel driving circuits to the total number of initialization connection lines is 1:P. Figure 3A , Figure 3B and Figure 3H , in the (2k-1)th column C(2k-1), the total number of pixel driving circuits (or the total number of sub-pixels) is P. In the (2k-1)th column C(2k-1), the ratio of the total number of third reset signal lines to the total number of second initialization connection lines Cli2 is 1:P; the ratio of the total number of third reset signal lines to the total number of first initialization connection lines Cli1 is 1:0. In the (2k)th column C(2k), the total number of pixel driving circuits (or the total number of sub-pixels) is P. In the (2k)th column C(2k), the ratio of the total number of fourth reset signal lines to the total number of first initialization connection lines Cli1 is 1:P; the ratio of the total number of fourth reset signal lines to the total number of second initialization connection lines Cli2 is 1:0. As used herein, in the context of “the ratio of the total number of reset signal lines extending along the second direction DR2 and passing through the P pixel driving circuits to the total number of initialization connection lines is 1:P”, the term “P pixel driving circuits” refers to a pixel driving circuit configured to drive a light-emitting element to emit light. For example, the array substrate may include a dummy sub-pixel, and the dummy sub-pixel may include a "dummy" pixel driving circuit that cannot drive the dummy sub-pixel to emit light. In these dummy sub-pixels, there may be no initialization connection line. Therefore, when the array substrate includes p dummy sub-pixels and (Pp) light-emitting sub-pixels, the ratio of the total number of reset signal lines extending along the second direction DR2 and passing through the (Pp) pixel driving circuits and the p "dummy" pixel driving circuits to the total number of initialization connection lines is 1: (Pp).

[0135] The inventors of the present disclosure have observed that in the relevant array substrates, sub-pixels of different colors experience different degrees of attenuation after the reliability test. In particular, in the relevant array substrates, the luminous efficiency in the red sub-pixels and the blue sub-pixels decreases faster than the luminous efficiency in the green sub-pixels. This results in a green bias in the relevant array substrate after the reliability test. The inventors of the present disclosure have found that the structure and layout of the array substrate of the present disclosure avoid this problem and achieve excellent display quality.

[0136] In some embodiments, an orthographic projection of the light shielding layer on the base substrate at least partially overlaps an orthographic projection of an active layer of each of the drive transistor, the data write transistor, the compensation transistor, and the reset transistor on the base substrate. Figure 5 It is shown Figure 3A Schematic diagram of the structure of the light shielding layer and the semiconductor material layer in a part of the array substrate depicted in FIG. Figure 5 In some embodiments, the orthographic projection of the light shielding layer on the base substrate at least partially overlaps with the orthographic projection of the active layer of each of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6 and the driving transistor Td on the base substrate. Optionally, the orthographic projection of the light shielding layer on the base substrate covers the orthographic projection of the active layer of each of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6 and the driving transistor Td on the base substrate.

[0137] In some embodiments, the orthographic projection of the light shielding layer on the base substrate at least partially overlaps with the orthographic projection of each of the gates of the driving transistor, the data writing transistor, the compensation transistor, and the reset transistor on the base substrate. Figure 3A , Figure 3C and Figure 3E In some embodiments, the orthographic projection of the light shielding layer on the base substrate at least partially overlaps with the orthographic projection of the gate of each of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6 and the driving transistor Td on the base substrate. Optionally, the orthographic projection of the light shielding layer on the base substrate covers the orthographic projection of the gate of each of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6 and the driving transistor Td on the base substrate.

[0138] Figure 6 yes Figure 3A Schematic diagram of the structure of the light shielding layer in a portion of the array substrate depicted in FIG. Figure 6In some embodiments, the shading layer includes a plurality of first shading lines (for example, a first shading line LSL1N corresponding to a current level (for example, a current row) among the plurality of first shading lines, and a first shading line LSL1(N+1) corresponding to a next adjacent level (for example, a next adjacent row) among the plurality of first shading lines), a plurality of second shading lines LSL2, and a plurality of third shading lines LSL3.

[0139] Reference Figure 5 and Figure 6 In some embodiments, the orthographic projections of the plurality of first shading lines on the substrate at least partially overlap with the orthographic projections of the active layer of the first transistor T1 and the active layer of the sixth transistor T6 on the substrate. Optionally, the orthographic projections of the plurality of first shading lines on the substrate cover the orthographic projections of the active layer of the first transistor T1 and the active layer of the sixth transistor T6 on the substrate.

[0140] Reference Figure 5 and Figure 6 In some embodiments, the orthographic projection of a corresponding first shading light line among the plurality of first shading light lines on the substrate substrate at least partially overlaps with the orthographic projection of the active layer of the first transistor T1 in the current row pixel driving circuit and the active layer of the sixth transistor T6 in the previous adjacent row pixel driving circuit on the substrate substrate. Optionally, the orthographic projection of each first shading light line among the plurality of first shading light lines on the substrate substrate covers the orthographic projection of the active layer of the first transistor T1 in the current row pixel driving circuit and the active layer of the sixth transistor T6 in the previous adjacent row pixel driving circuit on the substrate substrate.

[0141] Reference Figure 5 and Figure 6 In some embodiments, the orthographic projection of the first shading line LSL1(N+1) corresponding to the next adjacent row of the plurality of first shading lines on the substrate substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor T6 in the pixel driving circuit of the current row and the active layer of the first transistor T1 in the pixel driving circuit of the next adjacent row on the substrate substrate. Optionally, the orthographic projection of the first shading line LSL1(N+1) corresponding to the next adjacent row of the plurality of first shading lines on the substrate substrate covers the orthographic projection of the active layer of the sixth transistor T6 in the pixel driving circuit of the current row and the active layer of the first transistor T1 in the pixel driving circuit of the next adjacent row on the substrate substrate.

[0142] Reference Figure 5 and Figure 6In some embodiments, the orthographic projection of the first shading line LSL1N corresponding to the current row of the plurality of first shading lines on the substrate substrate at least partially overlaps with the orthographic projection of the active layer of the first transistor T1 in the pixel driving circuit of the current row and the active layer of the sixth transistor T6 in the pixel driving circuit of the previous adjacent row on the substrate substrate. Optionally, the orthographic projection of the first shading line LSL1N corresponding to the current row of the plurality of first shading lines on the substrate substrate covers the orthographic projection of the active layer of the first transistor T1 in the pixel driving circuit of the current row and the active layer of the sixth transistor T6 in the pixel driving circuit of the previous adjacent row on the substrate substrate.

[0143] Reference Figure 5 and Figure 6 In some embodiments, the orthographic projection of the corresponding second shading line among the plurality of second shading lines LSL2 on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor T2 and the active layer of the third transistor T3 on the substrate. Optionally, the orthographic projection of the corresponding second shading line among the plurality of second shading lines LSL2 on the substrate covers the orthographic projection of the active layer of the second transistor T2 and the active layer of the third transistor T3 on the substrate.

[0144] In some embodiments, each second shading line includes a main body MB extending in a direction substantially parallel to the first direction DR1, and a light-shielding protrusion LSP protruding away from the main body MB in a direction substantially parallel to the second direction DR2. The second direction DR2 is different from the first direction DR1. The orthographic projection of the light-shielding protrusion LSP on the substrate substrate overlaps at least partially with the orthographic projection of one of the two channel portions of the active layer of the third transistor T3 on the substrate substrate. Optionally, the orthographic projection of the light-shielding protrusion LSP on the substrate substrate covers the orthographic projection of one of the two channel portions of the active layer of the third transistor T3 on the substrate substrate.

[0145] Reference Figure 5 and Figure 6 In some embodiments, the orthographic projection of a corresponding third shading line among the plurality of third shading lines LSL3 on the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor Td on the substrate. Optionally, the orthographic projection of a corresponding third shading line among the plurality of third shading lines LSL3 on the substrate covers the orthographic projection of the active layer of the driving transistor Td on the substrate.

[0146] In some embodiments, each third shading line includes a plurality of islands Is and a plurality of bridges Br. Adjacent islands in the plurality of islands Is are connected by corresponding bridges in the plurality of bridges Br. The orthographic projection of each island in the plurality of islands Is on the substrate substrate overlaps at least partially with the orthographic projection of the active layer of the driving transistor Td on the substrate substrate. Optionally, the orthographic projection of each island in the plurality of islands Is on the substrate substrate covers the orthographic projection of the active layer of the driving transistor Td on the substrate substrate.

[0147] In some embodiments, each third light-shielding line further includes an extension E extending away from one of the plurality of islands. The plurality of islands Is and the plurality of bridges Br are alternately arranged along a direction substantially parallel to the first direction DR1. The extension E extends away from one of the plurality of islands Is along a direction substantially parallel to the second direction DR2. 3A to 3H as well as Figure 6 In some embodiments, the extension E is connected to one of the plurality of voltage supply lines Vdd. In one example, one of the plurality of voltage supply lines Vdd is connected to the extension E through a twelfth via v12. For example, the twelfth via v12 extends through the interlayer dielectric layer ILD, the insulating layer IN, the gate insulating layer GI, and the buffer layer BUF. In some embodiments, the corresponding third shielding line is configured to be provided with a voltage supply signal from one of the plurality of voltage supply lines Vdd.

[0148] Figure 7 It is shown Figure 3A Schematic diagram of the structure of the light shielding layer and the first conductive layer in a portion of the array substrate depicted in FIG. Figure 3E , Figure 6 and Figure 7 In some embodiments, the orthographic projections of the plurality of first shading lines on the base substrate overlap at least partially with the orthographic projections of the plurality of reset control signal lines on the base substrate. Optionally, the orthographic projections of the plurality of first shading lines on the base substrate cover the orthographic projections of the plurality of reset control signal lines on the base substrate.

[0149] In some embodiments, the orthographic projection of the first shading line LSL1N corresponding to the current row of the plurality of first shading lines on the substrate substrate overlaps at least partially with the orthographic projection of the reset control signal line rstN corresponding to the current row of the plurality of reset control signal lines on the substrate substrate; the orthographic projection of the first shading line LSL1(N+1) corresponding to the next adjacent row of the plurality of first shading lines on the substrate substrate overlaps at least partially with the orthographic projection of the reset control signal line rst(N+1) corresponding to the next adjacent row of the plurality of reset control signal lines on the substrate substrate. Optionally, the orthographic projection of the first shading line LSL1N corresponding to the current row of the plurality of first shading lines on the substrate substrate covers the orthographic projection of the reset control signal line rstN corresponding to the current row of the plurality of reset control signal lines on the substrate substrate; the orthographic projection of the first shading line LSL1(N+1) corresponding to the next adjacent row of the plurality of first shading lines on the substrate substrate covers the orthographic projection of the reset control signal line rst(N+1) corresponding to the next adjacent row of the plurality of reset control signal lines on the substrate substrate.

[0150] In some embodiments, the orthographic projection of each second shading line in the plurality of second shading lines LSL2 on the substrate substrate overlaps at least partially with the orthographic projection of the corresponding gate line in the plurality of gate lines GL on the substrate substrate. Optionally, the orthographic projection of each second shading line in the plurality of second shading lines LSL2 on the substrate substrate covers the orthographic projection of the corresponding gate line GL in the plurality of gate lines GL on the substrate substrate.

[0151] In some embodiments, the orthographic projection of the main body MB of each second shading line on the substrate substrate overlaps at least partially with the orthographic projection of the main part MP of the corresponding gate line on the substrate substrate. Optionally, the orthographic projection of the main body MB of each second shading line on the substrate substrate covers the orthographic projection of the main part MP of the corresponding gate line on the substrate substrate.

[0152] In some embodiments, the orthographic projection of the light-shielding protrusion LSP of each second shading line on the substrate substrate overlaps at least partially with the orthographic projection of the gate protrusion GP of the corresponding gate line on the substrate substrate. Optionally, the orthographic projection of the light-shielding protrusion LSP of each second shading line on the substrate substrate covers the orthographic projection of the gate protrusion GP of the corresponding gate line on the substrate substrate.

[0153] In some embodiments, the orthographic projection of the corresponding island among the plurality of islands Is of the corresponding third light-shielding line on the substrate at least partially overlaps with the orthographic projection of the first capacitor electrode Ce1 of the storage capacitor on the substrate. Optionally, the orthographic projection of the corresponding island among the plurality of islands Is of the corresponding third light-shielding line on the substrate covers the orthographic projection of the first capacitor electrode Ce1 of the storage capacitor on the substrate.

[0154] Figure 8The layout of the light shielding layer, the semiconductor material layer and the first conductive layer in a part of the array substrate in some embodiments of the present disclosure is shown. Fig. 9 Shows Figure 8 Layout of the light shielding layer in a portion of the array substrate depicted in FIG. Figure 8 and Fig. 9 , the array substrate includes a display area DA and a peripheral area PA. As used herein, the term "display area" refers to the area of ​​the array substrate that actually displays the image. Optionally, the display area may include a sub-pixel area and an inter-sub-pixel area. The sub-pixel area refers to the light-emitting area of ​​the sub-pixel (for example, the area corresponding to the pixel electrode in the liquid crystal display or the area corresponding to the light-emitting layer in the organic light-emitting diode display panel). The inter-sub-pixel area refers to the area between adjacent sub-pixel areas, such as the area corresponding to the black matrix in the liquid crystal display or the area corresponding to the pixel defining layer in the organic light-emitting display. Optionally, the inter-sub-pixel area is the area between adjacent sub-pixel areas in the same pixel. Optionally, the inter-sub-pixel area is the area between two adjacent sub-pixel areas in two adjacent pixels. The term "peripheral area" refers to the following area of ​​the array substrate: in this area, various circuits and wires are provided to transmit signals to the display substrate. In order to increase the transparency of the display device, the opaque or light-proof components of the display device (for example, batteries, printed circuit boards, metal frames) can be arranged in the peripheral area instead of in the display area.

[0155] In some embodiments, the plurality of first shading lines and the plurality of second shading lines LSL2 are configured to be provided with a gate scanning signal. In some embodiments, the plurality of first shading lines and the plurality of second shading lines LSL2 are connected to a gate scanning circuit (e.g., an array gate scanning circuit) configured to provide a gate scanning signal. Optionally, the gate scanning circuit is located in the peripheral area PA.

[0156] In some embodiments, a second shielding line corresponding to a current row of the plurality of second shielding line LSL2 and a first shielding line LSL1(N+1) corresponding to a next adjacent row of the plurality of first shielding line are connected to each other in the peripheral area PA.

[0157] In some embodiments, the second shielding line corresponding to a current row of the plurality of second shielding line LSL2 and the first shielding line LSL1(N+1) corresponding to the next adjacent row of the plurality of first shielding line are connected to each other in the peripheral area PA on both sides of the display area DA. Fig.10 A ring structure in some embodiments according to the present disclosure is shown, which is formed by second shading lines corresponding to a current row of a plurality of second shading lines and first shading lines corresponding to a next adjacent row of a plurality of first shading lines.

[0158] In some embodiments, the plurality of third light-shielding lines LSL3 are configured to be provided with a voltage supply signal. As described above, the corresponding third light-shielding lines are configured to be provided with a voltage supply signal from one of the plurality of voltage supply lines. For example, one of the plurality of voltage supply lines is connected to an extension of the corresponding third light-shielding line through a via. Optionally, the plurality of third light-shielding lines LSL3 are connected to the same voltage supply line among the plurality of voltage supply lines.

[0159] Fig.11 Figure 2 shows the Id-Vg curves of some array substrates. Fig.11 , Vg represents the gate voltage of the transistor, and Id represents the drain current corresponding to the gate voltage. The Id-Vg curve shows the relationship between the drain current and the gate voltage. S0 is the Id-Vg curve of the array substrate in the initial state. S1 is the Id-Vg curve of the related array substrate without the light shielding layer. S2 is the Id-Vg curve of the array substrate with the light shielding layer according to the present disclosure. Fig.11 As shown, compared with the Id-Vg curve of the array substrate with a light shielding layer according to the present disclosure, the Id-Vg curve of the related array substrate has a larger drift relative to the Id-Vg curve of the array substrate in the initial state. In the array substrate with a light shielding layer according to the present disclosure, the green shift is greatly reduced.

[0160] Fig.12 The Wy-Lv correspondence of some array substrates is shown. Fig.12 , Wy represents the yellow-blue axis in the color space, and Lv represents the brightness axis in the color space. Fig.12 As shown, if the Wy value is less than 0.45 when the brightness value is less than 0.065nit, it is considered that the array substrate has no green shift. W0 is the Wy-Lv correspondence of the array substrate in the initial state. W1 is the Wy-Lv correspondence of the relevant array substrate without the shading layer. W2 is the Wy-Lv correspondence of the array substrate with the shading layer according to the present disclosure. W3 is the Wy-Lv correspondence of the array substrate with the shading layer that only blocks the driving transistor in the array substrate but does not block other transistors. Fig.12 As shown, the array substrate with the light shielding layer according to the present disclosure does not have a green color cast.

[0161] Various alternative arrangements of light shielding layers may be implemented in the present disclosure. Fig.13A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure. Fig. 13B It is shown Fig.13A Schematic diagram of the arrangement of multiple pixel driving circuits in a portion of an array substrate depicted in FIG. Fig. 13C It is shown Fig.13ASchematic diagram of the structure of a light shielding layer in a portion of an array substrate depicted in FIG. Fig.13D It is shown Fig.13A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG. Fig.13E It is shown Fig.13A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG. Fig.13F It is shown Fig.13A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG.

[0162] Reference Fig.13A and Fig. 13C In some embodiments, the light shielding layer includes a light shielding member LS. Figure 2A , Figure 2B , Fig.13A and Fig.13D , each pixel driving circuit is labeled with a number, and the number represents the region corresponding to the plurality of transistors (including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the driving transistor Td) in each pixel driving circuit. Each pixel driving circuit is also labeled with a number representing a component of each of the plurality of transistors in the pixel driving circuit. Figure 2A , Figure 2B , Fig.13A and Fig.13E In some embodiments, the first conductive layer includes a first capacitor electrode Ce1 of a storage capacitor Cst, a plurality of light emitting control signal lines em, a first gate pad including a gate G1 of a first transistor T1, a second gate pad including a gate G3 of a third transistor T3, and a third gate pad including a gate G6 of a sixth transistor T6. Figure 2A , Figure 2B , Fig.13A and Fig.13F In some embodiments, the first signal line layer includes a plurality of first reset control signal lines rst1, a plurality of second reset control signal lines rst2, a plurality of gate lines GL, and a plurality of voltage supply lines Vdd.

[0163] In some embodiments, the light shielding member LS is an integral structure. In some embodiments, the orthographic projection of the integral structure of the light shielding member LS on the substrate at least partially overlaps with the orthographic projection of the active layer of each of the driving transistor, the data writing transistor, the compensation transistor and the reset transistor on the substrate. Fig.14 yes Fig.13A Schematic diagram of the structure of the light shielding layer and the semiconductor material layer in a part of the array substrate depicted in FIG. Fig.14In some embodiments, the orthographic projection of the overall structure of the light shielding member LS on the substrate at least partially overlaps with the orthographic projection of the active layer of each of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6 and the driving transistor Td on the substrate. Optionally, the orthographic projection of the overall structure of the light shielding member LS on the substrate covers the orthographic projection of the active layer of each of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6 and the driving transistor Td on the substrate.

[0164] In some embodiments, the orthographic projection of the light shielding layer on the base substrate at least partially overlaps with the orthographic projection of each of the gates of the driving transistor, the data writing transistor, the compensation transistor, and the reset transistor on the base substrate. Fig.13A , Fig. 13C and Fig.13E In some embodiments, the orthographic projection of the overall structure of the light shielding member LS on the substrate at least partially overlaps with the orthographic projection of the gate of each of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6 and the driving transistor Td on the substrate. Optionally, the orthographic projection of the overall structure of the light shielding member LS on the substrate covers the orthographic projection of the gate of each of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6 and the driving transistor Td on the substrate.

[0165] Fig.15 FIG. 2 shows the layout of the light shielding layer in a portion of the array substrate in some embodiments of the present disclosure. Fig.15 In some embodiments, the light shielding layer is an interconnected light shielding network extending throughout a plurality of sub-pixels in the array substrate. The interconnected light shielding network includes light shielding lines extending in a direction substantially parallel to the first direction DR1 and light shielding lines extending in a direction substantially parallel to the second direction DR2. In some embodiments, the light shielding layer includes a plurality of first islands Is1, a plurality of second islands Is2, a plurality of first bridges Br1, a plurality of second bridges Br2, a plurality of third bridges Br3, and a plurality of branches Ba.

[0166] In some embodiments, the light shielding layer includes multiple rows of islands; each row of islands in the multiple rows of islands includes multiple first islands arranged along a direction substantially parallel to the first direction DR1 in multiple first islands Is1 and multiple second islands arranged along a direction substantially parallel to the first direction DR1 in multiple second islands Is2. In some embodiments, a corresponding first bridge in the multiple first bridges Br1 connects the first islands in the multiple first islands Is1 and the second islands in the multiple second islands Is2 in two adjacent rows. In some embodiments, a corresponding second bridge in the multiple second bridges Br2 connects the first islands in the multiple first islands Is1 and the second islands in the multiple second islands Is2 in the same row. In some embodiments, a corresponding third bridge in the multiple third bridges Br3 connects two adjacent first islands in the multiple first islands Is1 in the same row. In some embodiments, each branch in the multiple branches Ba, for example, extends away from the corresponding first island in the multiple first islands Is1 in a direction substantially parallel to the second direction DR2.

[0167] Reference Fig.14 , Fig.15 as well as FIG. 13A to FIG. 13E In some embodiments, the orthographic projection of the corresponding first island among the plurality of first islands Is1 on the substrate substrate at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td on the substrate substrate. Optionally, the orthographic projection of the corresponding first island among the plurality of first islands Is1 on the substrate substrate covers the orthographic projection of the active layer ACTd of the driving transistor Td on the substrate substrate. In some embodiments, the orthographic projection of the corresponding first island among the plurality of first islands Is1 on the substrate substrate at least partially overlaps with the orthographic projection of the first capacitor electrode Ce1 of the storage capacitor on the substrate substrate. Optionally, the orthographic projection of the corresponding first island among the plurality of first islands Is1 on the substrate substrate covers the orthographic projection of the first capacitor electrode Ce1 of the storage capacitor on the substrate substrate.

[0168] In some embodiments, the orthographic projection of the corresponding second island among the plurality of second islands Is2 on the substrate substrate at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate substrate. Optionally, the orthographic projection of the corresponding second island among the plurality of second islands Is2 on the substrate substrate covers the orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate substrate. In some embodiments, the orthographic projection of the corresponding second island among the plurality of second islands Is2 on the substrate substrate at least partially overlaps with the orthographic projection of the gate G3 of the third transistor T3 on the substrate substrate. Optionally, the orthographic projection of the corresponding second island among the plurality of second islands Is2 on the substrate substrate covers the orthographic projection of the gate G3 of the third transistor T3 on the substrate substrate.

[0169] In some embodiments, the orthographic projection of the corresponding branch Ba among the multiple branches Ba on the substrate substrate overlaps at least partially with the orthographic projection of the active layer ACT2 of the second transistor T2 on the substrate substrate. Optionally, the orthographic projection of the corresponding branch Ba among the multiple branches Ba on the substrate substrate covers the orthographic projection of the active layer ACT2 of the second transistor T2 on the substrate substrate. In some embodiments, the orthographic projection of the corresponding branch Ba among the multiple branches Ba on the substrate substrate overlaps at least partially with the orthographic projection of the gate of the second transistor T2 on the substrate substrate. Optionally, the orthographic projection of each branch Ba among the multiple branches Ba on the substrate substrate covers the orthographic projection of the gate of the second transistor T2 on the substrate substrate.

[0170] In some embodiments, the orthographic projection of the corresponding first bridge among the plurality of first bridges Br1 on the substrate substrate at least partially overlaps with the orthographic projection of the active layer ACT1 of the first transistor T1 and the active layer ACT6 of the sixth transistor T6 on the substrate substrate. Optionally, the orthographic projection of the corresponding first bridge among the plurality of first bridges Br1 on the substrate substrate covers the orthographic projection of the active layer ACT1 of the first transistor T1 and the active layer ACT6 of the sixth transistor T6 on the substrate substrate. In some embodiments, the orthographic projection of the corresponding first bridge among the plurality of first bridges Br1 on the substrate substrate at least partially overlaps with the orthographic projection of the gate G1 of the first transistor T1 and the gate G6 of the sixth transistor T6 on the substrate substrate. Optionally, the orthographic projection of the corresponding first bridge among the plurality of first bridges Br1 on the substrate substrate covers the orthographic projection of the gate G1 of the first transistor T1 and the gate G6 of the sixth transistor T6 on the substrate substrate.

[0171] In some embodiments, the light shielding member for shielding each of the drive transistor, the data write transistor, the compensation transistor, and the reset transistor is configured to be provided with the same voltage signal. In one example, the light shielding member for shielding each of the drive transistor, the data write transistor, the compensation transistor, and the reset transistor is configured to be provided with a voltage supply signal. In another example, the light shielding member for shielding each of the drive transistor, the data write transistor, the compensation transistor, and the reset transistor is configured to be provided with a gate scan signal.

[0172] Fig.16A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure. Fig. 16B It is shown Fig.16A Schematic diagram of the structure of a light shielding layer in a portion of an array substrate depicted in FIG. Fig. 16C It is shown Fig.16A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG. Fig.16D It is shown Fig.16AA schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG. Fig.16E It is shown Fig.16A Schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in FIG. FIG. 16A to FIG. 16E In some embodiments, the array substrate includes a display area DA and a peripheral area PA.

[0173] In some embodiments, the light shielding layer includes a peripheral light shielding signal line PLSL in the peripheral area PA and a plurality of peripheral connection lines PCL connecting the light shielding member LS in the display area DA and the peripheral light shielding signal line PLSL in the peripheral area PA. As described above, in some embodiments, the light shielding member LS in the display area DA includes a plurality of rows of islands; each row of islands in the plurality of rows of islands includes a plurality of first islands Is1 arranged along a direction substantially parallel to the first direction DR1 and a plurality of second islands Is2 arranged along a direction substantially parallel to the first direction DR1. Adjacent rows in the plurality of rows of islands are connected by a plurality of bridges (e.g., by a plurality of first bridges Br1).

[0174] In some embodiments, corresponding peripheral connection lines among the plurality of peripheral connection lines PCL connect corresponding rows in the plurality of row islands with the peripheral light shielding signal line PLSL. The light shielding member LS in the display area DA is configured to be provided with the same voltage signal provided by the peripheral light shielding member signal line PLSL. In one example, the peripheral light shielding signal line PLSL in the peripheral area PA and the light shielding member LS in the display area DA are configured to be provided with a voltage supply signal. In another example, the peripheral light shielding signal line PLSL in the peripheral area PA and the light shielding member LS in the display area DA are configured to be provided with a gate scan signal.

[0175] Fig.17A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure. Fig. 17B It is shown Fig.17A A schematic diagram of the structure of a light shielding layer in a portion of an array substrate depicted in FIG. Fig. 17C It is shown Fig.17A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG. Fig.17D It is shown Fig.17A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG. Fig.17E It is shown Fig.17A A schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG. Fig.17F It is shown Fig.17A Schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in FIG. FIG. 17A to FIG. 17FIn some embodiments, the light-shielding layer includes a plurality of first light-shielding lines LSL1, a plurality of second light-shielding lines LSL2, and a plurality of third light-shielding lines LSL3.

[0176] In some embodiments, the orthographic projections of the plurality of first shading light lines LSL1 on the substrate at least partially overlap with the orthographic projections of the active layer of the first transistor T1 and the active layer of the sixth transistor T6 on the substrate. Optionally, the orthographic projections of the plurality of first shading light lines on the substrate cover the orthographic projections of the active layer of the first transistor T1 and the active layer of the sixth transistor T6 on the substrate.

[0177] In some embodiments, the orthographic projection of the corresponding first shading line among the plurality of first shading lines LSL1 on the substrate substrate at least partially overlaps with the orthographic projection of the active layer of the first transistor T1 in the current row pixel driving circuit and the active layer of the sixth transistor T6 in the previous adjacent row pixel driving circuit on the substrate substrate. Optionally, the orthographic projection of the corresponding first shading line among the plurality of first shading lines LSL1 on the substrate substrate covers the orthographic projection of the active layer of the first transistor T1 in the current row pixel driving circuit and the active layer of the sixth transistor T6 in the previous adjacent row pixel driving circuit on the substrate substrate.

[0178] In some embodiments, the orthographic projection of the corresponding second shading line among the plurality of second shading lines LSL2 on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor T2 and the active layer of the third transistor T3 on the substrate. Optionally, the orthographic projection of the corresponding second shading line among the plurality of second shading lines LSL2 on the substrate covers the orthographic projection of the active layer of the second transistor T2 and the active layer of the third transistor T3 on the substrate.

[0179] In some embodiments, each second shading line includes a main body MB extending in a direction substantially parallel to the first direction DR1, and a light-shielding protrusion LSP protruding away from the main body MB in a direction substantially parallel to the second direction DR2. The second direction DR2 is different from the first direction DR1. The orthographic projection of the light-shielding protrusion LSP on the substrate substrate overlaps at least partially with the orthographic projection of one of the two channel portions of the active layer of the third transistor T3 on the substrate substrate. Optionally, the orthographic projection of the light-shielding protrusion LSP on the substrate substrate covers the orthographic projection of one of the two channel portions of the active layer of the third transistor T3 on the substrate substrate.

[0180] In some embodiments, the orthographic projection of the corresponding third shading line among the plurality of third shading lines LSL3 on the substrate substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor Td on the substrate substrate. Optionally, the orthographic projection of the corresponding third shading line among the plurality of third shading lines LSL3 on the substrate substrate covers the orthographic projection of the active layer of the driving transistor Td on the substrate substrate.

[0181] In some embodiments, each third shading line includes a plurality of islands Is and a plurality of bridges Br. Adjacent islands in the plurality of islands Is are connected by corresponding bridges in the plurality of bridges Br. The orthographic projection of the corresponding island in the plurality of islands Is on the substrate substrate overlaps at least partially with the orthographic projection of the active layer of the driving transistor Td on the substrate substrate. Optionally, the orthographic projection of the corresponding island in the plurality of islands Is on the substrate substrate covers the orthographic projection of the active layer of the driving transistor Td on the substrate substrate.

[0182] In some embodiments, the orthographic projections of the plurality of first shading lines on the base substrate at least partially overlap with the orthographic projections of the plurality of reset control signal lines on the base substrate. Optionally, the orthographic projections of the plurality of first shading lines on the base substrate cover the orthographic projections of the plurality of reset control signal lines on the base substrate.

[0183] In some embodiments, the orthographic projection of each second shading line in the plurality of second shading lines LSL2 on the substrate at least partially overlaps with the orthographic projection of the corresponding gate line in the plurality of gate lines GL on the substrate. Optionally, the orthographic projection of each second shading line in the plurality of second shading lines LSL2 on the substrate covers the orthographic projection of the corresponding gate line in the plurality of gate lines GL on the substrate.

[0184] In some embodiments, the orthographic projection of the main body MB of each second shading line on the substrate substrate overlaps at least partially with the orthographic projection of the main part MP of the corresponding gate line on the substrate substrate. Optionally, the orthographic projection of the main body MB of each second shading line on the substrate substrate covers the orthographic projection of the main part MP of the corresponding gate line on the substrate substrate.

[0185] In some embodiments, the orthographic projection of the light-shielding protrusion LSP of each second shading line on the substrate substrate overlaps at least partially with the orthographic projection of the gate protrusion GP of the corresponding gate line on the substrate substrate. Optionally, the orthographic projection of the light-shielding protrusion LSP of each second shading line on the substrate substrate covers the orthographic projection of the gate protrusion GP of the corresponding gate line on the substrate substrate.

[0186] In some embodiments, the orthographic projection of a corresponding island among the plurality of islands Is of each third light-shielding line on the substrate at least partially overlaps with the orthographic projection of the first capacitor electrode Ce1 of the storage capacitor on the substrate. Optionally, the orthographic projection of a corresponding island among the plurality of islands Is of each third light-shielding line on the substrate covers the orthographic projection of the first capacitor electrode Ce1 of the storage capacitor on the substrate.

[0187] In some embodiments, the array substrate includes a display area DA and a peripheral area PA. FIG. 17A to FIG. 17F The array substrate depicted in Figure 8 The difference between the array substrate depicted in FIG. 1 and FIG. 2 is that: FIG. 17A to FIG. 17F The light shielding layer in the array substrate depicted in FIG. 1 is not connected to the plurality of voltage supply lines in the display area DA. In addition, FIG. 17A to FIG. 17F Each third light-shielding line in the array substrate depicted in FIG. 1 need not include an extension portion E.

[0188] In some embodiments, the light shielding layer includes a peripheral light shielding signal line PLSL in the peripheral area PA, and a plurality of peripheral connection lines PCL connecting a plurality of third light shielding lines LSL3 in the display area DA and the peripheral light shielding signal line PLSL in the peripheral area PA.

[0189] In some embodiments, each of the plurality of peripheral connection lines PCL connects a corresponding third shading line in the plurality of third shading lines LSL3 to the peripheral shading signal line PLSL. Each third shading line in the display area DA is configured to be provided with the same voltage signal provided by the peripheral shading signal line PLSL. In one example, the peripheral shading signal line PLSL in the peripheral area PA and the plurality of third shading lines LSL3 in the display area DA are configured to be provided with a voltage supply signal. In another example, the peripheral shading signal line PLSL in the peripheral area PA and the plurality of third shading lines LSL3 in the display area DA are configured to be provided with a gate scan signal.

[0190] In some embodiments, multiple first shading line lines LSL1 and multiple second shading line lines LSL2 are connected to a gate scanning circuit in the peripheral area PA, and the gate scanning circuit (e.g., an on-array gate scanning circuit) is configured to provide a gate scanning signal to the multiple first shading line lines LSL1 and the multiple second shading line lines LSL2.

[0191] Fig.18A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure. Fig.18B It is shown Fig.18A Schematic diagram of the structure of a light shielding layer in a portion of an array substrate depicted in FIG. Fig.18C It is shown Fig.18A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG. Fig.18D It is shown Fig.18A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate depicted in FIG. Fig.18E It is shown Fig.18A Schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG. Fig.18F It is shown Fig.18A A schematic diagram of the structure of the first signal line layer in a portion of an array substrate depicted in FIG. FIG. 18A to FIG. 18F The array substrate depicted in FIG. 17A to FIG. 17F The difference between the array substrate depicted in FIG. 1 and FIG. 2 is that: FIG. 18A to FIG. 18FThe light shielding layer in the array substrate depicted in FIG. 1 is connected to both the peripheral light shielding signal line PLSL in the peripheral area PA and the plurality of voltage supply lines in the display area DA. FIG. 18A to FIG. 18F Each third light-shielding line in the array substrate depicted in FIG. 1 includes an extension portion E.

[0192] Reference FIG. 18A to FIG. 18F In some embodiments, each third light-shielding line further includes an extension E extending away from one of the plurality of islands. The plurality of islands Is and the plurality of bridges Br are alternately arranged along a direction substantially parallel to the first direction DR1. The extension E extends away from one of the plurality of islands Is along a direction substantially parallel to the second direction DR2. FIG. 18A to FIG. 18F In some embodiments, the extension E is connected to one of the plurality of voltage supply lines Vdd. In one example, the one of the plurality of voltage supply lines Vdd is connected to the extension E through a via. For example, the via extends through the interlayer dielectric layer ILD, the insulating layer IN, the gate insulating layer GI, and the buffer layer BUF. In some embodiments, the corresponding third shielding line is configured to be provided with a voltage supply signal from the one of the plurality of voltage supply lines Vdd.

[0193] Reference FIG. 18A to FIG. 18F In some embodiments, the light shielding layer includes a peripheral light shielding signal line PLSL in the peripheral area PA, and a plurality of peripheral connection lines PCL connecting a plurality of third light shielding lines LSL3 in the display area DA with the peripheral light shielding signal line PLSL in the peripheral area PA. In some embodiments, each of the plurality of peripheral connection lines PCL connects a corresponding third light shielding line in the plurality of third light shielding lines LSL3 with the peripheral light shielding signal line PLSL. Each third light shielding line in the display area DA is configured to be provided with the same voltage signal provided by the peripheral light shielding signal line PLSL. In one example, the peripheral light shielding signal line PLSL in the peripheral area PA and the plurality of third light shielding lines LSL3 in the display area DA are configured to be provided with a voltage supply signal.

[0194] Fig.19A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure. Fig.19B It is shown Fig.19A A schematic diagram of the structure of a light shielding layer in a portion of an array substrate depicted in FIG. Fig.19C It is shown Fig.19A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG. Fig.19D It is shown Fig.19A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG. Fig.19E It is shown Fig.19AA schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG. Fig.19F It is shown Fig.19A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG. FIG. 19A to FIG. 19F The array substrate depicted in FIG. 3A to FIG. 3H The difference between the array substrate depicted in FIG. 1 and FIG. 2 is that the plurality of islands Is are separated from each other and from other portions of the light shielding layer.

[0195] Reference FIG. 19A to FIG. 19F In some embodiments, the light shielding layer includes a plurality of first shielding lines LSL1, a plurality of second shielding lines LSL2, a plurality of islands Is separated from each other, and a plurality of extensions ET. Each of the plurality of extensions ET extends away from a corresponding island in the plurality of islands Is. Each of the extensions extends away from a corresponding island in the plurality of islands Is along a direction substantially parallel to the second direction DR2.

[0196] In some embodiments, each extension is connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd. In one example, each voltage supply line among a plurality of voltage supply lines Vdd is connected to a corresponding extension through a via. For example, the via extends through the interlayer dielectric layer ILD, the insulating layer IN, the gate insulating layer GI, and the buffer layer BUF. In some embodiments, the corresponding extension and the corresponding island are configured to be provided with a voltage supply signal from one of the plurality of voltage supply lines Vdd.

[0197] In some embodiments, the orthographic projection of a corresponding island among the plurality of islands Is on the substrate substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor Td on the substrate substrate. Optionally, the orthographic projection of a corresponding island among the plurality of islands Is on the substrate substrate covers the orthographic projection of the active layer of the driving transistor Td on the substrate substrate.

[0198] In some embodiments, the orthographic projection of a corresponding island among the plurality of islands Is on the substrate substrate at least partially overlaps with the orthographic projection of the first capacitor electrode Ce1 of the storage capacitor on the substrate substrate. Optionally, the orthographic projection of a corresponding island among the plurality of islands Is on the substrate substrate covers the orthographic projection of the first capacitor electrode Ce1 of the storage capacitor on the substrate substrate.

[0199] Reference Figures 8 to 10 , FIG. 17A to FIG. 17F , FIG. 18A to FIG. 18F as well as FIG. 19A to FIG. 19FIn some embodiments, the orthographic projection of the first portion of the light shielding layer on the substrate substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor on the substrate substrate, and the orthographic projection of the second portion of the light shielding layer on the substrate substrate at least partially overlaps with the orthographic projection of the active layer of the data writing transistor, the compensation transistor, and at least one of the one or more reset transistors on the substrate substrate. Optionally, the first portion and the second portion are configured to be provided with different signals. Optionally, the first portion is configured to be provided with a constant voltage signal and the second portion is configured to be provided with a pulse signal. In one example, the first portion is configured to be provided with a voltage supply signal and the second portion is configured to be provided with a gate scan signal.

[0200] Reference Figures 8 to 10 as well as FIG. 17A to FIG. 17F In some embodiments, the first portion includes a plurality of third light-shielding lines LSL3, and the second portion includes a plurality of first light-shielding lines and a plurality of second light-shielding lines LSL2. Optionally, the plurality of first light-shielding lines and the plurality of second light-shielding lines LSL2 are connected to a gate scanning circuit configured to provide a gate scanning signal. Optionally, the plurality of third light-shielding lines LSL3 are connected to a signal line configured to provide a voltage supply signal.

[0201] In some embodiments, reference Figures 8 to 10 , FIG. 3A to FIG. 3H as well as FIG. 4A to FIG. 4E One of the plurality of voltage supply lines Vdd is connected to an extension of a corresponding third light-shielding line among the plurality of third light-shielding lines LSL3 through a via. Alternatively, the plurality of third light-shielding lines LSL3 are connected to the same voltage supply line among the plurality of voltage supply lines Vdd.

[0202] In some embodiments, reference FIG. 17A to FIG. 17F The shading layer also includes a peripheral shading signal line PLSL located in the peripheral area PA of the array substrate, and a plurality of peripheral connecting lines PCL connecting a plurality of third shading lines LSL3 in the display area DA of the array substrate and the peripheral shading signal line PLSL in the peripheral area PA.

[0203] In some embodiments, reference FIG. 18A to FIG. 18F , one of the plurality of voltage supply lines Vdd is connected to an extension of a corresponding third shading line in a plurality of third shading lines LSL3 through a via. Optionally, the plurality of third shading lines LSL3 are connected to the same voltage supply line in the plurality of voltage supply lines Vdd. Optionally, the shading layer further includes a peripheral shading signal line PLSL located in the peripheral area PA of the array substrate, and a plurality of peripheral connection lines PCL connecting the plurality of third shading lines LSL3 in the display area DA of the array substrate with the peripheral shading signal line PLSL in the peripheral area PA.

[0204] In some embodiments, reference FIG. 19A to FIG. 19F , the first part includes a plurality of islands Is and a plurality of extensions ET separated from each other. The second part includes a plurality of first shading lines LSL1 and a plurality of second shading lines LSL2. Optionally, each of the plurality of extensions ET extends away from a corresponding island in the plurality of islands Is. Optionally, each of the plurality of voltage supply lines Vdd is connected to a corresponding extension through a via.

[0205] In another aspect, the present invention provides a display device, comprising an array substrate as described herein or manufactured by the method described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a micro light emitting diode display device. Optionally, the display device is a mini light emitting diode display device.

[0206] On the other hand, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming a plurality of pixel drive circuits. Optionally, forming each of the plurality of pixel drive circuits includes: forming a drive transistor, forming a data write transistor, forming a compensation transistor, forming one or more reset transistors, and forming a storage capacitor. Optionally, the method also includes: forming a light shielding layer. Optionally, the positive projection of the light shielding layer on the substrate substrate at least partially overlaps with the positive projection of the active layer of each of the drive transistor, the data write transistor, the compensation transistor and the one or more reset transistors on the substrate substrate.

[0207] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. An array substrate comprising a plurality of pixel driving circuits; in, Each pixel driving circuit of the plurality of pixel driving circuits includes a driving transistor, a data writing transistor, a compensation transistor, one or more reset transistors and a storage capacitor; Wherein, the array substrate further includes a light shielding layer; The orthographic projection of the light shielding layer on the base substrate at least partially overlaps with the orthographic projection of the active layer of each of the driving transistor, the data writing transistor, the compensation transistor and the one or more reset transistors on the base substrate.

2. The array substrate according to claim 1, wherein: An orthographic projection of the light shielding layer on the base substrate covers the orthographic projection of the active layer of each of the driving transistor, the data writing transistor, the compensation transistor, and the one or more reset transistors on the base substrate.

3. The array substrate according to claim 1, wherein: The light-shielding layer includes a plurality of first light-shielding lines; The orthographic projection of each first shading light line among the plurality of first shading light lines on the base substrate covers the orthographic projection of the active layer of the one or more reset transistors on the base substrate.

4. The array substrate according to claim 3, wherein: The orthographic projection of the first shielding light line corresponding to the current row of the plurality of first shielding light lines on the substrate covers the orthographic projection of the active layer of the first reset transistor in the pixel driving circuit of the current row and the active layer of the second reset transistor in the pixel driving circuit of the previous adjacent row on the substrate; as well as The orthographic projection of the corresponding first shading line of the next adjacent row of the multiple first shading line on the substrate covers the orthographic projection of the active layer of the second reset transistor in the pixel driving circuit of the current row and the active layer of the first reset transistor in the pixel driving circuit of the next adjacent row on the substrate.

5. The array substrate according to claim 3, further comprising a plurality of reset control signal lines; in, An orthographic projection of each of the first light-shielding lines on the base substrate at least partially overlaps with an orthographic projection of a corresponding reset control signal line among the plurality of reset control signal lines on the base substrate.

6. The array substrate according to any one of claims 1 to 5, wherein: The light-shielding layer further includes a plurality of second light-shielding lines; The orthographic projection of each second shading light line of the plurality of second shading light lines on the base substrate covers the orthographic projections of the active layer of the data writing transistor and the active layer of the compensation transistor on the base substrate.

7. The array substrate according to claim 6, further comprising a plurality of gate lines; in, An orthographic projection of each second shading light line on the base substrate at least partially overlaps with an orthographic projection of a corresponding gate line among the plurality of gate lines on the base substrate.

8. The array substrate according to claim 1, wherein: The light-shielding layer includes a plurality of first light-shielding lines and a plurality of second light-shielding lines; The second shading light lines corresponding to a current row of the plurality of second shading light lines and the first shading light lines corresponding to a next adjacent row of the plurality of first shading light lines are connected to each other in a peripheral area, thereby forming a ring structure.

9. The array substrate according to claim 1, wherein: The light-shielding layer includes a plurality of first light-shielding lines and a plurality of second light-shielding lines; The plurality of first light-shielding lines and the plurality of second light-shielding lines are connected to a gate scanning circuit, which is located in a peripheral area and configured to provide a gate scanning signal.

10. The array substrate according to claim 1, wherein: The light shielding layer includes a plurality of islands; The orthographic projection of each of the plurality of islands on the substrate at least partially overlaps with the orthographic projection of the first capacitor electrode of the storage capacitor on the substrate.

11. The array substrate according to claim 10, further comprising a plurality of voltage supply lines; in, The light shielding layer further includes a plurality of extension portions; wherein the plurality of islands are separated from each other; Each extension of the plurality of extensions extends away from a corresponding island of the plurality of islands; and The respective extending portions are connected to corresponding voltage supply lines among the plurality of voltage supply lines.

12. The array substrate according to claim 10, wherein: The light shielding layer further includes a plurality of bridges; Wherein, adjacent islands among the plurality of islands are connected by corresponding bridges among the plurality of bridges.

13. The array substrate according to claim 12, further comprising a plurality of voltage supply lines; in, The light shielding layer further includes an extension portion extending away from one of the plurality of islands; The extending portion is connected to one voltage supply line among the plurality of voltage supply lines.

14. The array substrate according to claim 12, comprising a display area and a peripheral area; in, The light shielding layer includes a plurality of third light shielding lines located in the display area, a peripheral light shielding signal line located in the peripheral area, and a plurality of peripheral connection lines located in the peripheral area; Each of the plurality of third shading light lines includes a portion of the plurality of islands and a portion of the plurality of bridges; as well as Each of the plurality of peripheral connection lines connects a corresponding third light-shielding line and the peripheral light-shielding signal line.

15. The array substrate according to claim 1, wherein: The light shielding layer is an overall structure of an interconnected light shielding network extending throughout a plurality of sub-pixels; The overall structure includes a plurality of first islands, a plurality of second islands, a plurality of first bridges, a plurality of second bridges, a plurality of third bridges and a plurality of branches.

16. The array substrate according to claim 15, wherein: The interconnected shading network includes multiple rows of islands; Each row of islands in the plurality of rows of islands comprises a plurality of first islands in the plurality of first islands arranged along a direction substantially parallel to a first direction and a plurality of second islands in the plurality of second islands arranged along a direction substantially parallel to the first direction; Each first bridge of the plurality of first bridges connects together a first island of the plurality of first islands and a second island of the plurality of second islands in two adjacent rows; Each second bridge of the plurality of second bridges connects together a first island of the plurality of first islands and a second island of the plurality of second islands in the same row; Each of the plurality of third bridges connects two adjacent first islands of the plurality of first islands in the same row; and Each branch of the plurality of branches extends away from a corresponding first island of the plurality of first islands.

17. The array substrate according to claim 16, wherein: The orthographic projection of the corresponding first island on the substrate covers the orthographic projection of the active layer of the driving transistor on the substrate; The orthographic projection of each second island of the plurality of second islands on the substrate covers the orthographic projection of the active layer of the compensation transistor on the substrate; The orthographic projection of each branch on the substrate covers the orthographic projection of the active layer of the data writing transistor on the substrate; as well as The orthographic projections of the first bridges on the substrate cover the orthographic projections of the active layer of the first reset transistor and the active layer of the second reset transistor on the substrate.

18. The array substrate according to claim 15, comprising a display area and a peripheral area; in, In the peripheral region, the light shielding layer further includes a peripheral light shielding signal line and a plurality of peripheral connecting lines connecting the overall structure located in the display region and the peripheral light shielding signal line located in the peripheral region; wherein the interconnected shading network comprises a plurality of rows of islands; Each row of the plurality of rows of islands includes a plurality of first islands among the plurality of first islands arranged along a direction substantially parallel to a first direction and a plurality of second islands among the plurality of second islands arranged along a direction substantially parallel to the first direction; and Each of the plurality of peripheral connection lines connects a corresponding row of the plurality of rows of islands and the peripheral light shielding signal line.

19. The array substrate according to any one of claims 1 to 18, comprising K reset signal lines, wherein the K reset signal lines are respectively configured to provide reset signals to reset transistors in K columns of pixel driving circuits of the array substrate; in, The K reset signal lines include: a plurality of third reset signal lines located in the (2k-1)th column among K columns, K and k are positive integers, 1≤k≤(K / 2); and a plurality of fourth reset signal lines located in the (2k)th column among the K columns; The third reset signal lines and the fourth reset signal lines have different line patterns.

20. An array substrate comprising a plurality of pixel driving circuits; in, Each pixel driving circuit of the plurality of pixel driving circuits includes a driving transistor, a data writing transistor, a compensation transistor, one or more reset transistors and a storage capacitor; Wherein, the array substrate further includes a light shielding layer; Wherein, an orthographic projection of the first part of the light shielding layer on the base substrate at least partially overlaps with an orthographic projection of the active layer of the driving transistor on the base substrate; An orthographic projection of the second portion of the light shielding layer on the base substrate at least partially overlaps with an orthographic projection of an active layer of at least one of the data writing transistor, the compensation transistor, and the one or more reset transistors on the base substrate; and The first portion and the second portion are configured to be provided with different signals.

21. The array substrate according to claim 20, wherein: The first portion is configured to be provided with a constant voltage signal, and the second portion is configured to be provided with a pulse signal.

22. The array substrate according to claim 20, wherein: The first portion is configured to be supplied with a voltage supply signal, and the second portion is configured to be supplied with a gate scan signal.

23. The array substrate according to claim 20, wherein: The first portion includes a plurality of third shading light lines; The second portion includes a plurality of first shading light lines and a plurality of second shading light lines; The plurality of first light-shielding lines and the plurality of second light-shielding lines are connected to a gate scanning circuit configured to provide a gate scanning signal; as well as The plurality of third light-shielding lines are connected to a signal line configured to provide a voltage supply signal.

24. The array substrate according to claim 23, further comprising a plurality of voltage supply lines located in a display area of ​​the array substrate; in, One of the plurality of voltage supply lines is connected to an extension of a corresponding third light-shielding line among the plurality of third light-shielding lines through a via hole; and The plurality of third light-shielding lines are connected to a same voltage supply line among the plurality of voltage supply lines.

25. The array substrate according to claim 23, wherein: The light-shielding layer further includes a peripheral light-shielding signal line located in a peripheral area of ​​the array substrate, and a plurality of peripheral connecting lines connecting the plurality of third light-shielding lines located in a display area of ​​the array substrate and the peripheral light-shielding signal line located in the peripheral area.

26. The array substrate according to claim 23, further comprising a plurality of voltage supply lines located in a display area of ​​the array substrate; in, One of the plurality of voltage supply lines is connected to an extension of a corresponding third light-shielding line among the plurality of third light-shielding lines through a via hole; the plurality of third light-shielding lines being connected to the same voltage supply line among the plurality of voltage supply lines; as well as The light-shielding layer further includes a peripheral light-shielding signal line located in a peripheral area of ​​the array substrate, and a plurality of peripheral connecting lines connecting the plurality of third light-shielding lines located in a display area of ​​the array substrate and the peripheral light-shielding signal line located in the peripheral area.

27. The array substrate according to claim 20, wherein: The first portion includes a plurality of islands separated from each other, and a plurality of extensions; The second portion includes a plurality of first shading light lines and a plurality of second shading light lines; Each extension of the plurality of extensions extends away from a corresponding island of the plurality of islands; Wherein, the array substrate further comprises a plurality of voltage supply lines located in the display area of ​​the array substrate; and Each of the plurality of voltage supply lines is connected to a corresponding extension portion through a via.

28. A display device comprising the array substrate according to any one of claims 1 to 27 and one or more integrated circuits connected to the array substrate.

Images