Micro-mechanical ultrasonic transducer capable of being arrayed on large scale and preparation method of micro-mechanical ultrasonic transducer

Abstract

The invention discloses a micromechanical ultrasonic transducer capable of being arrayed on a large scale and a preparation method of the micromechanical ultrasonic transducer. According to the device, an SOI wafer with a highly-doped substrate and a low resistance value is adopted, a dip angle groove is formed by etching a device silicon layer and a buried oxide layer of the SOI wafer, then an insulating layer is deposited on the upper surface of the SOI wafer, an electrode layer and a piezoelectric layer are sputtered and subjected to photoetching patterning, and then the electrode layer and the SOI wafer substrate are connected through metal evaporation of the dip angle groove, so that the device is formed. An inclined angle groove is formed in the wafer substrate, an annular insulation groove is formed in the wafer substrate below the inclined angle groove through a deep silicon etching technology and a vacuum filling technology, an all-silicon conductive supporting column is formed, an interconnection metal layer is deposited at the lower end of the all-silicon conductive supporting column, and finally a vibration cavity of the transduction unit is manufactured through deep silicon etching of the SOI wafer substrate.

Description

Technical Field

[0001] The present application relates to the technical field of ultrasonic transducers, and in particular to a micromechanical ultrasonic transducer device capable of large-scale array and a preparation method thereof. Background Art

[0002] High-density, large-array array transducers are key devices for ultrasonic 3D high-resolution imaging. Compared with conventional thick-film piezoelectric transducers, micromachined ultrasonic transducers (MUT) manufactured based on MEMS technology have the outstanding advantages of good array element consistency and high array integration, and are easy to achieve large-scale array transduction. However, since each array element in the array needs to independently excite ultrasound and receive echoes, their lead design and parasitic interference have become technical problems that restrict the scale of MUT device arrays.

[0003] At present, domestic and foreign scholars mostly adopt array structures with surface leads and fan-out on all sides when preparing MUT devices. Due to the limitation of lead space, the array size of these devices is often limited to dozens of array elements, such as the common 8×8 array structure. In addition, even if a larger MUT array is prepared, in order to enhance the ultrasonic signal or facilitate lead packaging, multiple MUT units have to be interconnected in parallel as an array element, so the actual array size is also extremely limited. Recently, STMicroelectronics International's patent CN118663539A disclosed an array architecture of piezoelectric micromechanical ultrasonic transducers PMUT for ultrasonic imaging, which uses substrate through-holes, structural epitaxy and sacrificial layer processes to prepare high-density PMUTs arrays, but the process is complex, the reliability is low, and it is not suitable for mass production. Summary of the invention

[0004] In view of this, the object of the present invention is to provide a micromechanical ultrasonic transducer device that can be arrayed on a large scale and a preparation method thereof. The device of the present invention uses a highly doped substrate and low resistance SOI wafer, forms an angled groove by etching the device silicon layer and buried oxide layer of the SOI wafer, then deposits an insulating layer on the upper surface of the SOI wafer, sputters an electrode layer and a piezoelectric layer and patterns the two by photolithography, then connects the electrode layer and the SOI wafer substrate by metal evaporation angled grooves, and then uses deep silicon etching process and vacuum filling process to manufacture an annular insulating groove on the wafer substrate below the angled groove to form an all-silicon conductive pillar, and deposits an interconnecting metal layer at the lower end of the all-silicon conductive pillar, and finally manufactures the vibration cavity of the PMUT transducer unit by deep silicon etching of the SOI wafer substrate.

[0005] The present invention provides a micro-mechanical ultrasonic transducer device capable of large-scale array, characterized in that the ultrasonic transducer device comprises a plurality of array elements and common electrode via leads, wherein the plurality of array elements and the common electrode via leads form an array structure; the ultrasonic transducer device comprises a surface passivation layer, a wafer substrate and a wafer back oxide layer;

[0006] The array element is composed of a transducer unit and signal electrode via leads;

[0007] The signal electrode via leads and the common electrode via leads are, from top to bottom, a surface passivation layer, an upper interconnection metal layer, an all-silicon conductive pillar, a lower interconnection metal layer, and an annular insulating groove that passes through the wafer substrate. The annular insulating groove electrically isolates the all-silicon conductive pillar from the wafer substrate.

[0008] Furthermore, the ultrasonic transducer device also includes a metal interconnect bump below the interconnect metal layer at the lower ends of the signal electrode via leads and the common electrode via leads, and the metal interconnect bump is electrically connected to the package carrier and supports and fixes the ultrasonic transducer device.

[0009] Furthermore, the metal interconnect bumps are spherical or columnar.

[0010] Furthermore, the package substrate is replaced with an IC device.

[0011] Furthermore, the array structure is a rectangular arrangement, a honeycomb arrangement or a parallel combination arrangement of multiple array elements.

[0012] In addition, the present invention provides a piezoelectric micromechanical ultrasonic transducer device using the above-mentioned large-scale arrayable micromechanical ultrasonic transducer device.

[0013] In addition, the present invention provides a capacitive micromechanical ultrasonic transducer device using the above-mentioned large-scale arrayable micromechanical ultrasonic transducer device.

[0014] The present invention provides a method for preparing a piezoelectric micromechanical ultrasonic transducer device that can be arrayed on a large scale, characterized in that it comprises the following steps:

[0015] ① Cleaning SOI wafers, which include wafer substrates with high doping and low resistance, wafer back oxide layers, wafer buried oxide layers, and wafer device silicon layers;

[0016] ② After photolithography masking, wet etching is performed on the wafer device silicon layer and the wafer buried oxide layer to expose the wafer substrate underneath, forming an inclined groove for manufacturing common electrode via leads and signal electrode via leads;

[0017] ③ Depositing an insulating layer on the wafer surface of the angled groove, and etching to form an insulating layer opening at the positions of the common electrode via lead and the signal electrode via lead, wherein the opening size of the insulating layer opening is smaller than the bottom size of the angled groove;

[0018] ④ Sputtering and depositing a common electrode metal layer, and etching at the positions of the common electrode via leads and the signal electrode via leads to form an electrical connection area and an electrical isolation area;

[0019] ⑤ Simultaneously sputtering and depositing the piezoelectric layer and the signal electrode metal layer, and etching at the positions of the common electrode via leads and the signal electrode via leads to form an electrical connection area and an electrical isolation area;

[0020] ⑥ Deposition to form the upper interconnection metal layer of the signal electrode via lead and the common electrode via lead, and use the evaporation process and stripping process of the photolithography mask to manufacture the upper interconnection metal layer;

[0021] ⑦Depositing a surface passivation layer on the upper surface of the wafer;

[0022] ⑧ Using the wafer buried oxide layer as the stop layer, a ring groove is manufactured on the back of the wafer substrate through a deep silicon etching process, and the ring groove is filled with an insulating polymer to form a ring-shaped insulating groove for electrical isolation between the all-silicon conductive pillar and the wafer substrate. Finally, the excess insulating polymer on the wafer substrate is removed by a chemical mechanical polishing process;

[0023] ⑨ Etching the wafer back oxide layer below the signal electrode via lead and the common electrode via lead, and forming an interconnect metal layer at the lower end of the signal electrode via lead and the common electrode via lead by metal deposition;

[0024] ⑩ The substrate cavity of the device transducer unit is manufactured on the back of the wafer substrate through a deep silicon etching process.

[0025] Furthermore, the common electrode metal layer can be used as a seed layer deposited in advance, so as to prepare a common electrode metal layer, a device piezoelectric layer, and a device signal electrode metal layer with high-quality crystal phase in a subsequent process.

[0026] Furthermore, the electrical connection area is a common electrode metal layer that can cover the insulating sidewall on the inclined groove.

[0027] Further, step ⑧ adopts the following steps:

[0028] ⑧-A: Thinning and polishing the wafer substrate, and removing the oxide layer on the back of the wafer;

[0029] ⑧-B: Using the wafer buried oxide layer as a stop layer, a ring groove is manufactured on the back of the wafer substrate by a deep silicon etching process, and the ring groove is filled with an insulating polymer and then polished by chemical mechanical grinding to form a ring-shaped insulating groove with a flat bottom surface;

[0030] ⑧-C: By spin coating and photolithography of insulating polymer, a bottom polymer insulating layer is formed, and the insulating layer at the bottom of the signal electrode via lead and the common electrode via lead is opened.

[0031] Beneficial effects of the present invention:

[0032] 1. Using a highly doped and low-resistance SOI wafer, the substrate is insulated by a ring groove to prepare an all-silicon conductive pillar, which greatly simplifies the conventional all-metal through-silicon via (TSV) process, and can overcome the depth limitation of the conventional TSV process, and can manufacture through-conductive pillars on thicker substrates. Conventional TSVs cannot manufacture deeper through-silicon vias (TSVs) on substrates due to the need for sidewall insulation, micro-hole electroplating and other processes, and micro-mechanical ultrasonic transducer devices require a very thick substrate as a support structure for film vibration, so it is difficult for conventional TSV processes to achieve vertical leads for electrode signals in these devices; 2. The present invention uses a process for preparing all-silicon conductive pillars using a highly doped and low-resistance SOI wafer on the substrate, which is compatible with the preparation process of micro-mechanical ultrasonic transducer devices, and the two can realize a high-density integrated array structure based on a single SOI wafer. 3. The present invention first wet-etches the device silicon layer and the buried oxide layer on the SOI wafer to form an angled groove, and then deposits and prepares the upper interconnection metal layer, which greatly improves the electrical reliability of the micro-mechanical ultrasonic transducer device. Since the device silicon layer of the SOI wafer is the main vibrating film of the micromechanical ultrasonic transducer and has a large thickness, if a vertical groove is formed directly on the conductive pillar by dry etching, there will be process reliability problems of electrical conduction at the sidewall and the right angle when the insulating layer and the metal layer are subsequently deposited on the sidewall. 4. The preparation process of the all-silicon conductive pillar of the present invention can vertically interconnect the electrode signal of the micromechanical ultrasonic transducer device with the packaging carrier (or IC device), which shortens the signal path, improves the signal quality, and is conducive to high-density array integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of the structure of a micromechanical ultrasonic transducer array that can be arrayed on a large scale according to an embodiment of the present invention.

[0034] Figure 2 AA cross-sectional view of the micromechanical ultrasonic transducer device array structure that can be arrayed on a large scale according to an embodiment of the present invention,

[0035] Figure 3 The schematic diagram of the process flow of preparing a piezoelectric micromechanical ultrasonic transducer device capable of large-scale array according to an embodiment of the present invention is as follows:

[0036] Figure 4 FIG. 8 is another process flow diagram of step ⑧ of the process for preparing a piezoelectric micromechanical ultrasonic transducer device capable of large-scale array according to an embodiment of the present invention.

[0037] Figure 5 A schematic diagram of a large-scale array integration of micromechanical ultrasonic transducer devices that can be arrayed in a large scale according to an embodiment of the present invention.

[0038] In the figure, Q0: array structure, Q1: array element; Q2: common electrode via lead, Q1a: transducer unit, Q1b: signal electrode via lead, 109: upper interconnection metal layer, 112: lower interconnection metal layer, 101a: all-silicon conductive pillar, 111: annular insulating groove, 101: wafer substrate, 102: wafer back oxide layer, 103: wafer buried oxide layer, 104: wafer device silicon layer, 105: insulating layer, 106: common electrode metal layer, 107: piezoelectric layer, 108: signal electrode metal layer, 113: substrate cavity, Q3: metal interconnection bump, Q4: package carrier. DETAILED DESCRIPTION

[0039] Example 1

[0040] The present invention will be described below in conjunction with the accompanying drawings. Figure 1 Schematic diagram of the structure of a micromechanical ultrasonic transducer array that can be arrayed on a large scale according to an embodiment of the present invention. Figure 2 It is an AA cross-sectional view of the micromechanical ultrasonic transducer device array structure that can be arrayed on a large scale according to an embodiment of the present invention.

[0041] The present invention provides a micro-mechanical ultrasonic transducer device capable of large-scale array, characterized in that the ultrasonic transducer device comprises a plurality of array elements Q1 and a common electrode via lead Q2, wherein the plurality of array elements Q1 and the common electrode via lead Q2 form an array structure Q0; the ultrasonic transducer device comprises a surface passivation layer 110, a wafer substrate 101 and a wafer back oxide layer 102;

[0042] The array element Q1 is composed of a transducer unit Q1a and a signal electrode via lead Q1b;

[0043] The signal electrode via lead Q1b and the common electrode via lead Q2 are, from top to bottom, a surface passivation layer 110, an upper interconnection metal layer 109, an all-silicon conductive pillar 101a, a lower interconnection metal layer 112, and an annular insulating groove 111 that passes through the wafer substrate 101. The annular insulating groove 111 electrically isolates the all-silicon conductive pillar 101a from the wafer substrate 101.

[0044] Furthermore, the ultrasonic transducer device also includes a metal interconnect bump Q3 below the lower interconnect metal layer 112 of the signal electrode via lead Q1b and the common electrode via lead Q2, and the metal interconnect bump Q3 is electrically connected to the package carrier Q4 and supports and fixes the ultrasonic transducer device.

[0045] Figure 5 Schematic diagram of large-scale array integration of micromechanical ultrasonic transducer devices that can be arrayed on a large scale according to an embodiment of the present invention.

[0046] Furthermore, the metal interconnection bump Q3 is spherical or columnar.

[0047] Furthermore, the package substrate Q4 is replaced with an IC device.

[0048] Furthermore, the array structure Q0 is a rectangular arrangement, a honeycomb arrangement or a parallel combination arrangement of multiple array elements Q1.

[0049] In addition, the present invention provides a piezoelectric micromechanical ultrasonic transducer device using the above-mentioned large-scale arrayable micromechanical ultrasonic transducer device.

[0050] In addition, the present invention provides a capacitive micromechanical ultrasonic transducer device using the above-mentioned large-scale arrayable micromechanical ultrasonic transducer device.

[0051] Figure 3 The present invention provides a method for preparing a piezoelectric micromechanical ultrasonic transducer device that can be arrayed on a large scale, which is characterized by comprising the following steps:

[0052] ① Cleaning the SOI wafer, the SOI wafer includes a wafer substrate 101 with high doping and low resistance, a wafer back oxide layer 102, a wafer buried oxide layer 103, and a wafer device silicon layer 104;

[0053] ② After photolithography masking, wet etching is performed on the wafer device silicon layer 104 and the wafer buried oxide layer 103 to expose the wafer substrate 101 below, forming an inclined groove 104a for manufacturing the common electrode via lead Q2 and the signal electrode via lead Q1b;

[0054] ③ Depositing an insulating layer 105 on the wafer surface of the angled groove 104a, and etching to form an insulating layer opening 105a at the positions of the common electrode via lead Q2 and the signal electrode via lead Q1b, wherein the opening size of the insulating layer opening 105a is smaller than the bottom size of the angled groove 105a;

[0055] ④ Sputtering and depositing a common electrode metal layer 106, and etching at the positions of the common electrode via lead Q2 and the signal electrode via lead Q1b to form an electrical connection area 106a and an electrical isolation area 106b;

[0056] ⑤ At the same time, the piezoelectric layer 107 and the signal electrode metal layer 108 are sputtered and deposited, and the electrical connection area 108a and the electrical isolation area 108b are etched at the positions of the common electrode via lead Q2 and the signal electrode via lead Q1b;

[0057] ⑥ Deposition to form the upper interconnection metal layer 109 of the signal electrode via lead Q1b and the common electrode via lead Q2, the upper interconnection metal layer 109 is manufactured by using an evaporation process and a stripping process using a photolithography mask;

[0058] ⑦ Depositing a surface passivation layer 110 on the upper surface of the wafer;

[0059] ⑧ Using the wafer buried oxide layer 103 as a stop layer, a ring groove is manufactured on the back of the wafer substrate by a deep silicon etching process, and the ring groove is filled with an insulating polymer to form a ring-shaped insulating groove 111 for electrical isolation of the all-silicon conductive pillar 101a from the wafer substrate 101, and finally a chemical mechanical grinding and polishing process is used to remove excess insulating polymer on the wafer substrate 101;

[0060] ⑨ Etching the wafer back oxide layer 102 below the signal electrode via lead Q1b and the common electrode via lead Q2, and forming an interconnect metal layer 112 at the lower end of the signal electrode via lead Q1b and the common electrode via lead Q2 by metal deposition;

[0061] ⑩ A substrate cavity 113 of the device transducer unit is manufactured on the back of the wafer substrate by a deep silicon etching process.

[0062] Furthermore, the common electrode metal layer 106 can be used as a seed layer deposited in advance, so as to prepare the common electrode metal layer 106 , the device piezoelectric layer 107 , and the device signal electrode metal layer 108 with high-quality crystal phase in the subsequent process.

[0063] Furthermore, the electrical connection region 106 a is the insulating sidewall where the common electrode metal layer 106 can cover the inclined groove 104 a .

[0064] Further, step ⑧ adopts the following steps:

[0065] ⑧-A: Thinning and polishing the wafer substrate 101, and removing the oxide layer 102 on the back of the wafer;

[0066] ⑧-B: Using the wafer buried oxide layer as a stop layer, a ring groove is manufactured on the back of the wafer substrate by a deep silicon etching process, and the ring groove is filled with an insulating polymer and then chemical mechanical polishing is used to form a ring-shaped insulating groove 111 with a flat bottom surface;

[0067] ⑧-C: By spin coating and photolithography of insulating polymer, a bottom polymer insulating layer 102a, an insulating layer opening 102b at the bottom of the signal electrode via lead Q1b and the common electrode via lead Q2 are formed.

[0068] The present invention is described in detail above in combination with specific implementation methods and exemplary examples. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments; the above description cannot be understood as limiting the present invention. Those skilled in the art understand that, without departing from the spirit and scope of the present invention, the technical solution of the present invention and its implementation methods may be subjected to a variety of equivalent substitutions, modifications or improvements, all of which fall within the scope of the present invention; the protection scope of the present invention shall be subject to the attached claims.

Claims

1. A micromechanical ultrasonic transducer device capable of large-scale array, characterized in that: The ultrasonic transducer device comprises a plurality of array elements (Q1) and a common electrode via lead (Q2), wherein the plurality of array elements (Q1) and the common electrode via lead (Q2) form an array structure (Q0); the ultrasonic transducer device comprises a surface passivation layer (110), a wafer substrate (101) and a wafer back oxide layer (102); The array element (Q1) is composed of a transducer unit (Q1a) and a signal electrode via lead (Q1b); The signal electrode via lead (Q1b) and the common electrode via lead (Q2) are, from top to bottom, the surface passivation layer (110), the upper interconnection metal layer (109), the all-silicon conductive pillar (101a), the lower interconnection metal layer (112), and an annular insulating groove (111) that penetrates the wafer substrate (101), wherein the annular insulating groove (111) electrically isolates the all-silicon conductive pillar (101a) from the wafer substrate (101).

2. The micromechanical ultrasonic transducer device capable of large-scale array according to claim 1, characterized in that: The ultrasonic transducer device also includes a metal interconnect bump (Q3) below the lower interconnect metal layer (112) of the signal electrode via lead (Q1b) and the common electrode via lead (Q2), wherein the metal interconnect bump (Q3) is electrically connected to the package carrier (Q4) and supports and fixes the ultrasonic transducer device.

3. The micromechanical ultrasonic transducer device capable of large-scale array according to claim 1, characterized in that: The package substrate (Q4) is replaced with the IC device.

4. The micromechanical ultrasonic transducer device capable of large-scale array according to claim 1, characterized in that: The array structure (Q0) is a rectangular arrangement, a honeycomb arrangement or a parallel combination arrangement of multiple array elements (Q1).

5. A piezoelectric micromechanical ultrasonic transducer device using the micromechanical ultrasonic transducer device capable of large-scale array as claimed in any one of claims 1 to 4.

6. A capacitive micromechanical ultrasonic transducer device using the large-scale arrayable micromechanical ultrasonic transducer device as claimed in any one of claims 1 to 4.

7. A method for preparing a piezoelectric micromechanical ultrasonic transducer device that can be arrayed on a large scale, characterized in that: The following steps are involved: ① Cleaning an SOI wafer, wherein the SOI wafer comprises a wafer substrate (101) with high doping and low resistance, a wafer back oxide layer (102), a wafer buried oxide layer (103), and a wafer device silicon layer (104); ② After photolithography masking, wet etching is performed on the wafer device silicon layer (104) and the wafer buried oxide layer (103) to expose the wafer substrate (101) below, thereby forming an inclined groove (104a) for manufacturing a common electrode via lead (Q2) and a signal electrode via lead (Q1b); ③ depositing an insulating layer (105) on the wafer surface of the angled groove (104a), and etching to form an insulating layer opening (105a) at the positions of the common electrode via lead (Q2) and the signal electrode via lead (Q1b), wherein the opening size of the insulating layer opening (105a) is smaller than the bottom size of the angled groove (105a); ④ sputtering and depositing a common electrode metal layer (106), and etching at the positions of the common electrode via lead (Q2) and the signal electrode via lead (Q1b) to form an electrical connection area (106a) and an electrical isolation area (106b); ⑤ Simultaneously sputtering and depositing a piezoelectric layer (107) and a signal electrode metal layer (108), and etching at the positions of the common electrode via lead (Q2) and the signal electrode via lead (Q1b) to form an electrical connection area (108a) and an electrical isolation area (108b); ⑥ depositing an upper interconnection metal layer (109) to form a signal electrode via lead (Q1b) and a common electrode via lead (Q2), and manufacturing the upper interconnection metal layer (109) by using an evaporation process and a stripping process using a photolithography mask; 7. Depositing a surface passivation layer (110) on the upper surface of the wafer; ⑧ Using the wafer buried oxide layer (103) as a stop layer, a ring groove is manufactured on the back of the wafer substrate by a deep silicon etching process, and the ring groove is filled with an insulating polymer to form a ring-shaped insulating groove (111) for electrical isolation of the all-silicon conductive pillar (101a) and the wafer substrate (101), and finally a chemical mechanical grinding and polishing process is used to remove excess insulating polymer on the wafer substrate (101); ⑨ Etching the wafer back oxide layer (102) below the signal electrode via lead (Q1b) and the common electrode via lead (Q2), and forming an interconnecting metal layer (112) at the lower end of the signal electrode via lead (Q1b) and the common electrode via lead (Q2) by metal deposition; ⑩ A substrate cavity (113) of the device transducer unit is manufactured on the back of the wafer substrate by a deep silicon etching process.

8. The method for preparing a large-scale arrayable piezoelectric micromechanical ultrasonic transducer device according to claim 7, characterized in that: The common electrode metal layer (106) can be used to deposit a seed layer in advance, and is used in a subsequent process to prepare a common electrode metal layer (106), a device piezoelectric layer (107), and a device signal electrode metal layer (108) with a high-quality crystal phase.

9. The method for preparing a large-scale array piezoelectric micromechanical ultrasonic transducer device according to claim 7, characterized in that: The electrical connection area (106a) is an insulating sidewall where the common electrode metal layer (106) can cover the inclined groove (104a).

10. The method for preparing a large-scale array piezoelectric micromechanical ultrasonic transducer device according to claim 7, characterized in that: Step ⑧ adopts the following steps: ⑧-A: Thinning and polishing the wafer substrate (101), and removing the oxide layer (102) on the back of the wafer; ⑧-B: using the wafer buried oxide layer as a stop layer, manufacturing an annular groove on the back of the wafer substrate by a deep silicon etching process, and filling the annular groove with an insulating polymer and then using chemical mechanical polishing to form an annular insulating groove (111) with a flat bottom surface; ⑧-C: By spin coating and photolithography of insulating polymer, a bottom polymer insulating layer (102a) is formed, and insulating layer openings (102b) are formed at the bottom of the signal electrode via lead (Q1b) and the common electrode via lead (Q2).

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