Voltage Regulator

Abstract

The present invention provides a voltage regulator, which can suppress the excessive voltage generated at the output terminal when a ground fault occurs at a voltage adjustment terminal. The voltage regulator (100) includes: an output transistor (14) that outputs an output voltage (VOUT) to an output terminal (3); a split resistor (12, 13) that divides an adjustment voltage (VADJ) input to a voltage adjustment terminal (4) to output a feedback voltage (Vfb); a first reference voltage circuit (11) that outputs a first reference voltage (Vref); an error amplifier circuit (10) that controls the gate voltage of the output transistor (14) based on the first reference voltage (Vref) and the feedback voltage (Vfb); and a ground fault protection circuit (20) that, when monitoring the adjustment voltage (VADJ) and detecting a ground fault at the voltage adjustment terminal (4), increases the feedback voltage (Vfb) to the first reference voltage (Vref).

Description

Technical Field

[0001] The invention relates to a voltage regulator. Background Art

[0002] Generally speaking, a voltage regulator generates a certain voltage from a power supply voltage input to an input terminal, outputs a certain voltage to an output terminal, and maintains the output voltage at a certain value even if the power supply voltage or load current changes. In addition, the voltage regulator includes an overcurrent protection circuit that controls the output transistor to be turned off when an excessive current flows through the output terminal, such as when a ground fault occurs at the output terminal (for example, refer to Patent Document 1).

[0003] [Prior art literature]

[0004] [Patent Document]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2009-169503 Summary of the invention

[0006] [Problems to be solved by the invention]

[0007] However, in the case of including a voltage adjustment terminal for adjusting the output voltage separately from the output terminal, it is difficult in the overcurrent protection circuit of the conventional voltage regulator to suppress the generation of an excessive voltage at the output terminal when a split resistor connected to the voltage adjustment terminal suffers a ground fault.

[0008] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a voltage regulator capable of suppressing an excessive voltage from being generated at an output terminal when a ground fault occurs at a voltage adjustment terminal.

[0009] [Technical means to solve the problem]

[0010] The voltage regulator of the embodiment of the present invention is characterized by including: an output transistor that outputs an output voltage to an output terminal; a dividing resistor that divides an adjustment voltage input to a voltage adjustment terminal and outputs a feedback voltage; a first reference voltage circuit that outputs a first reference voltage; an error amplifier circuit that controls a gate voltage of the output transistor based on the first reference voltage and the feedback voltage; and a ground fault protection circuit that, when monitoring the adjustment voltage and detecting a ground fault at the voltage adjustment terminal, increases the feedback voltage to the first reference voltage.

[0011] [Effects of the Invention]

[0012] According to the present invention, a voltage regulator can be provided, which includes a ground fault protection circuit that increases a feedback voltage to a first reference voltage when a ground fault occurs at a voltage adjustment terminal and a regulation voltage is monitored. Therefore, when a ground fault occurs at the voltage adjustment terminal, an excessive voltage generated at an output terminal can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a circuit diagram showing an example of a voltage regulator according to an embodiment of the present invention.

[0014] Figure 2 : is a circuit diagram showing an example of the ground fault protection circuit according to the present embodiment.

[0015] Figure 3 : is a circuit diagram showing another example of the ground fault protection circuit according to the present embodiment.

[0016] Figure 4 : is a circuit diagram showing still another example of the ground fault protection circuit according to the present embodiment.

[0017] Figure 5 : is a circuit diagram showing still another example of the ground fault protection circuit according to the present embodiment.

[0018] [Explanation of Symbols]

[0019] 1: Input terminal

[0020] 2: Ground terminal

[0021] 3: Output terminal

[0022] 4: Voltage adjustment terminal

[0023] 10: Error amplifier circuit

[0024] 11, 23: Reference voltage circuit

[0025] 12, 13: Resistors (division resistors)

[0026] 14: Output transistor

[0027] 20: Ground fault protection circuit

[0028] 21: Comparison circuit

[0029] 22: PMOS transistor

[0030] 24: Diode (anti-reverse current element)

[0031] 25: Constant current source (pull-up element)

[0032] 100: Voltage Regulator DETAILED DESCRIPTION

[0033] Hereinafter, a voltage regulator according to an embodiment of the present invention will be described with reference to the drawings.

[0034] Figure 1 1 is a circuit diagram of a voltage regulator 100 as an example of a voltage regulator according to an embodiment of the present invention.

[0035] The voltage regulator 100 includes an input terminal 1 , a ground terminal 2 , an output terminal 3 , a voltage adjustment terminal 4 , an error amplifier circuit 10 , a reference voltage circuit 11 , resistors 12 and 13 as dividing resistors, an output transistor 14 , and a ground fault protection circuit 20 .

[0036] The ground fault protection circuit 20 includes a comparison circuit 21 , a P-channel metal oxide semiconductor (PMOS) transistor 22 , and a reference voltage circuit 23 .

[0037] The source of the output transistor 14 is connected to the input terminal 1, the drain is connected to the output terminal 3, and the gate is connected to the output terminal of the error amplifier circuit 10. The inverting input terminal - of the error amplifier circuit 10 is connected to the output terminal of the reference voltage circuit 11, and the non-inverting input terminal + is connected to the connection point of the resistor 12 and the resistor 13. The resistor 12 and the resistor 13 are connected in series between the voltage adjustment terminal 4 and the ground terminal 2.

[0038] The ground fault protection circuit 20 is connected as follows.

[0039] The power supply terminal of the comparison circuit 21 is connected to the output terminal 3, the non-inverting input terminal + is connected to the voltage adjustment terminal 4, the inverting input terminal - is connected to the output terminal of the reference voltage circuit 23, and the output terminal is connected to the gate of the PMOS transistor 22. The source of the PMOS transistor 22 is connected to the output terminal 3, and the drain is connected to the non-inverting input terminal + of the error amplifier circuit 10.

[0040] The voltage adjustment terminal 4 is connected to a connection point of the resistor Ra and the resistor Rb as a division resistor. That is, the voltage regulator 100 can arbitrarily adjust the output voltage VOUT by the external resistor Ra and the external resistor Rb. The load LD is connected to the output terminal 3 .

[0041] The operation of the voltage regulator 100 will be described.

[0042] The voltage regulator 100 generates a constant voltage based on the voltage VIN input to the input terminal 1, and outputs it as an output voltage VOUT from the output terminal 3. The resistors 12 and 13 generate a feedback voltage Vfb based on the adjustment voltage VADJ input from the voltage adjustment terminal 4. The error amplifier circuit 10 controls the gate voltage of the output transistor 14 based on the reference voltage Vref output by the reference voltage circuit 11 and the feedback voltage Vfb. That is, the output voltage VOUT of the voltage regulator 100 is controlled to a voltage in which the feedback voltage Vfb is equal to the reference voltage Vref.

[0043] When a ground fault occurs at the voltage adjustment terminal 4 for some reason, the adjustment voltage VADJ, that is, the feedback voltage Vfb drops to the voltage of the ground terminal 2. The error amplifier circuit 10 reduces the output voltage when the feedback voltage Vfb decreases and becomes lower than the reference voltage Vref. Therefore, since the gate voltage of the output transistor 14 decreases, the output voltage VOUT of the voltage regulator 100 is higher than the desired voltage. At this time, since the resistor Ra is connected to the output terminal 3, the overcurrent does not flow through the output terminal 3. That is, even if an overcurrent protection circuit is included, the rise of the output voltage VOUT cannot be suppressed.

[0044] Next, the operation of the ground fault protection circuit 20 when a ground fault occurs in the voltage adjustment terminal 4 will be described.

[0045] When a ground fault occurs at the voltage adjustment terminal 4, the adjustment voltage VADJ and the feedback voltage Vfb drop to the voltage of the ground terminal 2. The error amplifier circuit 10 controls the gate voltage of the output transistor 14 to decrease and the output voltage VOUT to increase.

[0046] When the adjustment voltage VADJ input to the non-inverting input terminal + is lower than the reference voltage V1 of the reference voltage circuit 23 input to the inverting input terminal -, the voltage of the output terminal of the comparison circuit 21 decreases. The PMOS transistor 22 is turned on due to the decrease in gate voltage. Since the source of the PMOS transistor 22 is connected to the output terminal 3, the feedback voltage Vfb increases.

[0047] Therefore, when the feedback voltage Vfb input to the non-inverting input terminal + increases and becomes higher than the reference voltage Vref input to the inverting input terminal −, the error amplifier circuit 10 is controlled to increase the gate voltage of the output transistor 14 and reduce the output voltage VOUT.

[0048] At this time, the feedback voltage Vfb is generated by the current of the PMOS transistor 22 flowing through the resistors 12 and 13 connected in parallel. Therefore, the output voltage VOUT is stabilized at a voltage that is equal to the reference voltage Vref and lower than the desired voltage. In this way, when a ground fault occurs at the voltage adjustment terminal 4, the ground fault protection circuit 20 suppresses the output voltage VOUT from exceeding the desired voltage.

[0049] In addition, the ground fault protection circuit 20 does not hinder the operation of the voltage regulator 100 during normal operation.

[0050] First, before the voltage regulator 100 is started, the output voltage VOUT and the adjustment voltage VADJ are both low voltages. Since the source of the PMOS transistor 22 is the output voltage VOUT, it will not be turned on.

[0051] Next, when the voltage regulator 100 is activated, the adjustment voltage VADJ also rises with the rise of the output voltage VOUT, and therefore the PMOS transistor 22 is turned off.

[0052] Figure 2 2 is a circuit diagram showing an example of the ground fault protection circuit 20 according to the present embodiment.

[0053] Figure 2 In the ground fault protection circuit 20, the comparison circuit 21 is set as a comparator including two PMOS transistors, two N-channel metal oxide semiconductor (NMOS) transistors and a current source. Since the reference voltage V1 for detecting the ground fault of the voltage adjustment terminal 4 is set to a low voltage, the two NMOS transistors are preferably depletion-type. In the ground fault protection circuit 20, the comparator controls the on / off of the PMOS transistor 22, that is, performs a switching action.

[0054] Figure 3 2 is a circuit diagram showing another example of the ground fault protection circuit 20 according to the present embodiment.

[0055] Figure 3 In the ground fault protection circuit 20, a PMOS transistor and two NMOS transistors constitute a comparison circuit 21a, and a constant current source and a resistor constitute a reference voltage circuit 23a. The reference voltage circuit 23a generates a reference voltage V1 at the resistor. The PMOS transistor of the comparison circuit 21a and the PMOS transistor 22 constitute a current mirror circuit. Therefore, when the PMOS transistor 22 is turned on, a current corresponding to the current of the PMOS transistor flows, so that the feedback voltage Vfb increases.

[0056] Figure 42 is a circuit diagram showing still another example of the ground fault protection circuit 20 according to the present embodiment.

[0057] Figure 4 The ground fault protection circuit 20 in Figure 3 In the ground fault protection circuit 20, a diode 24 as a backflow prevention element is provided at the drain of the PMOS transistor 22. The anode of the diode 24 is connected to the drain of the PMOS transistor 22, and the cathode is connected to the non-inverting input terminal + of the error amplifier circuit 10.

[0058] The diode 24 is effective in preventing a current from flowing from a connection point between the resistor 12 and the resistor 13 to the output terminal 3 through the parasitic diode of the PMOS transistor 22 .

[0059] Figure 5 2 is a circuit diagram showing still another example of the ground fault protection circuit 20 according to the present embodiment.

[0060] Figure 5 The ground fault protection circuit 20 in Figure 3 In the ground fault protection circuit 20 , a current source 25 as a pull-up element is provided between the output terminal 3 and the gate of the PMOS transistor 22 .

[0061] The current source 25 is effective in preventing the leakage current of the PMOS transistor 22 from flowing through the connection point between the resistor 12 and the resistor 13 during normal operation.

[0062] As described above, according to the voltage regulator 100 of this embodiment, the ground fault protection circuit 20 is provided at the voltage adjustment terminal 4 . Therefore, even if a ground fault occurs at the voltage adjustment terminal 4 , generation of an excessive voltage at the output terminal 3 of the voltage regulator 100 can be suppressed.

[0063] In addition, the present invention is not limited to the above-described embodiments and can be implemented in various forms. Moreover, various omissions, additions, substitutions or changes can be made without departing from the scope of the main purpose of the invention. These embodiments or their variations are included in the scope or main purpose of the invention and are included in the invention described in the claims and their equivalents.

Claims

1. A voltage regulator, characterized in that: include: an output transistor for outputting an output voltage to an output terminal; A dividing resistor divides the adjustment voltage input to the voltage adjustment terminal to output a feedback voltage; A first reference voltage circuit outputting a first reference voltage; an error amplifier circuit, controlling a gate voltage of the output transistor based on the first reference voltage and the feedback voltage; as well as The ground fault protection circuit increases the feedback voltage to the first reference voltage when monitoring the adjustment voltage and detecting that a ground fault has occurred at the voltage adjustment terminal.

2. The voltage regulator according to claim 1, characterized in that The ground fault protection circuit comprises: a comparison circuit, for comparing the adjustment voltage with a second reference voltage; and The first metal oxide semiconductor transistor has a source connected to the output terminal, a drain connected to the output terminal of the dividing resistor, and a gate connected to the output terminal of the comparison circuit.

3. The voltage regulator according to claim 2, characterized in that The comparison circuit includes a comparator.

4. The voltage regulator according to claim 1, characterized in that The ground fault protection circuit comprises: A second reference voltage circuit includes a current source and a resistor connected in series between an input terminal and a ground terminal; a comparison circuit, comprising a second metal oxide semiconductor transistor disposed between the current source and the resistor and having a drain connected to a gate; a third metal oxide semiconductor transistor having a gate connected to the gate of the second metal oxide semiconductor transistor; and a fourth metal oxide semiconductor transistor having a gate and a drain connected to the drain of the third metal oxide semiconductor transistor, and comparing the adjustment voltage with the second reference voltage; and The first metal oxide semiconductor transistor has a source connected to the output terminal, a drain connected to the output terminal of the dividing resistor, and a gate connected to the gate of the fourth metal oxide semiconductor transistor of the comparison circuit.

5. The voltage regulator according to claim 4, characterized in that The ground fault protection circuit is provided with a backflow prevention element at the drain of the first metal oxide semiconductor transistor.

6. The voltage regulator according to claim 4 or 5, characterized in that: The ground fault protection circuit is provided with a pull-up element at the gate of the first metal oxide semiconductor transistor.

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