Non-operational-amplifier voltage-stabilizing starting circuit applied to high voltage and voltage-stabilizing starting method of non-operational-amplifier voltage-stabilizing starting circuit

Abstract

The invention discloses an operational-amplifier-free voltage-stabilizing starting circuit applied to high voltage and a voltage-stabilizing starting method thereof.The operational-amplifier-free voltage-stabilizing starting circuit comprises a voltage-stabilizing circuit and a starting circuit, the starting circuit generates bias current Ibias2, a triode Q7 and a PMOS tube PDM2 in the voltage-stabilizing circuit form a first common-emitter amplifier, an NMOS tube NDM2 and a PMOS tube PDM3 form a first common-source amplifier, and the first common-source amplifier and the second common-source amplifier form a second common-source amplifier. And the PMOS tube PDM4, the triode Q6, the resistor R4 and the triode Q5 form a second common source amplifier. According to the invention, a pre-voltage-stabilizing circuit and a high-voltage operational amplifier do not need to be additionally designed, so that the chip area is saved, and after the voltage-stabilizing starting circuit is started, the starting circuit does not need to be turned off.

Description

Technical Field

[0001] The present invention relates to a voltage-stabilizing starting circuit and a voltage-stabilizing starting method thereof, in particular to a voltage-stabilizing starting circuit and a voltage-stabilizing starting method thereof without an operational amplifier applied to high voltage, and belongs to the technical field of semiconductor integrated circuits. Background Art

[0002] As an important part of the chip, the voltage regulator circuit provides a stable operating voltage for the analog circuit and digital circuit in the chip to ensure that the chip can work normally. Since some applications have both low power supply voltage and high power supply voltage, it is very important to ensure that the voltage regulator circuit can work normally under both low power supply voltage and high power supply voltage.

[0003] The block diagram of the traditional voltage stabilization circuit used for high voltage is as follows Figure 2 As shown, its working principle is that the pre-stabilization circuit steps down the external high-voltage power supply VS and provides a low-voltage power supply for the low-voltage bandgap reference circuit to ensure that the low-voltage bandgap reference circuit is not damaged by the external high-voltage power supply VS. The output VREF of the bandgap reference circuit provides a reference voltage for the negative input terminal of the high-voltage operational amplifier HV_AMP1. The positive input terminal of the high-voltage operational amplifier HV_AMP1 is connected to the output terminal of the high-voltage operational amplifier HV_AMP1 and then input to the gate terminal of the high-voltage PMOS adjustment tube PDM1. The drain terminal of the high-voltage PMOS adjustment tube PDM1 is input to the positive input terminal of the high-voltage operational amplifier HV_AMP1 through the resistor R2, forming a negative feedback loop. Through this negative feedback loop, the positive input terminal and the negative input terminal of the high-voltage operational amplifier HV_AMP1 are clamped to be equal, so the output voltage VLDO of the voltage regulator circuit is: VLDO = VREF*(R1+R2) / R2 From the above analysis, it can be seen that the traditional voltage regulator circuit used for high voltage needs to design an additional pre-voltage regulator circuit in order to provide a low-voltage power supply that can work normally for the low-voltage bandgap reference circuit. In order to achieve negative feedback clamping under high voltage, a high-voltage operational amplifier needs to be designed, which greatly increases the complexity of the design and requires a larger chip area. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a voltage-stabilizing startup circuit and a voltage-stabilizing startup method thereof for high voltage, which do not require an additional op amp and can stably generate an output voltage VLDO.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: A non-op-amp voltage-stabilizing startup circuit for high voltage comprises a voltage-stabilizing circuit and a startup circuit, wherein the startup circuit generates a bias current Ibias2, and the voltage-stabilizing circuit comprises a transistor Q2, a transistor Q3, a transistor Q4, a transistor Q5, a transistor Q6, a transistor Q7, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a PMOS transistor PDM3, a PMOS transistor PDM4, an NMOS transistor NDM2 and a Zener diode Z2, wherein the cathode of the Zener diode Z2 is connected to the collector of the transistor Q7 and the gate of the NMOS transistor NDM2 and is connected to the bias current Ibias2, the base of the transistor Q7 is connected to the collector of the transistor Q5, the base of the transistor Q5, the base of the transistor Q4 and the collector of the transistor Q3, the base of the transistor Q3 is connected to the base of the transistor Q2, the collector of the transistor Q2 and the collector of the transistor Q4, and the cathode of the Zener diode Z2 is connected to the collector of the transistor Q7 and the gate of the NMOS transistor NDM2 and is connected to the bias current Ibias2, the base of the transistor Q7 is connected to the collector of the transistor Q5, the base of the transistor Q5, the base of the transistor Q4 and the collector of the transistor Q3, the base of the transistor Q3 is connected to the base of the transistor Q2, the collector of the transistor Q2 and the collector of the transistor Q4, and the cathode of the transistor Q The emitter of transistor Q3 is connected to one end of resistor R3, the emitter of transistor Q5 is connected to one end of resistor R4 and the emitter of transistor Q4, the other end of resistor R4 is connected to the emitter of transistor Q6, the collector of transistor Q6 is connected to the drain of PMOS tube PDM4 and one end of resistor R6 and generates output voltage VLDO, the base of transistor Q6 is connected to the other end of resistor R6 and one end of resistor R5, the source of PMOS tube PDM4 and the source of PMOS tube PDM3 are connected to power supply VS, the gate of PMOS tube PDM4 is connected to the gate of PMOS tube PDM3, the drain of PMOS tube PDM3 and the drain of NMOS tube NDM2, the anode of Zener diode Z2, the emitter of transistor Q7, the source of NMOS tube NDM2, the other end of resistor R3, the emitter of transistor Q2 and the other end of resistor R5 are grounded.

[0006] Furthermore, the startup circuit includes a resistor R1, a resistor R2, a transistor Q1, an NMOS transistor NDM1, a PMOS transistor PDM1, a PMOS transistor PDM2 and a Zener diode Z1, one end of the resistor R1 is connected to the source of the PMOS transistor PDM1, the source of the PMOS transistor PDM2 and the power supply VS, the other end of the resistor R1 is connected to the collector of the transistor Q1, the cathode of the Zener diode Z1 and the gate of the NMOS transistor NDM1, the base of the transistor Q1 is connected to the source of the NMOS transistor NDM1 and one end of the resistor R2, the drain of the NMOS transistor NDM1 is connected to the drain of the PMOS tube PDM1, the gate of the PMOS tube PDM1 and the gate of the PMOS tube PDM2, the drain of the PMOS tube PDM2 outputs a bias current Ibias2, and the emitter of the transistor Q1, the anode of the Zener diode Z1 and the other end of the resistor R2 are grounded.

[0007] Furthermore, the NMOS tube NDM1 and the NMOS tube NDM2 are high-voltage NMOS tubes, and the PMOS tube PDM1, the PMOS tube PDM2, the PMOS tube PDM3 and the PMOS tube PDM4 are high-voltage PMOS tubes.

[0008] Furthermore, the transistor Q7 and the PMOS transistor PDM2 form a first common emitter amplifier, the NMOS transistor NDM2 and the PMOS transistor PDM3 form a first common source amplifier, and the PMOS transistor PDM4 and the transistor Q6, the resistor R4 and the transistor Q5 form a second common source amplifier.

[0009] Furthermore, the transistors Q4 and Q5 are PNP transistors, the transistors Q4 and Q5 form a first PNP current mirror, and the transistors Q1, Q2, Q3, Q6 and Q7 are NPN transistors.

[0010] Furthermore, the PMOS transistor PDM1 and the PMOS transistor PDM2 form a first PMOS current mirror, and the PMOS transistor PDM3 and the PMOS transistor PDM4 form a second PMOS current mirror.

[0011] Furthermore, the resistor R1, the resistor R2, the transistor Q1, the NMOS transistor NDM1, the PMOS transistor PDM1, the PMOS transistor PDM2 and the Zener diode Z1 constitute a high-voltage Wilson current source.

[0012] A voltage stabilization starting method for a high voltage op amp-free voltage stabilization starting circuit comprises the following steps: The collector of the transistor Q5 is connected to the input end of the first common emitter amplifier composed of the transistor Q7 and the PMOS tube PDM2, the output end of the first common emitter amplifier is connected to the input end of the first common source amplifier composed of the NMOS tube NDM2 and the PMOS tube PDM3, the output end of the first common source amplifier is connected to the second common source amplifier composed of the high-voltage PMOS tube PDM4, the transistor Q6, the resistor R4 and the triode Q5, the first common emitter amplifier, the first common source amplifier and the second common source amplifier form a negative feedback loop, and a stable output voltage VLDO is obtained through negative feedback compensation; The first PNP current mirror composed of transistors Q4 and Q5 makes the currents flowing through transistors Q2 and Q3 equal. Since the areas of transistors Q2 and Q3 are different, there is a voltage difference △VBE with a positive temperature coefficient between the base-emitter voltages VBE of transistors Q2 and Q3. The voltage difference △VBE with a positive temperature coefficient is divided by the resistor R3 with a zero temperature coefficient to obtain the current Ip with a positive temperature coefficient. The base voltage of transistor Q6 is equal to the base-emitter voltage VBE7 of transistor Q7 with a negative temperature coefficient plus the base-emitter voltage VBE5 of transistor Q5 with a negative temperature coefficient plus the voltage drop 2*Ip*R4 of resistor R4 plus the base-emitter voltage VBE6 of transistor Q6 with a negative temperature coefficient, that is, VBE7+VBE5+2*Ip*R4+VBE6. Then the output voltage VLDO is: VLDO=(VBE7+VBE5+2*Ip*R4+VBE6)*(R6+R5) / R5 By adjusting the value of resistor R4, temperature compensation is achieved to obtain a voltage with zero temperature coefficient; The Zener diode Z2 is used to clamp the collector-emitter voltage VCE7 of the transistor Q7 and the gate-source voltage VGSN2 of the NMOS transistor NDM2 so as to prevent the collector-emitter of the transistor Q7 and the gate-source of the NMOS transistor NDM2 from being broken down. When the power supply VS starts to power on, the circuit is in a zero current state. At this time, the current on the resistor R1 is zero and the voltage drop is zero. The voltage at one end of the resistor R1 increases as VS increases. Similarly, the current on the resistor R2 is zero and the voltage drop is zero. The voltage at one end of the resistor R2 is zero. As the voltage at one end of the resistor R1 increases, the NMOS tube NDM1 gradually turns on to generate a bias current Ibias. The bias current Ibias flows through the resistor R2 to generate a voltage drop, causing the voltage at one end of the resistor R2 to start to increase, and finally the transistor Q1 turns on. After the circuit stabilizes, the voltage drop on the resistor R2 is the base-emitter voltage VBE1 of the transistor Q1, and the bias current Ibias is equal to VBE1 / R2. The bias current Ibias The PMOS tube PDM1 and the PMOS tube PDM2 in the first PMOS current mirror are copied and flow into the transistor Q7 to provide a bias current Ibias2 for the transistor Q7, thereby determining the base emitter voltage VBE7 of the transistor Q7; the high-voltage Wilson current source does not have a degeneracy point and can be started normally. After the high-voltage Wilson current source is started, the drain end of the PMOS tube PDM2 in the first PMOS current mirror is high, and the gate end of the NMOS tube NDM2 in the first common-source amplifier is high-conducting, then the gate end and the drain end of the PMOS tube PDM3 in the first common-source amplifier are low-conducting, and the gate end of the PMOS tube PDM4 in the second common-source amplifier is low-conducting, thereby starting the entire circuit.

[0013] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides an operational amplifier-free voltage-stabilizing startup circuit and a voltage-stabilizing startup method for high voltage, adopts a common-emitter amplifier and two common-source amplifiers to form a negative feedback loop, obtains a stable output voltage VLDO through negative feedback compensation, does not need to additionally design a pre-voltage-stabilizing circuit and a high-voltage operational amplifier, thereby saving chip area, and after the voltage-stabilizing startup circuit is started, there is no need to shut down the startup circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 The present invention is a schematic diagram of a voltage-stabilizing startup circuit without an operational amplifier applied to high voltage.

[0015] Figure 2 The present invention is a schematic diagram of a voltage stabilizing circuit structure applied to high voltage in the prior art. DETAILED DESCRIPTION

[0016] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0017] like Figure 1As shown, a voltage stabilizing startup circuit without operational amplifier for high voltage of the present invention comprises a voltage stabilizing circuit and a startup circuit, wherein the startup circuit generates a bias current Ibias2, and the voltage stabilizing circuit comprises transistors Q2, Q3, Q4, Q5, Q6, Q7, resistors R3, R4, R5, R6, PMOS transistors PDM3, PMOS transistors PDM4, NMOS transistors NDM2 and Zener diode Z2, wherein the cathode of Zener diode Z2 is connected to the collector of transistor Q7 and the gate of NMOS transistor NDM2 and is connected to the bias current Ibias2, the base of transistor Q7 is connected to the collector of transistor Q5, the base of transistor Q5, the base of transistor Q4 and the collector of transistor Q3, the base of transistor Q3 is connected to the base of transistor Q2, the collector of transistor Q2 and the collector of transistor Q4, The emitter of the transistor Q3 is connected to one end of the resistor R3, the emitter of the transistor Q5 is connected to one end of the resistor R4 and the emitter of the transistor Q4, the other end of the resistor R4 is connected to the emitter of the transistor Q6, the collector of the transistor Q6 is connected to the drain of the PMOS tube PDM4 and one end of the resistor R6 and generates an output voltage VLDO, the base of the transistor Q6 is connected to the other end of the resistor R6 and one end of the resistor R5, the source of the PMOS tube PDM4 and the source of the PMOS tube PDM3 are connected to the power supply VS, the gate of the PMOS tube PDM4 is connected to the gate of the PMOS tube PDM3, the drain of the PMOS tube PDM3 and the drain of the NMOS tube NDM2, the anode of the Zener diode Z2, the emitter of the transistor Q7, the source of the NMOS tube NDM2, the other end of the resistor R3, the emitter of the transistor Q2 and the other end of the resistor R5 are grounded; The startup circuit includes a resistor R1, a resistor R2, a transistor Q1, an NMOS transistor NDM1, a PMOS transistor PDM1, a PMOS transistor PDM2 and a Zener diode Z1. One end of the resistor R1 is connected to the source of the PMOS transistor PDM1, the source of the PMOS transistor PDM2 and the power supply VS. The other end of the resistor R1 is connected to the collector of the transistor Q1, the cathode of the Zener diode Z1 and the gate of the NMOS transistor NDM1. The base of the transistor Q1 is connected to the source of the NMOS transistor NDM1 and one end of the resistor R2. The drain of the NMOS transistor NDM1 is connected to the drain of the PMOS transistor PDM1, the gate of the PMOS transistor PDM1 and the gate of the PMOS transistor PDM2. The drain of the PMOS transistor PDM2 outputs a bias current Ibias2. The emitter of the transistor Q1, the anode of the Zener diode Z1 and the other end of the resistor R2 are grounded.

[0018] Among them, the NMOS tube NDM1 and the NMOS tube NDM2 are high-voltage NMOS tubes, and the PMOS tube PDM1, the PMOS tube PDM2, the PMOS tube PDM3 and the PMOS tube PDM4 are high-voltage PMOS tubes.

[0019] The transistor Q7 and the PMOS transistor PDM2 form a first common emitter amplifier, the NMOS transistor NDM2 and the PMOS transistor PDM3 form a first common source amplifier, and the PMOS transistor PDM4, the transistor Q6, the resistor R4 and the transistor Q5 form a second common source amplifier. The first common emitter amplifier, the first common source amplifier and the second common source amplifier form a negative feedback loop, and a stable output voltage VLDO is obtained through negative feedback compensation.

[0020] The transistor Q4 and the transistor Q5 are PNP transistors, and the transistor Q4 and the transistor Q5 form a first PNP current mirror. The transistor Q1, the transistor Q2, the transistor Q3, the transistor Q6 and the transistor Q7 are NPN transistors.

[0021] The PMOS tube PDM1 and the PMOS tube PDM2 form a first PMOS current mirror, and the PMOS tube PDM3 and the PMOS tube PDM4 form a second PMOS current mirror.

[0022] The resistor R1, the resistor R2, the transistor Q1, the NMOS transistor NDM1, the PMOS transistor PDM1, the PMOS transistor PDM2 and the Zener diode Z1 form a high-voltage Wilson current source.

[0023] A voltage stabilization starting method for a high voltage op amp-free voltage stabilization starting circuit comprises the following steps: The collector of the transistor Q5 is connected to the input end of the first common emitter amplifier composed of the transistor Q7 and the PMOS tube PDM2, the output end of the first common emitter amplifier is connected to the input end of the first common source amplifier composed of the NMOS tube NDM2 and the PMOS tube PDM3, the output end of the first common source amplifier is connected to the second common source amplifier composed of the high-voltage PMOS tube PDM4, the transistor Q6, the resistor R4 and the triode Q5, the first common emitter amplifier, the first common source amplifier and the second common source amplifier form a negative feedback loop, and a stable output voltage VLDO is obtained through negative feedback compensation.

[0024] The first PNP current mirror composed of transistors Q4 and Q5 makes the currents flowing through transistors Q2 and Q3 equal. Since the areas of transistors Q2 and Q3 are different, there is a voltage difference △VBE with a positive temperature coefficient between the base-emitter voltages VBE of transistors Q2 and Q3. The voltage difference △VBE with a positive temperature coefficient is divided by the resistor R3 with a zero temperature coefficient to obtain the current Ip with a positive temperature coefficient. The base voltage of transistor Q6 is equal to the base-emitter voltage VBE7 of transistor Q7 with a negative temperature coefficient plus the base-emitter voltage VBE5 of transistor Q5 with a negative temperature coefficient plus the voltage drop 2*Ip*R4 of resistor R4 plus the base-emitter voltage VBE6 of transistor Q6 with a negative temperature coefficient, that is, VBE7+VBE5+2*Ip*R4+VBE6. Then the output voltage VLDO is: VLDO=(VBE7+VBE5+2*Ip*R4+VBE6)*(R6+R5) / R5 Temperature compensation is achieved by adjusting the value of resistor R4 to obtain a voltage with a zero temperature coefficient.

[0025] The Zener diode Z2 is used to clamp the collector-emitter voltage VCE7 of the transistor Q7 and the gate-source voltage VGSN2 of the NMOS transistor NDM2 so as to be lower than the Zener diode clamping voltage VZ2, thereby preventing the collector-emitter of the transistor Q7 and the gate-source of the NMOS transistor NDM2 from being broken down.

[0026] Resistor R1, resistor R2, transistor Q1, NMOS transistor NDM1, PMOS transistor PDM1, PMOS transistor PDM2 and Zener diode Z1 form a high-voltage Wilson current source. When the power supply VS starts to power on, the circuit is in a zero current state. At this time, the current on resistor R1 is zero, the voltage drop is zero, and the voltage at one end of resistor R1 increases with the increase of VS; similarly, the current of resistor R2 is zero, the voltage drop is zero, and the voltage at one end of resistor R2 is zero. As the voltage at one end of resistor R1 increases, NMOS transistor NDM1 gradually turns on to generate bias current Ibias; bias current Ibias flows through resistor R2 to generate a voltage drop, causing the voltage at one end of resistor R2 to start to increase, and finally transistor Q1 turns on; after the circuit stabilizes, the voltage drop of resistor R2 is the base-emitter voltage VBE1 of transistor Q1, and the bias current Ibias is equal to VBE1 / R2; bias current Ibias The bias current Ibias2 is provided to the transistor Q7 by copying the PMOS tube PDM1 and PMOS tube PDM2 in the first PMOS current mirror and flowing into the transistor Q7, thereby determining the base emitter voltage VBE7 of the transistor Q7; the high-voltage Wilson current source does not have a degenerate point and can be started normally. After the high-voltage Wilson current source is started, the drain end of the PMOS tube PDM2 in the first PMOS current mirror is high, the gate end of the NMOS tube NDM2 in the first common source amplifier is high conduction, then the gate end and drain end of the PMOS tube PDM3 in the first common source amplifier are low conduction, and the gate end of the PMOS tube PDM4 in the second common source amplifier is low conduction, thereby starting the entire circuit. Moreover, compared with the traditional startup circuit, the startup circuit does not need to be shut down after the startup is completed.

[0027] The present invention provides an operational amplifier-free voltage-stabilizing startup circuit and a voltage-stabilizing startup method for high voltage. A common-emitter amplifier and two common-source amplifiers are used to form a negative feedback loop, and a stable output voltage VLDO is obtained through negative feedback compensation. No additional pre-voltage-stabilizing circuit and high-voltage operational amplifier need to be designed, thereby saving chip area. Moreover, after the voltage-stabilizing startup circuit is started, there is no need to shut down the startup circuit.

[0028] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A voltage-stabilizing startup circuit without an operational amplifier for high voltage, characterized in that: The invention comprises a voltage stabilizing circuit and a starting circuit, wherein the starting circuit generates a bias current Ibias2, and the voltage stabilizing circuit comprises transistors Q2, Q3, Q4, Q5, Q6, Q7, resistors R3, R4, R5, R6, PMOS transistors PDM3, PMOS transistors PDM4, NMOS transistors NDM2 and Zener diode Z2, wherein the cathode of Zener diode Z2 is connected to the collector of transistor Q7 and the gate of NMOS transistor NDM2 and is connected to the bias current Ibias2, the base of transistor Q7 is connected to the collector of transistor Q5, the base of transistor Q5, the base of transistor Q4 and the collector of transistor Q3, the base of transistor Q3 is connected to the base of transistor Q2, the collector of transistor Q2 and the collector of transistor Q4, and the emitter of transistor Q3 is connected to the resistor R 3, the emitter of the transistor Q5 is connected to one end of the resistor R4 and the emitter of the transistor Q4, the other end of the resistor R4 is connected to the emitter of the transistor Q6, the collector of the transistor Q6 is connected to the drain of the PMOS tube PDM4 and one end of the resistor R6 and generates an output voltage VLDO, the base of the transistor Q6 is connected to the other end of the resistor R6 and one end of the resistor R5, the source of the PMOS tube PDM4 and the source of the PMOS tube PDM3 are connected to the power supply VS, the gate of the PMOS tube PDM4 is connected to the gate of the PMOS tube PDM3, the drain of the PMOS tube PDM3 and the drain of the NMOS tube NDM2, the anode of the Zener diode Z2, the emitter of the transistor Q7, the source of the NMOS tube NDM2, the other end of the resistor R3, the emitter of the transistor Q2 and the other end of the resistor R5 are grounded.

2. The voltage-stabilizing starting circuit without an operational amplifier for high voltage according to claim 1, characterized in that: The startup circuit includes a resistor R1, a resistor R2, a transistor Q1, an NMOS transistor NDM1, a PMOS transistor PDM1, a PMOS transistor PDM2 and a Zener diode Z1. One end of the resistor R1 is connected to the source of the PMOS transistor PDM1, the source of the PMOS transistor PDM2 and the power supply VS. The other end of the resistor R1 is connected to the collector of the transistor Q1, the cathode of the Zener diode Z1 and the gate of the NMOS transistor NDM1. The base of the transistor Q1 is connected to the source of the NMOS transistor NDM1 and one end of the resistor R2. The drain of the NMOS transistor NDM1 is connected to the drain of the PMOS transistor PDM1, the gate of the PMOS transistor PDM1 and the gate of the PMOS transistor PDM2. The drain of the PMOS transistor PDM2 outputs a bias current Ibias2. The emitter of the transistor Q1, the anode of the Zener diode Z1 and the other end of the resistor R2 are grounded.

3. The voltage-stabilizing starting circuit without an operational amplifier for high voltage according to claim 2, characterized in that: The NMOS tube NDM1 and the NMOS tube NDM2 are high-voltage NMOS tubes, and the PMOS tubes PDM1, PMOS tube PDM2, PMOS tube PDM3 and PMOS tube PDM4 are high-voltage PMOS tubes.

4. The voltage-stabilizing startup circuit without an operational amplifier for high voltage according to claim 2, characterized in that: The transistor Q7 and the PMOS transistor PDM2 form a first common emitter amplifier, the NMOS transistor NDM2 and the PMOS transistor PDM3 form a first common source amplifier, and the PMOS transistor PDM4 and the transistor Q6, the resistor R4 and the transistor Q5 form a second common source amplifier.

5. The voltage-stabilizing startup circuit without an operational amplifier for high voltage according to claim 2, characterized in that: The transistors Q4 and Q5 are PNP transistors, and the transistors Q4 and Q5 form a first PNP current mirror. The transistors Q1, Q2, Q3, Q6 and Q7 are NPN transistors.

6. The voltage-stabilizing startup circuit without an operational amplifier for high voltage according to claim 2, characterized in that: The PMOS tube PDM1 and the PMOS tube PDM2 form a first PMOS current mirror, and the PMOS tube PDM3 and the PMOS tube PDM4 form a second PMOS current mirror.

7. The voltage-stabilizing startup circuit without an operational amplifier for high voltage according to claim 2, characterized in that: The resistor R1, the resistor R2, the transistor Q1, the NMOS transistor NDM1, the PMOS transistor PDM1, the PMOS transistor PDM2 and the Zener diode Z1 form a high-voltage Wilson current source.

8. A voltage stabilizing starting method for a high voltage non-op-amp voltage stabilizing starting circuit according to any one of claims 1 to 7, characterized in that The following steps are involved: The collector of the transistor Q5 is connected to the input end of the first common emitter amplifier composed of the transistor Q7 and the PMOS tube PDM2, the output end of the first common emitter amplifier is connected to the input end of the first common source amplifier composed of the NMOS tube NDM2 and the PMOS tube PDM3, the output end of the first common source amplifier is connected to the second common source amplifier composed of the high-voltage PMOS tube PDM4, the transistor Q6, the resistor R4 and the triode Q5, the first common emitter amplifier, the first common source amplifier and the second common source amplifier form a negative feedback loop, and a stable output voltage VLDO is obtained through negative feedback compensation; The first PNP current mirror composed of transistors Q4 and Q5 makes the currents flowing through transistors Q2 and Q3 equal. Since the areas of transistors Q2 and Q3 are different, there is a voltage difference △VBE with a positive temperature coefficient between the base-emitter voltages VBE of transistors Q2 and Q3. The voltage difference △VBE with a positive temperature coefficient is divided by the resistor R3 with a zero temperature coefficient to obtain the current Ip with a positive temperature coefficient. The base voltage of transistor Q6 is equal to the base-emitter voltage VBE7 of transistor Q7 with a negative temperature coefficient plus the base-emitter voltage VBE5 of transistor Q5 with a negative temperature coefficient plus the voltage drop 2*Ip*R4 of resistor R4 plus the base-emitter voltage VBE6 of transistor Q6 with a negative temperature coefficient, that is, VBE7+VBE5+2*Ip*R4+VBE6. Then the output voltage VLDO is: VLDO=(VBE7+VBE5+2*Ip*R4+VBE6)*(R6+R5) / R5 By adjusting the value of resistor R4, temperature compensation is achieved to obtain a voltage with zero temperature coefficient; The Zener diode Z2 is used to clamp the collector-emitter voltage VCE7 of the transistor Q7 and the gate-source voltage VGSN2 of the NMOS transistor NDM2 so as to prevent the collector-emitter of the transistor Q7 and the gate-source of the NMOS transistor NDM2 from being broken down. When the power supply VS starts to power on, the circuit is in a zero current state. At this time, the current on the resistor R1 is zero and the voltage drop is zero. The voltage at one end of the resistor R1 increases as VS increases. Similarly, the current on the resistor R2 is zero and the voltage drop is zero. The voltage at one end of the resistor R2 is zero. As the voltage at one end of the resistor R1 increases, the NMOS tube NDM1 gradually turns on to generate a bias current Ibias. The bias current Ibias flows through the resistor R2 to generate a voltage drop, causing the voltage at one end of the resistor R2 to start to increase, and finally the transistor Q1 turns on. After the circuit stabilizes, the voltage drop on the resistor R2 is the base-emitter voltage VBE1 of the transistor Q1, and the bias current Ibias is equal to VBE1 / R2. The bias current Ibias The PMOS tube PDM1 and the PMOS tube PDM2 in the first PMOS current mirror are copied and flow into the transistor Q7 to provide a bias current Ibias2 for the transistor Q7, thereby determining the base emitter voltage VBE7 of the transistor Q7; the high-voltage Wilson current source does not have a degeneracy point and can be started normally. After the high-voltage Wilson current source is started, the drain end of the PMOS tube PDM2 in the first PMOS current mirror is high, and the gate end of the NMOS tube NDM2 in the first common-source amplifier is high-conducting, then the gate end and the drain end of the PMOS tube PDM3 in the first common-source amplifier are low-conducting, and the gate end of the PMOS tube PDM4 in the second common-source amplifier is low-conducting, thereby starting the entire circuit.

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