Embedded reference high loop gain low dropout linear regulator and voltage stabilization method

Abstract

The invention provides an embedded reference high loop gain low dropout linear regulator and a voltage stabilization method, and the method comprises the steps: adjusting a power tube, the source electrode of which is connected with a voltage input end used for providing an input voltage, and the drain electrode of which is connected with a voltage output end used for outputting the voltage; the first loop is electrically connected with the grid electrode of the adjusting power tube and is used for forming a pseudo push-pull stage; and the second loop is electrically connected with the drain electrode of the adjusting power tube and is used for forming a bias circuit formed by the output voltage for the adjusting power tube. According to the invention, through the second loop, the whole circuit is enabled to have high DC gain, so that the linearity, the load regulation rate and the low-frequency PSR are improved, a pseudo push-pull output stage is realized at the grid electrode of the regulation power tube, the quiescent current of the whole circuit is only nA stage, and the circuit has the characteristics of compact structure, no amplifier, low power consumption and high gain.

Description

Technical Field

[0001] The present application belongs to the field of electronic technology, and in particular relates to a low-dropout linear regulator with an embedded reference high loop gain and a voltage stabilization method. Background Art

[0002] The growing demand for the Internet of Things (IoT) requires the use of self-powered, fully integrated system-on-chip (SoC)-based designs to ensure that sensing and computing are achieved on a single chip. Therefore, sensor nodes should have a long operating life in low-supply voltage systems below 1V (sub-1V). Low-dropout linear regulators (LDOs) have always been an integral part of power management systems. For fully integrated SoCs, LDOs are required to have on-chip load capacitance ranging from zero to hundreds of pF. At the same time, most advanced or traditional LDO architectures require a voltage reference (VR) (based on bandgap or CMOS), a differential to single-ended error amplifier (EA), and a power tube to support different load currents. However, due to the low supply voltage, it is difficult to design a compact and high-loop-gain LDO at a sub-1V supply voltage, resulting in weak linear and load regulation capabilities and power supply rejection ratio (PSR). Therefore, in order to ensure the excellent DC performance of sub-1V LDOs, architectural changes are essential. The loop gain of traditional LDOs with embedded references is only provided by the reference, which is not enough to ensure excellent DC performance.

[0003] Therefore, it is necessary to study a compact, low-power, high-gain LDO with an embedded reference amplifier. Summary of the invention

[0004] The purpose of the present application is to provide a low-dropout linear regulator with an embedded reference high loop gain and a voltage stabilization method, so as to at least solve one technical problem in the prior art.

[0005] The technical solution of this application is:

[0006] A low voltage drop linear regulator with built-in reference and high loop gain, comprising:

[0007] The regulating power tube has a source connected to a voltage input terminal for providing an input voltage, and a drain connected to a voltage output terminal for outputting a voltage;

[0008] The first loop is electrically connected to the gate of the adjustment power tube and is used to form a pseudo push-pull stage, which can achieve fast transient response to small step load current and provide DC gain;

[0009] The second loop is electrically connected to the drain of the adjusting power tube and is used to form a bias circuit composed of the output voltage for the adjusting power tube.

[0010] The first loop includes:

[0011] The eighth power tube;

[0012] A common-gate module, arranged between the drain of the eighth power tube and the gate of the adjustment power tube;

[0013] an eleventh power tube, arranged between the source of the eighth power tube and the gate of the adjusting power tube;

[0014] The source of the eleventh power tube is connected in parallel with the source connected to the adjusting power tube and then connected to the voltage input terminal;

[0015] The drain of the eleventh power tube is connected to the gate of the adjusting power tube.

[0016] The common-gate module comprises:

[0017] a ninth power tube, whose drain is electrically connected to the drain of the eighth power tube;

[0018] a tenth power tube, a drain of which is connected to the gate of the adjusting power tube;

[0019] The ninth power tube is electrically connected to the gate of the tenth power tube, and is electrically connected to the drain of the eighth power tube;

[0020] The sources of the ninth power tube and the tenth power tube are both electrically connected to the drain of the adjusting power tube.

[0021] A common drain module is also provided between the source of the tenth power tube and the drain of the adjusting power tube;

[0022] The common drain module comprises:

[0023] A twelfth power tube, a source of which is electrically connected to the drain of the adjusting power tube;

[0024] A thirteenth power tube, a drain of which is electrically connected to the drain of the twelfth power tube;

[0025] The gate of the twelfth power tube is connected to the voltage input terminal;

[0026] The gates of the thirteenth power tubes are all connected to the voltage output end.

[0027] A series connection module is provided between the gate of the twelfth power tube and the voltage input terminal;

[0028] The series connection module comprises:

[0029] A first power tube, a drain of which is electrically connected to a power input terminal;

[0030] a second power tube, a drain of which is electrically connected to the source of the first power tube;

[0031] a third power tube, whose source is electrically connected to the gate of the twelfth power tube;

[0032] The gates of the first power tube, the second power tube and the third power tube are connected in parallel and are electrically connected to the gate of the twelfth power tube.

[0033] The gate of the thirteenth power tube is electrically connected to the gate of the fifth power tube;

[0034] The source of the fifth power tube is connected to the voltage output terminal, and the drain of the fifth power tube is connected to the drain of the sixth power tube;

[0035] The source of the sixth power tube is connected to the voltage input terminal, and the gate of the sixth power tube is connected to the gate of the seventh power tube;

[0036] The drain of the seventh power tube is electrically connected to the gate of the eighth power tube, and the source of the seventh power tube is connected to the voltage input terminal.

[0037] The second loop includes:

[0038] A load series module, electrically connected to the voltage output terminal;

[0039] a fourth power tube, whose source is connected to the output end of the load series module;

[0040] The gate of the fourth power tube is connected to the voltage output end;

[0041] The drain of the fourth power tube is electrically connected to the load series module, and is used to form a bias circuit composed of the output voltage for the adjustment power tube.

[0042] The load series module comprises:

[0043] A first load tube, whose source is electrically connected to the drain of the adjustment power tube;

[0044] A second load tube, a drain of which is electrically connected to the drain of the first load tube;

[0045] The source of the second load tube is connected to the voltage output end.

[0046] A low-dropout linear voltage regulator method with an embedded reference high loop gain is based on the above-mentioned low-dropout linear voltage regulator with an embedded reference high loop gain, comprising:

[0047] By using the eighth power tube, the ninth power tube, the tenth power tube and the eleventh power tube in the low voltage difference linear regulator with an embedded reference high loop gain, a pseudo push-pull stage is formed at the gate of the adjustment power tube to form a first loop, thereby increasing the slew rate;

[0048] A second loop is constructed by a first load tube, a second load tube and a fourth power tube in a low-dropout linear regulator with an embedded reference high loop gain, so that the second loop directly biases the output voltage, making the output voltage insensitive to PVT changes;

[0049] The transfer function for the global loop is as follows:

[0050]

[0051] The overall DC gain is:

[0052]

[0053] The poles are:

[0054]

[0055]

[0056] Zero point is:

[0057]

[0058] Among them, ω p1 is the main pole, ω p2 is the secondary pole, ω p3 With ω p4 For other poles outside the bandwidth, z 1 is zero point, ω p3 With ω p4 Outside the bandwidth does not affect the phase margin; where β is the feedback resistor voltage divider coefficient, g mi For MOS tube M i The transconductance, g di For MOS tube M i The conductivity, C out is the output capacitance, C x is the compensation capacitor, C P is the gate capacitance of the power tube MP, C m is the Miller compensation capacitor, A ns is the pseudo push-pull stage gain, R b is the bias current source equivalent resistance, R o2 is the equivalent output resistance of the pseudo push-pull stage, R L is the load resistance, and s is the Laplace transform parameter.

[0059] An application of the above-mentioned low-dropout linear regulator with built-in reference and high loop gain in an Internet of Things device.

[0060] The beneficial effects of this application include at least:

[0061] The low-voltage difference linear regulator with an embedded reference high loop gain described in the present application forms a pseudo push-pull stage at the gate of the adjustment power tube to form a first loop through the eighth power tube, the ninth power tube, the tenth power tube and the eleventh power tube, and the first load tube, the second load tube and the fourth power tube in the low-voltage difference linear regulator construct a second loop, so that the overall high DC gain is achieved, thereby improving the linearity, load regulation rate and low-frequency PSR, and realizing a pseudo push-pull output stage at the gate of the power tube, so that the quiescent current of the overall circuit is only at the nA level, and has the characteristics of compact structure, no amplifier, low power consumption and high gain. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 It is a traditional low-dropout linear regulator with an embedded 5-tube reference;

[0063] Figure 2 It is an adaptive substrate bias circuit in the prior art;

[0064] Figure 3 It is a circuit diagram of a low-dropout linear regulator with an embedded reference and high loop gain according to the present invention;

[0065] Figure 4 yes Figure 3 Small signal analysis diagram of the LDO of the circuit shown;

[0066] Figure 5 yes Figure 3 Loop stability simulation of the circuit diagram shown, IL = 25mA;

[0067] Figure 6 yes Figure 3 The circuit diagram shown is a transient response simulation diagram, IL=1mA~25mA, tr=100ns. DETAILED DESCRIPTION

[0068] The present application is further described below in conjunction with the accompanying drawings.

[0069] In order to explain the present application in more detail, it is necessary to explain the prior art in detail.

[0070] like Figure 1It is a traditional low dropout linear regulator with an embedded 5-tube reference. The VR is integrated with the flip voltage follower (FVF) output stage to form a dual-loop structure. This ensures that the LDO has a high DC loop gain, thus providing excellent linearity and load regulation for the proposed design. The reference embedded design also ensures a tighter integration of reference and regulation, because no EA is required and the output of the LDO is directly controlled by the VR module.

[0071] VR is composed of devices M1-M5. Transistors M3-M5 improve line sensitivity by ensuring that the DC voltage across M1 is fixed and reducing drain-induced barrier lowering (DIBL), thereby improving the DC PSR of the reference. The subthreshold current source M1 and the bottom current sink M2 have the same drain current. When placed in negative feedback, M2 produces a specific VGS2 to carry the required drain current. For the appropriate size ratio of M1 and M2, VGS2 can make it temperature insensitive, so VGS2 = VREF, and its output voltage formula is

[0072]

[0073] In this structure, VR is used as a single-stage common source amplifier for the small signal gain of M2 from gate to drain. Considering the inverting gain provided by VR, a FVF is selected as the pass stage of the LDO to ensure dual-loop regulation of the output node. The advantage of this structural choice is low output impedance and bias flexibility is achieved through M7. However, the overall DC gain is not high, and the linearity, load regulation rate and PSR of this architecture are not superior to those of the LDO architecture with amplifiers. At the same time, due to the lack of an amplifier, the gate slew rate (SR) of the LDO power tube is low, and the transient response is also affected. Since loop L1 has a small UGB, 0.2kHz under nominal conditions, the transient recovery of VOUT is slow (ms level), and the recovery of VOUT after a sudden load change mainly depends on the bandwidth of the working loop. Therefore, in order to solve the problem of slow transient response, an adaptive substrate bias circuit is added to the circuit.

[0074] like Figure 2 , is an adaptive substrate bias circuit existing in the prior art. The gate of MB2 is connected to VBIAS, where MB2 is only 1 / 16 of Ib to reduce power consumption. MB2 is connected to a diode-connected PMOS device MB1. As the load current increases, Vin-Vbulk begins to increase, and the VTH of MP is reduced due to the body effect. The reduced VTH causes the VG of Mp to decrease as IL increases. The source-body voltage of MP gradually becomes positive, and the source-body leakage current flowing to the body terminal also increases. However, the self-bias circuit design is complex, and there is a risk of diode current leakage from the source to the body of MP. At the same time, the power consumption is also large.

[0075] It can be seen that in the prior art, in sub-1V, it is difficult for LDOs containing EA to obtain high DC gain under limited voltage margin; although the gain can be improved by cascading two gain stages, it is at the expense of increased static power consumption and reduced stability. Transistors with smaller threshold voltages can also be used, but the manufacturing process requires additional mask layers, which increases the manufacturing cost. At the same time, the existing LDO with embedded reference architecture omits EA to obtain a low-voltage compact design, but the DC gain is still not high enough, resulting in low linearity, load regulation and PSR performance. At the same time, due to the lack of EA, the SR of the power tube is low. Compared with the LDO architecture with EA, the transient response still has no advantage under the same bandwidth conditions. In order to increase SR, an adaptive substrate bias with higher power consumption is used, which is not conducive to achieving a longer working life of sensor nodes in IOT systems. Specific embodiment 1:

[0077] The present invention provides an embodiment:

[0078] Aiming at the problem of low DC gain of LDO with built-in reference and no EA, the present invention proposes a low voltage drop linear regulator with built-in reference and high loop gain, which has the characteristics of multiple feedback loops, high gain and low power consumption; Figure 3 As shown in the figure, the LDO core consists of two loops. LOOP2 provides excellent DC regulation performance such as linear and load regulation, and LOOP1 loop provides fast transient response.

[0079] like Figure 3 , a low-dropout linear regulator with an embedded reference high loop gain, the specific circuit is as follows: an adjustment power tube MP, whose source is connected to a voltage input terminal for providing an input voltage, and whose drain is connected to a voltage output terminal for outputting a voltage; a first loop is electrically connected to the gate of the adjustment power tube MP, and is used to form a pseudo push-pull stage, which can achieve a fast transient response to a small step load current and provide a DC gain; a second loop is electrically connected to the drain of the adjustment power tube MP, and is used to form a bias circuit composed of the output voltage for the adjustment power tube MP.

[0080] Specifically, the first loop is formed by arranging a common-gate module between the drain of the eighth power tube M8 and the gate of the adjusting power tube MP; the eleventh power tube M11 is arranged between the source of the eighth power tube M8 and the gate of the adjusting power tube MP; the source of the eleventh power tube M11 is connected in parallel with the source connected to the adjusting power tube MP and then connected to the voltage input terminal; the drain of the eleventh power tube M11 is connected to the gate of the adjusting power tube MP.

[0081] Preferably, the common-gate module includes: a ninth power tube M9 and a tenth power tube M10; wherein the drain of the ninth power tube M9 is electrically connected to the drain of the eighth power tube M8; the drain of the tenth power tube M10 is connected to the gate of the adjusting power tube MP; the ninth power tube M9 is electrically connected to the gate of the tenth power tube M10, and is electrically connected to the drain of the eighth power tube M8; the sources of the ninth power tube M9 and the tenth power tube M10 are both electrically connected to the drain of the adjusting power tube MP.

[0082] Specifically, a common drain module is further provided between the source of the tenth power tube M10 and the drain of the adjusting power tube MP;

[0083] The common drain module includes: a twelfth power tube M12 and a thirteenth power tube M13; wherein the source of the twelfth power tube M12 is electrically connected to the drain of the adjustment power tube MP; the drain of the thirteenth power tube M13 is electrically connected to the drain of the twelfth power tube M12; the gate of the twelfth power tube M12 is connected to the voltage input terminal; the gate of the thirteenth power tube M13 is connected to the voltage output terminal. A series module is arranged between the gate of the twelfth power tube M12 and the voltage input terminal.

[0084] Preferably, the series module includes: a first power tube M1, a second power tube M2, and a third power tube M3; wherein, the first power tube M1 has a drain electrically connected to the power input terminal; the second power tube M2 has a drain electrically connected to the source of the first power tube M1; the third power tube M3 has a source electrically connected to the gate of the twelfth power tube M12; the gates of the first power tube M1, the second power tube M2 and the third power tube M3 are connected in parallel and electrically connected to the gate of the twelfth power tube M12. The gate of the thirteenth power tube M13 is electrically connected to the gate of the fifth power tube M5; the source of the fifth power tube M5 is connected to the voltage output end, and the drain thereof is connected to the drain of the sixth power tube M6; the source of the sixth power tube M6 is connected to the voltage input end, and the gate of the sixth power tube M6 is connected to the gate of the seventh power tube M7; the drain of the seventh power tube M7 is electrically connected to the gate of the eighth power tube M8, and the source of the seventh power tube M7 is connected to the voltage input end.

[0085] The second loop includes: a load series module and a fourth power tube M4; wherein the load series module is electrically connected to the voltage output end; the fourth power tube M4 has a source connected to the output end of the load series module; the gate of the fourth power tube M4 is connected to the voltage output end; the drain of the fourth power tube M4 is electrically connected to the load series module, and is used to form a bias circuit composed of the output voltage for the adjustment power tube MP.

[0086] Preferably, the load series module includes: a first load tube Mf1 and a second load tube Mf2; wherein the source of the first load tube Mf1 is electrically connected to the drain of the adjustment power tube MP; the drain of the second load tube Mf2 is electrically connected to the drain of the first load tube Mf1; and the source of the second load tube Mf2 is connected to the voltage output terminal.

[0087] The low-dropout linear regulator with an embedded reference high loop gain described in this embodiment can provide ultra-low IQ and high load current driving capability. However, this requirement will reduce the load transient performance due to the poor SR at the gate of the power tube. This limitation is caused by the large gate capacitance of MP and nA constant current sources Ib1 and Ib2. In order to overcome this shortcoming, this embodiment adds a slew rate enhancement feedback loop LOOP1, forming a pseudo push-pull stage at the gate of MP, which is composed of the eighth power tube M8, the ninth power tube M9, the tenth power tube M10, and the eleventh power tube M11. For small step load currents, the loop shortens the recovery time to tens of us, thereby achieving fast transient response. At the same time, LOOP1 provides the main DC gain for the overall loop, which is about 90db. In addition, since the parasitic capacitance of each node is small and the overall power consumption is low, the poles generated by these nodes are mostly outside the bandwidth and do not affect the loop stability. The high DC gain Loop1 ensures the good performance of the linearity, load regulation and low-frequency PSR of the LDO.

[0088] For LOOP2, it can be seen that LOOP2 directly biases VOUT instead of the current mirror based approach based on single-tube controlled FVF. Therefore, the output voltage depends directly on VR, so the output voltage of the LDO is insensitive to PVT changes.

[0089] For the overall small signal analysis Figure 4 For simplicity, the channel length modulation effect of the MOS tube is ignored here (ro12≈∞), so looking from Vout to the drain of M12, the gain can be simplified to

[0090]

[0091] Therefore, gm12B can be simplified to

[0092]

[0093] The transfer function for the global loop is as follows:

[0094]

[0095] The overall DC gain is

[0096]

[0097] The poles are:

[0098]

[0099]

[0100] Zero point is:

[0101]

[0102] Among them, ω p1 is the main pole, ω p2 is the secondary pole, ω p3 With ω P4 For other poles outside the bandwidth, z 1 is zero point, z 1 Located in p1 With ω p2 Then ensure that the phase margin (PM) is good. In addition, ω p3 With ω p4 Outside the bandwidth, the circuit should be designed to ensure that p3 Can't get too close to z 1 Otherwise, PM will drop seriously and cause loop instability. At the same time, Ib2 should not be too small, which will cause ω p4 Too close to z 1 .

[0103] However, since the embedded VR only flows a pA-level static current, the effective resistance rds4 at the drain of M4 is hundreds of MΩ. Due to this large impedance, the dominant left half plane pole of Loop1 is at ω p1 =gds 4 / Cx (for all process corners <1kHz), therefore, at ω p1 After that, the effective output impedance at VOUT will increase due to the reduction in loop gain, causing the PSR to begin to decrease. However, due to the high overall DC gain, the PSR still performs well in the 1-100Hz range.

[0104] Compared with the low-dropout linear regulator with an embedded 5-tube reference, this embodiment can obtain better transient response without the need for an adaptive substrate bias circuit, greatly reducing power consumption, and improving the overall gain by combining high-bandwidth and high-gain LOOP1 and LOOP2, ensuring good linearity, load regulation and low-frequency PSR of the LDO. In addition, the pseudo push-pull stage increases the slew rate at the MP gate, further improving the transient response.

[0105] Compared with the low-dropout linear regulator with an embedded 5-tube reference, the load regulation, line regulation and PSR are all improved. At the same time, compared with the traditional LDO, the amplifier is not required, which greatly saves power consumption.

[0106] The DC gain of this embodiment is

[0107]

[0108] The DC gain of the low-dropout linear regulator with an embedded 5-tube reference is:

[0109]

[0110] At low frequency, the DC gain of the present invention is about 150db, and the DC gain of the low-voltage dropout linear regulator with an embedded 5-tube reference is about 60db. It can be seen that the DC gain of the present invention has been greatly improved. The following is a comparison of the loop stability simulation and transient simulation of the present invention and the data of the low-voltage dropout linear regulator with an embedded 5-tube reference. Figure 5 and 6 ; Specific data are shown in Table 1.

[0111] Table 1 Data comparison

[0112]

[0113] In summary, the present invention proposes a multi-loop controlled, high loop gain, low voltage drop linear regulator with an embedded reference, which can achieve high gain and good transient response without using an amplifier, and has a more compact structure. Specific embodiment 2:

[0115] The present invention also provides an embodiment:

[0116] A method for low-dropout linear voltage regulation with an embedded reference high loop gain is based on the low-dropout linear voltage regulator with an embedded reference high loop gain described in specific embodiment 1, comprising: forming a pseudo push-pull stage at the gate of the adjustment power tube MP to form a first loop through an eighth power tube M8, a ninth power tube M9, a tenth power tube M10 and an eleventh power tube M11 in the low-dropout linear voltage regulator with an embedded reference high loop gain, thereby increasing the slew rate; constructing a second loop through a first load tube Mf1, a second load tube Mf2 and a fourth power tube M4 in the low-dropout linear voltage regulator with an embedded reference high loop gain, so that the second loop directly biases the output voltage, so that the output voltage is insensitive to PVT changes. Specific embodiment 3:

[0118] This application also provides an embodiment:

[0119] An electronic device comprises: a storage medium and a processing unit; wherein the storage medium is used to store a computer program, and the processing unit exchanges data with the storage medium, and is used to execute the computer program through the processing unit when performing linear voltage regulation, and perform the steps of the low-voltage difference linear voltage regulation method with an embedded reference high loop gain as described in specific embodiment 2. Specific embodiment 4:

[0121] A computer-readable storage medium having a computer program stored therein; when the computer program is run, the steps of the low-dropout linear voltage regulation method with an embedded reference high loop gain as described in specific embodiment 2 are executed.

[0122] In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, apparatus, or device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0123] The above disclosures are only several specific implementation scenarios of the present application, but the present application is not limited thereto, and any changes that can be thought of by a person skilled in the art should fall within the protection scope of the present application. The above application numbers are only for description and do not represent the advantages and disadvantages of the implementation scenarios.

Claims

1. A low dropout linear regulator with built-in reference high loop gain, characterized in that: include: The regulating power tube has a source connected to a voltage input terminal for providing an input voltage, and a drain connected to a voltage output terminal for outputting a voltage; The first loop is electrically connected to the gate of the adjustment power tube and is used to form a pseudo push-pull stage, which can achieve fast transient response to small step load current and provide DC gain; The second loop is electrically connected to the drain of the adjusting power tube and is used to form a bias circuit composed of the output voltage for the adjusting power tube to improve the DC regulation performance.

2. The low-dropout linear regulator with built-in reference and high loop gain according to claim 1, characterized in that: The first loop includes: The eighth power tube; A common-gate module, arranged between the drain of the eighth power tube and the gate of the adjustment power tube; an eleventh power tube, arranged between the source of the eighth power tube and the gate of the adjusting power tube; The source of the eleventh power tube is connected in parallel with the source connected to the adjusting power tube and then connected to the voltage input terminal; The drain of the eleventh power tube is connected to the gate of the adjusting power tube.

3. The low-dropout linear regulator with built-in reference and high loop gain according to claim 2, characterized in that: The common-gate module comprises: a ninth power tube, whose drain is electrically connected to the drain of the eighth power tube; a tenth power tube, a drain of which is connected to the gate of the adjusting power tube; The ninth power tube is electrically connected to the gate of the tenth power tube, and is electrically connected to the drain of the eighth power tube; The sources of the ninth power tube and the tenth power tube are both electrically connected to the drain of the adjusting power tube.

4. The low-dropout linear regulator with built-in reference and high loop gain according to claim 3, characterized in that: A common drain module is also provided between the source of the tenth power tube and the drain of the adjusting power tube; The common drain module comprises: A twelfth power tube, a source of which is electrically connected to the drain of the adjusting power tube; A thirteenth power tube, a drain of which is electrically connected to the drain of the twelfth power tube; The gate of the twelfth power tube is connected to the voltage input terminal; The gates of the thirteenth power tubes are all connected to the voltage output end.

5. The low-dropout linear regulator with built-in reference and high loop gain according to claim 4, characterized in that: A series connection module is provided between the gate of the twelfth power tube and the voltage input terminal; The series connection module comprises: A first power tube, a drain of which is electrically connected to a power input terminal; a second power tube, a drain of which is electrically connected to the source of the first power tube; a third power tube, whose source is electrically connected to the gate of the twelfth power tube; The gates of the first power tube, the second power tube and the third power tube are connected in parallel and are electrically connected to the gate of the twelfth power tube.

6. The low-dropout linear regulator with built-in reference and high loop gain according to claim 4, characterized in that: The gate of the thirteenth power tube is electrically connected to the gate of the fifth power tube; The source of the fifth power tube is connected to the voltage output terminal, and the drain of the fifth power tube is connected to the drain of the sixth power tube; The source of the sixth power tube is connected to the voltage input terminal, and the gate of the sixth power tube is connected to the gate of the seventh power tube; The drain of the seventh power tube is electrically connected to the gate of the eighth power tube, and the source of the seventh power tube is connected to the voltage input terminal.

7. The low-dropout linear regulator with built-in reference and high loop gain according to claim 1, characterized in that: The second loop includes: A load series module, electrically connected to the voltage output terminal; a fourth power tube, whose source is connected to the output end of the load series module; The gate of the fourth power tube is connected to the voltage output end; The drain of the fourth power tube is electrically connected to the load series module, and is used to form a bias circuit composed of the output voltage for the adjustment power tube.

8. The low-dropout linear regulator with built-in reference and high loop gain according to claim 4, characterized in that: The load series module comprises: A first load tube, whose source is electrically connected to the drain of the adjustment power tube; A second load tube, a drain of which is electrically connected to the drain of the first load tube; The source of the second load tube is connected to the voltage output terminal.

9. A method for low-dropout linear voltage regulation with an embedded reference and high loop gain, based on the low-dropout linear voltage regulator with an embedded reference and high loop gain as claimed in any one of claims 1 to 8, characterized in that: include: By using the eighth power tube, the ninth power tube, the tenth power tube and the eleventh power tube in the low voltage difference linear regulator with an embedded reference high loop gain, a pseudo push-pull stage is formed at the gate of the adjustment power tube to form a first loop, thereby increasing the slew rate; A second loop is constructed by a first load tube, a second load tube and a fourth power tube in a low-dropout linear regulator with an embedded reference high loop gain, so that the second loop directly biases the output voltage, making the output voltage insensitive to PVT changes; The transfer function for the global loop is as follows: The overall DC gain is: The poles are: Zero point is: Among them, ω p1 is the main pole, ω p2 is the secondary pole, ω p3 With ω p4 are other poles outside the bandwidth, z1 is the zero point, ω p3 With ω p4 Outside the bandwidth does not affect the phase margin; where β is the feedback resistor voltage divider coefficient, g mi For MOS tube M i The transconductance, g di For MOS tube M i The conductivity, C out is the output capacitance, C x is the compensation capacitor, C P is the gate capacitance of the power tube MP, C m is the Miller compensation capacitor, A ns is the pseudo push-pull stage gain, R b is the bias current source equivalent resistance, R o2 is the equivalent output resistance of the pseudo push-pull stage, R L is the load resistance, and s is the Laplace transform parameter.

10. An application of the low-dropout linear regulator with built-in reference and high loop gain as claimed in any one of claims 1 to 8 in an Internet of Things device.

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