A multi-stage high-voltage step-down circuit suitable for chip interior

Abstract

The present invention discloses a multi-stage high-voltage step-down circuit suitable for the inside of a chip, comprising: a first resistor, a second resistor, a third resistor, a fourth resistor, a first Zener tube, a first N-type high-voltage MOS tube, a second N-type high-voltage MOS tube and a third N-type high-voltage MOS tube. The present invention can reduce the medium voltage or high voltage VDD inputted into the chip to a low voltage outputted from LVDD to supply power to the low-voltage circuit inside the chip; the circuit structure is simple, and compared with the traditional high-voltage step-down circuit, the circuit structure is improved, and the step-by-step step-down is realized by using an enhanced high-voltage NMOS tube, and finally the low-voltage LVDD is outputted from the source end of the enhanced high-voltage NMOS tube adopting a source follower structure, thereby avoiding the dilemma of no suitable process selection caused by directly using a high-voltage NPN tube, and the circuit structure is simple, the versatility is strong, and the working voltage range is wider; it can be widely used in chips with medium voltage or high voltage wide input range such as artificial intelligence, robots and automotive electronics.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a multi-stage high-voltage step-down circuit suitable for use inside a chip. Background Art

[0002] In recent years, with the huge demand for electronic products in popular industries such as artificial intelligence (AI), robots, and automotive electronics, semiconductor integrated circuits have experienced rapid development, and the chip's operating voltage VDD has also increased from the original low voltage to medium voltage or even high voltage. In medium-voltage or high-voltage chips, due to the limitations of process and chip area, part of the circuit works at medium voltage or high voltage, and the other part of the circuit, such as digital logic circuits, works at low voltages of 5V and below. Circuits working at low voltages of 5V and below need to step down the medium-voltage or high-voltage VDD input to the chip to become a low-voltage voltage source LVDD before they can be used.

[0003] Traditional high voltage step-down circuit such as Figure 1 As shown, VDD is the chip input power supply, and LVDD is the low-voltage output after being stepped down by this structure. When the input VDD is low, LVDD synchronously and linearly follows the change of VDD; when VDD is large, the output voltage of LVDD is maintained at the voltage VZ of the Zener tube Z minus the VBE voltage of the NPN tube Q.

[0004] The above-mentioned traditional high-voltage step-down circuit has a simple structure, but has limitations in application. When VDD is high, a high-voltage NPN tube is required. There are high requirements for the voltage resistance of VCE, VCB, VEB of the NPN tube and each port to the substrate. There are few processes in China that include high-voltage NPN. This increases the difficulty of process selection for chip designers, so it is necessary to improve the structure and reduce the design difficulty. Summary of the invention

[0005] The object of the present invention is to provide a multi-stage high-voltage step-down circuit suitable for use inside a chip to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a multi-stage high-voltage step-down circuit suitable for use in a chip, comprising: a first resistor, a second resistor, a third resistor, a fourth resistor, a first Zener transistor, a first N-type high-voltage MOS transistor, a second N-type high-voltage MOS transistor, and a third N-type high-voltage MOS transistor;

[0007] The upper end of the first resistor is connected to the input voltage VDD, the lower end is connected to the negative electrode of the first Zener tube, and the positive electrode of the first Zener tube is connected to GND;

[0008] The upper end of the second resistor is connected to the input voltage VDD, the lower end is connected to the upper end of the third resistor, the lower end of the third resistor is connected to the upper end of the fourth resistor, and the lower end of the fourth resistor is connected to the negative electrode of the first Zener tube;

[0009] The drain end of the first N-type high-voltage MOS tube is connected to the input voltage VDD, the gate end is connected to the upper end of the third resistor, and the source end is connected to the drain end of the second N-type high-voltage MOS tube; the gate end of the second N-type high-voltage MOS tube is connected to the upper end of the fourth resistor, and the source end is connected to the drain end of the third N-type high-voltage MOS tube; the gate end of the third N-type high-voltage MOS tube is connected to the negative electrode of the first Zener tube, and the source end is connected to the output LVDD.

[0010] In one implementation, the first N-type high-voltage MOS transistor, the second N-type high-voltage MOS transistor, and the third N-type high-voltage MOS transistor are all enhancement-type high-voltage NMOS transistors.

[0011] The present invention provides a multi-stage high-voltage step-down circuit suitable for the inside of a chip. By improving the structure, an enhanced high-voltage NMOS tube is used to realize step-by-step voltage reduction. Finally, a low-voltage LVDD is output from the source end of the enhanced high-voltage NMOS tube with a source follower structure, thereby avoiding the dilemma of no suitable process to be selected when directly using a high-voltage NPN tube. The medium-voltage or high-voltage VDD input to the chip can be reduced to a low voltage and output from the LVDD to supply power to the low-voltage circuit inside the chip. The circuit structure is simple, the versatility is strong, and the operating voltage range is wider. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is the internal high voltage step-down circuit diagram of a traditional chip;

[0013] Figure 2 The multi-stage high-voltage step-down circuit suitable for the inside of a chip proposed by the present invention;

[0014] Figure 3 This is a schematic diagram of the working waveform of the multi-stage high-voltage step-down circuit suitable for use inside a chip proposed by the present invention. DETAILED DESCRIPTION

[0015] The following is a further detailed description of a multi-stage high-voltage step-down circuit suitable for use in a chip proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0016] The present invention provides a multi-stage high-voltage step-down circuit suitable for the inside of a chip, which can reduce the medium voltage or high voltage VDD input to a low voltage and output it from LVDD to power the low voltage circuit inside the chip. The circuit structure of the present invention is also relatively simple. Compared with the traditional high-voltage step-down circuit, by improving the circuit structure, the enhanced high-voltage NMOS tube is used to achieve step-by-step voltage reduction, and finally the low-voltage LVDD is output from the source end of the enhanced high-voltage NMOS tube with a source follower structure, avoiding the dilemma of no suitable process selection caused by directly using a high-voltage NPN tube. It has strong versatility and a wider operating voltage range, and can be widely used in chips with medium voltage or high voltage wide input ranges such as artificial intelligence, robots, and automotive electronics.

[0017] The specific structure of the present invention is as follows Figure 2 As shown, it is composed of a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first Zener transistor Z1, a first N-type high-voltage MOS transistor HVN1, a second N-type high-voltage MOS transistor HVN2 and a third N-type high-voltage MOS transistor HVN3;

[0018] The upper end of the first resistor R1 is connected to the input voltage VDD, the lower end is connected to the negative electrode of the first Zener tube Z1, and the positive electrode of the first Zener tube Z1 is connected to GND; the upper end of the second resistor R2 is connected to the input voltage VDD, the lower end is connected to the upper end of the third resistor R3, the lower end of the third resistor R3 is connected to the upper end of the fourth resistor R4, and the lower end of the fourth resistor R4 is connected to the negative electrode of the first Zener tube Z1; the drain end of the first N-type high-voltage MOS tube HVN1 is connected to the input voltage VDD, the gate end is connected to the upper end of the third resistor R3, and the source end is connected to the drain end of the second N-type high-voltage MOS tube HVN2; the gate end of the second N-type high-voltage MOS tube HVN2 is connected to the upper end of the fourth resistor R4, and the source end is connected to the drain end of the third N-type high-voltage MOS tube HVN3; the gate end of the third N-type high-voltage MOS tube HVN3 is connected to the negative electrode of the first Zener tube Z1, and the source end is connected to the output LVDD. The first N-type high-voltage MOS transistor HVN1 , the second N-type high-voltage MOS transistor HVN2 , and the third N-type high-voltage MOS transistor HVN3 are all enhanced high-voltage NMOS transistors.

[0019] The detailed working process of the present invention is as follows:

[0020] like Figure 2As shown, the second resistor R2, the third resistor R3 and the fourth resistor R4 are connected in series and then connected in parallel with the first resistor R1 to form a current limiting resistor of the first Zener tube Z1. At the same time, the second resistor R2, the third resistor R3, the fourth resistor R4 and the first Zener tube Z1 are connected in series to lead out nodes a, b and c to provide gate bias voltage for the first N-type high-voltage MOS tube HVN1, the second N-type high-voltage MOS tube HVN2 and the third N-type high-voltage MOS tube HVN3. The first N-type high-voltage MOS tube HVN1, the second N-type high-voltage MOS tube HVN2 and the third N-type high-voltage MOS tube HVN3 are enhancement MOS tubes, and the threshold voltages are all V TH_HVN The three MOS tubes are designed with a source follower structure. The source voltage of each MOS tube is approximately equal to its gate voltage minus a threshold voltage, which realizes the step-by-step voltage reduction of the input high voltage VDD, so that the high voltage is reasonably distributed on each MOS tube, reducing the voltage resistance requirements of each port of the MOS tube, and further reducing the requirements for the process. Even if a thin-gate-oxide N-type high-voltage MOS tube is used, the voltage reduction function can be realized, which greatly expands the overall input operating voltage of the chip.

[0021] The output impedance of the source follower structure is approximately equal to 1 / gm, and has good driving capability.

[0022] When the input voltage VDD is low and the first Zener tube Z1 does not break down, the current flowing through the Zener tube is almost 0, and the Zener tube is equivalent to an open circuit state. Therefore, the output voltage LVDD of the high-voltage buck circuit is approximately:

[0023] V LVDD ≈V DD -V TH_HVN

[0024] When the input voltage VDD is high and the first Zener diode Z1 breaks down, the voltage at node c is equal to the breakdown voltage of the Zener diode, that is, Vc = V Z1 ,

[0025] Therefore, the current I1 flowing through resistors R2, R3 and R4 is:

[0026]

[0027] The voltage V at node a a for:

[0028] V a =V DD -(I1*R2)

[0029] Then the source voltage V of the first high-voltage N-type MOS transistor HVN1 is s_HVN1 for:

[0030] V s_HVN1 =Va -V TH_HVN

[0031] The voltage at node b is V b for:

[0032] V b =V DD -[I1*(R2+R3)]

[0033] Then the source voltage V of the second high-voltage N-type MOS transistor HVN2 is s_HVN2 for:

[0034] V s_HVN2 =V b -V TH_HVN

[0035] When the first Zener diode Z1 breaks down, the voltage at node c is equal to the breakdown voltage of the Zener diode, that is, Vc = V Z1 ,

[0036] Then the source voltage of the third high-voltage N-type MOS transistor HVN3, that is, the final output LVDD of the high-voltage step-down circuit is:

[0037] V LVDD =V Z1 -V TH_HVN

[0038] The detailed working process of the present invention is as follows Figure 3 As shown, when the chip input voltage VDD is low and the Zener tube has not broken down, LVDD approximately changes linearly with VDD; as the VDD input becomes higher and the Zener tube breaks down, LVDD no longer changes linearly with VDD, but remains at a preset value.

[0039] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A multi-stage high-voltage step-down circuit suitable for use inside a chip, characterized in that: include: A first resistor, a second resistor, a third resistor, a fourth resistor, a first Zener transistor, a first N-type high-voltage MOS transistor, a second N-type high-voltage MOS transistor, and a third N-type high-voltage MOS transistor; The upper end of the first resistor is connected to the input voltage VDD, the lower end is connected to the negative electrode of the first Zener tube, and the positive electrode of the first Zener tube is connected to GND; The upper end of the second resistor is connected to the input voltage VDD, the lower end is connected to the upper end of the third resistor, the lower end of the third resistor is connected to the upper end of the fourth resistor, and the lower end of the fourth resistor is connected to the negative electrode of the first Zener tube; The drain end of the first N-type high-voltage MOS tube is connected to the input voltage VDD, the gate end is connected to the upper end of the third resistor, and the source end is connected to the drain end of the second N-type high-voltage MOS tube; the gate end of the second N-type high-voltage MOS tube is connected to the upper end of the fourth resistor, and the source end is connected to the drain end of the third N-type high-voltage MOS tube; the gate end of the third N-type high-voltage MOS tube is connected to the negative electrode of the first Zener tube, and the source end is connected to the output LVDD.

2. The multi-stage high-voltage step-down circuit suitable for use inside a chip as claimed in claim 1, characterized in that: The first N-type high-voltage MOS transistor, the second N-type high-voltage MOS transistor and the third N-type high-voltage MOS transistor are all enhancement-type high-voltage NMOS transistors.

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