Soft start circuit and linear voltage regulator

Abstract

The invention discloses a soft start circuit and a linear voltage regulator. The soft start circuit comprises a voltage generating circuit, a first current generating circuit, a second current generating circuit, an operational circuit and an output circuit. The voltage generating circuit generates a preset voltage which changes along with the input voltage and reaches a target value; the first current generating circuit is used for generating first current based on preset voltage; the second current generating circuit generates a second current based on the preset voltage and generates an adjusting current based on the preset voltage; the operation circuit performs operation on the first current and the second current to generate third current; the output circuit generates a fourth current based on the input voltage, and generates a control current based on the preset voltage, the third current, and the fourth current to adjust the output voltage. According to the soft start circuit, it is guaranteed that in the power-on process, the voltage margin in the chip is enough, output oscillation of the chip during slow power-on is not caused, the controllable power-on rate of the output voltage is obtained, and the strong dependence on the technology and the like is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a soft start circuit and a linear voltage stabilizer. Background Art

[0002] Power management chips are analog chips, and are the power supply heart of electronic devices. They are responsible for the power conversion, distribution, and detection functions required by electronic devices. The quality of their performance has a direct impact on the performance and reliability of electronic products. They are widely used in various electronic products and are one of the largest market segments for analog chips. LDO (Low dropout regulator) is a major component of power management chips, and the soft start circuit is a necessary circuit in the LDO power-on startup process. If there is no soft start circuit, voltage overshoot will occur during the power-on process, causing damage to the subsequent circuits.

[0003] Figure 1 This is a typical application scenario of 3PIN (pin) LDO. The circuit consists of a regulator (regulation) loop and an EA (operational amplifier) ​​main loop. The regulator loop controls the input voltage VIN-output voltage VOUT to a stable value; the EA main loop controls the output voltage VOUT to be the same as the internal reference voltage VREF. The selector MUX determines the working loop required by the chip based on the output voltage VOUT. When the power is just turned on, the regulator loop ensures that there is enough voltage headroom inside the chip; after the power is turned on, the main loop ensures that the chip has sufficient performance during normal operation.

[0004] The existing 3PIN LDO only supports tantalum capacitors (load capacitors CL) with large ESR (equivalent series resistance). The regulator loop and EA main loop jointly drive the power tube PowerMOS to ensure the loop stability requirements. When power is on, the soft-start rate of the output voltage VOUT can be controlled by controlling the output current of the regulator loop. Figure 1 In order to improve the loop stability of the circuit, a buffer is required to drive the power tube PowerMOS. However, the parasitic capacitance Cgg of the buffer is much smaller than the parasitic capacitance of the power tube PowerMOS, so the soft-start rate of the output voltage cannot be controlled by adjusting the regulator loop output current.

[0005] The traditional 4PIN LDO clamps the output voltage VOUT and the reference voltage VREF to the same voltage through an operational amplifier, and controls the power-on rate of the reference voltage VREF through a large resistor R and capacitor C to control the power-on rate of the output voltage VOUT. The working principle of the regulator loop is to clamp the output voltage VOUT and the input voltage VIN to a fixed voltage difference, and draw current from the input voltage VIN during operation. If a large resistor is used, a large voltage difference will be generated, affecting the circuit performance; if a large capacitor is used, it will waste a lot of area. Therefore, a new soft-start circuit is proposed for the 3PIN LDO that supports ESR-free (equivalent series resistance compensation).

[0006] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0007] The purpose of the present invention is to provide a soft start circuit and a linear voltage regulator, which meet the requirements of supporting ESR-free function. The load capacitor can be selected from ceramic capacitors, tantalum capacitors, and electrolytic capacitors. The current difference is used to complete the soft start of the output voltage when power is turned on. Compared with the traditional RC soft start circuit, it saves layout area and improves circuit performance.

[0008] To achieve the above objective, a specific embodiment of the present invention provides a soft start circuit for a linear regulator, the soft start circuit comprising: a voltage generating circuit, a first current generating circuit, a second current generating circuit, an operation circuit and an output circuit.

[0009] The voltage generating circuit is used to generate a preset voltage that follows the input voltage change of the linear regulator and reaches a target value; the first current generating circuit is used to generate a first current based on the preset voltage and the output voltage; the second current generating circuit includes a first current generating unit and a regulating unit, the first current generating unit is connected to the preset voltage to generate a second current based on the preset voltage, the regulating unit is connected to the preset voltage to generate a time-varying regulating current based on the preset voltage, and the regulating unit is connected to the first current generating unit to regulate the second current based on the regulating current; the operation circuit is connected to the first current generating circuit and the first current generating unit, and is used to operate the first current and the second current to generate a third current; the output circuit is connected to the input voltage, the preset voltage and the operation circuit, and is used to generate a fourth current based on the input voltage, and generate a control current based on the third current and the fourth current while controlling the preset voltage to adjust the output voltage of the linear regulator.

[0010] In one or more embodiments of the present invention, the voltage generating circuit includes a junction field effect transistor, the control end of the junction field effect transistor is connected to a reference voltage, the second end of the junction field effect transistor is connected to an input voltage, and the voltage at the first end of the junction field effect transistor follows the input voltage of the linear regulator and reaches a preset value.

[0011] In one or more embodiments of the present invention, the first current generating circuit includes a first resistor and a first current mirror unit, the first end of the first resistor is used to receive a preset voltage, the second end of the first resistor is connected to the first current mirror unit, and the first current mirror unit is used to mirror the current generated by the preset voltage on the first resistor to output a first current.

[0012] In one or more embodiments of the present invention, the first current generating unit includes a second resistor and a second current mirror unit, the first end of the second resistor is used to receive a preset voltage, the second end of the second resistor is connected to the second current mirror unit, and the second current mirror unit is used to mirror the current generated by the preset voltage on the first resistor to output a second current.

[0013] In one or more embodiments of the present invention, the regulating unit includes a current unit, a capacitor, a second current generating unit and a third current mirror unit, the current unit is used to provide a charging current, the first end of the capacitor is connected to the second current unit to generate a charging voltage that varies with time based on the charging current, the second end of the capacitor is connected to a reference voltage, the second current generating unit is connected to the first end of the capacitor to generate a current that varies with the charging voltage based on the charging voltage, and the third current mirror unit is connected to the second current generating unit to mirror the current generated by the second current generating unit and output a regulating current.

[0014] In one or more embodiments of the present invention, the second current generating unit includes a fourteenth transistor and a third resistor, the control end of the fourteenth transistor is connected to the first end of the capacitor, the first end of the fourteenth transistor is connected to the first end of the third resistor, the second end of the third resistor is connected to the reference voltage, and the second end of the fourteenth transistor is connected to the third current mirror unit.

[0015] In one or more embodiments of the present invention, the operation circuit includes a fourth current mirror unit, which is connected to the first current generating circuit and the first current generating unit to operate the first current and the second current to generate a third current.

[0016] In one or more embodiments of the present invention, the operation circuit includes a redundant protection unit, which is connected to the fourth current mirror unit and the output circuit, and is used to buffer the third current generated by the fourth current mirror unit.

[0017] In one or more embodiments of the present invention, the redundant protection unit includes a first operation unit and a second operation unit, the first operation unit is connected to the fourth current mirror unit, the first operation unit is used to operate the current generated by the fourth current mirror unit and the first reference current to generate an intermediate current, the second operation unit is connected to the first operation unit and the output circuit, and the second operation unit is used to operate the intermediate current and the second reference current to generate a third current.

[0018] In one or more embodiments of the present invention, the first operation unit includes a first current source, a seventh transistor and an eighth transistor, the first current source is used to generate a first reference current, a first end of the first current source is connected to a preset voltage, a second end of the first current source is connected to a second end of the seventh transistor and a fourth current mirror unit, a second end of the seventh transistor is connected to a control end of the seventh transistor and a control end of the eighth transistor, and a second end of the eighth transistor is connected to the second operation unit; and / or

[0019] The second operation unit includes a second current source, a ninth transistor and a tenth transistor, the second current source is used to generate a second reference current, the first end of the second current source is connected to a preset voltage, the second end of the second current source is connected to the first operation unit and the second end of the ninth transistor, the second end of the ninth transistor is connected to the control end of the ninth transistor and the control end of the tenth transistor, the second end of the tenth transistor is connected to the output circuit, and the second end of the tenth transistor is used to generate a third current.

[0020] In one or more embodiments of the present invention, the output circuit includes an output tube and a third current source, the first end of the third current source is connected to the input voltage, the third current source is used to generate a fourth current, the control end of the output tube is connected to a preset voltage, the first end of the output tube is connected to the operation circuit, and the second end of the output tube is connected to the second end of the third current source to form a control node for generating a control current.

[0021] The invention also discloses a linear voltage stabilizer, comprising the soft start circuit.

[0022] Compared with the prior art, the soft start circuit and the linear voltage regulator of the present invention ensure that the voltage margin / margin (headroom) inside the chip is sufficient during the power-on process, and the output oscillation of the chip during slow power-on will not be caused; the soft start circuit and the linear voltage regulator of the present invention obtain a controllable output voltage power-on rate, and reduce the strong dependence on the process and the process design kit (PDK); the soft start circuit and the linear voltage regulator of the present invention adopt a method of charging from the upper plate of the capacitor to the inside to have a high power supply rejection ratio (PSRR), and avoid the output voltage oscillation caused by power supply jitter during power-on; the soft start circuit and the linear voltage regulator of the present invention only need to use one high-voltage output tube, which greatly saves the layout area and improves the circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 The circuit diagram of the linear regulator in the prior art is shown in FIG.

[0025] Figure 2 4 is a circuit schematic diagram of a soft start circuit in an embodiment. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0027] "Coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0028] In the detailed description of the specification, reference is made to the accompanying drawings forming a part thereof, wherein like reference numerals refer to like parts throughout, and wherein are shown by way of exemplary embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered in a limiting sense.

[0029] The various operations in the specification may be described in turn as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0030] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0031] Various components and devices may be referred to or shown in the singular form herein (e.g., "transistor," "transistor," "switch," etc.), but this is merely for ease of discussion, and any element referred to in the singular form may include multiple such elements in accordance with the teachings herein.

[0032] The specification describes the use of the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of the present disclosure are synonymous.

[0033] like Figure 2 As shown, a soft start circuit in an embodiment of the present invention is used for a linear regulator (that is, the soft start circuit can be Figure 1 The soft start circuit includes a voltage generating circuit 10, a first current generating circuit 20, a second current generating circuit 30, an operation circuit 40 and an output circuit 50.

[0034] The voltage generating circuit 10 is used to generate a following linear regulator (refer to Figure 1 ) changes and reaches a preset voltage PREVDD of a target value. In one embodiment, the value of the preset voltage PREVDD increases as the input voltage VIN increases and eventually reaches the target value.

[0035] The first current generating circuit 20 is configured to generate a first current Ia based on a preset voltage PREVDD and an output voltage VOUT.

[0036] In one embodiment, the second current generating circuit 30 includes a first current generating unit 31 and a regulating unit 32. The first current generating unit 31 is connected to a preset voltage PREVDD to generate a second current Ib based on the preset voltage PREVDD, the regulating unit 32 is connected to the preset voltage PREVDD to generate a time-varying regulating current It based on the preset voltage PREVDD, and the regulating unit 32 is connected to the first current generating unit 31 to regulate the second current Ib based on the regulating current It.

[0037] The operation circuit 40 is connected to the first current generating circuit 20 and the first current generating unit 31 to form a node SS. The operation circuit 40 is used to operate the first current Ia and the second current Ib to generate the third current Ic.

[0038] The output circuit 50 is connected to the input voltage VIN, the preset voltage PREVDD and the operation circuit 40. The output circuit 50 is used to generate a fourth current Id based on the input voltage VIN, and to generate a control current Iout based on the third current Ic and the fourth current Id while controlling the preset voltage PREVDD to adjust the output voltage VOUT of the linear regulator.

[0039] Specifically, Figure 2 As shown, the voltage generating circuit 10 includes a junction field effect transistor J1, the control end of the junction field effect transistor J1 is connected to the reference voltage ADJ, the second end of the junction field effect transistor J1 is connected to the input voltage VIN, and the voltage of the first end of the junction field effect transistor J1 follows the input voltage VIN of the linear regulator and reaches a preset value. In one embodiment, the junction field effect transistor J1 is an N-channel junction field effect transistor, the first end of the junction field effect transistor J1 is the source, the second end of the junction field effect transistor J1 is the drain, the control end of the junction field effect transistor J1 is the gate, and the reference voltage ADJ is Figure 1 In other embodiments, the voltage generating circuit 10 may be other circuits, such as a linear regulator LDO.

[0040] like Figure 2 As shown, the first current generating circuit 20 includes a first resistor R1 and a first current mirror unit, wherein the first end of the first resistor R1 is connected to the first end of the junction field effect transistor J1 for receiving a preset voltage PREVDD, and the second end of the first resistor R1 is connected to the first current mirror unit, and the first current mirror unit is used to mirror the current generated by the preset voltage PREVDD on the first resistor R1 and output the first current Ia. In other embodiments, the first current generating circuit 20 may be other circuits.

[0041] In one embodiment, the first current mirror unit includes a first transistor M1 and a second transistor M2, wherein a first end of the first transistor M1 and a first end of the second transistor M2 (connected to the output end of the linear regulator) are used to receive the output voltage VOUT, a second end of the first transistor M1 is connected to a second end of the first resistor R1, a control end of the first transistor M1 is connected to a second end of the first transistor M1 and a control end of the second transistor M2, and a second end of the second transistor M2 is connected to the operation circuit 40 and the first current generating unit 31 to form a node SS. In other embodiments, the first current mirror unit may be other circuits.

[0042] like Figure 2 As shown, the first current generating unit 31 includes a second resistor R2 and a second current mirror unit, the first end of the second resistor R2 is connected to the first end of the junction field effect transistor J1 for receiving the preset voltage PREVDD, the second end of the second resistor R2 is connected to the second current mirror unit, and the second current mirror unit is used to mirror the current generated by the preset voltage PREVDD on the first resistor R1 and output the second current Ib. In other embodiments, the first current generating unit 31 can be other circuits.

[0043] In one embodiment, the second current mirror unit includes a sixteenth transistor M16, an eighteenth transistor M18, a seventeenth transistor M17, and a nineteenth transistor M19, wherein the first end of the sixteenth transistor M16 and the first end of the eighteenth transistor M18 are connected to the reference voltage ADJ, the second end of the eighteenth transistor M18 is connected to the second end of the second resistor R2, the control end of the sixteenth transistor M16 is connected to the second end of the sixteenth transistor M16 and the control end of the eighteenth transistor M18, and the second end of the sixteenth transistor M16 is connected to the adjustment unit 32 and the second end of the seventeenth transistor M17. The first end of the seventeenth transistor M17 and the first end of the nineteenth transistor M19 are connected to the preset voltage PREVDD, the control end of the seventeenth transistor M17 is connected to the second end of the seventeenth transistor M17 and the control end of the nineteenth transistor M19, and the second end of the nineteenth transistor M19 is connected to the second end of the second transistor M2 and the operation circuit 40 to form a node SS. In other embodiments, the second current mirror unit may be other circuits.

[0044] The sixteenth transistor M16 and the eighteenth transistor M18 form a current mirror unit, the seventeenth transistor M17 and the nineteenth transistor M19 form another current mirror unit, the current on the second resistor R2 is mirrored by the sixteenth transistor M16 and the eighteenth transistor M18 and is subtracted from the adjustment current It to obtain the second current Ib on the seventeenth transistor M17 and the nineteenth transistor M19, thereby achieving regulation of the second current Ib based on the adjustment current It.

[0045] like Figure 2 As shown, the regulating unit 32 includes a current unit, a capacitor C1, a second current generating unit and a third current mirror unit, the current unit is used to provide a charging current Ic1, the first end of the capacitor C1 is connected to the second current unit to generate a charging voltage that varies with time based on the charging current Ic1, the second end of the capacitor C1 is connected to the reference voltage ADJ, the second current generating unit is connected to the first end of the capacitor C1 to generate a current that varies with the charging voltage based on the charging voltage, and the third current mirror unit is connected to the second current generating unit to mirror the current generated by the second current generating unit and output the regulating current It. In one embodiment, the charging current Ic1 is used to inject current into the capacitor C1 from the first end (upper plate) of the capacitor C1 to improve the power supply rejection ratio. In other embodiments, the regulating unit 32 can be other circuits, and the capacitor C1 can be charged by a transistor to draw current from the second end (lower plate) of the capacitor C1, but the power supply rejection ratio of this method is relatively poor.

[0046] In one embodiment, the current unit includes a fourth current source A4, an eleventh transistor M11 and a twelfth transistor M12, the first end of the fourth current source A4 is connected to the reference voltage ADJ, the control end of the eleventh transistor M11 is connected to the second end of the eleventh transistor M11 and the control end of the twelfth transistor M12, the first end of the eleventh transistor M11 and the first end of the twelfth transistor M12 are used to receive a preset voltage PREVDD, the second end of the twelfth transistor M12 is connected to the first end of the capacitor C1 and the second current generating unit, the eleventh transistor M11 and the twelfth transistor M12 constitute a current mirror unit, the fourth current source A4 generates a current and charges the capacitor C1 after being mirrored by the eleventh transistor M11 and the twelfth transistor M12. In other embodiments, the current unit may be other circuits.

[0047] In one embodiment, the second current generating unit includes a fourteenth transistor M14 and a third resistor R3, the control end of the fourteenth transistor M14 is connected to the first end of the capacitor C1 and the second end of the twelfth transistor M12, the first end of the fourteenth transistor M14 is connected to the first end of the third resistor R3, the second end of the third resistor R3 is connected to the reference voltage ADJ, and the second end of the fourteenth transistor M14 is connected to the third current mirror unit. In other embodiments, the second current generating unit may be other circuits.

[0048] In one embodiment, the third current mirror unit includes a thirteenth transistor M13 and a fifteenth transistor M15. The first end of the thirteenth transistor M13 and the first end of the fifteenth transistor M15 are connected to the preset voltage PREVDD, the control end of the thirteenth transistor M13 is connected to the second end of the thirteenth transistor M13 and the control end of the fifteenth transistor M15, the second end of the thirteenth transistor M13 is connected to the second end of the fourteenth transistor M14, and the second end of the fifteenth transistor M15 is connected to the second end of the sixteenth transistor M16 of the first current generating unit 31 and the second end of the seventeenth transistor M17. In other embodiments, the third current mirror unit can be other circuits.

[0049] like Figure 2 As shown, the operation circuit 40 includes a fourth current mirror unit and a redundant protection unit. The fourth current mirror unit is connected to the first current generating circuit 20 and the first current generating unit 31 to perform a difference operation on the first current Ia and the second current Ib to generate a current Ip. The redundant protection unit is connected to the fourth current mirror unit to buffer the current Ip to generate a third current Ic that varies with the current Ip. Further, the redundant protection unit operates the current Ip and the reference current to generate the third current Ic, thereby achieving the purpose of buffering and redundant protection. In other embodiments, the redundant protection unit may not be provided, and the current output by the fourth current mirror unit is the third current Ic.

[0050] In one embodiment, the fourth current mirror unit includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The first end of the third transistor M3 and the first end of the fourth transistor M4 are connected to a preset voltage PREVDD, the control end of the third transistor M3 is connected to the second end of the third transistor M3 and the control end of the fourth transistor M4, the second end of the third transistor M3 is connected to the second end of the second transistor M2 to form a node SS, the second end of the fourth transistor M4 is connected to the second end of the fifth transistor M5, the control end of the fifth transistor M5, and the control end of the sixth transistor M6, the first end of the fifth transistor M5 and the first end of the sixth transistor M6 are connected to a reference voltage ADJ, the second end of the sixth transistor M6 generates a current Ip, and the second end of the sixth transistor M6 is connected to the redundant protection unit. In other embodiments, the fourth current mirror unit can be other circuits.

[0051] In one embodiment, the redundant protection unit includes a first operation unit and a second operation unit, the first operation unit is connected to the fourth current mirror unit, the first operation unit is used to operate the current Ip generated by the fourth current mirror unit and the first reference current Iref1 to generate an intermediate current, the second operation unit is connected to the first operation unit and the output circuit 50, and the second operation unit is used to operate the intermediate current and the second reference current Iref2 to generate a third current Ic. In other embodiments, the redundant protection unit can be other circuits.

[0052] The first operation unit includes a first current source A1, a seventh transistor M7, and an eighth transistor M8, and the second operation unit includes a second current source A2, a ninth transistor M9, and a tenth transistor M10. The first current source A1 is used to generate a first reference current Iref1, and the second current source A2 is used to generate a second reference current Iref2. The first end of the first current source A1 and the first end of the second current source A2 are connected to a preset voltage PREVDD, the second end of the first current source A1 is connected to the second end of the seventh transistor M7 and the second end of the sixth transistor M6, the second end of the seventh transistor M7 is connected to the control end of the seventh transistor M7 and the control end of the eighth transistor M8, and the second end of the eighth transistor M8 generates an intermediate current. The second end of the eighth transistor M8 is connected to the second end of the second current source A2 and the second end of the ninth transistor M9, the second end of the ninth transistor M9 is connected to the control end of the ninth transistor M9 and the control end of the tenth transistor M10, the first end of the seventh transistor M7, the first end of the eighth transistor M8, the first end of the ninth transistor M9, and the first end of the tenth transistor M10 are connected to the reference voltage ADJ, the second end of the tenth transistor M10 is used to generate the third current Ic, and the second end of the tenth transistor M10 is connected to the output circuit 50. In other embodiments, the first operation unit and / or the second operation unit may be other circuits.

[0053] like Figure 2 As shown, the output circuit 50 includes an output tube NED1 and a third current source A3, a first end of the third current source A3 is connected to the input voltage VIN, the third current source A3 is used to generate a fourth current Id, a control end of the output tube NED1 is connected to a preset voltage PREVDD, a first end of the output tube NED1 is connected to a second end of the tenth transistor M10 of the operation circuit 40, a second end of the output tube NED1 is connected to a second end of the third current source A3 to form a control node VEA for generating a control current Iout, and the control node VEA is connected to Figure 1 The input end of the selector MUX is connected.

[0054] In one embodiment, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the fourteenth transistor M14, the sixteenth transistor M16, the eighteenth transistor M18 and the output transistor NED1 are N-channel MOS transistors; the third transistor M3, the fourth transistor M4, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fifteenth transistor M15, the seventeenth transistor M17 and the nineteenth transistor M19 are P-channel MOS transistors. In other embodiments, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the fourteenth transistor M14, the sixteenth transistor M16, the eighteenth transistor M18 and the output transistor NED1 may be P-channel MOS transistors; the third transistor M3, the fourth transistor M4, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fifteenth transistor M15, the seventeenth transistor M17 and the nineteenth transistor M19 may be N-channel MOS transistors.

[0055] A first end of the first transistor M1, a first end of the second transistor M2, a first end of the fifth transistor M5, a first end of the sixth transistor M6, a first end of the seventh transistor M7, a first end of the eighth transistor M8, a first end of the ninth transistor M9, a first end of the tenth transistor M10, a first end of the fourteenth transistor M14, a first end of the sixteenth transistor M16, a first end of the eighteenth transistor M18, a first end of the output tube NED1, a first end of the third transistor M3, a first end of the fourth transistor M4, a first end of the eleventh transistor M11, a first end of the twelfth transistor M12, a first end of the thirteenth transistor M13, a first end of the fifteenth transistor M15, a first end of the seventeenth transistor M17 and a first end of the nineteenth transistor M19 are sources.

[0056] The second end of the first transistor M1, the second end of the second transistor M2, the second end of the fifth transistor M5, the second end of the sixth transistor M6, the second end of the seventh transistor M7, the second end of the eighth transistor M8, the second end of the ninth transistor M9, the second end of the tenth transistor M10, the second end of the fourteenth transistor M14, the second end of the sixteenth transistor M16, the second end of the eighteenth transistor M18, the second end of the output tube NED1, the second end of the third transistor M3, the second end of the fourth transistor M4, the second end of the eleventh transistor M11, the second end of the twelfth transistor M12, the second end of the thirteenth transistor M13, the second end of the fifteenth transistor M15, the second end of the seventeenth transistor M17 and the second end of the nineteenth transistor M19 are drains.

[0057] The control end of the first transistor M1, the control end of the second transistor M2, the control end of the fifth transistor M5, the control end of the sixth transistor M6, the control end of the seventh transistor M7, the control end of the eighth transistor M8, the control end of the ninth transistor M9, the control end of the tenth transistor M10, the control end of the fourteenth transistor M14, the control end of the sixteenth transistor M16, the control end of the eighteenth transistor M18, the control end of the output transistor NED1, the control end of the third transistor M3, the control end of the fourth transistor M4, the control end of the eleventh transistor M11, the control end of the twelfth transistor M12, the control end of the thirteenth transistor M13, the control end of the fifteenth transistor M15, the control end of the seventeenth transistor M17 and the control end of the nineteenth transistor M19 are gates.

[0058] In one embodiment, the output transistor NED1 is a high-voltage transistor, and the other transistors are low-voltage transistors, thereby greatly saving layout area.

[0059] Utilizing the working characteristics of the junction field effect transistor J1, when VIN-ADJ<-VP (Vp is the pinch-off voltage of the junction field effect transistor J1, VP<0V), the junction field effect transistor J1 is in the resistance working area, at which time the preset voltage VPREVDD≈VIN; when VIN-ADJ>-VP, the junction field effect transistor J1 is in the saturation amplification area, VPREVDD≈ADJ-VP.

[0060] When the input voltage VIN is slow power-up and Figure 1 When the circuit control chip is in the regulator loop control, Figure 2 The loop composed of the voltage generating circuit 10, the first current generating circuit 20, the operation circuit 40 and the output circuit 50 will control the preset voltage PREVDD to slowly rise with the input voltage VIN, and the output tube NED1 to slowly turn on, so that the output voltage VOUT is slowly powered on with the input voltage VIN, and the voltage difference between the output voltage VOUT and the input voltage VIN is a constant value VPR. Figure 2 Iref1=Iref2=Id=I can be set in Figure 2 The size relationship (width-to-length ratio W / L) of the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 in the embodiment can be set as follows:

[0061]

[0062] The third transistor M3 and the fourth transistor M4 have the same size. Therefore, when the loop is stable, IM1 (the current on the first transistor M1) = IM10 (the current on the tenth transistor M10) = I, and the constant value VPR is:

[0063] VPR=I*R1+V GSM1 ≈I*R1+V thM1

[0064] V GSM1 is the voltage between the gate and source of the first transistor M1, V thM1 is the turn-on voltage of the first transistor M1. By adjusting the resistance of the first resistor R1, a constant value VPR with zero temperature drift can be obtained.

[0065] When the input voltage VIN is fast power-on, Figure 1 The regulator loop will be used to control the output voltage VOUT to soft-start. The input voltage VIN rises quickly, causing the preset voltage PREVDD to rise quickly and stabilize at a target value (due to the characteristics of the junction field effect transistor J1, the target value will not be too large, and the target value is less than the input voltage VIN). The output tube NED1 opens quickly. When the voltage difference between the preset voltage PREVDD and the output voltage VOUT is large, the third current Ic on the tenth transistor M10 will be greater than the fourth current Id of the third current source A3. At this time, current will be drawn from the gate of the input tube of the buffer buffer. Since the parasitic capacitance Cgg of the buffer buffer is only about 1pF, if the output voltage VOUT power-on time is expected to reach the millisecond level, a picoampere-level current extraction is required, which will place higher requirements on the process, PDK, etc. Figure 2 The loop formed by the second current generating circuit 30 can reduce the circuit's dependence on the process by means of current soft start.

[0066] When the input voltage VIN is almost powered on, the power tube PowerMOS has not yet turned on, and the output voltage VOUT is still 0, the current on the first transistor M1 is:

[0067]

[0068] The voltage on the control terminal of the fourteenth transistor M14 is zero, and the second current Ib on the nineteenth transistor M19 is:

[0069]

[0070] V thM18 is the turn-on voltage of the eighteenth transistor M18, (W / L) M16 is the width-to-length ratio of the sixteenth transistor M16, (W / L) M17 is the width-to-length ratio of the seventeenth transistor M17, (W / L) M18 is the width-to-length ratio of the eighteenth transistor M18, (W / L) M19 is the width-to-length ratio of the nineteenth transistor M19.

[0071] At this time, the current on the third transistor M3 is:

[0072] I M3 =I a -I b

[0073] Correspondingly, by adjusting the ratio of each resistor and each transistor, it can be ensured that Id>Ic at this time, so that the control current Iout injected into the gate of the input tube of the buffer buffer is very large, the voltage on the control node VEA is equal to VIN, the regulator loop turns off the power tube PowerMOS, and the output voltage VOUT remains at 0.

[0074] After the input voltage VIN is powered on for a period of time, Figure 2 The fourth current source A4 also charges the capacitor C1 for a period of time. Figure 1 When the power-on reset circuit POR controls the second current generating circuit 30 to be enabled, the voltage at the control end of the fourteenth transistor M14 is slowly increased, the fourteenth transistor M14 is turned on and generates a current on the third resistor R3, and outputs the regulating current It through the fifteenth transistor M15, and the regulating current It is subtracted from the current on the second resistor R2, so that the second current Ib on the nineteenth transistor M19 is gradually reduced, and the current on the third transistor M3 is slowly increased, so that the third current Ic on the tenth transistor M10 is slowly increased, and after the third current Ic on the tenth transistor M10 increases to be greater than the fourth current Id, the voltage on the control node VEA is gradually reduced, the power tube PowerMOS is gradually turned on, and the output voltage VOUT is slowly powered on. The voltage rise rate of the control end of the fourteenth transistor M14 is:

[0075]

[0076] Wherein, IA4 is the current of the fourth current source A4.

[0077] The rising rate of the regulating current It on the fifteenth transistor M15 is:

[0078]

[0079] The falling rate of the second current Ib on the nineteenth transistor M19 is:

[0080]

[0081] Therefore, the rising rate of the third current Ic in the tenth transistor M10 is:

[0082]

[0083] Then the voltage drop rate on the control node VEA is:

[0084]

[0085] It can be seen from the above formula that by ensuring the matching of corresponding devices, as the voltage on the control node VEA decreases, the voltage at the control end of the power tube PowerMOS slowly decreases, and a controllable output voltage VOUT rising rate can be obtained.

[0086] In one embodiment, in order to prevent the first current Ia generated by the first current generating circuit 20 from being too large when power is on quickly, and the second current Ib generated by the first current generating unit 31 cannot be fully provided to the first current Ia, the current Ip generated by the fourth current mirror unit is also too large through the mirror relationship. When a redundant protection unit is not set, the third current Ic generated by the operation circuit 40 will become a large pull-down current much larger than the fourth current Id on the output circuit 50, so that the voltage of the control node VEA is pulled down, resulting in an overshoot of the output voltage VOUT. Therefore, a redundant protection unit is set to buffer the current Ip and provide redundant protection to prevent the above situation from occurring.

[0087] It should be noted that after the input voltage VIN is slowly powered on for a period of time, when the power-on reset circuit POR controls the second current generating circuit 30 to be enabled, the output voltage VOUT will also have a period of rapid rise, and at this time, the loop formed by the second current generating circuit 30 can also play a role in controlling the rising rate of the output voltage VOUT. After this period of rapid rise, the output voltage VOUT maintains a constant voltage difference VPR with the input voltage VIN to perform slow power-on.

[0088] The present invention also discloses a linear voltage stabilizer, comprising the above-mentioned soft start circuit. In one embodiment, the linear voltage stabilizer is as follows Figure 1 In the structure shown, the linear regulator includes a buffer, a selector MUX, a regulator loop, a power-on reset circuit POR, an operational amplifier EA, a power tube PowerMOS, a load capacitor CL and a voltage divider unit (composed of a first resistor RFB1 and a second resistor RFB2 connected in series), and the soft start circuit is the structure corresponding to the regulator loop.

[0089] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0090] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A soft start circuit, characterized in that: For a linear regulator, the soft start circuit comprises: A voltage generating circuit, used for generating a preset voltage that follows the input voltage change of the linear regulator and reaches a target value; A first current generating circuit, configured to generate a first current based on a preset voltage and an output voltage; A second current generating circuit, comprising a first current generating unit and a regulating unit, wherein the first current generating unit is connected to a preset voltage to generate a second current based on the preset voltage, the regulating unit is connected to the preset voltage to generate a time-varying regulating current based on the preset voltage, and the regulating unit is connected to the first current generating unit to regulate the second current based on the regulating current; an operation circuit connected to the first current generating circuit and the first current generating unit, and configured to operate the first current and the second current to generate a third current; and The output circuit is connected to the input voltage, the preset voltage and the operation circuit, and is used to generate a fourth current based on the input voltage, and to generate a control current based on the third current and the fourth current while controlling the preset voltage to adjust the output voltage of the linear regulator.

2. The soft start circuit according to claim 1, characterized in that: The voltage generating circuit includes a junction field effect transistor, a control end of the junction field effect transistor is connected to a reference voltage, a second end of the junction field effect transistor is connected to an input voltage, and a voltage at a first end of the junction field effect transistor follows the input voltage of a linear regulator and reaches a preset value.

3. The soft start circuit according to claim 1, characterized in that: The first current generating circuit includes a first resistor and a first current mirror unit, the first end of the first resistor is used to receive a preset voltage, the second end of the first resistor is connected to the first current mirror unit, and the first current mirror unit is used to mirror the current generated by the preset voltage on the first resistor to output a first current.

4. The soft start circuit according to claim 1, characterized in that: The first current generating unit includes a second resistor and a second current mirror unit, the first end of the second resistor is used to receive a preset voltage, the second end of the second resistor is connected to the second current mirror unit, and the second current mirror unit is used to mirror the current generated by the preset voltage on the first resistor to output a second current.

5. The soft start circuit according to claim 1, characterized in that: The regulating unit includes a current unit, a capacitor, a second current generating unit and a third current mirror unit. The current unit is used to provide a charging current. The first end of the capacitor is connected to the second current unit to generate a charging voltage that varies with time based on the charging current. The second end of the capacitor is connected to a reference voltage. The second current generating unit is connected to the first end of the capacitor to generate a current that varies with the charging voltage based on the charging voltage. The third current mirror unit is connected to the second current generating unit to mirror the current generated by the second current generating unit and output a regulating current.

6. The soft start circuit according to claim 5, characterized in that: The second current generating unit includes a fourteenth transistor and a third resistor, the control end of the fourteenth transistor is connected to the first end of the capacitor, the first end of the fourteenth transistor is connected to the first end of the third resistor, the second end of the third resistor is connected to the reference voltage, and the second end of the fourteenth transistor is connected to the third current mirror unit.

7. The soft start circuit according to claim 1, characterized in that: The operation circuit includes a fourth current mirror unit, and the fourth current mirror unit is connected to the first current generating circuit and the first current generating unit to operate the first current and the second current to generate a third current.

8. The soft start circuit according to claim 7, characterized in that: The operation circuit includes a redundant protection unit, which is connected to the fourth current mirror unit and the output circuit, and is used to buffer the third current generated by the fourth current mirror unit.

9. The soft start circuit according to claim 8, characterized in that: The redundant protection unit includes a first operation unit and a second operation unit, the first operation unit is connected to the fourth current mirror unit, the first operation unit is used to operate the current generated by the fourth current mirror unit and the first reference current to generate an intermediate current, the second operation unit is connected to the first operation unit and the output circuit, the second operation unit is used to operate the intermediate current and the second reference current to generate a third current.

10. The soft start circuit according to claim 9, characterized in that: The first operation unit includes a first current source, a seventh transistor and an eighth transistor, the first current source is used to generate a first reference current, a first end of the first current source is connected to a preset voltage, a second end of the first current source is connected to a second end of the seventh transistor and a fourth current mirror unit, a second end of the seventh transistor is connected to a control end of the seventh transistor and a control end of the eighth transistor, and a second end of the eighth transistor is connected to the second operation unit; and / or The second operation unit includes a second current source, a ninth transistor and a tenth transistor, the second current source is used to generate a second reference current, the first end of the second current source is connected to a preset voltage, the second end of the second current source is connected to the first operation unit and the second end of the ninth transistor, the second end of the ninth transistor is connected to the control end of the ninth transistor and the control end of the tenth transistor, the second end of the tenth transistor is connected to the output circuit, and the second end of the tenth transistor is used to generate a third current.

11. The soft start circuit according to claim 1, characterized in that: The output circuit includes an output tube and a third current source, wherein a first end of the third current source is connected to an input voltage, the third current source is used to generate a fourth current, a control end of the output tube is connected to a preset voltage, a first end of the output tube is connected to an operation circuit, and a second end of the output tube is connected to a second end of the third current source to form a control node for generating a control current.

12. A linear regulator, characterized in that: It comprises a soft start circuit as described in any one of claims 1 to 11.

Images