SSD data clearing method and device, computer equipment and storage medium

Abstract

The invention relates to an SSD (Solid State Disk) data clearing method and device, computer equipment and a storage medium. The SSD data clearing method comprises the following steps: receiving a plurality of data clearing requests, calculating the total information data volume of the plurality of data clearing requests, and detecting the available storage space of an SRAM (Static Random Access Memory); whether the available storage space is smaller than the total information data volume or not is judged, if the available storage space is smaller than the total information data volume, the priority of each data clearing request is determined, the priorities of the data clearing requests comprise the first priority and the second priority, and the data clearing requests are screened according to the priorities of the data clearing requests; executing a cache elimination algorithm on the SRAM, so that the residual storage space of the SRAM is not less than the total information data volume of the data clearing request of the first priority; writing the data clearing request of the first priority into the SRAM; and executing the data clearing request. The method and the device have the effect of improving the data clearing efficiency of the SSD when the capacity of the SRAM is relatively small or the data clearing requests are excessive.

Description

Technical Field

[0001] The present application relates to the technical field of SSD storage management, and in particular to an SSD data clearing method, device, computer equipment, and storage medium. Background Art

[0002] Currently, SSD, as a high-performance data storage device, is widely used in cloud computing, database, high-speed computing and other fields. Since SSD uses NAND flash memory as the main storage medium, its data storage management involves cache management, data clearing, garbage collection and other mechanisms to ensure efficient storage and reading performance.

[0003] Existing SSD data clearing methods usually rely on sequential scheduling, that is, writing data clearing requests one by one into the SRAM and executing data clearing operations. However, when the SRAM capacity is small or there are too many data clearing requests, it is necessary to wait for the SRAM to free up storage space before continuing to process new clearing requests, resulting in some data clearing requests that need to be processed in time not being processed, reducing data clearing efficiency. Summary of the invention

[0004] In order to solve the problem that the data clearing requests that need to be processed in time cannot be processed in time when the SRAM capacity is small or there are too many data clearing requests, the present application provides an SSD data clearing method, device, computer equipment and storage medium.

[0005] The above-mentioned invention objective of the present application is achieved through the following technical solutions: A method for clearing SSD data, the method for clearing SSD data is applicable to an SSD solid state drive, the SSD solid state drive has an SRAM and an auxiliary storage medium, the method for clearing SSD data comprises: Receiving multiple data clearing requests of a single data operation, calculating the total information data volume of the multiple data clearing requests, and detecting the available storage space of the SRAM; Determine whether the available storage space is less than the total amount of information data, if the available storage space is less than the total amount of information data, determine the priority of each of the data clearing requests, the priority of the data clearing request includes a first priority and a second priority, and screen the data clearing requests according to the priority of the data clearing request, wherein the first priority is higher than the second priority; Executing a cache elimination algorithm on the SRAM so that the remaining storage space of the SRAM is not less than the total information data volume of the data clearing request of the first priority; Writing the data clearing request of the first priority into the SRAM, and writing the data clearing request of the second priority into the auxiliary storage medium; The data clearing request is executed.

[0006] By adopting the above technical solution, by receiving multiple data clearing requests of a single data operation and calculating the total information data volume of the multiple data clearing requests, the storage space required for the multiple data clearing requests can be accurately evaluated before the data is cleared, so as to reasonably schedule the storage resources of the SRAM and avoid task blocking or delay caused by insufficient storage space; by detecting the available storage space of the SRAM and judging whether the available storage space is less than the total information data volume, the storage space status can be evaluated in advance before the data clearing request is written, so as to avoid the backlog of data clearing requests and improve the overall efficiency of the write operation; by determining the priority of the data clearing request and screening the data clearing request according to the priority, it can ensure that the data clearing request with high time sensitivity or related to system stability is executed first, so as to improve the execution efficiency of the data clearing request and reduce the performance degradation caused by the system resource competition; by executing the cache elimination algorithm, sufficient SRAM space is freed up to ensure that the first priority data clearing request can be executed smoothly, and the cache management can be optimized while ensuring the normal execution of high priority tasks, so as to improve the data clearing efficiency of the SSD.

[0007] In one example, the present application may be further configured as follows: the performing of a cache elimination algorithm on the SRAM includes: Obtaining access frequencies and access times of a plurality of write data blocks in the SRAM; Determine a cache elimination coefficient of a corresponding written data block in the SRAM according to the access frequency and the access time; Determining whether the cache elimination coefficient is not greater than a first preset cache elimination value; If the cache elimination coefficient is not greater than the first preset cache elimination value, executing the cache elimination algorithm on the corresponding write data block in the SRAM, the cache elimination algorithm including the LRU algorithm and the LFU algorithm; If the cache elimination coefficient is greater than the first preset cache elimination value, the data of the corresponding written data block in the SRAM is retained.

[0008] By adopting the above technical solution, by obtaining the access frequency and access time of multiple write data blocks in SRAM, the usage of data blocks can be accurately grasped, thereby providing basic data support for the cache management strategy and improving the rationality of cache elimination decisions; by calculating the cache elimination coefficient and judging whether it is not greater than the first preset cache elimination value, low-priority or low-frequency access data blocks can be effectively screened, thereby freeing up more cache space without affecting high-frequency data access, thereby improving the utilization rate of storage resources; by executing the cache elimination algorithm on qualified data blocks and adopting a strategy combining LRU and LFU, the access frequency and time factors can be taken into account, thereby ensuring that high-value data is retained in the write data block as much as possible, and clearing the write data blocks occupied by low-value data as much as possible, thereby freeing up enough SRAM space.

[0009] In one example, the present application may be further configured as follows: determining the cache elimination coefficient of the corresponding write data block in the SRAM according to the access frequency and the access time includes: The cache elimination coefficient is calculated by the formula:

[0010] The cache elimination coefficient is calculated, where C is the cache elimination coefficient, T is the access time, F is the access frequency, and α and β are weight coefficients.

[0011] By adopting the above technical solution, by calculating the cache elimination coefficient based on the access frequency and access time, the cache elimination algorithm executed on the written data block can be intelligently adjusted according to the historical access situation of the written data block, thereby optimizing the cache management of the SRAM and improving data access efficiency; by setting the weight parameters α and β, the access frequency and access time are balanced, and the cache elimination strategy can be flexibly adjusted in different application scenarios, thereby freeing up enough SRAM space as much as possible.

[0012] In one example, the present application may be further configured as follows: executing the cache elimination algorithm on the corresponding written data block in the SRAM includes: Determining whether the cache elimination coefficient is not greater than a second preset cache elimination value; If the cache elimination coefficient is not greater than the second preset cache elimination value, merging a plurality of corresponding written data blocks into a first data block group, and then executing the LRU algorithm on the first data block group; If the cache elimination coefficient is greater than the second preset cache elimination value, a plurality of corresponding written data blocks are merged into a second data block group, and then the LFU algorithm is executed on the second data block group.

[0013] By adopting the above technical solution, by judging whether the cache elimination coefficient is not greater than the second preset cache elimination value, the screening conditions can be further optimized before the data block is eliminated, so that low-value data blocks can be eliminated first when storage resources are tight, thereby improving the utilization efficiency of SRAM storage space.

[0014] In one example, the present application may be further configured as follows: determining the priority of each of the data clearing requests, the priority of the data clearing request including a first priority and a second priority, and screening the data clearing requests according to the priority of the data clearing request, including: Obtaining the creation time and execution deadline of the data clearing request; Determine the remaining execution time of the data clearing request according to the creation time and the execution deadline; Determine whether the remaining execution time is greater than a preset time value; If the remaining execution time is not greater than the preset time value, the priority of the corresponding data clearing request is determined as the first priority; If the remaining execution time is greater than the preset time value, the priority of the corresponding data clearing request is determined as the second priority.

[0015] By adopting the above technical solution, by obtaining the creation time and execution deadline of the data clearing request and calculating the remaining execution time, the urgency of the data clearing request can be accurately evaluated, thereby ensuring the rationality of task scheduling and improving resource allocation efficiency; by comparing the remaining execution time with the preset time value and determining the priority of the data clearing request according to the calculation result, it can ensure that time-sensitive tasks are executed first, thereby reducing data consistency problems caused by delayed processing and improving the data clearing efficiency of the SSD.

[0016] In one example, the present application may be further configured as follows: before calculating the total information data volume of the plurality of data clearing requests, the present application may further include: Detecting addresses of cleared data blocks pointed to by a plurality of the data clearing requests; Determining whether addresses of a plurality of cleared data blocks overlap; If the addresses of the plurality of cleared data blocks overlap, the corresponding data clearing requests are merged into a new data clearing request.

[0017] By adopting the above technical solution, by detecting the addresses of the cleared data blocks pointed to by multiple data clearing requests and judging whether there is overlap, repeated clearing operations can be avoided, thereby reducing unnecessary data reading and writing burdens and improving the data clearing efficiency of the SSD; by merging multiple data clearing requests pointing to the same data block into a new data clearing request, redundant requests can be reduced, thereby optimizing task scheduling and improving the execution efficiency of data clearing tasks.

[0018] The second object of the invention is achieved by the following technical solutions: An SSD data device, the SSD data device comprising: A request processing module, used for receiving multiple data clearing requests of a single data operation, and calculating the total information data volume of the multiple data clearing requests; A storage space management module, used to detect the available storage space of the SRAM and determine whether the available storage space is less than the total amount of information data; a priority allocation module, configured to determine the priority of each of the data clearing requests when the available storage space is less than the total amount of information data, and to screen the data clearing requests according to the priorities of the data clearing requests; A cache management module, used for executing a cache elimination algorithm on the SRAM so that the remaining storage space of the SRAM is not less than the total information data volume of the data clearing request of the first priority; A data writing module, used for writing the data clearing request of the first priority into the SRAM, and writing the data clearing request of the second priority into an auxiliary storage medium; The data clearing execution module is used to execute the data clearing request.

[0019] By adopting the above technical solution, by receiving multiple data clearing requests of a single data operation and calculating the total information data volume of the multiple data clearing requests, the storage space required for the multiple data clearing requests can be accurately evaluated before the data is cleared, so as to reasonably schedule the storage resources of the SRAM and avoid task blocking or delay caused by insufficient storage space; by detecting the available storage space of the SRAM and judging whether the available storage space is less than the total information data volume, the storage space status can be evaluated in advance before the data clearing request is written, so as to avoid the backlog of data clearing requests and improve the overall efficiency of the write operation; by determining the priority of the data clearing request and screening the data clearing request according to the priority, it can ensure that the data clearing request with high time sensitivity or related to system stability is executed first, so as to improve the execution efficiency of the data clearing request and reduce the performance degradation caused by the system resource competition; by executing the cache elimination algorithm, sufficient SRAM space is freed up to ensure that the first priority data clearing request can be executed smoothly, and the cache management can be optimized while ensuring the normal execution of high priority tasks, so as to improve the data clearing efficiency of the SSD.

[0020] The third objective of the present application is achieved through the following technical solutions: A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned SSD data clearing method when executing the computer program.

[0021] The fourth objective of the present application is achieved through the following technical solutions: A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned SSD data clearing method are implemented.

[0022] In summary, this application includes the following beneficial technical effects: 1. By receiving multiple data clearing requests for a single data operation and calculating the total information data volume of multiple data clearing requests, the storage space required for multiple data clearing requests can be accurately evaluated before data clearing, thereby reasonably scheduling the storage resources of SRAM and avoiding task blocking or delay caused by insufficient storage space; by detecting the available storage space of SRAM and judging whether the available storage space is less than the total information data volume, the storage space status can be evaluated in advance before the data clearing request is written, thereby avoiding the backlog of data clearing requests and improving the overall efficiency of write operations; by determining the priority of data clearing requests and screening data clearing requests according to the priority, it can ensure that data clearing requests with high time sensitivity or related to system stability are executed first, thereby improving the execution efficiency of data clearing requests and reducing the performance degradation caused by system resource competition; by executing the cache elimination algorithm, sufficient SRAM space is freed up to ensure that the first priority data clearing request can be executed smoothly, and the cache management can be optimized while ensuring the normal execution of high-priority tasks, thereby improving the data clearing efficiency of SSD; 2. By obtaining the access frequency and access time of multiple write data blocks in SRAM, the usage of data blocks can be accurately grasped, thereby providing basic data support for cache management strategies and improving the rationality of cache elimination decisions; by calculating the cache elimination coefficient and judging whether it is not greater than the first preset cache elimination value, low-priority or low-frequency access data blocks can be effectively screened, thereby freeing up more cache space without affecting high-frequency data access, thereby improving the utilization rate of storage resources; by executing the cache elimination algorithm for qualified data blocks and adopting a strategy combining LRU and LFU, the access frequency and time factors can be taken into account, thereby ensuring that high-value data is retained in the write data blocks as much as possible, and clearing the write data blocks occupied by low-value data as much as possible, thereby freeing up sufficient SRAM space; 3. By judging whether the cache elimination coefficient is not greater than the second preset cache elimination value, the screening conditions can be further optimized before the data block is eliminated, so that low-value data blocks are eliminated first when storage resources are tight, thereby improving the utilization efficiency of the SRAM storage space. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a flow chart of a method for clearing SSD data in one embodiment of the present application; Figure 2 is a flowchart for implementing step S3 in the SSD data clearing method in one embodiment of the present application; Figure 3 is a flowchart for implementing step S32 in the SSD data clearing method in one embodiment of the present application; Figure 4 is a flowchart for implementing step S34 in the SSD data clearing method in one embodiment of the present application; Figure 5 is a flowchart for implementing step S2 in the SSD data clearing method in one embodiment of the present application; Figure 6 is another flow chart of the SSD data clearing method in one embodiment of the present application; Figure 7 This is a principle block diagram of an SSD data clearing device in one embodiment of the present application; Figure 8 It is a schematic diagram of a device in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The present application is further described in detail below in conjunction with the accompanying drawings.

[0025] In one embodiment, if Figure 1 As shown, the present application discloses a method for clearing data from an SSD (Solid State Disk), which specifically includes the following steps: S1: receiving multiple data clearing requests of a single data operation, calculating the total information data volume of the multiple data clearing requests, and detecting the available storage space of the SRAM.

[0026] Specifically, after receiving multiple data clearing requests, each data clearing request is parsed and the information data volume of the data clearing request is extracted, and then the total information data volume of the multiple data clearing requests is calculated. When detecting the available storage space of SRAM (Static Random-Access Memory), the current usage status of SRAM is obtained, the total size of the stored data blocks is checked and the available storage space of SRAM is calculated.

[0027] In this embodiment, the information data volume of the data clearing request is the size of the space occupied by the data clearing request in the SRAM after the data clearing request is written into the SRAM.

[0028] S2: Determine whether the available storage space is less than the total amount of information data. If the available storage space is less than the total amount of information data, determine the priority of each data clearing request. The priority of the data clearing request includes a first priority and a second priority. The data clearing requests are screened according to the priority of the data clearing request, wherein the first priority is higher than the second priority.

[0029] Specifically, the available storage space is compared with the total amount of information data. If the available storage space is less than the total amount of information data, the priority is assigned according to the importance of the data clearing request. In the priority determination process, multiple factors are considered, including the timeliness of the request, the impact of data clearing on system performance, the historical execution frequency of the request, etc. The first priority data clearing request includes time-critical requests that affect data integrity or system stability, while the second priority data clearing request is usually a non-critical clearing operation or a task that can be delayed.

[0030] S3: Execute a cache elimination algorithm on the SRAM so that the remaining storage space of the SRAM is not less than the total information data volume of the data clearing request of the first priority.

[0031] Specifically, the information data volume of all first-priority data clearing requests is calculated, and then a cache elimination algorithm is executed on the SRAM to release the storage space of the SRAM. In the process of executing the cache elimination algorithm on the SRAM, data blocks with low access frequency or that have not been accessed for a long time in the SRAM are selected as priority clearing objects, while avoiding clearing data that still has access needs in the near future to reduce the impact on subsequent system operations. When executing the cache elimination algorithm on the SRAM, the meta-information of the cleared data blocks is recorded to ensure data consistency, and some SRAM space is reserved to cope with sudden data write requests.

[0032] Furthermore, after executing the cache elimination algorithm on the SRAM, the available storage space of the SRAM is detected again to determine whether the available storage space of the SRAM is less than the total amount of information data. If the available storage space of the SRAM is less than the amount of information data of all first-priority data clearing requests, the cache elimination algorithm is executed on the SRAM again, and this cycle is repeated so that the remaining storage space of the SRAM is not less than the total amount of information data of the first-priority data clearing requests.

[0033] S4: Write the data clearing request with the first priority into the SRAM, and write the data clearing request with the second priority into the auxiliary storage medium.

[0034] Specifically, when writing a data clear request, the write operation is performed in the order of priority of the data clear request, and the storage requirements of the first priority data clear request are given priority. The first priority data clear request is written into the SRAM, and at the same time, it is ensured that the storage resources required for the first priority data clear request have been locked to avoid subsequent overwriting, and the second priority data clear request is written into the auxiliary storage medium.

[0035] Furthermore, the execution status of the second priority data clearing request is marked to ensure that the second priority data clearing request is written into the SRAM after the first priority data clearing request and the storage space of the SRAM is sufficient, thereby improving the execution efficiency of the second priority data clearing request.

[0036] In some specific embodiments, the execution status of the second-priority data clear request can be marked according to its timeliness, the execution status of the second-priority data clear request with lower timeliness can be marked as suspended execution, and the execution status of the second-priority data clear request with higher timeliness can be marked as immediate execution, and the second-priority data clear request with lower timeliness can be written into the SRAM after the first-priority data clear request and the SRAM storage space is sufficient, thereby improving the execution efficiency of the second-priority data clear request with lower timeliness.

[0037] In this embodiment, the auxiliary storage medium may be DRAM.

[0038] S5: Execute the data clearing request.

[0039] Specifically, data clearing requests are executed separately according to their storage locations, with priority given to data clearing requests stored in SRAM. Data clearing operations are called directly, and data storage space is released after the data clearing request is executed. The data management table is updated, and during the execution of the data clearing request, it is checked and ensured that the relevant data blocks are not locked by other tasks to prevent data competition. Finally, after the clearing operation is completed, the system log is updated to record detailed information on this data clearing for subsequent tracking.

[0040] By receiving multiple data clearing requests for a single data operation and calculating the total information data volume of the multiple data clearing requests, the storage space required for the multiple data clearing requests can be accurately evaluated before data clearing, thereby reasonably scheduling the storage resources of the SRAM and avoiding task blocking or delays caused by insufficient storage space; by detecting the available storage space of the SRAM and judging whether the available storage space is less than the total information data volume, the storage space status can be evaluated in advance before the data clearing request is written, thereby avoiding the backlog of data clearing requests and improving the overall efficiency of the write operation; by determining the priority of the data clearing request and screening the data clearing request according to the priority, it can ensure that the data clearing request with high time sensitivity or related to system stability is executed first, thereby improving the execution efficiency of the data clearing request and reducing the performance degradation caused by the system resource competition; by executing the cache elimination algorithm, sufficient SRAM space is freed up to ensure that the first priority data clearing request can be executed smoothly, and the cache management can be optimized while ensuring the normal execution of high priority tasks, thereby improving the data clearing efficiency of the SSD.

[0041] In one embodiment, if Figure 2 As shown, in step S3, the cache elimination algorithm is executed on the SRAM, specifically including: S31: Obtain access frequency and access time of multiple write data blocks in the SRAM.

[0042] Specifically, traverse multiple write data blocks in the SRAM and record the most recent access time and access frequency of each write data block. The access time refers to the last time the write data block was read or written, and the access frequency represents the cumulative number of accesses to the write data block within a certain time window. In order to ensure the data accuracy of the access frequency and access time, a sliding window mechanism can be used to regularly refresh the data access status to ensure that the cache elimination decision is based on the latest access frequency and access time.

[0043] S32: Determine a cache elimination coefficient of a corresponding write data block in the SRAM according to the access frequency and the access time.

[0044] Specifically, before executing the cache elimination algorithm, the cache elimination coefficient of each written data block is calculated first. The calculation of the cache elimination coefficient depends on the access frequency and access time of the data block. In order to ensure the accuracy of the calculation, the access record of each written data block needs to be updated in real time to reflect the latest access situation. In practical applications, a sliding time window mechanism can be used to only retain data access records in the recent period of time, thereby avoiding the interference of historical access data on current decisions. During the calculation process, if the access frequency of a data block is zero, that is, it has not been accessed in the current time window, its cache elimination coefficient is directly set to the maximum value so that it can be eliminated as soon as possible, thereby releasing more SRAM space.

[0045] Furthermore, for some special write data blocks, such as write data blocks storing key metadata or system logs, a minimum elimination threshold can be set to ensure that these write data blocks will not be mistakenly deleted due to the adjustment of the cache elimination strategy. In addition, for some write data blocks with unstable access patterns, such as write data blocks whose access frequency increases sharply in a short period of time but then decreases in access volume, a dynamic cache strategy can be adopted. That is, when it is detected that the access frequency of the write data block increases significantly in a short period of time, the cache elimination coefficient of the write data block is temporarily increased to avoid the content in the write data block from being mistakenly deleted. However, if the access frequency decreases in the subsequent time period, the cache elimination coefficient of the write data block is appropriately reduced, thereby ensuring the rational use of SRAM resources and improving the continuity of data access and system response speed.

[0046] S33: Determine whether the cache elimination coefficient is not greater than a first preset cache elimination value.

[0047] Specifically, the calculated cache elimination coefficient is compared with the first preset cache elimination value. If the cache elimination coefficient is less than or equal to the first preset cache elimination value, it indicates that the importance of the written data block remaining in the SRAM is relatively low and it can be used as a candidate for elimination. If the cache elimination coefficient is higher than the first preset cache elimination value, the data block still has a high access demand and should continue to be retained in the SRAM to reduce unnecessary cache data migration. In addition, the preset cache elimination value can be adaptively adjusted to adapt to different storage load conditions and improve the flexibility of cache management.

[0048] In some specific embodiments, the setting of the first preset cache elimination value can comprehensively consider factors such as access frequency, access time, cache space utilization, and system I / O load, and use static basic values ​​and dynamic adjustment strategies for optimization. The setting of the first preset cache elimination value ensures that the write data blocks with high frequency access will not be mistakenly eliminated, and at the same time eliminates the write data blocks with low priority, thereby improving the SSD data clearing efficiency and storage management performance. The static basic value can set a first preset cache elimination value through historical access pattern analysis to ensure that under typical load conditions, the SRAM can efficiently store high-priority data clearing requests and will not affect performance due to cache full load. Then, the first preset cache elimination value is adjusted using a dynamic adjustment strategy. If the data with high access frequency occupies a large amount of SRAM storage space, the first preset cache elimination value is appropriately increased. If the overall access frequency is low, the first preset cache elimination value is reduced to reduce unnecessary write data block elimination and improve the cache hit rate.

[0049] Furthermore, a sliding time window can be used to record the past N cache elimination events. If the cache elimination coefficients of most eliminated write data blocks are higher than the current first preset cache elimination, it means that the first preset cache elimination value is too low and needs to be increased. Otherwise, the first preset cache elimination value should be appropriately reduced to achieve dynamic optimization.

[0050] S34: If the cache elimination coefficient is not greater than the first preset cache elimination value, a cache elimination algorithm is executed on the corresponding written data block in the SRAM, and the cache elimination algorithm includes an LRU algorithm and an LFU algorithm.

[0051] Specifically, when the cache elimination coefficient is not greater than the preset cache elimination value, data elimination is performed according to the LRU algorithm or the LFU algorithm. When LRU is used, the least recently used write data block is cleared to ensure that data with high access timeliness can be retained in the SRAM. When LFU is used, the write data block with the lowest access frequency is cleared to ensure that storage resources serve high-frequency access data as much as possible. In order to improve the adaptability of the elimination strategy, the advantages of the two algorithms can be combined to adaptively select the optimal strategy to optimize storage resource management.

[0052] S35: If the cache elimination coefficient is greater than the first preset cache elimination value, retaining the data of the corresponding written data block in the SRAM.

[0053] Specifically, for cache elimination coefficients higher than the first preset cache elimination value, the corresponding data blocks will continue to be retained in the SRAM to ensure that high-priority data can be continuously stored in the cache, thereby improving data access efficiency. At the same time, by regularly updating the cache elimination coefficients, high-priority data blocks can be prevented from reducing the overall system performance due to long-term occupation of cache space.

[0054] By obtaining the access frequency and access time of multiple write data blocks in SRAM, the usage of data blocks can be accurately understood, thereby providing basic data support for cache management strategies and improving the rationality of cache eviction decisions; by calculating the cache eviction coefficient and judging whether it is not greater than the first preset cache eviction value, low-priority or low-frequency access data blocks can be effectively screened, thereby freeing up more cache space without affecting high-frequency data access, thereby improving the utilization rate of storage resources; by executing the cache eviction algorithm on qualified data blocks and adopting a strategy that combines LRU and LFU, the access frequency and time factors can be taken into account, thereby ensuring that high-value data is retained in the write data blocks as much as possible, and clearing the write data blocks occupied by low-value data as much as possible, thereby freeing up sufficient SRAM space.

[0055] In one embodiment, if Figure 3 As shown, in step S32, the cache elimination coefficient of the corresponding write data block in the SRAM is determined according to the access frequency and the access time, specifically including: S321: Calculate the cache elimination coefficient using the following formula:

[0056] The cache elimination coefficient is calculated, where C is the cache elimination coefficient, T is the access time, F is the access frequency, and α and β are weight coefficients.

[0057] Specifically, when executing cache elimination decisions, the cache elimination coefficient calculation formula is used To determine the elimination priority of each written data block, where F represents the access frequency of the data block, that is, the number of times the written data block is read or written within the specified time window, T represents the time interval of the last access to the written data block, that is, the length of time from the last access to the current moment, α and β are adjustable weight parameters used to balance the impact of access frequency and access time on the cache elimination coefficient. When α is larger, the cache elimination algorithm is more inclined to retain frequently accessed data blocks, and when β is larger, the cache elimination algorithm is more inclined to eliminate data blocks that have not been accessed for a long time.

[0058] In this embodiment, the setting of α and β can comprehensively consider factors such as access time, access frequency, system I / O load, and SRAM space utilization, and optimize using static basic values ​​and dynamic adjustment strategies. The setting of α and β ensures that the cache elimination algorithm can be dynamically adjusted between the LRU algorithm and the LFU algorithm, ensuring that the write data blocks with high access frequency are retained first, while reducing the residence of data that has not been accessed for a long time, thereby optimizing the data clearing efficiency and storage management performance of the SSD.

[0059] The static base value can be set by analyzing historical access patterns, and the values ​​of α and β are initially set to adapt to different typical storage load scenarios. For example, in read-intensive applications, such as database queries, a higher β is set to increase the LFU impact weight to ensure that frequently accessed data blocks have a higher priority, while α is relatively low to avoid premature elimination of data that has not been used recently but may still be needed. In write-intensive applications, such as log storage, a higher α is set to strengthen the LRU strategy and prioritize the elimination of data blocks that have not been accessed for a long time, while β is lower to reduce dependence on access frequency. In load-balanced applications, α and β need to maintain an appropriate balance to ensure that the cache can retain frequently accessed data while promptly clearing data that has not been accessed for a long time.

[0060] The dynamic adjustment strategy can be used to further optimize the values ​​of α and β. When the SRAM storage space is sufficient, β is increased to reduce the frequent loading of data on the SSD, and when the SRAM storage space is tight, α is increased to free up space to store new requests. When the I / O load is high, β is increased to reduce the SSD read and write burden and improve the cache hit rate, and when the I / O load is low, α is increased to eliminate recently unaccessed data to ensure efficient use of storage space.

[0061] By adopting the above technical solution, by calculating the cache elimination coefficient based on the access frequency and access time, the cache elimination algorithm executed on the written data block can be intelligently adjusted according to the historical access situation of the written data block, thereby optimizing the cache management of the SRAM and improving data access efficiency; by setting the weight parameters α and β, the access frequency and access time are balanced, and the cache elimination strategy can be flexibly adjusted in different application scenarios, thereby freeing up enough SRAM space as much as possible.

[0062] In one embodiment, if Figure 4 As shown, in step S34, the cache elimination algorithm is executed on the corresponding written data block in the SRAM, specifically including: S341: Determine whether the cache elimination coefficient is not greater than a second preset cache elimination value.

[0063] Specifically, after calculating the cache elimination coefficient of each written data block, the cache elimination coefficient is compared with a second preset cache elimination value, which is a threshold dynamically set by the system according to the current storage load, access mode and performance requirements.

[0064] In this embodiment, the setting of the second preset cache elimination value can comprehensively consider factors such as access frequency, access time, cache space occupancy ratio and system I / O load, and optimize by combining static setting and dynamic adjustment strategy. The setting of the second preset cache elimination value ensures that in the cache elimination process, it is possible to reasonably distinguish between write data blocks with high access frequency and write data blocks with low access frequency, ensure the effective use of SRAM storage space, and improve SSD data clearing efficiency and storage management performance.

[0065] The static setting method can analyze the historical access patterns of the system and initially set the second preset cache elimination value to adapt it to different storage load scenarios. For example, in application scenarios with high access frequency, such as database queries, a lower second preset cache elimination value will be set to ensure that only write data blocks with extremely low access frequency are eliminated, ensuring that data with high access frequency is retained. In application scenarios with low access frequency, such as log storage, a higher second preset cache elimination value will be set to improve cache utilization and timely eliminate write data blocks that occupy space but are less accessed.

[0066] The dynamic adjustment strategy can adjust the second preset cache eviction value based on the system I / O load. When the I / O load is high, the second preset cache eviction value is increased to reduce the additional storage operations caused by cache eviction; when the I / O load is low, the second preset cache eviction value is reduced to improve the storage efficiency of the cache.

[0067] S342: If the cache elimination coefficient is not greater than the second preset cache elimination value, a plurality of corresponding written data blocks are merged into a first data block group, and then an LRU algorithm is executed on the first data block group.

[0068] Specifically, after determining that the cache elimination coefficients of multiple write data blocks are not greater than the second preset cache elimination value, in order to improve the cache elimination efficiency, these write data blocks are merged to form a first data block group. The principle of write data block merging can be based on the address continuity, storage association or business logic association of the data blocks to reduce the fragmentation problem of data clearing operations. The LRU algorithm is executed on the first data block group. Under the LRU algorithm, the system will give priority to eliminating the least recently used data blocks to release cache space. This method is particularly suitable for data blocks that are frequently accessed in a short period of time, because their access patterns are relatively unstable and they are prone to lose access value in a short period of time. The use of the LRU strategy can effectively improve cache utilization and reduce unnecessary occupation of write data blocks, thereby freeing up SRAM storage space as much as possible.

[0069] S343: If the cache elimination coefficient is greater than the second preset cache elimination value, a plurality of corresponding written data blocks are merged into a second data block group, and then the LFU algorithm is executed on the second data block group.

[0070] Specifically, for written data blocks whose cache elimination coefficient is greater than the second preset cache elimination value, these written data blocks are merged to form a second data block group. The data merging method can be based on the logical association of the data blocks or the storage access mode to reduce the complexity of data management. Subsequently, the LFU algorithm is executed on the second data block group. Under the LFU algorithm, the system prioritizes the elimination of data blocks with the lowest access frequency to ensure that high-frequency access data blocks can be retained in the cache for a long time. This strategy is particularly suitable for data blocks with long-term and stable access, such as operating system caches, index tables, etc. Through the LFU mechanism, high-value data can be prevented from being accidentally deleted due to short-term access fluctuations, thereby improving the storage stability and access efficiency of the SSD.

[0071] By determining whether the cache elimination coefficient is not greater than the second preset cache elimination value, the screening conditions can be further optimized before data blocks are eliminated, thereby giving priority to eliminating low-value data blocks when storage resources are tight, thereby improving the utilization efficiency of SRAM storage space.

[0072] In one embodiment, if Figure 5As shown, in step S2, the priority of each data clearing request is determined. The priority of the data clearing request includes a first priority and a second priority. The data clearing request is screened according to the priority of the data clearing request, specifically including: S21: Obtain the creation time and execution deadline of the data clearing request.

[0073] Specifically, after receiving multiple data clearing requests, the creation time and execution deadline of each data clearing request are recorded. The creation time refers to the time when the data clearing request is generated in the system, and the execution deadline refers to the latest time when the data clearing request must be executed. In order to ensure the data accuracy of the creation time and the execution deadline, the creation time can be automatically recorded based on the system clock, and the execution deadline can be set by external control logic, for example, by the task scheduling module according to the importance of the data clearing request or business rules. When the data clearing request enters the queue, the creation time and the execution deadline will be synchronously stored in the management table for subsequent priority determination.

[0074] S22: Determine the remaining execution time of the data clearing request according to the creation time and the execution deadline.

[0075] Specifically, before the data clearing task is executed, the remaining execution time of each data clearing request is calculated. The calculation formula for the remaining execution time is: ,in is the remaining execution time, To execute the deadline, To create time, the remaining execution time calculation formula can be used to determine the data clearing request closest to the execution deadline, ensuring that urgent data clearing requests can be executed first. In the process of calculating the remaining execution time, the accuracy of the system clock is considered, and the timestamp is standardized to avoid incorrect calculations due to clock drift or time zone issues. In the case of a large number of concurrent requests, the system can batch calculate the remaining execution time of multiple data clearing requests to optimize computing performance and improve task scheduling efficiency.

[0076] S23: Determine whether the remaining execution time is greater than a preset time value.

[0077] Specifically, the calculated remaining execution time is compared with the preset time value. The preset time value can be dynamically set according to the storage policy of the SSD device. For example, when the system is under high load, the preset time value can be appropriately reduced to ensure that high-priority tasks can be completed in time. When the system is under low load, the preset time value can be appropriately extended to reduce unnecessary resource scheduling.

[0078] S24: If the remaining execution time is not greater than the preset time value, the priority of the corresponding data clearing request is determined as the first priority.

[0079] Specifically, for data clearing requests whose remaining execution time is not greater than the preset time value, the system will mark the corresponding data clearing request as the first priority to ensure that the corresponding data clearing request can be executed first. Such data clearing requests are usually highly time-sensitive, such as storing data blocks that are about to be full, system-level garbage collection tasks, or other data that must be cleared immediately. After assigning priorities, these data clearing requests will be placed in the first priority queue and written to the SRAM first during the scheduling process to improve the execution efficiency of the data clearing requests.

[0080] Furthermore, in order to prevent a large number of high-priority tasks from saturating system resources, a maximum task number threshold can be set, and tasks exceeding the threshold will be temporarily stored in the auxiliary storage medium and scheduled after the SRAM storage space is released.

[0081] S25: If the remaining execution time is greater than the preset time value, the priority of the corresponding data clearing request is determined as the second priority.

[0082] Specifically, for data clearing requests whose remaining execution time is greater than the preset time value, the system will mark the corresponding data clearing requests as the second priority and temporarily store them in the auxiliary storage medium. The time requirements of these data clearing requests are relatively loose and do not need to be executed immediately, such as some background data sorting, clearing of low-frequency access data, etc. During the scheduling process, the second-priority data clearing requests will not occupy the storage space of the first-priority data clearing requests, but will be executed when the system load is low or the cache resources are sufficient. In order to avoid long-term backlog of low-priority tasks, a regular inspection mechanism can be set to re-evaluate the execution requirements of the tasks after a certain period of time. If a change in the priority of the data clearing request is detected, the scheduling strategy will be adjusted to ensure the rationality of the execution of the data clearing request.

[0083] By obtaining the creation time and execution deadline of the data clearing request and calculating the remaining execution time, the urgency of the data clearing request can be accurately evaluated, thereby ensuring the rationality of task scheduling and improving resource allocation efficiency; by comparing the remaining execution time with the preset time value and determining the priority of the data clearing request based on the calculation result, it can ensure that time-sensitive tasks are executed first, thereby reducing data consistency problems caused by delayed processing and improving the data clearing efficiency of the SSD.

[0084] In one embodiment, if Figure 6 As shown, before the step of calculating the total information data volume of multiple data clearing requests, the SSD data clearing method also includes: S6: Detect addresses of clear data blocks pointed to by multiple data clearing requests.

[0085] Specifically, all data clearing requests are traversed, and the clearing data block address corresponding to each data clearing request is extracted. The method of detecting the clearing data block address is usually based on a mapping table inside the SSD, such as an FTL mapping table, etc., and in the process of detecting the clearing data block address, the clearing data block logical address and physical address can be combined to ensure the recognition accuracy of the clearing data block address.

[0086] In this embodiment, the clear data block refers to a data block on which a data clearing request needs to perform a data clearing operation on the SSD. One data clearing request can perform a data clearing operation on one clear data block, or one data clearing request can perform a data clearing operation on multiple clear data blocks.

[0087] S7: Determine whether addresses of multiple cleared data blocks overlap.

[0088] Specifically, after completing the address detection of the cleared data block, the system will check whether multiple data clearing requests point to the same address of the cleared data block. The judgment logic of this step is based on the address matching algorithm. For example, a hash table is used to store the addresses of the cleared data blocks that have appeared, and the hash table is checked when traversing new data clearing requests. If the same cleared data block address is found, the data clearing request is marked as a duplicate data clearing request. If the addresses of multiple data clearing requests overlap, the system will further merge these data clearing requests to reduce unnecessary data clearing operations.

[0089] S8: If the addresses of multiple clear data blocks overlap, the corresponding data clear requests are merged into a new data clear request.

[0090] Specifically, after detecting that multiple data clearing requests point to the same storage address, the system will merge the corresponding data clearing requests into a new data clearing request. The execution method of the new data clearing request is the same as that of the ordinary clearing request, but the execution result of the new data clearing request will overwrite the original multiple data clearing requests, thereby avoiding repeated execution of data clearing requests.

[0091] Furthermore, when merging requests, the priority, execution time and storage location of the cleared data blocks of each data clearing request will be comprehensively considered to ensure that the merged data clearing request still complies with the logic of task scheduling. For example, if the priorities of multiple data clearing requests are different, the merged data clearing request will be executed at a higher priority to ensure the stability of system performance. In addition, in order to further optimize the merging process of data clearing requests, the system can adopt a batch merging strategy to improve the clearing efficiency and reduce the SSD load when processing large batch requests.

[0092] Furthermore, if the addresses of the multiple clearing data blocks do not overlap, the total information data volume of the multiple data clearing requests is calculated.

[0093] By detecting the addresses of the cleared data blocks pointed to by multiple data clearing requests and determining whether there is overlap, repeated clearing operations can be avoided, thereby reducing unnecessary data reading and writing burdens and improving the data clearing efficiency of the SSD; by merging multiple data clearing requests pointing to the same data block into a new data clearing request, redundant requests can be reduced, thereby optimizing task scheduling and improving the execution efficiency of data clearing tasks.

[0094] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0095] In one embodiment, a SSD data clearing device is provided, and the SSD data clearing device corresponds to the SSD data clearing method in the above embodiment. Figure 7 As shown, the SSD data clearing device includes a request processing module, a storage space management module, a priority allocation module, a cache management module, a data writing module and a data clearing execution module. The functional modules are described in detail as follows: A request processing module, used for receiving multiple data clearing requests of a single data operation, and calculating the total information data volume of the multiple data clearing requests; A storage space management module, used to detect the available storage space of the SRAM and determine whether the available storage space is less than the total amount of information data; a priority allocation module, configured to determine the priority of each of the data clearing requests when the available storage space is less than the total amount of information data, and to screen the data clearing requests according to the priorities of the data clearing requests; A cache management module, used for executing a cache elimination algorithm on the SRAM so that the remaining storage space of the SRAM is not less than the total information data volume of the data clearing request of the first priority; A data writing module, used for writing the data clearing request of the first priority into the SRAM, and writing the data clearing request of the second priority into the auxiliary storage medium; The data clearing execution module is used to execute the data clearing request.

[0096] Optionally, the cache management module includes: A data access statistics module, used to obtain access frequencies and access times of multiple write data blocks in the SRAM; A cache elimination coefficient determination module, used to determine the cache elimination coefficient of the corresponding write data block in the SRAM according to the access frequency and the access time; A cache elimination judgment module, used to judge whether the cache elimination coefficient is not greater than a first preset cache elimination value; The cache optimization execution module is used to execute the cache elimination algorithm on the corresponding write data block in the SRAM if the cache elimination coefficient is not greater than the first preset cache elimination value, and the cache elimination algorithm includes the LRU algorithm and the LFU algorithm. If the cache elimination coefficient is greater than the first preset cache elimination value, the data of the corresponding write data block in the SRAM is retained.

[0097] Optionally, the cache elimination coefficient determination module includes: The cache elimination coefficient calculation module is used to calculate the cache elimination coefficient through the formula: , the cache elimination coefficient is calculated, where C is the cache elimination coefficient, T is the access time, F is the access frequency, and α and β are weight coefficients.

[0098] Optionally, the cache optimization execution module includes: A cache elimination strategy determination module, used to determine whether the cache elimination coefficient is not greater than a second preset cache elimination value; A data block merging and elimination module is used to merge multiple corresponding written data blocks into a first data block group if the cache elimination coefficient is not greater than the second preset cache elimination value, and then execute the LRU algorithm on the first data block group; if the cache elimination coefficient is greater than the second preset cache elimination value, merge multiple corresponding written data blocks into a second data block group, and then execute the LFU algorithm on the second data block group.

[0099] Optional: Priority Assignment Module includes: A request time calculation module, used to obtain the creation time and execution deadline of the data clearing request; a remaining execution time calculation module, configured to determine the remaining execution time of the data clearing request according to the creation time and the execution deadline; The priority judgment module is used to determine the priority of the corresponding data clearing request as the first priority if the remaining execution time is not greater than the preset time value; if the remaining execution time is greater than the preset time value, determine the priority of the corresponding data clearing request as the second priority.

[0100] Optionally, the SSD data clearing device further includes: A clear data block address detection module, used to detect the addresses of clear data blocks pointed to by the multiple data clearing requests; A data block overlap judgment module, used to judge whether the addresses of a plurality of cleared data blocks overlap; The data clearing request merging module is used to merge the corresponding data clearing requests into a new data clearing request if the addresses of the plurality of clearing data blocks overlap.

[0101] For the specific definition of the SSD data clearing device, please refer to the definition of the SSD data clearing method above, which will not be repeated here. Each module in the above-mentioned SSD data clearing device can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0102] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 8 As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a SSD data clearing method is implemented.

[0103] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program: Receiving multiple data clearing requests of a single data operation, calculating the total information data volume of the multiple data clearing requests, and detecting the available storage space of the SRAM; Determine whether the available storage space is less than the total amount of information data, if the available storage space is less than the total amount of information data, determine the priority of each data clearing request, the priority of the data clearing request includes a first priority and a second priority, and screen the data clearing requests according to the priority of the data clearing request, wherein the first priority is higher than the second priority; Execute a cache elimination algorithm on the SRAM so that the remaining storage space of the SRAM is not less than the total information data volume of the data clearing request of the first priority; Writing a data clearing request of a first priority level into the SRAM and writing a data clearing request of a second priority level into the auxiliary storage medium; Executes a data purge request.

[0104] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented: Receiving multiple data clearing requests of a single data operation, calculating the total information data volume of the multiple data clearing requests, and detecting the available storage space of the SRAM; Determine whether the available storage space is less than the total amount of information data, if the available storage space is less than the total amount of information data, determine the priority of each data clearing request, the priority of the data clearing request includes a first priority and a second priority, and screen the data clearing requests according to the priority of the data clearing request, wherein the first priority is higher than the second priority; Execute a cache elimination algorithm on the SRAM so that the remaining storage space of the SRAM is not less than the total information data volume of the data clearing request of the first priority; Writing a data clearing request of a first priority level into the SRAM and writing a data clearing request of a second priority level into the auxiliary storage medium; Executes a data purge request.

[0105] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0106] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0107] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for clearing SSD data, the method being applicable to an SSD solid state drive, the SSD solid state drive having an SRAM and an auxiliary storage medium, characterized in that: The SSD data clearing method comprises: Receiving multiple data clearing requests of a single data operation, calculating the total information data volume of the multiple data clearing requests, and detecting the available storage space of the SRAM; Determine whether the available storage space is less than the total amount of information data, if the available storage space is less than the total amount of information data, determine the priority of each of the data clearing requests, the priority of the data clearing request includes a first priority and a second priority, and screen the data clearing requests according to the priority of the data clearing request, wherein the first priority is higher than the second priority; Executing a cache elimination algorithm on the SRAM so that the remaining storage space of the SRAM is not less than the total information data volume of the data clearing request of the first priority; Writing the data clearing request of the first priority into the SRAM, and writing the data clearing request of the second priority into the auxiliary storage medium; The data clearing request is executed.

2. The SSD data clearing method according to claim 1, characterized in that: The performing of a cache elimination algorithm on the SRAM comprises: Obtaining access frequencies and access times of a plurality of write data blocks in the SRAM; Determine a cache elimination coefficient of a corresponding written data block in the SRAM according to the access frequency and the access time; Determining whether the cache elimination coefficient is not greater than a first preset cache elimination value; If the cache elimination coefficient is not greater than the first preset cache elimination value, executing the cache elimination algorithm on the corresponding write data block in the SRAM, the cache elimination algorithm including the LRU algorithm and the LFU algorithm; If the cache elimination coefficient is greater than the first preset cache elimination value, the data of the corresponding written data block in the SRAM is retained.

3. The SSD data clearing method according to claim 2, characterized in that: The step of determining a cache elimination coefficient of a corresponding write data block in the SRAM according to the access frequency and the access time includes: The cache elimination coefficient is calculated by the formula: The cache elimination coefficient is calculated, where C is the cache elimination coefficient, T is the access time, F is the access frequency, and α and β are weight coefficients.

4. The SSD data clearing method according to claim 2, characterized in that: The executing the cache elimination algorithm on the corresponding written data block in the SRAM includes: Determining whether the cache elimination coefficient is not greater than a second preset cache elimination value; If the cache elimination coefficient is not greater than the second preset cache elimination value, merging a plurality of corresponding written data blocks into a first data block group, and then executing the LRU algorithm on the first data block group; If the cache elimination coefficient is greater than the second preset cache elimination value, a plurality of corresponding written data blocks are merged into a second data block group, and then the LFU algorithm is executed on the second data block group.

5. The SSD data clearing method according to claim 1, characterized in that: The step of determining a priority of each of the data clearing requests, wherein the priority of the data clearing requests includes a first priority and a second priority, and screening the data clearing requests according to the priority of the data clearing requests includes: Obtaining the creation time and execution deadline of the data clearing request; Determine the remaining execution time of the data clearing request according to the creation time and the execution deadline; Determine whether the remaining execution time is greater than a preset time value; If the remaining execution time is not greater than the preset time value, the priority of the corresponding data clearing request is determined as the first priority; If the remaining execution time is greater than the preset time value, the priority of the corresponding data clearing request is determined as the second priority.

6. The SSD data clearing method according to claim 1, characterized in that: Before calculating the total information data volume of the plurality of data clearing requests, the method further includes: Detecting addresses of cleared data blocks pointed to by a plurality of the data clearing requests; Determining whether addresses of a plurality of cleared data blocks overlap; If the addresses of the plurality of cleared data blocks overlap, the corresponding data clearing requests are merged into a new data clearing request.

7. An SSD data device, characterized in that: The SSD data device comprises: A request processing module, used for receiving multiple data clearing requests of a single data operation, and calculating the total information data volume of the multiple data clearing requests; A storage space management module, used to detect the available storage space of the SRAM and determine whether the available storage space is less than the total amount of information data; a priority allocation module, configured to determine the priority of each of the data clearing requests when the available storage space is less than the total amount of information data, and to screen the data clearing requests according to the priorities of the data clearing requests; A cache management module, used for executing a cache elimination algorithm on the SRAM so that the remaining storage space of the SRAM is not less than the total information data volume of the data clearing request of the first priority; A data writing module, used for writing the data clearing request of the first priority into the SRAM, and writing the data clearing request of the second priority into an auxiliary storage medium; The data clearing execution module is used to execute the data clearing request.

8. The SSD data device according to claim 7, characterized in that: The SSD data device further comprises: A data access statistics module, used to obtain access frequencies and access times of multiple write data blocks in the SRAM; A cache elimination coefficient calculation module, used to determine the cache elimination coefficient of the corresponding write data block in the SRAM according to the access frequency and the access time; A cache elimination judgment module, used to judge whether the cache elimination coefficient is not greater than a first preset cache elimination value; The cache optimization execution module is used to execute the cache elimination algorithm on the corresponding write data block in the SRAM if the cache elimination coefficient is not greater than the first preset cache elimination value, and the cache elimination algorithm includes the LRU algorithm and the LFU algorithm. If the cache elimination coefficient is greater than the first preset cache elimination value, the data of the corresponding write data block in the SRAM is retained.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the SSD data clearing method according to any one of claims 1 to 6 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the SSD data clearing method according to any one of claims 1 to 6 are implemented.

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