N-dimensional discrete hyper-chaos pseudo-random number generator and generation method thereof

Abstract

The invention provides an n-dimensional discrete hyper-chaos pseudo-random number generator and a generation method thereof.The n-dimensional discrete hyper-chaos pseudo-random number generator comprises a plurality of operational circuits, each operational circuit comprises an adder, the adder is connected with a first register, the first register is connected with a multiplier, the multiplier is connected with a second register, and the second register is connected with a third register. And the second register is connected with an output module and a circulation module. The circuit is simple in structure, extremely few in occupied FPGA resources, high in utilization rate and low in hardware power consumption, the rate of generated pseudo-random numbers can reach 8 * nGbps, generated pseudo-random number sequences can pass various famous randomness tests, most encryption requirements can be met, the method can also be used for enterprises or military applications with higher requirements, the equation is simple, and the method is easy to implement. The algorithm is easy to implement, the hardware resource occupancy rate is very low, meanwhile, the speed is very high, and the low cost, low power consumption and high throughput far exceed the limits which can be reached by an existing pseudo-random number algorithm.

Description

Technical Field

[0001] The present invention belongs to the field of communication security technology and relates to a n dimensional discrete hyperchaotic pseudo-random number generator and its generation method. Background Art

[0002] In today's information age, random numbers have been widely used in many fields. The main methods for generating random numbers include algorithms to generate pseudo-random numbers, physical entropy sources to generate true random numbers, and chaotic circuits to generate random numbers. Among them, the methods of generating pseudo-random numbers by algorithms and generating true random numbers by physical entropy sources are feasible, but they have fatal shortcomings such as platform limitations, susceptibility to environmental interference, and high costs. At present, the pseudo-random number generation of chaotic circuits has the following main characteristics: the traditional chaotic model is implemented using an XOR circuit. Although this model is small in scale and has low resource occupancy, the random numbers it generates are not random and require post-processing, with a rate of only 7.38 Mbit / s; the model using an enhanced low-dimensional chaotic system plus sin operation can be miniaturized and chip-based, but the complex algorithm causes its generation rate to be low; finally, although the pseudo-random number generator produced by Agilent Technologies in the United States has been mass-produced, the high cost is prohibitive. Summary of the invention

[0003] The purpose of the present invention is to provide a n dimensional discrete hyperchaotic pseudo-random number generator and its generation method.

[0004] To this end, the present invention adopts the following technical solutions: A sort of n The invention discloses a 3D discrete hyperchaotic pseudo-random number generator, comprising a plurality of operation circuits, wherein the operation circuit comprises an adder, the adder is connected to a multiplier, the multiplier is connected to an output module for outputting random numbers and a circulation module, and the circulation module is used to input the random numbers back to the adder for cyclic calculation.

[0005] Furthermore, the adder is connected to the multiplier via a first register.

[0006] Furthermore, the multiplier is connected to the output module and the circulation module through the second register.

[0007] Furthermore, the adder is 64 bit Enter the unsigned adder.

[0008] Furthermore, the multiplier is 64 bit Enter the unsigned multiplier.

[0009] Furthermore, there are at least three computing circuits.

[0010] The present invention also provides a n dimensional discrete hyperchaotic pseudo-random number generation method, using the above n The method comprises the following steps: (1) Enter multiple initial values k m , and bring the initial value into n The intermediate value is calculated in the dimensional chaos model, and then the modulus operation is performed on the intermediate value to obtain the calculated value. k m+1 , n The dimensional chaos model is as follows: In the formula a n is the coefficient, and a n Is a positive number.

[0011] Furthermore, in the calculation process of step (1), n The modulo operation is performed on 1 in the dimensional chaotic model, and the modulo operation is to truncate the integer bits of the intermediate value and take 64 bit Decimal gets calculated value k m+1 Output, clear the intermediate integer, and then truncate 4 bit Integers and 60 bit Bringing back the decimals n Iterative calculation is performed in a 3D chaotic model.

[0012] Furthermore, the initial value in step (1) k m For 64 bit Fixed point number, where high 4 bit Indicates the integer part, low 60 bit Indicates the decimal part.

[0013] The beneficial effects of the present invention are: (1) The circuit structure of this generator is simple, it occupies very little FPGA resources, shows a high utilization rate, low hardware power consumption, and the pseudo-random number rate generated can reach 8*nGbps, which can meet most encryption requirements and can also be used for enterprise or higher military purposes. Its equation is simple, the algorithm is easy to implement, the hardware resource occupancy rate is extremely low, and it has a very high speed. Compared with the existing random number generator, the generation rate is the same while the cost is greatly reduced, which improves FPGA The resource utilization efficiency is improved while the power consumption is reduced. Whether it is low cost, low power consumption or high throughput, it far exceeds the limit that the existing pseudo-random number algorithm can achieve.

[0014] (2) The pseudo-random numbers generated have a sufficiently high randomness that they can pass strict and high-standard randomness tests without any additional operations, and the generated sequence has a high complexity and can pass the internationally renowned NIST , TestU 01 and Dieharder test.

[0015] (3) The pseudo-random numbers generated by the present invention only rely on FPGA The chip costs less than 5,000 yuan and is FPGA The usage of internal resources is extremely low, for a single FPGA The chip can output pseudo-random numbers through multiple channels to further improve throughput. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 For the present invention n Schematic diagram of the structure of a dimensional random number generator; Figure 2 For the present invention n Schematic diagram of a dimensional chaos model; Figure 3 This is a schematic diagram of the structure of a random number generator when the present invention adopts three-dimensional discrete hyperchaos; Figure 4 is a schematic diagram of a three-dimensional chaotic model of the present invention; Figure 5 is the 2D phase diagram output by the three-dimensional chaos model algorithm k1, k2 of the present invention; Figure 6 It is the 2D phase diagram output by the three-dimensional chaos model algorithm k2, k3 of the present invention; Figure 7 It is the 2D phase diagram output by the three-dimensional chaos model algorithm k1, k3 of the present invention; Figure 8 is a 3D phase diagram of the three-dimensional chaos model algorithm of the present invention; Fig. 9 It is a Lyapunov exponent diagram when the coefficient a1 of the three-dimensional chaos model algorithm of the present invention changes; Fig.10 It is a Lyapunov exponent diagram when the coefficient a2 of the three-dimensional chaos model algorithm of the present invention changes; Fig.11 It is a Lyapunov exponent diagram when the coefficient a3 of the three-dimensional chaos model algorithm of the present invention changes; Fig.12 A comparison diagram of sample entropy when the present invention adopts a three-dimensional chaos model and sample entropy of other chaos models; Fig.13 This is a comparison diagram of the permutation entropy when the present invention adopts a three-dimensional chaos model and the permutation entropy of other chaos models; In the figure, 1-adder, 2-first register, 3-multiplier, 4-second register, 5-output module, 6-loop module. DETAILED DESCRIPTION

[0017] The present invention is described in detail below in conjunction with embodiments: A sort of n dimensional discrete hyperchaotic pseudo-random number generator, the structure of the hardware circuit is as follows Figure 1 As shown, it includes multiple operation circuits, specifically no less than three operation circuits, the operation circuit includes an adder 1, the adder 1 is used for adding and summing two initial values, and the adder 1 adopts 64 bit Input unsigned adder. Since the initial value is a fixed-point decimal modulo 1, there is no need to consider the carry. Set 64 bit Output, in this embodiment, adder 1 can be two 64 bit The initial value is added and then a 64 bit The value of adder 1 is 64 bit Initial value and 64 bit The output values ​​are all expressed in fixed-point numbers. bit Integer digit, 60 bit The adder 1 is connected to a first register 2, which is used to store a pre-stored value (the value stored before the operation starts) or a value output after the adder 1 operates. The first register 2 is connected to a multiplier 3, and the value output by the first register 2 can be input into the multiplier 3 and multiplied by a coefficient through the multiplier 3. a n , multiplier 3 uses 64 bit Input unsigned multiplier, which can be implemented by cascading DSP hard cores inside FPGA or using LUT Resource construction, after multiplication by multiplier 3, a 128 bit The value of the obtained value is a fixed-point number, where the first 8 bit 120 after the integer bit The multiplier 3 is connected to a second register 4, which is used to store a pre-stored value (a value stored before the operation starts) or a value output by the multiplier 3 after the operation (i.e., an intermediate value). The first register 2 and the second register 4 are used to split the combinational logic to realize a two-stage pipeline operation, and at the same time, two sets of number operations can be performed alternately. The second register 4 is connected to an output module 5 and a loop module 6, which can be used to perform a modulo operation on 1. Specifically, the value in the second register 4 can be divided into two paths, one of which is truncated by the output module 5 to obtain 64. bitThe decimal is used as the output, that is, the output module 5 takes the [119:56] bits of the second register 4 [127:0] as the output, and the other way is cleared to zero by the loop module 6, and 4 is intercepted. bit Integers and 60 bit The decimals form a fixed-point number as the next round of input, that is, the loop module 6 takes the [119:60] bits of the second register 4[127:0] as a 60-bit decimal, and splices 4 bits of zero in the high bit to form the next round of input. bit Integer digit, 60 bit The decimal place is input back to the adder 1 in the corresponding operation circuit for a new round of cycle operation.

[0018] When the present invention is used, a pre-stored value is first stored in the first register 2 and the second register 4. Specifically, the first register 2 stores 64 bit The pre-stored value is input to the multiplier 3 to be multiplied by the corresponding coefficient, and the multiplied value is transmitted to the input port of the second register 4. The second register 4 also stores 128 bit The pre-stored value is divided into two paths. One path is to cut off the integer bit through the output module 5 and take the 64-bit decimal as the output. The other path is to clear the integer through the loop module 6, and then cut off the 4-bit integer and the 60-bit decimal to form the next round of input. The next round of input is divided into two paths, entering the adder 1 in the specific operation circuit to sum with other inputs. After the summation is completed, the value obtained is transmitted to the input port of the first register 2. When the clock rising edge comes, the first register 2 and the second register 4 simultaneously latch the data at their input ports to complete the first operation. With the arrival of the clock rising edge, the first register 2 and the second register 4 do not need to reload the pre-stored value, and automatically latch the value of the input port. The circuit repeats the above steps to realize alternating two sets of number operations.

[0019] The present invention also provides a n dimensional discrete hyperchaotic pseudo-random number generation method, using the above n The method comprises the following steps: Enter multiple 64 bit Initial value of k m , specifically, the initial value k m For 64 bit Fixed point number, where high 4 bit Indicates the integer part, low 60 bit Indicates the decimal part and puts the initial value into n The intermediate value is calculated in the dimensional chaos model, and then the modulus operation is performed on the intermediate value to obtain the calculated value. k m+1 , calculated value k m+1 For 64 bit Numeric value, n The dimensional chaos model is as follows: In the formula a n is the coefficient, and a n is a positive number, specifically a 1 , a 2 and a 3 are also coefficients. In order to prevent negative numbers from appearing in the modulo operation results, in addition, during the calculation process, n In the dimensional chaos model, a modulo operation is performed on 1, and the modulo operation on 1 can be directly expressed as truncating the integer bits of the fixed-point number. Specifically, the modulo operation is to truncate the integer bits of the intermediate value and take 64 bit Decimal gets calculated value k m+1 Output, clear the intermediate integer, and then truncate 4 bit Integers and 60 bit The decimal is brought back into the n-dimensional chaos model for iterative calculation. The structural diagram of the model is shown in Figure 2 As shown in the figure, the equation constructed by the model is very simple, the calculation steps are few, and the algorithm is easy to implement. The model algorithm is implemented in FPGA. In order to improve the sequence complexity and suppress chaotic degradation, the overall operation of the present invention in the FPGA circuit adopts 64 bit Fixed-point design, i.e. high 4 bit Indicates the integer part, low 60 bit The algorithm adopts a two-stage pipeline design to improve the accuracy while suppressing chaotic degradation, and also improve the output bandwidth and throughput, and make the output sequence obtain better chaotic characteristics, which provides a guarantee for further applications (such as encryption, etc.). n In the dimensional chaos model, the initial value is first k m Add and then multiply by the coefficient a n Multiplication, that is, for the operation in the modulus brackets, the coefficients are taken out, the addition in the brackets is calculated first and then the multiplication is calculated, which reduces the multiplication steps that are more time-consuming: In the formula a is the coefficient ， That is, adder 1 can be used to add two 64 bit Initial value of k m Add.

[0020] The following takes a three-dimensional discrete hyperchaotic pseudo-random number generator with three operation circuits as an example to realize a three-dimensional chaotic model (such as Figure 3 Specifically, the three-dimensional chaos model is as follows (as shown in Figure 4 shown): in, k 1. k 2. k 3 represents the output of three dimensions, a 1. a 2 and a 3 are constant coefficients, let the coefficients a 1. a 2 and a 3 are 14.2, 15.1, 15.7 respectively, initial values k 1 m , k 2 m and k 3 m 0.2, 0.1, and 0.7 respectively (in this embodiment, the first register 2 and the second register 4 input the same set of initial values), and a pre-stored value is stored in the first register 2 of each operation circuit, that is, the pre-stored values ​​are k1 m +k2 m , k2 m +k3 m and k1 m +k3 m (i.e. k1 m +k2 m The value of k2 is 0.3, m +k3 m The value of k1 is 0.8, m +k3 m The value is 0.9), and a pre-stored value is stored in the second register 4 of each operation circuit, that is, the pre-stored values ​​are (k1 m +k2 m )* a 1.(k2 m +k3 m )* a 2 and (k1 m +k3 m ) * a 3 (i.e. (k1 m +k2 m )* a The value of 1 is 4.26, (k2 m +k3 m )* a The value of 2 is 12.08, (k1m +k3 m ) * a 3 has a value of 14.13), and then the operation is performed. Specifically, 128 in the second register 4 bit The pre-stored value is divided into two paths after the loop module 6, k1 m+1 and k2 m+1 The sum is performed by adder 1 of the first operation circuit, k2 m+1 and k3 m+1 The sum is performed by adder 1 of the second operation circuit. In addition, k1 m+1 and k3 m+1 The sum is obtained by adding adder 1 of the third operation circuit to obtain k1 m+1 +k2 m+1 , k2 m+1 +k3 m+1 and k1 m+1 +k3 m+1 , the value obtained after the summation is completed is input into the first register 2. At the same time, the pre-stored value in the first register 2 is directly input into the multiplier 3 to be multiplied by the corresponding coefficient, and the intermediate value obtained after the multiplication is transmitted to the second register 4. At the same time, the pre-stored value in the second register 4 is divided into two paths, and the modulo operation is performed on 1. One path is truncated by the output module 5 and a 64-bit decimal is taken as the output, and the other path is cleared by the loop module 6, and then a 4-bit integer and a 60-bit decimal are truncated to form the next round of input. When 50,000 data points are calculated, the 2D and 3D phase diagrams are shown in Figures 5-8. It can be seen from the phase diagram that the distribution is very uniform. In addition, let one of the coefficients change from 0 to 50 to obtain the Lyapunov index (such as Figure 9-11 As shown in Figure 2, it can be seen that as the coefficient increases from 0, the system quickly enters a hyperchaotic state and takes a larger Lyapunov exponent. In addition, by changing a3 from 0 to 1, we can obtain the sample entropy graph and permutation entropy graph, which are compared with the sample entropy and permutation entropy of other chaotic models. Fig.12 , Fig.13 It can be seen that the chaos model algorithm (NDSHS) proposed in the present invention is far superior to the existing algorithm, and if the pseudo-random number generator proposed in this embodiment simultaneously inputs two sets of different initial values ​​for calculation, better chaos performance can be obtained.

[0021] The three-dimensional chaos model of the present invention is implemented in FPGA. The main resource occupancy rates in FPGA are shown in Table 1. The FPGA model selected is Xilinx Kintex-7 xc7k325tffg900-2: Table 1 It can be seen from Table 1 that the consumption of FPGA resources is extremely low.

[0022] The power consumption of the invention is 267mw, and the efficiency is 10pJ / b. Compared with the random number generators available on the market, the energy consumption is extremely low.

[0023] And the timing analysis shows that the generator operates at a maximum frequency of 136Mhz and a rate of about 24Gbps (since the rate increases linearly with the increase of the dimension, n The circuit speed is approximately n *8 Gbps ), which can meet most daily needs, such as picture and video encryption, etc. Take high-bandwidth video as an example (after H.264 encoding): video (4K60P) 20-50Mbps, video (8K60P) 80-200Mbps, and can also meet the requirements of Gbps rate for enterprises or higher purposes. Whether it is low cost, low power consumption or high throughput, it far exceeds the limit that the existing pseudo-random number algorithm can achieve. At the same time, the generated sequence complexity is high and can pass the internationally renowned NIST, TestU01 and Dieharder and other randomness standard tests.

[0024] In addition to the performance advantages, the present invention also has significant cost advantages. The current market price of pseudo-random code generator products with the same performance is usually several hundred thousand RMB. For example, the 3.35 Gb / s pseudo-random code generator (81134A) of Agilent Technologies is about 500,000 RMB per unit, while the cost of the true random password module and true random password generator developed by Taiyuan University of Technology is only about 50,000 RMB per unit. The pseudo-random numbers generated by the present invention only rely on FPGA chips, and the cost is only less than 5,000 RMB. In addition, the use of FPGA internal resources is extremely low. Therefore, for a single FPGA chip, multiple channels can be used to output pseudo-random numbers, further improving throughput and reducing costs.

Claims

1. A n dimensional discrete hyperchaotic pseudo-random number generator, characterized in that: It comprises a plurality of operation circuits, wherein the operation circuit comprises an adder, the adder is connected to a multiplier, the multiplier is connected to an output module for outputting random numbers and a circulation module, and the circulation module is used to input the random numbers back to the adder for circulation calculation.

2. A method according to claim 1 n dimensional discrete hyperchaotic pseudo-random number generator, characterized in that: The adder is connected to the multiplier via a first register.

3. A method according to claim 1 n dimensional discrete hyperchaotic pseudo-random number generator, characterized in that: The multiplier is connected to the output module and the circulation module through the second register.

4. A method according to claim 1 n dimensional discrete hyperchaotic pseudo-random number generator, characterized in that: The adder is 64 bit Enter the unsigned adder.

5. A method according to claim 1 n dimensional discrete hyperchaotic pseudo-random number generator, characterized in that: The multiplier is 64 bit Enter the unsigned multiplier.

6. A method according to claim 1 n dimensional discrete hyperchaotic pseudo-random number generator, characterized in that: There are at least three operation circuits.

7. A n A method for generating dimensional discrete hyperchaotic pseudo-random numbers, using any one of claims 1 to 6 n dimensional discrete hyperchaotic pseudo-random number generator, characterized in that: The following steps are involved: (1) Enter multiple initial values k m , and bring the initial value into n The intermediate value is calculated in the dimensional chaos model, and then the modulus operation is performed on the intermediate value to obtain the calculated value. k m+1 , n The dimensional chaos model is as follows: In the formula a n is the coefficient, and a n Is a positive number.

8. A method according to claim 7 n The discrete hyperchaotic pseudo-random number generation method is characterized by: The modulo operation is n 1 is performed in the dimensional chaos model, specifically by truncating the intermediate value to an integer and taking 64 bit Decimal gets calculated value k m+1 Output, clear the intermediate integer, and then truncate 4 bit Integers and 60 bit Bringing back the decimals n Iterative calculation is performed in a 3D chaotic model.

9. A method according to claim 7 n The discrete hyperchaotic pseudo-random number generation method is characterized by: The initial value in step (1) k m For 64 bit Fixed point number, where high 4 bit Indicates the integer part, low 60 bit Indicates the decimal part.

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