A CRC-32 check code generation method based on RISC-V instruction set extension

Abstract

This invention relates to a CRC-32 checksum generation method based on a RISC-V instruction set extension, comprising: defining an instruction set and adding CRC-32 instructions to the RISC-V instruction set; adding a CRC calculation unit to the RISC-V processor for calculating and processing the CRC-32 operation logic; modifying the RISC-V toolchain accordingly to support the compilation and generation of CRC-32 instructions; 1) initialization; 2) reading data in blocks; 3) executing CRC-32 instructions; 4) updating data blocks until all data blocks have been processed; 5) outputting the result: after processing all data blocks, inverting the bits to obtain the final CRC-32 checksum. This invention uses CRC-32 instructions to improve the speed of cryptographic algorithms and reduce the size of application programs, allowing users to directly call them and thus improve development efficiency.

Description

Technical Field

[0001] This invention relates to a CRC-32 checksum generation method based on RISC-V instruction set extension, belonging to the field of CRC-32 checksum generation technology. Background Technology

[0002] CRC-32 checksums are widely used in data transmission and storage to verify data integrity. Currently, calculating CRC-32 checksums using high-level programming languages ​​results in numerous repetitive operations and increased instructions, reducing efficiency. While using FPGAs to implement CRC-32 checksum generation is the fastest, its versatility is limited. Traditional CRC-32 checksum generation algorithms typically process data byte-by-byte, involving table lookups, shifting, and XOR operations. This computational process demands high performance, especially when handling large datasets, where it is computationally inefficient. Therefore, implementing a CRC-32 checksum algorithm using instructions balances versatility and hardware acceleration performance.

[0003] RISC-V is a modular and open instruction set architecture that allows users to define custom extension instructions. These extension instructions can enhance the performance of specific computing tasks, thereby improving performance and efficiency in certain scenarios. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a CRC-32 checksum generation method based on RISC-V instruction set extension;

[0005] The purpose of this invention is to address the problem that CRC-32 checksum generation in the prior art can only be implemented through hardware circuit design or software. By using the RISC-V instruction set extension method, the CRC-32 calculation process is integrated into a dedicated hardware instruction.

[0006] This invention improves the speed and efficiency of CRC-32 checksum generation by extending the RISC-V instruction set and designing acceleration instructions specifically for the CRC-32 checksum generation process.

[0007] Terminology Explanation:

[0008] 1. The ALU, or Arithmetic Logic Unit, is a component in a processor used to perform arithmetic and logical operations. It is responsible for performing operations such as addition, subtraction, multiplication, division, and bitwise operations. In this invention, the ALU will be used to assist in CRC-32 calculations, especially when performing bitwise operations and shift operations.

[0009] 2. Memory refers to the hardware in a computer system used to store data and programs. In this invention, the memory will be used to store the data to be calculated for CRC-32 and the pre-calculated CRC-32 value.

[0010] 3. Registers are fast storage areas within the processor used to temporarily store data during instruction execution. In this invention, Registers will be used to store intermediate results and states during the CRC-32 calculation process.

[0011] 4. CRC, Cyclic Redundancy Check, is a commonly used division-based checksum technique used to detect errors during data transmission or storage. CRC-32 is a type of CRC that uses a 32-bit polynomial to generate a checksum to ensure data integrity.

[0012] To achieve the above objectives, the present invention provides the following technical solution:

[0013] A method for generating CRC-32 checksums based on RISC-V instruction set extensions, comprising:

[0014] Defining an instruction set means adding CRC-32 instructions to the RISC-V instruction set;

[0015] Add a CRC calculation unit to the RISC-V processor. The CRC calculation unit is used to calculate and process the CRC-32 operation logic.

[0016] The RISC-V toolchain was modified accordingly to support the compilation and generation of CRC-32 instructions;

[0017] 1) Initialization; initialize the CRC register to 0xFFFFFFFF;

[0018] 2) Read data in blocks: Load data into register rs2 block by block according to the bit width of the data to be processed, and load the current CRC register value into register rs1;

[0019] 3) Execute CRC-32 instructions: Execute CRC-32 instructions on registers rs1 and rs2, calculate and update the CRC registers; after each instruction execution, the contents of the CRC registers are updated, including the new CRC calculation result;

[0020] 4) Update data blocks: Repeat steps 2) and 3) for the next data block until all data blocks have been processed;

[0021] 5) Output result: After processing all data blocks, the final value in the CRC register is bitwise inverted with 0xFFFFFFFF to obtain the final CRC-32 checksum.

[0022] According to a preferred embodiment of the present invention, different CRC-32 instructions are designed for different data types, as follows:

[0023] When the data type is byte data, the CRC-32 instruction is CRC32_B;

[0024] When the data type is half-word data, the CRC-32 instruction is CRC32_H;

[0025] When the data type is processed word data, the CRC-32 instruction is CRC32_W;

[0026] When the data type is double-word data, the CRC-32 instruction is CRC32_D;

[0027] The operation format of each instruction is as follows:

[0028] CRC32_B rd,rs1,rs2 refers to: calculating the CRC32 value of 8-bit data;

[0029] CRC32_H rd,rs1,rs2 refers to: calculating the CRC32 value of 16-bit data;

[0030] CRC32_W rd,rs1,rs2 refers to: calculating the CRC32 value of 32-bit data;

[0031] CRC32_D rd,rs1,rs2 refers to: calculating the CRC32 value of 64-bit data;

[0032] Among them, the target register rd is used to store the final CRC32 value; register rs1 is used to store the original data; and register rs2 is used to store the current CRC32 accumulated value.

[0033] A further preferred format for the CRC-32 instruction is:

[0034] For CRC-32 instructions, R-type instructions are used to process data in registers; R-type instructions have 3 operands, two source registers and one destination register; the two source registers are register rs1 and register rs2, and the destination register is the CRC register.

[0035] According to a preferred embodiment of the present invention, the RISC-V processor includes an instruction register, a decoding unit, an ALU, a memory, registers, a CRC operation unit, and a lookup register; the instruction register, decoding unit, ALU, and memory are connected in sequence; the instruction register, registers, CRC operation unit, and lookup register are connected in sequence, the decoding unit is connected to registers, and the memory is connected to the CRC operation unit;

[0036] Instruction Register: Stores intermediate CRC results and updates them cumulatively with each instruction execution; Decoding Unit: Parses instructions retrieved from instruction memory and extracts key information required to execute the instruction; ALU: Assists in CRC-32 calculation; Memory: Stores data to be calculated for CRC-32 and pre-calculated CRC-32 values; Registers: Stores intermediate results and states during CRC-32 calculation; CRC Operation Unit: Calculates and processes the CRC-32 operation logic; Lookup Register: Stores the pre-calculated CRC32 value for each byte.

[0037] According to a preferred embodiment of the present invention, the RISC-V toolchain is modified accordingly to support the compilation and generation of CRC-32 instructions; including:

[0038] Modify the assembler: Add support for CRC-32 instructions to the assembler;

[0039] Modify the compiler: Add embedded CRC-32 instruction support in the GCC or LLVM compiler;

[0040] Modify the linker: Ensure the linker correctly processes the target code format of CRC-32 instructions and ensures the generated binary program correctly executes extended instructions.

[0041] A computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the above-described CRC-32 checksum generation method based on the RISC-V instruction set extension.

[0042] A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above-described CRC-32 checksum generation method based on the RISC-V instruction set extension.

[0043] The beneficial effects of this invention are as follows:

[0044] This invention enables CRC-32 checksum generation instructions to be integrated into RISC-V processors. Compared to pure software implementation, using these instructions can improve the speed of cryptographic algorithms and reduce the size of application programs. Users can directly call these instructions to improve development efficiency. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the RISC-V processor architecture.

[0046] Figure 2 A flowchart illustrating the process of executing CRC-32 checksum generation instructions in a RISC-V processor;

[0047] Figure 3 A flowchart illustrating the detailed process of generating CRC-32 checksums. Detailed Implementation

[0048] The present invention will be further defined below with reference to the accompanying drawings and embodiments, but is not limited thereto.

[0049] Example 1

[0050] A method for generating CRC-32 checksums based on RISC-V instruction set extensions, comprising:

[0051] Defining an instruction set means adding dedicated CRC-32 instructions to the RISC-V instruction set; these instructions can directly perform CRC-32 calculations by manipulating the data in registers.

[0052] Hardware modification: To implement custom CRC-32 instructions, a dedicated CRC calculation unit needs to be added to the RISC-V processor. The CRC calculation unit is used to calculate and process the CRC-32 operation logic.

[0053] Software modification: In order to use custom CRC-32 instructions, the RISC-V toolchain (such as GCC, LLVM) needs to be modified accordingly to support the compilation and generation of CRC-32 instructions;

[0054] 1) Initialization; initialize the CRC register to 0xFFFFFFFF;

[0055] 2) Read data in blocks: Load data into register rs2 block by block according to the bit width of the data to be processed (8, 16, 32 or 64 bits), and load the current CRC register value (initially 0xFFFFFFFF) into register rs1;

[0056] 3) Execute CRC-32 instructions: Execute CRC-32 instructions on registers rs1 and rs2, calculate and update the CRC registers; after each instruction execution, the contents of the CRC registers are updated, including the new CRC calculation result;

[0057] 4) Update data blocks: Repeat steps 2) and 3) for the next data block until all data blocks have been processed;

[0058] 5) Output result: After processing all data blocks, the final value in the CRC register is bitwise inverted with 0xFFFFFFFF to obtain the final CRC-32 checksum.

[0059] Example 2

[0060] The difference between the CRC-32 checksum generation method based on the RISC-V instruction set extension described in Example 1 and the method described in Example 1 is as follows:

[0061] Different CRC-32 instructions are designed for different data types, as follows:

[0062] When the data type is byte data (8 bits), the CRC-32 instruction is CRC32_B;

[0063] When the data type is half-word data (16 bits), the CRC-32 instruction is CRC32_H;

[0064] When the data type is processing word data (32 bits), the CRC-32 instruction is CRC32_W;

[0065] When the data type is double-word data (64 bits), the CRC-32 instruction is CRC32_D;

[0066] The operation format of each instruction is as follows:

[0067] CRC32_B rd,rs1,rs2 refers to: calculating the CRC32 value of 8-bit data;

[0068] CRC32_H rd,rs1,rs2 refers to: calculating the CRC32 value of 16-bit data;

[0069] CRC32_W rd,rs1,rs2 refers to: calculating the CRC32 value of 32-bit data;

[0070] CRC32_D rd,rs1,rs2 refers to: calculating the CRC32 value of 64-bit data;

[0071] Among them, the target register rd is used to store the final CRC32 value; register rs1 is used to store the original data; and register rs2 is used to store the current CRC32 accumulated value.

[0072] The format of the CRC-32 instruction is:

[0073] RISC-V instructions typically come in three types: R-type, I-type, and S-type. For CRC-32 instructions, R-type instructions are used to process data in registers; R-type instructions have three operands, two source registers and one destination register; the two source registers are register rs1 and register rs2, and the destination register is the CRC register.

[0074] As shown in Table 1:

[0075] funct7 rs2 rs1 funct3 rd opcode

[0076] In this configuration, `funct7` specifies the function category, identifying the CRC-32 operation type. `rs2` is the source register 2, used to store the data to be calculated. `rs1` is the source register 1, used to store the current CRC value. `funct3` distinguishes the bit width of the operation data (8-bit, 16-bit, 32-bit, 64-bit). `rd` is the destination register, storing the calculated CRC value. `opcode` specifies the operation type, allowing a specific value to be assigned to the CRC-32 operation.

[0077] like Figure 1 As shown, the RISC-V processor includes an instruction register, a decoding unit, an ALU, a memory, registers, a CRC operation unit, and a lookup table register (LUT); the instruction register, decoding unit, ALU, and memory are connected in sequence; the instruction register, registers, CRC operation unit, and lookup table register are connected in sequence, the decoding unit is connected to the registers, and the memory is connected to the CRC operation unit;

[0078] Instruction Register: Stores intermediate CRC results and updates them cumulatively with each instruction execution; Decoding Unit: Parses instructions retrieved from instruction memory and extracts key information required for execution; ALU: Assists in CRC-32 calculation, especially during bitwise operations and shift operations; Memory: Stores data to be calculated for CRC-32 and pre-calculated CRC-32 values; Registers: Stores intermediate results and states during CRC-32 calculation; CRC Operation Unit: Calculates and processes the CRC-32 operation logic; Lookup Register: Stores the pre-calculated CRC32 value for each byte.

[0079] Specific implementation steps:

[0080] Register read: When the instruction is executed, input data is read from the source register rs1.

[0081] Lookup operation: Based on the byte value of the input data, find the corresponding CRC-32 value from the LUT.

[0082] XOR operation: Perform an XOR operation between the found value and the current CRC cumulative value (from the rs2 register).

[0083] Shift operation: Update the CRC value by shifting.

[0084] Result storage: Store the calculated final CRC value into the target register rd.

[0085] The RISC-V toolchain was modified accordingly to support the compilation and generation of CRC-32 instructions; including:

[0086] Modify the assembler: Add support for CRC-32 instructions to the assembler; enable it to recognize and parse CRC-32 extended instructions.

[0087] Modify the compiler: Add embedded CRC-32 instruction support to the GCC or LLVM compiler; developers can directly call these instructions using inline assembly or compiler built-in functions.

[0088] Modify the linker: Ensure the linker correctly processes the target code format of CRC-32 instructions and ensures the generated binary program correctly executes extended instructions.

[0089] like Figure 2 As shown, the CRC-32 checksum generation instructions are executed in the RISC-V processor; including:

[0090] 1) Start: Start from the start node;

[0091] 2) Fetching instructions from the instruction register: The RISC-V processor reads the next instruction to be executed from the instruction register;

[0092] 3) Determine if the instruction is a CRC calculation instruction: The decoding unit checks whether the current instruction is an extended instruction specifically for CRC-32 calculation. If not, proceed to execute a normal instruction. If yes, proceed to step 4).

[0093] 4) Start the CRC-32 operation logic: The RISC-V processor will start the CRC-32 operation logic and begin to execute the CRC-32 operation.

[0094] 5) Store the CRC-32 result in the register file: After the calculation is completed, store the CRC-32 calculation result in the specified register in the register file.

[0095] 6) Update program counter: The RISC-V processor updates its program counter to point to the next instruction to be executed.

[0096] 7) Fetch the next instruction from the instruction register: The RISC-V processor reads the next instruction from the instruction register again, and the process returns to step 3) to continue to determine the instruction type.

[0097] like Figure 3 The diagram shows the detailed process of CRC-32 checksum generation, including:

[0098] 1) Start: Start from the start node;

[0099] 2) Initialize the CRC register: Set the initial value of the CRC register, usually a predefined constant. (The most common CRC-32 polynomial is defined in the IEEE 802.3 standard, with an initial value of 0xFFFFFFFF.)

[0100] 3) Read into data register: Read data from the data source into the data register.

[0101] 4) Has all data been processed?: Check if all data has been processed. If all data has been processed, the process proceeds to the next step after CRC-32 calculation is complete. If not all data has been processed, the process continues to the next step.

[0102] 5) XOR the data bits with the highest bit of the CRC register: XOR the current highest bit in the data register with the highest bit of the CRC register.

[0103] 6) Shift the CRC register one bit to the left: Shift all bits in the CRC register one bit to the left to prepare for the XOR operation of the next bit of data.

[0104] 7) Store the XOR result in the most significant bit of the CRC register: Store the XOR result from step 5 in the most significant bit of the CRC register.

[0105] 8) Read the next bit of data: Read the next bit of data from the data register to prepare for the next round of XOR operation.

[0106] 9) Return to step 4): The process returns to step 4) to continue checking whether all data has been processed.

[0107] 10) CRC-32 calculation complete: The CRC-32 calculation is complete after all data bits have been processed.

[0108] 11) Store the result in a register: Store the final CRC-32 value in a register or output it to a specified location.

[0109] 12) Return to main process: The process ends and returns to the main program or performs subsequent operations.

[0110] Example 3

[0111] A computer device includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the CRC-32 checksum generation method based on the RISC-V instruction set extension described in Embodiment 1 or 2.

[0112] Example 4

[0113] A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the CRC-32 checksum generation method based on the RISC-V instruction set extension described in Embodiment 1 or 2.

Claims

1. A method for generating CRC-32 checksums based on RISC-V instruction set extensions, characterized in that, include: Defining an instruction set means adding CRC-32 instructions to the RISC-V instruction set; Add a CRC calculation unit to the RISC-V processor. The CRC calculation unit is used to calculate and process the CRC-32 operation logic. The RISC-V toolchain was modified accordingly to support the compilation and generation of CRC-32 instructions; 1) Initialization; 2) Read data in blocks: Load data into register rs2 block by block according to the bit width of the data to be processed, and load the current CRC register value into register rs1; 3) Execute CRC-32 instructions: Execute CRC-32 instructions on registers rs1 and rs2, calculate and update the CRC registers; after each instruction execution, the contents of the CRC registers are updated, including the new CRC calculation result; 4) Update data blocks: Repeat steps 2) and 3) for the next data block until all data blocks have been processed; 5) Output result: After processing all data blocks, the final value in the CRC register is bitwise inverted with 0xFFFFFFFF to obtain the final CRC-32 checksum. Different CRC-32 instructions are designed for different data types, as follows: When the data type is byte data, the CRC-32 instruction is CRC32_B; When the data type is half-word data, the CRC-32 instruction is CRC32_H; When the data type is processed word data, the CRC-32 instruction is CRC32_W; When the data type is double-word data, the CRC-32 instruction is CRC32_D; The operation format of each instruction is as follows: CRC32_B rd, rs1, rs2 refer to: calculating the CRC32 value of 8-bit data; CRC32_H rd, rs1, rs2 refer to: calculating the CRC32 value of 16-bit data; CRC32_W rd, rs1, rs2 refers to: calculating the CRC32 value of 32-bit data; CRC32_D rd, rs1, rs2 refer to: calculating the CRC32 value of 64-bit data; Among them, the target register rd is used to store the final CRC32 value; register rs1 is used to store the original data; and register rs2 is used to store the current accumulated CRC32 value. The RISC-V processor includes an instruction register, a decoding unit, an ALU, a memory, registers, a CRC operation unit, and a lookup table register; the instruction register, decoding unit, ALU, and memory are connected in sequence; the instruction register, registers, CRC operation unit, and lookup table register are connected in sequence, the decoding unit is connected to the registers, and the memory is connected to the CRC operation unit; Instruction Register: Stores intermediate CRC results and updates them cumulatively with each instruction execution; Decoding Unit: Parses instructions retrieved from instruction memory and extracts key information required to execute the instruction; ALU: Assists in CRC-32 calculation; Memory: Stores data to be calculated for CRC-32 and pre-calculated CRC-32 values; Registers: Stores intermediate results and states during CRC-32 calculation; CRC Operation Unit: Calculates and processes the CRC-32 operation logic; Lookup Register: Stores the pre-calculated CRC32 value for each byte.

2. The CRC-32 checksum generation method based on RISC-V instruction set extension according to claim 1, characterized in that, The format of the CRC-32 instruction is: For CRC-32 instructions, R-type instructions are used to process data in registers; R-type instructions have 3 operands, two source registers and one destination register; the two source registers are register rs1 and register rs2, and the destination register is the CRC register.

3. A CRC-32 checksum generation method based on RISC-V instruction set extension as described in claim 1 or 2, characterized in that, The RISC-V toolchain was modified accordingly to support the compilation and generation of CRC-32 instructions; including: Modify the assembler: Add support for CRC-32 instructions to the assembler; Modify the compiler: Add embedded CRC-32 instruction support in the GCC or LLVM compiler; Modify the linker: Ensure the linker correctly processes the target code format of CRC-32 instructions and ensures the generated binary program correctly executes extended instructions.

4. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the CRC-32 checksum generation method based on any one of claims 1-3.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the CRC-32 checksum generation method based on the RISC-V instruction set extension as described in any one of claims 1-3.

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