A data prefetch control system and a processor

Abstract

The present invention discloses a data prefetching control system and a processor, relating to the technical field of processors. The system includes: a fusion prefetching module, a prefetching control module, a prefetching cache control module, a prefetching cache module, and a multi-level cache module; wherein, the fusion prefetching module includes prefetchers corresponding to respective caches at all levels in the multi-level cache module, and the prefetchers corresponding to at least two levels of caches in the multi-level cache module are different; the present invention utilizes the setting of the fusion prefetching module to fuse and use prefetching algorithms at different cache levels, facilitating the scheduling of complementary data between algorithms, and capable of reusing a part of storage resources, enabling rapid data interaction, reducing resource consumption, and improving the prefetching accuracy rate; and through the settings of the prefetching cache module and the multi-level cache module, hierarchical storage of prefetching data can be achieved, and by using the prefetching cache module to store prefetching data with relatively low prefetching priorities, the data prefetching coverage rate can be improved, achieving a better data prefetching effect.

Description

Technical Field

[0001] The present invention relates to the technical field of processors, and particularly to a data prefetch control system and a processor. Background Art

[0002] Data prefetching refers to the process of loading data that may be accessed in the future from the main memory (i.e., the memory) into the cache or other fast storage areas in advance during the operation of a processor (such as a central processing unit CPU), so as to reduce the latency of data access by the processor and improve the program execution efficiency. Currently, the data prefetching function is widely applied in various processors, and the prefetching effect directly affects the performance of the processor. Prefetching algorithms are generally trained and decision-making based on the characteristics of data access, such as consecutive access, interval access, and associative access in terms of time and space; at the same time, there are also requirements for the timing, frequency, and amount of data prefetching, otherwise problems such as waste of memory access bandwidth and pollution of the cache (cache memory) will occur. In multi-threaded data processing and superscalar out-of-order parallel execution architectures, data access and dependency relationships are complex, and memory access patterns are diverse, and the requirements for prefetching algorithms and prefetch control are also getting higher and higher.

[0003] Currently, most processors adopt prefetching algorithms such as stream prefetching and offset prefetching with relatively clear characteristics. The prefetching in different levels of caches is relatively independent, and the prefetching decision-making is relatively conservative. Although a certain prefetching accuracy rate is guaranteed, the prefetching coverage rate is not very high, it is difficult to adapt to relatively complex application scenarios, and the improvement of system performance is limited. Therefore, how to improve the data prefetching coverage rate on the basis of ensuring the accuracy rate and achieve a better data prefetching effect is an urgent problem to be solved today. Summary of the Invention

[0004] The purpose of the present invention is to provide a data prefetch control system and a processor to improve the data prefetching coverage rate on the basis of ensuring the accuracy rate and achieve a better data prefetching effect.

[0005] To solve the above technical problems, the present invention provides a data prefetch control system, including: a fusion prefetch module, a prefetch control module, a prefetch cache control module, a prefetch cache module, and a multi-level cache module;

[0006] The fusion prefetch module is configured to receive a memory access request sent by a memory access execution unit; make a prefetch decision according to the memory access address in the memory access request by using the prefetch algorithms of each prefetch unit to obtain prefetch decision information; wherein, the fusion prefetch module includes prefetch units corresponding to each level of cache in the multi-level cache module, and the prefetch units corresponding to at least two levels of cache in the multi-level cache module are different;

[0007] The prefetch control module is configured to prioritize the prefetch decision information and store the sorted prefetch decision information into a prefetch information queue;

[0008] The prefetch cache control module is configured to retrieve and determine the target decision information in the prefetch information queue; find and obtain the prefetch data corresponding to the target decision information from the memory; and store each of the prefetch data into their respective multi-level cache modules and prefetch cache modules according to the prefetch priority of the target decision information; wherein, if the prefetch data corresponding to the target decision information is not stored in the multi-level cache module or both the multi-level cache module and the prefetch cache module, the prefetch priority of the prefetch data stored in the multi-level cache module is higher than the prefetch priority of the prefetch data stored in the prefetch cache module.

[0009] On the other hand, the prefetch control module is specifically configured to prioritize the prefetch decision information according to the decision threshold and / or prefetch marker corresponding to each of the prefetch decision information, and store the sorted prefetch decision information into the prefetch information queue.

[0010] On the other hand, the system further includes:

[0011] A prefetch configuration module, configured to store the prefetch parameters corresponding to each of the prefetch algorithms; wherein, the prefetch parameters include at least one of a decision threshold, a prefetch priority, a prefetch degree, and / or a prefetch data block.

[0012] On the other hand, the step of prioritizing the prefetch decision information according to the decision threshold and / or prefetch marker corresponding to each of the prefetch decision information, and storing the sorted prefetch decision information into the prefetch information queue includes:

[0013] According to the prefetch markers in each of the prefetch decision information, find and determine the prefetch priority and decision threshold of each of the prefetch decision information from the prefetch configuration module;

[0014] Sort the prefetch decision information according to the prefetch priority and decision threshold of each of the prefetch decision information to obtain a decision information queue; wherein, for two adjacent prefetch decision information in the decision information queue, the prefetch priority of the previous prefetch decision information is higher than that of the subsequent prefetch decision information, or the decision threshold of the previous prefetch decision information is greater than that of the subsequent prefetch decision information;

[0015] Store the prefetch decision information in the decision information queue into the prefetch information queue in the order from front to back.

[0016] On the other hand, the prefetch control module is specifically configured to receive each prefetch decision information group sent by the fusion prefetch module; prioritize the prefetch decision information groups according to the decision thresholds and / or prefetch flags corresponding to the prefetch decision information groups, and store the sorted prefetch decision information groups into the prefetch information queue; wherein, the prefetch decision information group includes prefetch decision information within the same prefetch area range.

[0017] On the other hand, the prefetch information queue includes a retrieval counter, a prefetch counter, a retrieval address pointer, a prefetch address pointer, and retrieval flags, prefetch flags, and decision group flags corresponding to each of the prefetch decision information; wherein, the decision group flag includes at least one of a group flag counter, a decision count, and a valid flag; the retrieval counter is used to count the number of times to be retrieved, the prefetch counter is used to count the number of times to be prefetched, the retrieval address pointer is used to indicate the prefetch decision information currently retrieved in the prefetch information queue, the prefetch address pointer is used to indicate the prefetch decision information currently prefetched in the prefetch information queue, the retrieval flag is used to indicate whether each prefetch decision information in the prefetch information queue has been retrieved, the prefetch flag is used to indicate whether each prefetch decision information in the prefetch information queue needs to be prefetched, the group flag counter is used to indicate the prefetch decision information group where each prefetch decision information in the prefetch information queue is located, the decision count is used to indicate the number of prefetch decision information in the prefetch decision information group where each prefetch decision information in the prefetch information queue is located, and the valid flag is used to indicate whether each prefetch decision information in the prefetch information queue is valid; the prefetch decision information group includes prefetch decision information within the same prefetch area range.

[0018] On the other hand, the retrieval to determine the target decision information in the prefetch information queue includes:

[0019] If the retrieval counter is greater than 0, then according to the retrieval address pointer, read the current prefetch decision information in the prefetch information queue;

[0020] Detect whether the prefetch data corresponding to the current prefetch decision information is stored in the multi-level cache module;

[0021] If the prefetch data corresponding to the current prefetch decision information is stored, then set the retrieval flag corresponding to the current prefetch decision information to the retrieved identifier, and keep the prefetch flag corresponding to the current prefetch decision information as the default non-prefetch identifier;

[0022] If there is no prefetch data corresponding to the current prefetch decision information, then use the current prefetch decision as the target decision information, set the retrieval flag corresponding to the current prefetch decision information to the retrieved flag, and set the prefetch flag corresponding to the current prefetch decision information to the to-be-prefetched flag.

[0023] On the other hand, the finding and obtaining the prefetch data corresponding to the target decision information from the memory includes:

[0024] If the prefetch counter is greater than 0, then read the retrieval flag and the prefetch flag corresponding to the current prefetch decision information pointed to by the prefetch address pointer;

[0025] When the retrieval flag corresponding to the current prefetch decision information pointed to by the prefetch address pointer is the retrieved flag and the prefetch flag is the to-be-prefetched flag, find and obtain the prefetch data corresponding to the current prefetch decision information from the memory;

[0026] When the retrieval flag corresponding to the current prefetch decision information pointed to by the prefetch address pointer is the retrieved flag and the prefetch flag is the not-to-be-prefetched flag, subtract 1 from the value of the prefetch counter and update the pointing position of the prefetch address pointer;

[0027] When the retrieval flag corresponding to the current prefetch decision information pointed to by the prefetch address pointer is the default non-retrieved flag, execute the step of reading the retrieval flag and the prefetch flag corresponding to the current prefetch decision information pointed to by the prefetch address pointer.

[0028] On the other hand, the finding and obtaining the prefetch data corresponding to the target decision information from the memory includes:

[0029] According to the priority information corresponding to each of the target decision information, determine the bus read data priority of each of the target decision information; wherein, the priority information includes at least one of the prefetch priority, the decision threshold, and the prefetch degree execution situation;

[0030] In the order from high to low of the bus read data priority, use the target data reading method corresponding to each of the bus read data priorities to find and obtain the prefetch data corresponding to each of the target decision information from the memory.

[0031] On the other hand, the storing each of the prefetch data into the respective multi-level cache module and prefetch cache module according to the prefetch priority of the target decision information includes:

[0032] Determine target prefetch data from the prefetch data; wherein, the target prefetch data includes prefetch data corresponding to prefetch decision information with the highest prefetch priority and a decision threshold greater than the multi-level cache threshold in each target prefetch decision information group, the target prefetch decision information group is the prefetch decision information group where the prefetch decision information corresponding to each prefetch data is located, and the prefetch decision information group includes prefetch decision information within the same prefetch area range;

[0033] Store the target prefetch data into the multi-level cache module, and store the non-target prefetch data in the prefetch data into the prefetch cache module.

[0034] On the other hand, the prefetch cache control module is further configured to configure the initial life cycle of each prefetch data according to the prefetch priority corresponding to each prefetch data in the prefetch cache module.

[0035] On the other hand, the prefetch cache control module is further configured to receive the memory access request sent by the memory access execution unit; retrieve whether the access data corresponding to the memory access address in the memory access request is stored in the prefetch cache module; if the access data is stored in the prefetch cache module, obtain the access data from the prefetch cache module and return it to the memory access execution unit; if the access data is not stored in both the prefetch cache module and the multi-level cache module, obtain the access data corresponding to the memory access address from the memory according to the memory access address in the memory access request and return it to the memory access execution unit.

[0036] On the other hand, the prefetch cache control module is further configured to, if the access data is not stored in the prefetch cache module and the access data is stored in the multi-level cache module, set the valid flag corresponding to the same-group decision information in the prefetch decision information group corresponding to the access data in the prefetch information queue to an invalid flag; wherein, the same-group decision information is the prefetch decision information other than the prefetch decision information corresponding to the access data in the prefetch decision information group corresponding to the access data.

[0037] After obtaining the access data from the prefetch cache module and returning it to the memory access execution unit, it includes: storing the access data into the multi-level cache module, and setting the valid flag corresponding to the same-group decision information in the prefetch decision information group corresponding to the access data in the prefetch information queue to the invalid flag.

[0038] On the other hand, the system further includes:

[0039] The memory access execution unit is used to generate the memory access request according to the received memory access instruction information of the processor; and send the memory access request to the fusion prefetch module, the prefetch cache control module, and the multi-level cache module.

[0040] The multi-level cache module is further used to detect whether the access data corresponding to the memory access address in the memory access request is stored in each level of cache according to the received memory access request; if so, return the stored access data to the memory access execution unit, and send the corresponding cache hit information to the prefetch cache control module; if not, send the corresponding cache miss information to the prefetch cache control module.

[0041] In addition, the present invention also provides a processor, including the data prefetch control system as described above.

[0042] A data prefetch control system provided by the present invention includes: a fusion prefetch module, a prefetch control module, a prefetch cache control module, a prefetch cache module, and a multi-level cache module; the fusion prefetch module is used to receive the memory access request sent by the memory access execution unit; make a prefetch decision according to the memory access address in the memory access request by using the prefetch algorithms of each prefetch unit to obtain prefetch decision information; wherein, the fusion prefetch module includes prefetch units corresponding to each level of cache in the multi-level cache module, and the prefetch units corresponding to at least two levels of cache in the multi-level cache module are different; the prefetch control module is used to sort the prefetch decision information by priority, and store the sorted prefetch decision information in the prefetch information queue; the prefetch cache control module is used to retrieve and determine the target decision information in the prefetch information queue; find and obtain the prefetch data corresponding to the target decision information from the memory; store each prefetch data in its corresponding multi-level cache module and prefetch cache module according to the prefetch priority of the target decision information; wherein, the prefetch data corresponding to the target decision information is not stored in the multi-level cache module or both the multi-level cache module and the prefetch cache module, and the prefetch priority of the prefetch data stored in the multi-level cache module is higher than that of the prefetch data stored in the prefetch cache module.

[0043] It can be seen that the present invention uses the setting of the fusion prefetch module to fuse the prefetch algorithms of different cache levels, which is convenient for the scheduling of complementary data between algorithms, can reuse a part of the storage resources, can quickly interact data, reduce resource consumption, and improve the prefetch accuracy; and through the settings of the prefetch cache module and the multi-level cache module, hierarchical storage of prefetch data can be realized, and the prefetch cache module is used to store prefetch data with relatively low prefetch priority, which can improve the data prefetch coverage rate and achieve a better data prefetch effect. Description of the Drawings

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on the provided accompanying drawings.

[0045] Figure 1 The structural block diagram of a data prefetch control system provided by an embodiment of the present invention;

[0046] Figure 2 The structural schematic diagram of another data prefetch control system provided by an embodiment of the present invention;

[0047] Figure 3 The flowchart of data prefetch control of another data prefetch control system provided by an embodiment of the present invention. Specific embodiments

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0049] Please refer to Figure 1 , Figure 1 The structural block diagram of a data prefetch control system provided by an embodiment of the present invention. The system may include: a fusion prefetch module 10, a prefetch control module 20, a prefetch cache control module 30, a prefetch cache module 40, and a multi-level cache module 50;

[0050] The fusion prefetch module 10 is configured to receive a memory access request sent by a memory access execution unit; make a prefetch decision based on the memory access address in the memory access request using the prefetch algorithms of each prefetch unit to obtain prefetch decision information; wherein, the fusion prefetch module 10 includes prefetch units corresponding to each level of cache in the multi-level cache module 50, and the prefetch units corresponding to at least two levels of cache in the multi-level cache module 50 are different;

[0051] The prefetch control module 20 is configured to sort the prefetch decision information by priority and store the sorted prefetch decision information in a prefetch information queue;

[0052] The prefetch cache control module 30 is configured to retrieve and determine the target decision information in the prefetch information queue; find and obtain the prefetch data corresponding to the target decision information from the memory; and store each prefetch data into its corresponding multi-level cache module 50 and prefetch cache module 40 according to the prefetch priority of the target decision information. Among them, the prefetch data corresponding to the target decision information is not stored in the multi-level cache module 50 or both the multi-level cache module 50 and the prefetch cache module 40, and the prefetch priority of the prefetch data stored in the multi-level cache module 50 is higher than that of the prefetch data stored in the prefetch cache module 40.

[0053] It can be understood that the memory access execution unit (Load–Store Unit, LSU) in this embodiment can be a unit in the processor configured to receive the memory access instruction information emitted by the processor instruction pipeline and execute the memory access operation. That is, the memory access execution unit can generate a corresponding memory access request according to the received memory access instruction information of the processor to obtain the corresponding memory data. For example, the memory access execution unit can use its internal Memory Management Unit (MMU) to convert the virtual address into a physical address (i.e., the memory access address in the memory access request) to access the data in the memory.

[0054] Among them, the multi-level cache module 50 in this embodiment can be caches (such as Cache) at different levels conventionally set in a processor (such as a central processing unit CPU). For example, the multi-level cache module 50 can include two levels of caches, such as Figure 2 the first-level cache (L1Cache) and the second-level cache (L2Cache) as shown; the multi-level cache module 50 can also have three or more levels of caches, and this embodiment does not impose any restrictions on this.

[0055] Correspondingly, the integrated prefetcher module 10 in this embodiment can be a module formed by fusing two or more prefetcher (Prefetcher) with corresponding prefetch algorithms. Each prefetcher in the integrated prefetcher module 10 shares the memory access address interface and part of the historical data storage (such as the data in the prefetch cache module 40). For the specific number of prefetcher in the integrated prefetcher module 10 in this embodiment, it can be set by the designer according to the practical scenario and user requirements. For example, each prefetcher in this embodiment can be set with a prefetch algorithm, and the integrated prefetcher module 10 includes the prefetcher corresponding to each level of cache in the multi-level cache module 50, and the prefetcher corresponding to at least two levels of cache in the multi-level cache module 50 is different; such as Figure 2 shown, when the multi-level cache module 50 includes two levels of caches, the integrated prefetcher module 10 can include 4 prefetcher (prefetcher 1-4), that is, 2 prefetcher corresponding to the first-level cache and 2 prefetcher corresponding to the second cache.

[0056] Similarly, for the prefetch algorithms and fusion architectures of the respective prefetchers in the fusion prefetcher module 10, they can be set by the designer himself. As long as the fusion prefetcher module 10 can use the prefetch algorithms of the respective prefetchers to make prefetch decisions, so that each prefetcher in the fusion prefetcher module 10 can be relatively independent and complementary to each other, this embodiment does not impose any restrictions on this.

[0057] It should be noted that the prefetch control module 20 (Pref_Ctrl) in this embodiment can perform priority sorting on the prefetch decision information output by the fusion prefetcher module 10 according to the configurations of the respective prefetch algorithms (such as prefetch parameters), and store the sorted prefetch decision information in the prefetch information queue, so that the prefetch decision information with a high prefetch priority can be processed preferentially. For example, the prefetch control module 20 is specifically configured to perform priority sorting on the prefetch decision information according to the decision thresholds and / or prefetcher tags respectively corresponding to the respective prefetch decision information, and store the sorted prefetch decision information in the prefetch information queue; for example, when the prefetch priorities of a prefetch algorithm set in different prefetchers are different, the prefetch control module 20 can determine the prefetch priorities corresponding to the respective prefetch decision information according to the prefetcher tags in the respective prefetch decision information and perform sorting; or, when the decision thresholds of all or some different prefetch algorithms are different, the prefetch control module 20 can determine the prefetch priorities corresponding to the respective prefetch decision information according to the decision thresholds corresponding to the respective prefetch decision information and perform sorting.

[0058] In some other embodiments, the prefetch control module 20 can also determine the respective prefetch priorities and decision thresholds of the respective prefetch decision information according to the prefetcher tags in the respective prefetch decision information; sort the prefetch decision information according to the respective prefetch priorities and decision thresholds of the respective prefetch decision information to obtain a decision information queue; store the prefetch decision information in the decision information queue in the prefetch information queue in the order from front to back; wherein, the prefetch priority of the previous prefetch decision information among two adjacent prefetch decision information in the decision information queue is higher than that of the latter prefetch decision information, or the decision threshold of the previous prefetch decision information is greater than that of the latter prefetch decision information. For example, two prefetch decision information with the same prefetch priority are sorted according to the decision threshold, and two prefetch decision information with the same prefetch priority and prefetch decision information are sorted according to the reception order.

[0059] For example, such as Figure 2As shown in the figure, in order to facilitate the priority sorting of the prefetch control module 20, the data prefetch control system provided in this embodiment may further include a prefetch configuration module for storing the prefetch parameters corresponding to each prefetch algorithm, so that the prefetch control module 20 can find and determine the prefetch parameters of the corresponding prefetch algorithm from the prefetch configuration module according to the prefetch flag in the prefetch decision information; wherein, the prefetch parameters include at least one of a decision threshold, a prefetch priority, a prefetch degree, and / or a prefetch data block. For example, the prefetch control module 20 can find and determine the prefetch priority and decision threshold of each prefetch decision information from the prefetch configuration module according to the prefetch flag in each prefetch decision information; sort the prefetch decision information according to the prefetch priority and decision threshold of each prefetch decision information to obtain a decision information queue; store the prefetch decision information in the decision information queue into the prefetch information queue in the order from front to back.

[0060] Correspondingly, the specific values of the prefetch parameters corresponding to each prefetch algorithm in the prefetch control module 20 can be set by designers or users according to requirements, so that the prefetch algorithms in each prefetch unit in the integrated prefetch module 10 can make prefetch decisions according to the corresponding prefetch parameters (such as decision threshold, prefetch degree, and prefetch data block). The prefetch control module 20 can also coordinate to complete the reading and writing process of the prefetch parameters by the prefetch configuration module; for example, the integrated prefetch module 10 can train and optimize the prefetch algorithms in each prefetch unit according to the hit feedback information of the prefetch data (such as the feedback information of processor access hit and miss) to obtain updated prefetch parameters; the prefetch control module 20 can use the updated prefetch parameters to update the storage of the prefetch parameters of the corresponding prefetch algorithm stored in the prefetch configuration module.

[0061] In some other embodiments, the prefetch control module 20 may be specifically configured to receive each prefetch decision information group sent by the integrated prefetch module 10; sort the prefetch decision information groups according to the decision threshold and / or prefetch flag corresponding to each prefetch decision information group, and store the sorted prefetch decision information groups into the prefetch information queue; wherein, the prefetch decision information group includes the prefetch decision information within the same prefetch area range (such as the same cache line); that is to say, in order to facilitate reading associated prefetch data from the memory, the prefetch control module 20 can also sort the prefetch decision information groups according to the decision threshold and / or prefetch flag of each prefetch decision information in each prefetch decision information group, such as sorting each prefetch decision information group according to the maximum prefetch priority within the group corresponding to each prefetch decision information group, and sorting the prefetch decision information within each prefetch decision information group according to the prefetch priority and decision threshold of each prefetch decision information within the group.

[0062] Among them, the prefetch information queue in this embodiment can adopt a memory with circular read and write (such as a random access memory RAM). The prefetch information queue is not only used to store prefetch decision information, but also can maintain a retrieval counter (ck_cnt), a prefetch counter (prf_cnt), and corresponding read and write address pointers, namely a retrieval address pointer (ck_addr_wr / rd) and a prefetch address pointer (prf_addr_wr / rd); the retrieval counter and the prefetch counter can count the number of decisions to be retrieved and to be prefetched, and the corresponding values are updated as the prefetch decision information is written, retrieved and read, and prefetched; when new prefetch decision information is written into the prefetch information queue, the corresponding retrieval flag (ck_flag) and prefetch flag (pre_flag) are also stored, such as the default values are both 0; and the corresponding decision group markers, such as a group marker counter (grp_cnt), the number of decisions (grp_num), and a valid marker (grp_valid), etc. The prefetch decision information within the same prefetch area range can be grouped into the same group (such as the above-mentioned prefetch decision information group).

[0063] That is to say, the prefetch information queue can include a retrieval counter, a prefetch counter, a retrieval address pointer, a prefetch address pointer, and the corresponding retrieval flag, prefetch flag, and decision group marker for each prefetch decision information; among them, the decision group marker includes at least one of a group marker counter, the number of decisions, and a valid flag; the retrieval counter is used to count the number of times to be retrieved, the prefetch counter is used to count the number of times to be prefetched, the retrieval address pointer is used to indicate the prefetch decision information currently retrieved in the prefetch information queue, the prefetch address pointer is used to indicate the prefetch decision information currently prefetched in the prefetch information queue, the retrieval flag is used to indicate whether each prefetch decision information in the prefetch information queue has been retrieved, the prefetch flag is used to indicate whether each prefetch decision information in the prefetch information queue needs to be prefetched, the group marker counter is used to indicate the prefetch decision information group where each prefetch decision information in the prefetch information queue is located, the number of decisions is used to indicate the number of prefetch decision information in the prefetch decision information group where each prefetch decision information in the prefetch information queue is located, and the valid flag is used to indicate whether each prefetch decision information in the prefetch information queue is valid; the prefetch decision information group includes prefetch decision information within the same prefetch area range.

[0064] Correspondingly, the prefetch cache control module 30 (PCache_Ctrl) in this embodiment can utilize the prefetch decision information read from the prefetch information queue, retrieve and determine the target decision information in the prefetch information queue, and find and obtain the prefetch data corresponding to the target decision information from the memory, so as to store each prefetch data into the corresponding multi-level cache module 50 and prefetch cache module 40 (PCache) according to the prefetch priority of the target decision information, and realize the hierarchical storage of the prefetch data.

[0065] For example, in the process of the above-mentioned retrieval to determine the target decision information in the prefetch information queue, when the retrieval counter is greater than 0, the prefetch cache control module 30 can read the current prefetch decision information in the prefetch information queue according to the retrieval address pointer; detect whether the prefetch data corresponding to the current prefetch decision information is stored in the multi-level cache module 50 (or the multi-level cache module 50 and the prefetch cache module 40); if the prefetch data corresponding to the current prefetch decision information is stored, set the retrieval flag corresponding to the current prefetch decision information to the retrieved flag (such as 1), and keep the prefetch flag corresponding to the current prefetch decision information as the default non-prefetch flag (such as 0); if the prefetch data corresponding to the current prefetch decision information is not stored, take the current prefetch decision as the target decision information, set the retrieval flag corresponding to the current prefetch decision information to the retrieved flag, and set the prefetch flag corresponding to the current prefetch decision information to the prefetch required flag (such as 1).

[0066] Correspondingly, in the process of the above-mentioned finding and obtaining the prefetch data corresponding to the target decision information from the memory, when the prefetch counter is greater than 0, the prefetch cache control module 30 can read the retrieval flag and the prefetch flag corresponding to the current prefetch decision information pointed to by the prefetch address pointer; when the retrieval flag corresponding to the current prefetch decision information pointed to by the prefetch address pointer is the retrieved flag and the prefetch flag is the prefetch required flag, find and obtain the prefetch data corresponding to the current prefetch decision information from the memory; when the retrieval flag corresponding to the current prefetch decision information pointed to by the prefetch address pointer is the retrieved flag and the prefetch flag is the non-prefetch flag, subtract 1 from the value of the prefetch counter and update the pointing position of the prefetch address pointer; when the retrieval flag corresponding to the current prefetch decision information pointed to by the prefetch address pointer is the default non-retrieved flag, directly or after waiting for a certain time, execute the step of reading the retrieval flag and the prefetch flag corresponding to the current prefetch decision information pointed to by the prefetch address pointer.

[0067] Furthermore, since the hit probability of other data is relatively low when one of the prefetch data corresponding to multiple prefetch decision information (i.e., the prefetch decision information group) within the same prefetch area range is hit; when the prefetch data corresponding to the current prefetch decision information is stored in the multi-level cache module 50, the prefetch cache control module 30 can not only set the retrieval flag corresponding to the current prefetch decision information to the retrieved flag, but also set the valid flag corresponding to other prefetch decision information (i.e., the same group decision information) in the prefetch decision information group where the current prefetch decision information is located to the invalid flag (such as 0), so as to avoid prefetching invalid prefetch decision information or enabling the corresponding prefetch data to be replaced in time during subsequent cache updates.

[0068] That is to say, when ck_cnt (retrieval counter) is greater than 0, it indicates prefetch decision information to be retrieved. The prefetch cache control module 30 can read the pointed prefetch decision information (i.e., the current prefetch decision information) according to the retrieval address pointer (ck_addr_wr / rd), and retrieve it in the multi-level cache module 50 (such as Figure 2 the first-level cache and the second-level cache in

[0069] ). If it misses, the pre_flag (prefetch flag) at the corresponding position in the prefetch information queue is updated to 1, indicating that prefetch needs to be executed for the current decision; otherwise, no operation is required and the pre_flag remains 0 by default. Whether it hits or not, the ck_flag (retrieval flag) is set to 1. Continue to retrieve until ck_cnt is 0.

[0070] Meanwhile, when pre_cnt (prefetch counter) is greater than 0, the prefetch cache control module 30 reads the pointed prefetch decision information according to the prefetch address pointer (pre_addr_wr / rd). If its ck_flag value is 0, it indicates that the current decision has not completed the retrieval verification, and continue to read when the current retrieval verification is completed; if its ck_flag value is 1 and its pre_flag is also 1, the prefetch cache control module 30 parses the prefetch decision information and looks up and obtains the corresponding prefetch data from the memory; if its ck_flag value is 1 but its pre_flag is 0, it indicates redundant prefetch decision and no prefetch is required, and the next prefetch queue information can be read continuously until pre_cnt is 0.

[0071] Correspondingly, the specific method of storing each prefetch data into its corresponding multi-level cache module 50 and prefetch cache module 40 according to the prefetch priority of the target decision information can be set by the designer according to the usage scenario and user requirements. For example, the prefetch control module 20 can directly store each prefetch data into its corresponding multi-level cache module 50 and prefetch cache module 40 according to the prefetch priority of each prefetch data or the prefetch priority and decision threshold. For example, directly store the prefetch data with a prefetch priority greater than the set priority into the corresponding first-level cache in the multi-level cache module 50; store the prefetch data with a prefetch priority not greater than the priority into the prefetch cache module 40.

[0072] In some other embodiments, since the hit probability of other data is relatively low if there is a hit for the prefetch data corresponding to multiple prefetch decision information (i.e., prefetch decision information group) within the same prefetch area range; therefore, the prefetch control module 20 can determine the target prefetch data from the prefetch data; store the target prefetch data into the multi-level cache module 50, and store the non-target prefetch data in the prefetch data into the prefetch cache module 40; wherein, the target prefetch data can be the prefetch data with the highest prefetch accuracy within each prefetch area range. For example, the target prefetch data can include the prefetch data corresponding to the prefetch decision information with the highest prefetch priority in each target prefetch decision information group, or the prefetch data corresponding to the prefetch decision information with the highest prefetch priority and a decision threshold greater than the multi-level cache threshold in each target prefetch decision information group; the target prefetch decision information group is the prefetch decision information group where the prefetch decision information corresponding to each prefetch data is located, and the prefetch decision information group includes the prefetch decision information within the same prefetch area range.

[0073] Furthermore, the prefetch cache control module 30 can also be used to configure the initial life cycle of each prefetch data in the prefetch cache module 40 according to the prefetch priority of each prefetch data, so as to facilitate the update and replacement of the data in the prefetch cache module 40. For example, the initial life cycle corresponding to the prefetch data with a high prefetch priority can be greater than or equal to that of the prefetch data with a low prefetch priority; for example, when the prefetch cache control module 30 stores the prefetch data in the prefetch cache module 40, it can set different life cycle length counts (such as clock count and memory access count, etc.) according to the level of the prefetch priority; when the count value is cleared, it means that the hit probability is relatively low and it can be replaced during subsequent cache updates.

[0074] It should be noted that in this embodiment, a prefetch cache module 40 independent of the multi-level cache module 50 is provided to store prefetch data with relatively low prefetch priority. The caches at all levels of the multi-level cache module 50 can be shared, and the cache size can be configured according to requirements, reducing resource and control overheads and sharing the impact of prefetch data on the multi-level cache module 50. The system provided in this embodiment can not only implement the data prefetch process corresponding to the above memory access requests, such as Figure 3 the prefetch process on the left side in

[0075] For example, the prefetch cache control module 30 can also be used to receive a memory access request sent by the memory access execution unit; retrieve whether there is access data corresponding to the memory access address in the memory access request stored in the prefetch cache module 40; if there is access data stored in the prefetch cache module 40, obtain the access data from the prefetch cache module 40 and return it to the memory access execution unit; if there is no access data stored in both the prefetch cache module 40 and the multi-level cache module 50, then according to the memory access address in the memory access request, find and obtain the access data corresponding to the memory access address from the memory and return it to the memory access execution unit, and the memory access address can also be stored in the multi-level cache module 50. Correspondingly, if there is no access data stored in the prefetch cache module 40 while there is access data stored in the multi-level cache module 50, the access data can be returned by the multi-level cache module 50.

[0076] Correspondingly, the system provided in this embodiment may further include a memory access execution unit; the memory access execution unit can be used to generate a memory access request according to the received memory access instruction information of the processor; and send the memory access request to the integrated prefetch module 10, the prefetch cache control module 30, and the multi-level cache module 50. The multi-level cache module 50 in this embodiment can also be used to detect whether there is access data corresponding to the memory access address in the memory access request stored in each level of cache according to the received memory access request; if so, return the stored access data to the memory access execution unit and send corresponding cache hit information to the prefetch cache control module 30; if not, send corresponding cache miss information to the prefetch cache control module 30; thereby implementing the normal memory access process of the multi-level cache module 50 corresponding to the memory access request.

[0077] For example, as Figure 3 shown, the memory access execution unit can generate a memory access request including a memory access address according to the information of the memory access instruction of the processor and send it to the integrated prefetch module 10, the prefetch cache control module 30, and the multi-level cache module 50 for processing in these three paths, implementing the data prefetch process and the memory access processes of the multi-level cache module 50 and the prefetch cache module 40. As Figure 2As shown, the memory access request is sent to the first-level cache of the multi-level cache module 50 for normal data memory access operations. When the memory access is hit, the corresponding data (i.e., the accessed data) is directly returned. When the access misses, the memory access continues to the second-level cache of the next level. When the second-level cache is hit, the data is directly returned. When the access misses, the memory access can be uniformly processed by the prefetch cache control module 30 for unified priority regulation, which is faster. The hit and miss indication information of the multi-level cache module 50 will be transmitted to the prefetch cache control module 30 to facilitate its cache data management of the prefetch cache module 40 and feedback to the fusion prefetch module 10 for prefetch algorithm training and optimization.

[0078] Correspondingly, the memory access request is sent to the prefetch cache control module 30 for retrieving the prefetch cache module 40. The retrieval process can be executed synchronously and in parallel with the memory access process of the multi-level cache module 50 mentioned above. When the prefetch cache module 40 is hit, the corresponding data can be directly and quickly returned. At the same time, the hit data is backfilled and updated to the cache of the multi-level cache module 50 (different according to inclusive or exclusive mode), and the data corresponding to the same-group decision information in the prefetch cache module 40 and the multi-level cache module 50 is retrieved according to the group tag counter (grp_cnt) and the number of decisions (grp_num), and the valid flag (grp_valid) is set to 0 (i.e., invalid flag). If the prefetch cache module 40 misses, the memory access information is generated according to the memory access address, the bus read data priority is set to the highest, and the hit or miss indication information of the multi-level cache module 50 is waited for. If the multi-level cache module 50 is hit, the memory access information is cancelled, and the data corresponding to the same-group decision information in the prefetch cache module 40 is retrieved according to the group tag counter and the number of decisions, and the valid flag (grp_valid) is set to 0. If the multi-level cache module 50 misses, the memory access request is quickly initiated using the memory access information; the accessed data found in the memory is directly returned to the application and backfilled to the multi-level cache module 50.

[0079] That is to say, the prefetch cache control module 30 can also be used to set the valid flag corresponding to the same-group decision information in the prefetch decision information group corresponding to the accessed data in the prefetch information queue to an invalid flag if the accessed data is not stored in the prefetch cache module 40 and is stored in the multi-level cache module 50; where the same-group decision information is the prefetch decision information other than the prefetch decision information corresponding to the accessed data in the prefetch decision information group corresponding to the accessed data. If the accessed data is stored in the prefetch cache module 40, the accessed data is obtained from the prefetch cache module 40 and returned to the memory access execution unit, and the accessed data is stored in the multi-level cache module 50, and the valid flag corresponding to the same-group decision information in the prefetch decision information group corresponding to the accessed data in the prefetch information queue is set to an invalid flag, which is convenient for the data to be replaced during subsequent cache updates.

[0080] Among them, the system provided in this embodiment can be a system set based on the RISC-V architecture or other instruction set architectures. Among them, RISC-V is a brand-new open-source instruction set architecture (ISA) based on the principle of reduced instruction set (RISC), and it is the fifth-generation instruction set architecture starting from RISC-I.

[0081] In this embodiment, the embodiment of the present invention uses the setting of the fusion prefetcher module 10 to fuse the prefetch algorithms of different cache levels, which facilitates the scheduling of complementary data between algorithms, can reuse a part of the storage resources, can quickly interact data, reduce resource consumption, and improve the prefetch accuracy rate; and through the settings of the prefetch cache module 40 and the multi-level cache module 50, hierarchical storage of prefetch data can be realized, and the prefetch cache module 40 is used to store prefetch data with relatively low prefetch priority, which can improve the data prefetch coverage rate and achieve a better data prefetch effect.

[0082] Corresponding to the above system embodiment, the embodiment of the present invention also provides a processor, and a processor described below can be correspondingly referred to with a data prefetch control system described above.

[0083] The embodiment of the present invention provides a processor, including the data prefetch control system provided in the above embodiment.

[0084] Among them, the processor provided in this embodiment can specifically be a central processing unit CPU, or can specifically be other types of processors, such as a graphics processing unit GPU.

[0085] The various embodiments in the specification are described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the processor disclosed in the embodiment, since it corresponds to the system disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the system part.

[0086] The above has introduced in detail a data prefetch control system and a processor provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the system of the present invention and its core idea. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A data pre-fetching control system, characterized in that: include: Fusion prefetcher module, prefetch control module, prefetch cache control module, prefetch cache module and multi-level cache module; The fusion prefetcher module is used to receive a memory access request sent by a memory access execution unit; according to the memory access address in the memory access request, a prefetch decision is made using the prefetch algorithm of each prefetcher to obtain prefetch decision information; wherein the fusion prefetcher module includes prefetchers corresponding to each level of cache in the multi-level cache module, and the prefetchers corresponding to at least two levels of cache in the multi-level cache module are different; The prefetch control module is specifically used to prioritize the prefetch decision information according to the prefetcher mark and / or the decision threshold of the prefetch algorithm corresponding to each of the prefetch decision information, and store the sorted prefetch decision information into the prefetch information queue; The prefetch cache control module is used to retrieve and determine the target decision information in the prefetch information queue; search and obtain the prefetch data corresponding to the target decision information from the memory; store each prefetch data in the corresponding multi-level cache module and prefetch cache module according to the prefetch priority of the target decision information; wherein the prefetch data corresponding to the target decision information is not stored in the multi-level cache module or the multi-level cache module and the prefetch cache module, and the prefetch priority corresponding to the prefetch data stored in the multi-level cache module is higher than the prefetch priority corresponding to the prefetch data stored in the prefetch cache module.

2. The data pre-fetching control system according to claim 1, characterized in that: Also includes: The prefetch configuration module is used to store the prefetch parameters corresponding to each of the prefetch algorithms; wherein the prefetch parameters include at least one of a decision threshold, a prefetch priority, a prefetch degree and / or a prefetch data block.

3. The data pre-fetching control system according to claim 2, characterized in that: The method of prioritizing the prefetch decision information according to the prefetcher mark and / or the decision threshold of the prefetch algorithm corresponding to each of the prefetch decision information, and storing the sorted prefetch decision information in the prefetch information queue, comprises: According to the prefetcher mark in each of the prefetch decision information, searching and determining the prefetch priority and decision threshold of each of the prefetch decision information from the prefetch configuration module; The prefetch decision information is sorted according to the prefetch priority and decision threshold of each of the prefetch decision information to obtain a decision information queue; wherein the prefetch priority of the first prefetch decision information of two adjacent prefetch decision information in the decision information queue is higher than the prefetch priority of the second prefetch decision information, or the decision threshold of the first prefetch decision information is higher than the decision threshold of the second prefetch decision information; The pre-fetch decision information in the decision information queue is stored in the pre-fetch information queue in a front-to-back order.

4. The data pre-fetching control system according to claim 1, characterized in that: The prefetch control module is specifically used to receive each prefetch decision information group sent by the fusion prefetcher module; prioritize the prefetch decision information groups according to the decision threshold and / or prefetcher mark corresponding to each prefetch decision information group, and store the sorted prefetch decision information groups into the prefetch information queue; wherein the prefetch decision information groups include prefetch decision information within the same prefetch area range.

5. The data pre-fetching control system according to claim 1, characterized in that: The prefetch information queue includes a retrieval counter, a prefetch counter, a retrieval address pointer, a prefetch address pointer, and a retrieval flag, a prefetch flag, and a decision group flag corresponding to each of the prefetch decision information; wherein the decision group flag includes at least one of a group flag counter, a decision number, and a valid flag; the retrieval counter is used to count the number of times to be retrieved, the prefetch counter is used to count the number of times to be prefetched, the retrieval address pointer is used to indicate the prefetch decision information currently retrieved in the prefetch information queue, the prefetch address pointer is used to indicate the prefetch decision information currently prefetched in the prefetch information queue, and the retrieval flag is used to indicate Whether each prefetch decision information in the prefetch information queue has been retrieved, the prefetch flag is used to indicate whether each prefetch decision information in the prefetch information queue needs to be prefetched, the group tag counter is used to indicate the prefetch decision information group to which each prefetch decision information in the prefetch information queue belongs, the number of decisions is used to indicate the number of prefetch decision information in the prefetch decision information group to which each prefetch decision information in the prefetch information queue belongs, and the valid flag is used to indicate whether each prefetch decision information in the prefetch information queue is valid; the prefetch decision information group includes prefetch decision information in the same prefetch area range.

6. The data pre-fetching control system according to claim 5, characterized in that: The retrieving and determining the target decision information in the pre-fetch information queue includes: If the retrieval counter is greater than 0, the current prefetch decision information in the prefetch information queue is read according to the retrieval address pointer; Detecting whether prefetch data corresponding to current prefetch decision information is stored in the multi-level cache module; If the pre-fetch data corresponding to the current pre-fetch decision information is stored, the search flag corresponding to the current pre-fetch decision information is set to the searched flag, and the pre-fetch flag corresponding to the current pre-fetch decision information is kept as the default no-pre-fetch flag; If the prefetch data corresponding to the current prefetch decision information is not stored, the current prefetch decision is used as the target decision information, the search flag corresponding to the current prefetch decision information is set to the searched flag, and the prefetch flag corresponding to the current prefetch decision information is set to the prefetch required flag.

7. The data pre-fetching control system according to claim 6, characterized in that: The step of searching for pre-fetched data corresponding to the target decision information from the memory includes: If the prefetch counter is greater than 0, then reading the search flag and prefetch flag corresponding to the current prefetch decision information pointed to by the prefetch address pointer; When the search flag corresponding to the current prefetch decision information pointed to by the prefetch address pointer is the searched flag and the prefetch flag is the prefetch-required flag, searching and acquiring the prefetch data corresponding to the current prefetch decision information from the memory; When the search flag corresponding to the current prefetch decision information pointed to by the prefetch address pointer is the searched flag and the prefetch flag is the no-prefetch flag, the value of the prefetch counter is reduced by 1, and the pointing position of the prefetch address pointer is updated; When the search flag corresponding to the current prefetch decision information pointed to by the prefetch address pointer is a default unsearched flag, the step of reading the search flag and prefetch flag corresponding to the current prefetch decision information pointed to by the prefetch address pointer is performed.

8. The data pre-fetching control system according to claim 1, characterized in that: The step of searching for pre-fetched data corresponding to the target decision information from the memory includes: Determine the bus read data priority of each target decision information according to the priority information corresponding to each target decision information; wherein the priority information includes at least one of the prefetch priority, the decision threshold and the prefetch degree execution status; According to the order of the bus read data priorities from high to low, the pre-fetched data corresponding to each of the target decision information is searched and acquired from the memory using the target data reading method corresponding to each of the bus read data priorities.

9. The data pre-fetching control system according to claim 1, characterized in that: According to the prefetching priority of the target decision information, storing each of the prefetched data into the corresponding multi-level cache module and prefetch cache module includes: Determine target prefetch data from the prefetch data; wherein the target prefetch data includes prefetch data corresponding to prefetch decision information with the highest prefetch priority and a decision threshold greater than a multi-level cache threshold in each target prefetch decision information group, the target prefetch decision information group is a prefetch decision information group where the prefetch decision information corresponding to each of the prefetch data is located, and the prefetch decision information group includes prefetch decision information within the same prefetch area range; The target pre-fetch data is stored in the multi-level cache module, and non-target pre-fetch data in the pre-fetch data is stored in the pre-fetch cache module.

10. The data pre-fetching control system according to claim 1, characterized in that: The pre-fetch cache control module is further used to configure the initial life cycle of each pre-fetched data according to the pre-fetch priority corresponding to each pre-fetched data in the pre-fetch cache module.

11. The data pre-fetching control system according to any one of claims 1 to 10, characterized in that: The pre-fetch cache control module is also used to receive the memory access request sent by the memory access execution unit; to retrieve whether the pre-fetch cache module stores access data corresponding to the memory access address in the memory access request; if the pre-fetch cache module stores the access data, the access data is obtained from the pre-fetch cache module and returned to the memory access execution unit; if the access data is not stored in the pre-fetch cache module and the multi-level cache module, the access data corresponding to the memory access address is obtained from the memory according to the memory access address in the memory access request and returned to the memory access execution unit.

12. The data pre-fetching control system according to claim 11, characterized in that: The pre-fetch cache control module is also used to set the valid flag corresponding to the same group decision information in the pre-fetch decision information group corresponding to the access data in the pre-fetch information queue to an invalid flag if the access data is not stored in the pre-fetch cache module and the access data is stored in the multi-level cache module; wherein the same group decision information is pre-fetch decision information other than the pre-fetch decision information corresponding to the access data in the pre-fetch decision information group corresponding to the access data; After obtaining the access data from the pre-fetch cache module and returning it to the memory access execution unit, it includes: storing the access data in the multi-level cache module, and setting the valid flag corresponding to the same group of decision information in the pre-fetch decision information group corresponding to the access data in the pre-fetch information queue to the invalid flag.

13. The data pre-fetching control system according to claim 11, characterized in that: Also includes: The memory access execution unit is used to generate the memory access request according to the memory access instruction information received from the processor; Sending the memory access request to the fusion prefetcher module, the prefetch cache control module and the multi-level cache module; The multi-level cache module is also used to detect whether access data corresponding to the memory access address in the memory access request is stored in each level of cache based on the received memory access request; if so, the stored access data is returned to the memory access execution unit, and the corresponding cache hit information is sent to the pre-fetch cache control module; if not, the corresponding cache miss information is sent to the pre-fetch cache control module.

14. A processor, characterized in that: It comprises the data pre-fetch control system as claimed in any one of claims 1 to 13.

Images