Modulation signal classification method based on fixed bit width LSTM neural network
By performing fixed-pointing processing of the weight, bias matrix and input data of the LSTM neural network, an LSTM neural network based on a fixed bit width is solved, and the problem of excessive resource consumption in the existing technology is achieved, efficient hardware deployment and approximate recognition accuracy are achieved.
Patent Information
- Application Number
- CN202411815930.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-11
- Publication Date
- 2025-04-01
AI Technical Summary
Existing neural networks use high-precision floating point numbers in modulated signal recognition, resulting in excessive resource consumption during hardware deployment and difficult to achieve efficient digital signal processing.
Using an LSTM neural network based on fixed bit width, the weight, bias matrix and input data are fixedly processed to achieve smaller floating point accuracy and reduce resource consumption.
Resource consumption is greatly reduced during hardware deployment, while maintaining recognition accuracy approximate to high-precision floating-point numbers.
Smart Images
Figure CN119740122A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of low resource consumption neural network modulation classification, and more specifically, relates to a modulation signal classification method based on a fixed bit width LSTM neural network. Background Art
[0002] With the rapid development of emerging technologies such as the Internet of Things, cloud computing, augmented reality (AR), virtual reality (VR) and digital twins, the transmission capacity and coverage of communication networks are expected to grow by leaps and bounds. In order to meet the multi-dimensional needs of "air, space, land and sea" of future communication networks, overcome the attenuation of different transmission channels and meet various transmission performance requirements, it is necessary to adopt multiple signal modulation formats in the network. In a highly complex communication network environment, how the receiver can accurately demodulate the signal and perform efficient digital signal processing in the absence of prior knowledge has become a key issue. The application of modulation format recognition technology can help the receiver identify the modulation method of the signal, thereby improving the accuracy of demodulation and the overall performance of the system.
[0003] In 2017, Wang et al. from Beijing University of Posts and Telecommunications proposed a modulation format recognition method based on eye diagrams. By using an oscilloscope and a simulation system, four modulation format signals were generated with an SNR range of 10 to 25 dB. In order to reduce the data size, the article downsampled the received eye diagram signal to generate a grayscale image. The network uses two convolutional layers and two pooling layers, and then flattens the output into a one-dimensional signal, which is input into the fully connected layer to finally obtain the recognition result. To compare the effect of CNN, the authors also compared CNN with four traditional machine learning algorithms (decision tree, KNN, artificial neural network, SVM). The results show that CNN performs better in extracting high-dimensional features, and the recognition effect is significantly better than traditional algorithms. In order to further explore the application of CNN in modulation recognition, the researchers tried other two-dimensional image data sets, such as fuzzy function images, spectral correlation function images, and discrete Fourier images.
[0004] In 2019, Zeng et al. from the Southern University of Science and Technology pointed out that the main difference between radio signals with different modulation formats is the change of frequency over time. Based on this, the researchers used short-time discrete Fourier transform to convert the one-dimensional signal into a spectrogram as CNN input for training. Similar to the aforementioned eye diagram method, the spectrogram is generated by the simulation system and then downsampled to reduce the size of the data set.
[0005] In 2020, Du et al. from Beijing University of Posts and Telecommunications proposed using asynchronous amplitude histograms as feature inputs to CNN for training, further optimizing recognition performance. In 2021, Lu et al. from the University of Science and Technology Beijing tried to combine signal amplitude histograms with CNN in order to reduce computational complexity while improving recognition performance.
[0006] In 2018, Rajendran et al. from the University of Leuven in Belgium proposed a modulation recognition method based on LSTM, which can achieve classification by learning long-term time series without explicit feature extraction. This method uses a two-layer LSTM network and takes amplitude-phase signals or FFT signals as input. After the LSTM layer, the information is classified through the fully connected layer and the SoftMax layer. Experimental results show that when using time domain amplitude and phase information as input, the recognition accuracy can reach 90%, while the recognition effect is poor when using time domain in-phase signal and orthogonal signal samples.
[0007] However, the training and recognition of the above neural networks all utilize high-precision floating-point numbers, which consumes a large amount of logical resources during hardware deployment. Therefore, it is necessary to integrate the traditional neural networks and perform fixed-point processing on all parameter matrices and all calculation processes in the middle. Summary of the invention
[0008] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a modulation signal classification method based on a fixed-bit-width LSTM neural network, which uses a smaller floating-point precision to realize the recognition of the modulation signal type, so that the neural network can greatly reduce the consumption of resources when it is implemented on the hardware side and achieve a recognition accuracy similar to that under high-precision floating-point conditions.
[0009] To achieve the above-mentioned object of the invention, the present invention provides a modulation signal classification method based on a fixed-bit-width LSTM neural network, characterized in that it comprises the following steps:
[0010] (1) Build and train the LSTM neural network;
[0011] (2) The weight and bias matrix of the LSTM neural network are processed in fixed-point and floating-point form in turn to obtain a fixed-bit-width LSTM neural network;
[0012] (3) Collect the modulation signal to be tested and perform fixed-point and floating-point processing;
[0013] (4) Modulation classification of the modulated signal to be tested is realized based on the LSTM neural network with fixed bit width;
[0014] The object of the invention of the present invention is achieved in this way:
[0015] The present invention is based on a modulation signal classification method of a fixed-bit-width LSTM neural network. First, a traditional LSTM neural network is constructed and trained. Then, the weight and bias matrix of the LSTM neural network are successively processed into fixed-point and floating-point forms to obtain a fixed-bit-width LSTM neural network. Then, the modulation signal to be tested is collected in real time and processed into fixed-point and floating-point forms, and then input into the fixed-bit-width LSTM neural network. In this way, a smaller floating-point number precision is used to realize recognition of the type of modulation signal, which can greatly reduce resource consumption and achieve recognition accuracy similar to that under high-precision floating-point conditions.
[0016] The modulation signal classification method based on the fixed bit width LSTM neural network of the present invention also has the following beneficial effects:
[0017] (1) By performing fixed-point processing on the weights, biases, input data, and all intermediate calculation processes of the neural network, the logical resource consumption of the network during hardware deployment is greatly reduced, which makes a great contribution to reducing costs;
[0018] (2) The activation function is fitted in three-order segments and fixed-point processed step by step, which can approximate the traditional activation function without using dividers and exponential operations, thus improving the flexibility of subsequent hardware deployment. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 It is a flow chart of the modulation signal classification method based on the fixed bit width LSTM neural network of the present invention;
[0020] Figure 2 This is the LSTM neural network structure diagram;
[0021] Figure 3 is a diagram showing recognition results of modulation signals of five modulation formats in the embodiment; DETAILED DESCRIPTION
[0022] The specific implementation of the present invention is described below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.
[0023] Example
[0024] In this embodiment, if Figure 1 As shown, the present invention provides a modulation signal classification method based on a fixed-bit-width LSTM neural network, comprising the following steps:
[0025] (1) Build and train the LSTM neural network;
[0026] like Figure 2 As shown in the figure, the LSTM neural network includes 2 LSTM layers, 1 fully connected layer and 1 softmax layer; each LSTM layer includes an input layer, a hidden layer and an output layer, and the input layer and the hidden layer are composed of an input gate I, a forget gate F, a unit state gate G and an output gate O. The output layer contains a memory cell matrix C0, a sigmoid activation function and a tanh activation function, and the element values in the initialized memory cell matrix C0 are all 0;
[0027] In this embodiment, modulation signals of five modulation signal formats, BPSK, QPSK, 8PSK, 16QAM, and 64QAM, are collected to train a fixed-bit-width LSTM neural network. The specific training process is the same as the traditional neural network training method, which will not be repeated here.
[0028] After the training is completed, the weight and bias matrix of the LSTM neural network are recorded, including: the weight matrix W of the input gate I in the input layer i And the bias matrix B i , the weight matrix W of the forget gate F f And the bias matrix B f , the weight matrix W of the unit state gate G g And the bias matrix B g , the weight matrix W of the output gate O o And the bias matrix B o ; The weight matrix W of the input gate I in the hidden layer ih And the bias matrix B ih , the weight matrix W of the forget gate F fh And the bias matrix B fh , the weight matrix W of the unit state gate G gh And the bias matrix B gh , the weight matrix W of the output gate O oh And the bias matrix B oh ; The weight matrix W of the fully connected layer fc And the bias matrix B fc ;
[0029] (2) The weight and bias matrix of the LSTM neural network are processed in fixed-point and floating-point form in turn to obtain a fixed-bit-width LSTM neural network;
[0030] Each weight and each element in the bias matrix of the LSTM neural network is first processed in fixed point format and then in floating point format. The fixed point processing process is as follows: retain 1 integer bit, 1 sign bit and 16 decimal places, perform truncation based on rounding for decimal places exceeding 16, and finally combine the sign bit, integer bit and decimal place into a binary string format;
[0031] The floating point conversion process is as follows: the integer and decimal parts are split according to the number of integer digits and decimal digits, and then the integer part is converted to decimal. The decimal part is converted to decimal by accumulating each binary bit, and finally a floating point representation is obtained;
[0032] The weight and bias matrices of the original records are updated by the weight and bias matrices processed by fixed-point and floating-point conversion to obtain a fixed-bit-width LSTM neural network.
[0033] (3) Collect the modulation signal to be tested and perform fixed-point and floating-point processing;
[0034] The acquisition system acquires the modulated signal to be tested in real time and obtains the I / Q baseband signals, which are recorded as X = {x1, x2, ..., x j ,…,x N}, x j represents the jth sampling value, N represents the number of sampling points. In this embodiment, the number of sampling points N is 128;
[0035] Traverse each sample value in X, for each sample value x j First, perform fixed-point processing, and then perform floating-point processing. The fixed-point processing process is as follows: retain 3 integer bits, 1 sign bit, and 14 decimal bits, perform truncation based on rounding for decimal bits exceeding 14, and finally combine the sign bit, integer bit, and decimal bit into a binary string format;
[0036] The floating point conversion process is as follows: split the integer and decimal parts according to the number of integer digits and decimal digits, convert the integer part into decimal, and convert the decimal part into decimal by accumulating each binary bit to finally get the floating point representation;
[0037] Finally, the sequence of X after fixed-point conversion and floating-point conversion is represented as:
[0038] (4) Modulation classification of the modulated signal to be tested is realized based on the LSTM neural network with fixed bit width;
[0039] (4.1), the input sequence X ifixed Input to the LSTM neural network based on fixed bit width,
[0040] (4.2), initialize j = 1, and set the sample value Input to the first LSTM layer, and get the output of the four gates in the input layer after the jth iteration through the input layer: the output matrix I of the input gate j , the output matrix F of the forget gate j , the output matrix G of the unit state gate j The output matrix O of the output gatej ;
[0041] (4.3) The output of the four gates fed back to the input layer after the j-1th iteration of the hidden layer is: output matrix I h,j-1 , the output matrix F of the forget gate h,j-1 , the output matrix G of the unit state gate h,j-1 The output matrix O of the output gate h,j-1 ;
[0042] The four-gate output after the j-th iteration of the input layer is added to the four-gate output fed back after the j-1-th iteration of the corresponding hidden layer to obtain the final output matrix of the four gates after the j-th iteration of the input layer, and then the elements in the four output matrices are processed in fixed-point and floating-point in turn. The fixed-point processing process is: retain 6 integer bits, 1 sign bit and 14 decimal bits, and truncate the decimal bits exceeding 14 bits based on rounding. Finally, the sign bit, integer bit and decimal bit are combined into a binary string format;
[0043] Finally, the four output matrices in the input layer are fixed-point and floating-point processed as follows: j,fixed 、F j,fixed , G j,fixed and O j,fixed ;
[0044] (4.4), the four output matrices I of the input layer j,fixed 、F j,fixed , G j,fixed and O j,fixed Input to the output layer, and then activate I through the sigmoid activation function j,fixed 、F j,fixed , O j,fixed Perform activation processing and use the tanh activation function to activate G j,fixed Perform activation processing;
[0045] In this embodiment, both the sigmoid activation function and the tanh function activation use a third-order piecewise fitting method for function activation, and the specific activation process is:
[0046] Let the input data be x;
[0047] First, the input data x is roughly segmented into: [0,0.5), [0.5,1), [1,1.5), [1.5,3), [3,5), [5,8), [8,+∞);
[0048] Next, define the activation function fitting polynomial of the input data x: Ax 3 +Bx 2 +Cx+D, where A, B, C, and D represent the multiplication parameters of the activation function at different segments;
[0049] Secondly, the input data x is processed for absolute value to obtain the data |x|; then |x| is fixed-point converted to 4 integer digits and 14 decimal digits; x 2 Fixed point conversion to 7 integer bits and 14 decimal places; x 3 Convert Cx to 6 integer bits and 14 decimal places; convert Bx to 10 integer bits and 14 decimal places. 2 Convert Ax to 9 integer digits and 14 decimal digits. 3 Fixed point conversion to 12 integer bits and 14 decimal places;
[0050] After the fixed-point processing is completed, the integer bits and decimal bits are combined into a binary string format and then processed into floating-point format. For the sigmoid activation function, the floating-point processing result is used as the final activation output, while for the tanh function, it needs to be processed according to the positive or negative of the input data x. If x is negative, the floating-point processing result is negative as the final activation output, otherwise, the floating-point processing result is directly used as the final activation output;
[0051] Finally, the activated matrix is recorded as I j,fixed_sig 、F j,fixed_sig , G j,fixed_tanh and O j,fixed_sig ;
[0052] (4.5) Update the memory cell matrix C and perform fixed-point and floating-point processing;
[0053] C j =F j,fixed_sig *C j-1,fixed +I j,fixed_sig *G j,fixed_tanh
[0054] Among them, C fixed It represents the matrix representation of the memory cell matrix C after fixed-point and floating-point processing in the previous iteration;
[0055] For the updated memory cell matrix C j Perform fixed-point and floating-point processing to obtain the memory cell matrix C j,fixed , and then the memory cell matrix C is activated by the tanh activation function j,fixed Perform activation processing to obtain the activated matrix C j,fixed_tanh ;
[0056] The fixed-point processing process is as follows: retain 7 integer bits, 1 sign bit and 14 decimal bits, perform truncation based on rounding for decimal bits exceeding 14, and finally combine the sign bit, integer bit and decimal bit into a binary string format;
[0057] (4.6) Calculate the output matrix H of the output layer after the jth iteration j And perform fixed-point and floating-point processing;
[0058] H j =O j,fixed_sig *C j,fixed_tanh
[0059] For the output matrix H j Perform fixed-point and floating-point processing to obtain the output matrix H j,fixed , where the fixed-point processing process is: retain 1 integer bit, 1 sign bit and 25 decimal places, perform truncation based on rounding for decimal places exceeding 25, and finally combine the sign bit, integer bit and decimal place into a binary string format;
[0060] (4.7), the output matrix H of the output layer j,fixed Input to the hidden layer, and get the output matrix I of the input gate through the four gates of the hidden layer h,j , the output matrix F of the forget gate h,j , the output matrix G of the unit state gate h,j The output matrix O of the output gate h,j ; Then the four gate output matrices of the hidden layer are fed back to the input layer;
[0061] At the same time, the output matrix H of the output layer j,fixed As the input of the second LSTM layer, Then, follow steps (4.2) to (4.7) to complete the calculation of the second LSTM layer and obtain the final output matrix H of the second LSTM layer. j,fixed ;
[0062] (4.8) Traverse the sampled data Finally, the final output matrix H of the second LSTM layer after the Nth iteration is obtained j,fixed ;
[0063] (4.9), the output matrix H j,fixed As the input of the fully connected layer, a set of probability vectors of length M is obtained through the fully connected layer Indicates the probability value of the modulation signal to be tested belonging to the mth modulation type;
[0064] H fc =h L ·W fc +B fc
[0065] (4.10) The probability vector output by the fully connected layer The input is sent to the softmax layer, and the modulation type corresponding to the maximum probability value is output as the final classification result.
[0066] In this embodiment, Figure 3 is a diagram showing the recognition results of modulation signals of five modulation formats in the embodiment, wherein: Figure 3 The five figures a to e correspond to the recognition results of five modulation signals, namely BPSK, QPSK, 8PSK, 16QAM and 64QAM, respectively. Therefore, it can be seen that the present invention can accurately recognize the five modulation signals.
[0067] Although the above describes the illustrative specific embodiments of the present invention to facilitate those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations using the concept of the present invention are protected.
Claims
1. A modulation signal classification method based on a fixed-bit-width LSTM neural network, characterized in that: The following steps are involved: (1) Build and train the LSTM neural network; The LSTM neural network includes 2 LSTM layers, 1 fully connected layer and 1 softmax layer; each LSTM layer includes an input layer, a hidden layer and an output layer, and the input layer and the hidden layer are composed of an input gate I, a forget gate F, a unit state gate G and an output gate O. The output layer contains a memory cell matrix C0, a sigmoid activation function and a tanh activation function. The element values in the initialized memory cell matrix C0 are all 0; Use M different formats of modulated signals to train a fixed-bit-width LSTM neural network. After the training is completed, record the weight and bias matrix of the LSTM neural network, including: the weight matrix W of the input gate I in the input layer i And the bias matrix B i , the weight matrix W of the forget gate F f And the bias matrix B f , the weight matrix W of the unit state gate G g And the bias matrix B g , the weight matrix W of the output gate O o And the bias matrix B o ; The weight matrix W of the input gate I in the hidden layer ih And the bias matrix B ih , the weight matrix W of the forget gate F fh And the bias matrix B fh , the weight matrix W of the unit state gate G gh And the bias matrix B gh , the weight matrix W of the output gate O oh And the bias matrix B oh ; The weight matrix W of the fully connected layer fc And the bias matrix B fc ; (2) The weight and bias matrix of the LSTM neural network are processed in fixed-point and floating-point form in turn to obtain a fixed-bit-width LSTM neural network; Each weight and each element in the bias matrix of the LSTM neural network is first processed in fixed point format and then in floating point format. The fixed point processing process is as follows: retain 1 integer bit, 1 sign bit and 16 decimal places, perform truncation based on rounding for decimal places exceeding 16, and finally combine the sign bit, integer bit and decimal place into a binary string format; The floating point conversion process is as follows: the integer and decimal parts are split according to the number of integer digits and decimal digits, and then the integer part is converted to decimal. The decimal part is converted to decimal by accumulating each binary bit, and finally a floating point representation is obtained; The weight and bias matrices of the original records are updated by the weight and bias matrices processed by fixed-point and floating-point conversion to obtain a fixed-bit-width LSTM neural network. (3) Collect the modulation signal to be tested and perform fixed-point and floating-point processing; The acquisition system acquires the modulated signal to be tested in real time and obtains the I / Q baseband signals, which are recorded as X = {x1, x2, ..., x j ,…,x N }, x j represents the jth sampling value, and N represents the number of sampling points; Traverse each sample value in X, for each sample value x j First, perform fixed-point processing, and then perform floating-point processing. The fixed-point processing process is as follows: retain 3 integer bits, 1 sign bit, and 14 decimal bits, perform truncation based on rounding for decimal bits exceeding 14, and finally combine the sign bit, integer bit, and decimal bit into a binary string format; The floating point conversion process is as follows: split the integer and decimal parts according to the number of integer digits and decimal digits, convert the integer part into decimal, and convert the decimal part into decimal by accumulating each binary bit to finally get the floating point representation; Finally, the sequence of X after fixed-point conversion and floating-point conversion is represented as: (4) Modulation classification of the modulated signal to be tested is realized based on the LSTM neural network with fixed bit width; (4.1), the input sequence X ifixed Input to the LSTM neural network based on fixed bit width, (4.2), initialize j = 1, and set the sample value Input to the first LSTM layer, and get the output of the four gates in the input layer after the jth iteration through the input layer: the output matrix I of the input gate j , the output matrix F of the forget gate j , the output matrix G of the unit state gate j The output matrix O of the output gate j ; (4.3) The output of the four gates fed back to the input layer after the j-1th iteration of the hidden layer is: output matrix I h,j-1 , the output matrix F of the forget gate h,j-1 , the output matrix G of the unit state gate h,j-1 The output matrix O of the output gate h,j-1 ; The four-gate output after the j-th iteration of the input layer is added to the four-gate output fed back after the j-1-th iteration of the corresponding hidden layer to obtain the final output matrix of the four gates after the j-th iteration of the input layer, and then the elements in the four output matrices are processed in fixed-point and floating-point in turn. The fixed-point processing process is: retain 6 integer bits, 1 sign bit and 14 decimal bits, and truncate the decimal bits exceeding 14 bits based on rounding. Finally, the sign bit, integer bit and decimal bit are combined into a binary string format; Finally, the four output matrices in the input layer are fixed-point and floating-point processed as follows: j,fixed 、F j,fixed , G j,fixed and O j,fixed ; (4.4), the four output matrices I of the input layer j,fixed 、F j,fixed , G j,fixed and O j,fixed Input to the output layer, and then activate I through the sigmoid activation function j,fixed 、F j,fixed , O j,fixed Perform activation processing and use the tanh activation function to activate G j,fixed Perform activation processing; the activated matrix is recorded as I j,fixed_sig 、F j,fixed_sig , G j,fixed_tanh and O j,fixed_sig ; (4.5) Update the memory cell matrix C and perform fixed-point and floating-point processing; C j =F j,fixed_sig *C j-1,fixed +I j,fixed_sig *G j,fixed_tanh Among them, C fixed It represents the matrix representation of the memory cell matrix C after fixed-point and floating-point processing in the previous iteration; For the updated memory cell matrix C j Perform fixed-point and floating-point processing to obtain the memory cell matrix C j,fixed , and then the memory cell matrix C is activated by the tanh activation function j,fixed Perform activation processing to obtain the activated matrix C j,fixed_tanh ; The fixed-point processing process is as follows: retain 7 integer bits, 1 sign bit and 14 decimal bits, perform truncation based on rounding for decimal bits exceeding 14, and finally combine the sign bit, integer bit and decimal bit into a binary string format; (4.6) Calculate the output matrix H of the output layer after the jth iteration j And perform fixed-point and floating-point processing; H j =O j,fixed_sig *C j,fixed_tanh For the output matrix H j Perform fixed-point and floating-point processing to obtain the output matrix H j,fixed , where the fixed-point processing process is: retain 1 integer bit, 1 sign bit and 25 decimal places, perform truncation based on rounding for decimal places exceeding 25, and finally combine the sign bit, integer bit and decimal place into a binary string format; (4.7), the output matrix H of the output layer j,fixed Input to the hidden layer, and get the output matrix I of the input gate through the four gates of the hidden layer h,j , the output matrix F of the forget gate h,j , the output matrix G of the unit state gate h,j The output matrix O of the output gate h,j ; Then the four gate output matrices of the hidden layer are fed back to the input layer; At the same time, the output matrix H of the output layer j,fixed As the input of the second LSTM layer, Then, follow steps (4.2) to (4.7) to complete the calculation of the second LSTM layer and obtain the final output matrix H of the second LSTM layer. j,fixed ; (4.8) Traverse the sampled data Finally, the final output matrix H of the second LSTM layer after the Nth iteration is obtained j,fixed ; (4.9), the output matrix H j,fixed As the input of the fully connected layer, a set of probability vectors of length M is obtained through the fully connected layer Indicates the probability value of the modulation signal to be tested belonging to the mth modulation type; H fc =h L ·W fc +B fc (4.10) The probability vector output by the fully connected layer The input is sent to the softmax layer, and the modulation type corresponding to the maximum probability value is output as the final classification result.
2. The modulation signal classification method based on the fixed bit width LSTM neural network according to claim 1 is characterized in that: The sigmoid activation function and the tanh function activation both use a third-order piecewise fitting method for function activation, and the specific activation process is: Let the input data be x; First, the input data x is roughly segmented into: [0,0.5), [0.5,1), [1,1.5), [1.5,3), [3,5), [5,8), [8,+∞); Next, define the activation function fitting polynomial of the input data x: Ax 3 +Bx 2 +Cx+D, where A, B, C, and D represent the multiplication parameters of the activation function at different segments; Secondly, the input data x is processed for absolute value to obtain the data |x|; then |x| is fixed-point converted to 4 integer digits and 14 decimal digits; x 2 Fixed point conversion to 7 integer bits and 14 decimal places; x 3 Convert Cx to 6 integer bits and 14 decimal places; convert Bx to 10 integer bits and 14 decimal places. 2 Convert Ax to 9 integer digits and 14 decimal digits. 3 Fixed point conversion to 12 integer bits and 14 decimal places; After the fixed-point processing is completed, the integer bits and decimal bits are combined into a binary string format and then processed into floating-point form. For the sigmoid activation function, the floating-point processing result is used as the final activation output, while for the tanh function, it is necessary to process according to the positive or negative of the input data x. If x is negative, the floating-point processing result is negative and used as the final activation output. Otherwise, the floating-point processing result is directly used as the final activation output.