GPU acceleration method and system for homomorphic encryption technology

Abstract

The invention discloses a GPU acceleration method and system for a homomorphic encryption technology, relates to homomorphic encryption and GPU acceleration technologies, and aims to solve the problems that complex polynomial calculation with relatively long coefficient digits needs to be carried out for realizing homomorphic encryption, and a GPU lacks the capability of processing such data. The technical key points of the invention are as follows: an optimization technology based on thread beam shuffling is adopted to eliminate synchronization overhead; the problem of imbalance between memory access and calculation is solved by utilizing kernel fusion; for neural network reasoning application, different coding methods are designed for different scenes: for small-batch data, a full-connection layer calculation method based on a large-step and small-step algorithm is adopted, and the number of rotation keys required for data transmission is reduced. For mass data, a stream-based calculation method is introduced to improve the GPU utilization rate. Through thread beam shuffling, kernel fusion and neural network reasoning optimization, compared with a homomorphic encryption open source library SEAL, 256 times of acceleration is realized, and millisecond and sub-millisecond reasoning speeds are respectively provided for small-batch and large-batch data on the convolutional neural network.

Description

Technical Field

[0001] The present invention relates to the field of homomorphic encryption and GPU acceleration technology, and in particular to a GPU acceleration method for homomorphic encryption technology. Background Art

[0002] Homomorphic encryption (HE) is an encryption technique that allows operations to be performed directly on ciphertext and still obtain the correct result after decryption. This feature makes it widely used in the fields of privacy protection and data security, especially in cloud computing. However, traditional homomorphic encryption calculations are often accompanied by huge computational overhead and are difficult to meet the performance requirements of practical applications. Early homomorphic encryption schemes required a large amount of computing resources during the encryption and decryption process, which led to their low efficiency in practical applications. Although these methods can perform calculations while ensuring data privacy, they are difficult to promote in application scenarios requiring real-time processing due to their high computational cost and slow computing speed.

[0003] In order to solve this problem, homomorphic encryption schemes based on GPU acceleration have emerged in recent years. By utilizing the parallel computing power of GPUs, these methods can significantly improve the speed of homomorphic encryption calculations, thereby achieving sufficiently fast operation efficiency while ensuring data privacy. This method can be effectively applied in cloud computing, which not only meets the privacy protection needs but also greatly reduces computing latency. However, the implementation of homomorphic encryption requires complex polynomial calculations. The number of digits of these polynomial coefficients is relatively long, and GPUs lack the ability to process such data. In addition, in machine learning applications of private data, HE faces the challenges of complex operations of deep learning algorithms (such as convolution and pooling). The current fully homomorphic encryption (FHE) only supports addition and multiplication, and cross-slot operations introduce additional overhead, which limits its efficiency and scalability.

[0004] For example, the existing patent document with document number CN118690414A discloses a privacy information retrieval method and system based on GPU fast response, which includes: preprocessing database data to obtain preprocessed database data; storing the preprocessed database data in the GPU of the server; the CPU obtains the query data of the user client, the CPU sends the query data to the GPU, the GPU uses a homomorphic encryption algorithm to expand the query data to obtain the expanded query data; the GPU matches the preprocessed database data based on the expanded query data to obtain a response result in ciphertext form; the GPU sends the response result in ciphertext form to the CPU; the CPU sends the response result in ciphertext form to the user client, and the user client decrypts the response result to obtain the decrypted response result. This prior art provides a GPU acceleration solution with low data transfer times and high execution efficiency. Summary of the invention

[0005] The technical problems to be solved by the present invention are:

[0006] In view of the following problems in existing homomorphic encryption schemes based on GPU acceleration: the implementation of homomorphic encryption requires complex polynomial calculations with long coefficient digits, and GPUs lack the ability to process such data; and the current fully homomorphic encryption (FHE) only supports addition and multiplication and cannot perform complex convolution and pooling operations, and cross-slot operations introduce additional overhead, which limits its efficiency and scalability. The present invention provides a GPU acceleration method and system for homomorphic encryption technology.

[0007] The technical solution adopted by the present invention to solve the above technical problems is:

[0008] According to one aspect of the present invention, a GPU acceleration method for homomorphic encryption technology is proposed, which includes:

[0009] The step of data encoding and encryption is to preprocess and encode the plaintext data in floating point form, convert the plaintext data into a polynomial form of homomorphic encryption, and encrypt the encoded data;

[0010] The step of decomposing large number operations is to apply the Chinese Remainder Theorem (CRT) to decompose large number operations into multiple parallel operations under small moduli, so as to utilize the multi-threaded architecture of GPU to perform the decomposed small number operations;

[0011] The steps of fast number theoretic transform, apply fast number theoretic transform (NTT) to perform multiplication operation, and convert polynomial convolution into point value multiplication;

[0012] The basic operation steps use the parallel computing power of GPU to accelerate homomorphic addition, homomorphic multiplication, homomorphic rotation, key switching and rescaling operations in homomorphic encryption;

[0013] The steps of advanced operations are to implement complex homomorphic operations based on basic operations, including matrix-vector multiplication and convolution in neural networks.

[0014] Optionally, the plaintext data in the data encoding and encryption module includes neural network convolution kernel parameters and fully connected layer parameters.

[0015] Furthermore, the Chinese remainder theorem module includes:

[0016] In the decomposition stage, the coefficients of the polynomial are moduli-reduced by different moduli, and the remainders are stored in different addresses;

[0017] In the synthesis stage, multiple residual numbers are synthesized using mixed radix conversion (MRC). These residual numbers are first stored in registers, and the thread bundle shuffle mechanism is used between different GPU threads to reduce communication overhead.

[0018] Furthermore, the fast number theory transformation module comprises the following steps:

[0019] Step 1: Convert the one-dimensional NTT to a two-dimensional NTT by first performing NTT on the columns and then on the rows. Each operation is implemented by a kernel function.

[0020] Step 2: Each time the kernel function is started, the data in the global memory is copied to the shared memory, and the shared memory is used instead of the direct access to the global memory;

[0021] Step 3: In the last five rounds of the butterfly transformation, data exchange within the same warp is achieved through warp shuffling to optimize communication efficiency.

[0022] Furthermore, the basic operation module uses batch optimization technology to execute multiple operations under different moduli in a single kernel function, thereby reducing the kernel function startup overhead.

[0023] Furthermore, the key switching operation involves inner product calculation and NTT transformation. To improve efficiency, the kernel functions of the two are merged into one to reduce the communication between kernel functions.

[0024] Furthermore, the advanced operation module adopts the big-step small-step method (BSGS) when performing matrix-vector multiplication to reduce the dependence on homomorphic rotation operations.

[0025] Furthermore, the advanced computing module divides computing tasks without data conflicts into different computing streams for execution through stream processing technology, so as to further improve the efficiency of parallel computing.

[0026] A GPU acceleration system for homomorphic encryption technology, comprising: the system has a program module corresponding to the steps of the above technical solution, and executes the steps in the above GPU acceleration method for homomorphic encryption technology during operation;

[0027] The data encoding and encryption module preprocesses and encodes the plaintext data in floating point form, converts the plaintext data into a polynomial form of homomorphic encryption, and encrypts the encoded data;

[0028] Large number operation decomposition module (Chinese remainder theorem module), which applies the Chinese remainder theorem (CRT) to decompose large number operations into parallel operations under multiple small moduli, so as to utilize the multi-threaded architecture of GPU to perform the decomposed small number operations;

[0029] The fast number theoretic transform module applies the fast number theoretic transform (NTT) to perform multiplication operations and convert polynomial convolution into point value multiplication;

[0030] Basic computing module, which uses the parallel computing power of GPU to accelerate homomorphic addition, homomorphic multiplication, homomorphic rotation, key switching and rescaling operations in homomorphic encryption;

[0031] Advanced computing module, which implements complex homomorphic operations based on basic operations, including matrix-vector multiplication and convolution in neural networks.

[0032] The technical features further defined in each module in a GPU acceleration system for homomorphic encryption technology are consistent with the steps in a GPU acceleration method for homomorphic encryption technology.

[0033] A computer-readable storage medium stores a computer program, wherein the computer program is configured to implement the steps of a GPU acceleration method for homomorphic encryption technology when called by a processor.

[0034] The beneficial technical effects of the present invention are:

[0035] The present invention adopts an optimization technology based on thread bundle shuffling to eliminate synchronization overhead; kernel fusion is used to solve the imbalance between memory access and calculation; for neural network reasoning applications, different encoding methods are designed for different scenarios (i.e., small batches and large batches): for small batches of data, a fully connected layer calculation method based on a large-step small-step algorithm is adopted to reduce the number of rotation keys required for data transmission. For large batches of data, a stream-based calculation method is introduced to improve GPU utilization. Through thread bundle shuffling, kernel fusion and neural network reasoning optimization, the present invention achieves a 256-fold acceleration compared to the homomorphic encryption open source library SEAL, and provides millisecond and sub-millisecond reasoning speeds for small batches and large batches of data on convolutional neural networks, respectively.

[0036] This paper uses an optimization technique based on warp shuffling to mitigate synchronization overhead in homomorphic encryption. Specifically, in the Inverse Chinese Remainder Theorem (ICRT) stage, multiple threads in the same warp are used to compute mixed radix representations, thereby improving GPU utilization. By ensuring that the number of factorized polynomials is less than the maximum number of threads in the warp, synchronization overhead is effectively eliminated.

[0037] By fusing the NTT kernel with the inner product kernel, the imbalance between memory access and computation is resolved. By fusing these two kernels, a relative balance between memory and computation requirements is achieved.

[0038] For neural network inference applications, different encoding methods are designed for different scenarios (i.e., small batch and large batch). For small batch data, a fully connected layer calculation method based on the Baby-Step Giant-Step (BSGS) algorithm is proposed, which effectively reduces the number of rotation keys required for data transmission. For large batch data, a stream-based calculation method is introduced to improve GPU utilization.

[0039] Through thread bundle shuffling, kernel fusion and neural network inference optimization, the present invention achieves 256 times acceleration compared to the homomorphic encryption open source library SEAL. In addition, the present invention provides millisecond and sub-millisecond inference speeds for convolutional neural network (CNN) models on small and large batch MNIST datasets, respectively.

[0040] The present invention realizes the ability of GPU homomorphic encryption to process complex polynomials (these polynomial coefficients have long digits) to calculate such data. In addition, in the machine learning application of privacy data, HE faces the challenge of complex operations of deep learning algorithms (such as convolution and pooling), while the present invention supports convolution and pooling operations without introducing additional overhead by cross-slot operations, and has good efficiency and scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The present invention can be better understood by referring to the description given below in conjunction with the accompanying drawings, which together with the following detailed description are included in this specification and form a part of this specification, and are used to further illustrate the preferred embodiments of the present invention and explain the principles and advantages of the present invention.

[0042] Figure 1 is a flow chart of large number synthesis described in the embodiment;

[0043] Figure 2 is a schematic diagram of data grouping of the fast number theory transformation described in the embodiment;

[0044] Figure 3 is a flow chart of the BSGS algorithm described in the embodiment;

[0045] Figure 4 is a schematic diagram of the stream processing technology described in the embodiment;

[0046] Figure 5 This is a comparison diagram of SM utilization before and after kernel fusion optimization according to an embodiment of the present invention;

[0047] Figure 6 This is a comparison chart of memory utilization before and after kernel fusion optimization according to an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the scheme of the present invention, exemplary implementations or embodiments of the present invention will be described below in conjunction with the accompanying drawings. Obviously, the described implementations or embodiments are only implementations or embodiments of a part of the present invention, not all of them. Based on the implementations or embodiments of the present invention, all other implementations or embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present invention.

[0049] The system of the present invention comprises the following modules:

[0050] The data encoding and encryption module preprocesses and encodes the plaintext data in floating point form, converts the plaintext data into a polynomial form of homomorphic encryption, and encrypts the encoded data;

[0051] Large number operation decomposition module (Chinese remainder theorem module), which applies the Chinese remainder theorem (CRT) to decompose large number operations into parallel operations under multiple small moduli, so as to utilize the multi-threaded architecture of GPU to perform the decomposed small number operations;

[0052] The fast number theoretic transform module applies the fast number theoretic transform (NTT) to perform multiplication operations and convert polynomial convolution into point value multiplication;

[0053] Basic computing module, which uses the parallel computing power of GPU to accelerate homomorphic addition, homomorphic multiplication, homomorphic rotation, key switching and rescaling operations in homomorphic encryption;

[0054] Advanced computing module, which implements complex homomorphic operations based on basic operations, including matrix-vector multiplication and convolution in neural networks.

[0055] In this embodiment, optionally, the plaintext data in the data encoding and encryption module includes neural network convolution kernel parameters and fully connected layer parameters. Specifically, different encoding methods are designed for large-batch and small-batch user inputs. In the scenario of large-batch data, the image pixels at the same position in a batch will be packed into a ciphertext, and the corresponding convolution kernel parameters and fully connected layer parameters will encode an element for broadcasting the operation to all batches; in the scenario of small-batch data, all data will be packed into a ciphertext, and the corresponding convolution kernel parameters and fully connected layer parameters will encode all elements. The large-batch encoding method is suitable for scenarios with high requirements for effective bandwidth, while the small-batch encoding method is suitable for scenarios with requirements for latency.

[0056] In this embodiment, optionally, the Chinese remainder theorem module includes:

[0057] In the decomposition stage, the coefficients of the polynomial are moduli-reduced by different moduli, and the remainders are stored in different addresses;

[0058] In the synthesis stage, multiple residual numbers are synthesized using mixed radix conversion (MRC). These residual numbers are first stored in registers, and the thread bundle shuffle mechanism is used between different GPU threads to reduce communication overhead.

[0059] Figure 1 The MRC data dependency graph is shown, with the remainder representation on the top and the mixed radix representation on the bottom. In order to make full use of the characteristics of GPU parallel computing, the present invention allocates a thread to each vertical data stream in the graph, and the communication between horizontal data streams adopts the thread bundle shuffle mechanism. Considering the characteristics of thread bundle execution, that is, the threads in the thread bundle execute the same operation at the same time, as long as the size of the thread bundle exceeds the number of radixes of the mixed radix, no synchronization is required. Since the number of moduli required for homomorphic encryption is generally smaller than the thread bundle size, synchronization operations are avoided.

[0060] In this embodiment, optionally, the fast number theory transformation module includes the following steps:

[0061] Step 1: Convert the one-dimensional NTT to a two-dimensional NTT by first performing NTT on the columns and then on the rows. Each operation is implemented by a kernel function.

[0062] Step 2: Each time the kernel function is started, the data in the global memory is copied to the shared memory, and the shared memory is used instead of the direct access to the global memory;

[0063] Step 3: In the last five rounds of the butterfly transformation, data exchange within the same warp is achieved through warp shuffling to optimize communication efficiency.

[0064] The N-point NTT is divided into log N stages by the butterfly transform. In the basic GPU implementation of the NTT algorithm, each thread requires O(log N) global memory accesses, which results in a large amount of memory access overhead. A common optimization strategy is to transfer data from global memory to shared memory. However, the scope of shared memory is limited to the thread block level, and the current GPU architecture limits the number of threads per thread block to a maximum of 1024. Therefore, only a Radix-2 NTT of 2048 points can be processed. For NTTs with higher point numbers, multiple kernel functions must be used, which results in a large amount of global memory access overhead. Therefore, before executing step two, the present invention divides the one-dimensional NTT into a two-dimensional NTT, and the number of points of the NTT in each dimension is less than 2048, so that in step two, shared memory can be used to access all data in one dimension, and the grouping method is as follows: Figure 2 shown.

[0065] Similar to the optimization of the large number operation decomposition module, the present invention again uses the thread bundle shuffle optimization to improve memory access efficiency and reduce synchronization. Another benefit of this optimization is that bank conflicts are avoided. Bank conflicts refer to the conflict phenomenon caused when the shared memory is divided into 32 banks, each bank stores continuous 32-bit data, and multiple threads in the thread bundle access the same bank at the same time. During the execution of NTT, all threads in the thread bundle read the elements of the butterfly transformation at the same time. When the stride in a round is greater than or equal to 32 (bank size), no bank conflict will occur; but when the stride is less than 32, a conflict will occur because only 16 banks are used. In order to solve this problem, registers are used instead of shared memory in the last five stages of NTT to eliminate bank conflicts.

[0066] In order to reduce the synchronization overhead, the present invention utilizes implicit synchronization within the thread bundle. In the last five stages of NTT, it can be decomposed into multiple 64-point NTT transformations, so that data dependencies are limited to within a thread bundle, and thread bundle internal communication is achieved through thread bundle shuffling. Given that the NTT point range in homomorphic encryption is usually 2 11 to 2 15 ,This implicit synchronization is very beneficial.,By optimizing the last five stages of NTT using warp shuffling, the present invention eliminates most of the synchronization.

[0067] In this embodiment, the basic operation module can optionally perform multiple operations under different moduli in a single kernel function through batch optimization technology to reduce the kernel function startup overhead. Specifically, data under different moduli are converted into one thread and optimized using loop unrolling.

[0068] In this embodiment, optionally, the key switching operation involves inner product calculation and NTT transformation. To improve efficiency, the kernel functions of the two are merged into one to reduce the communication between kernel functions. Specifically, the key switching first needs to switch the ciphertext from the NTT domain to the polynomial coefficient domain, then perform module switching on the ciphertext, and then switch the ciphertext to the NTT domain to perform inner product with the key. After the module switching, the data will expand to several times the input. In order to reduce the cost of data transmission, the data switched to the NTT domain is directly read by the inner product kernel function to reduce data transmission.

[0069] In this embodiment, optionally, the advanced operation module adopts the big-step small-step method (BSGS) when performing matrix-vector multiplication to reduce the dependence on homomorphic rotation operations. Figure 3 As shown, specifically, when performing matrix-vector multiplication, the operation is decomposed into the multiplication of multiple plaintexts and rotated ciphertexts. When performing rotation, only the ciphertext with a small step length is rotated, and the calculation results are accumulated before performing a large step length rotation.

[0070] In this embodiment, optionally, the advanced computing module divides computing tasks without data conflicts into different computing streams for execution through stream processing technology to further improve the efficiency of parallel computing. Figure 4 Specifically, CUDA streams optimize large batch encoding by assigning independent kernel functions to different streams to achieve parallelization. In fully connected layers and convolutional layers, kernel functions associated with each result element are merged into one stream to mask kernel launch latency.

[0071] The technical effect of the present invention is further verified by experiments. The experiments are divided into four parts, which verify respectively:

[0072] The optimization effect of the Chinese Remainder Theorem module and NTT module based on the thread bundle shuffling technology.

[0073] The optimization effect of the basic computing module based on batch processing and kernel fusion optimization.

[0074] Performance comparison between the present invention and other open source libraries.

[0075] Performance comparison of the present invention in neural network reasoning applications.

[0076] The present invention compares the Chinese remainder theorem module and the fast number theory transformation module with the baseline, both of which benefit from the optimization based on the thread bundle shuffle. Table 1 shows the comparison between the implementation of the inverse Chinese remainder theorem and HE-Booster, which processes all the remainder numbers in one thread. It can be seen from the experimental results that the method of the present invention shows significant advantages, especially under smaller parameters, namely the polynomial length N and the number of moduli L. It shows that there is a large room for improvement in GPU utilization. This method improves computing efficiency by improving GPU utilization. Although this method requires additional synchronization operations, the present invention eliminates the overhead caused by synchronization through implicit synchronization of threads within the thread bundle.

[0077] Table 1 Performance of Chinese Remainder Theorem Module

[0078]

[0079] As shown in Table 2, in Scheme I, the present invention uses shared memory instead of global memory, limiting global memory access to the beginning and end of each kernel function. This is in contrast to the baseline method, which requires interaction with global memory at each iteration. Therefore, as the number of NTT points and the number of iterations increase, the advantage of this optimization becomes more and more obvious. In Scheme II, the present invention further introduces a 2D NTT transformation, which reduces the number of kernel launches and further reduces global memory accesses, thereby significantly improving performance. In Scheme III, the present invention further uses registers instead of shared memory, and uses thread bundle shuffles for communication, which reduces the time of synchronization operations while avoiding memory bank conflicts.

[0080] Figure 5 and Figure 6 The unoptimized inner product (IP), kernel 1 (K1), and kernel 2 (K2), as well as the kernels optimized with batching (K1-Opt) and kernel fusion (K2-Opt) were analyzed. The optimized kernels showed significant utilization improvements, mainly due to batching. The unoptimized inner product showed a large imbalance in memory usage, which was alleviated with kernel fusion, achieving a balance in memory and stream processor (SM) utilization.

[0081] As shown in Table 3, GPU acceleration does not significantly improve homomorphic addition because these operations are independent of NTT and INTT and are not affected by NTT optimization. However, due to frequent conversions between NTT and INTT domains, relinearization and rotation operations show significant acceleration effects. Kernel fusion and batch processing methods further reduce the computational overhead of these operations. As shown in Table 3, under the same GPU model, the method of the present invention shows better performance.

[0082] Table 2 Fast number theory transformation module performance

[0083]

[0084] Table 3. Comparison of homomorphic encryption operation performance

[0085]

[0086]

[0087] Table 4 Convolutional neural network performance under different batches

[0088]

[0089] In order to evaluate the practical applicability of the algorithm proposed in this paper, the present invention implements a convolutional neural network (CNN) and designs a CNN based on the structure of Cryptonet. The CNN of the present invention includes a convolutional layer and two fully connected layers, using the square function as the activation function. The convolutional layer uses zero padding, a stride of 1, and a filter size of (5×5,1). The configurations of the fully connected layers are (784,64) and (64,10) respectively. The model is pre-trained on the MNIST dataset using PyTorch, and the present invention experiments with inference applications for different batch sizes.

[0090] In the large-batch scenario, the present invention encapsulates one pixel of 4096 images into one ciphertext, and the size of the transmitted ciphertext is 367.5MB (28*28*2*8192*240bit). In the small-batch scenario, the present invention encapsulates 8 data blocks into one ciphertext, and the size of the transmitted ciphertext is 1.56MB (2*16384*400bit). The results show that for smaller input data scales, small-batch processing effectively reduces the number of homomorphic operations (HOPs). Table 4 provides a comparative analysis with existing methods. For small-batch encoding, the average inference time is 1.88 milliseconds per inference. In terms of large-batch processing, stream processing significantly improves efficiency, reducing the inference time for a batch of data to less than 1 second.

[0091] In summary, the method proposed in the present invention significantly improves the stream processing efficiency in large batch processing. The method of the present invention has been verified through simulation experiments and practical applications, and the technical effects and practicality claimed by the present invention have been verified.

[0092] The algorithm (method) proposed in the present invention is the underlying technical core of the present invention, and various products can be derived based on the algorithm.

[0093] Based on the algorithm (method) proposed in the present invention, a GPU acceleration system for homomorphic encryption technology is developed using a programming language. The system has program modules corresponding to the steps of the above-mentioned technical solution, and executes the steps in the above-mentioned GPU acceleration method for homomorphic encryption technology during operation.

[0094] The computer program of the developed system (software) is stored on a computer-readable storage medium, and the computer program is configured to implement the steps of the above-mentioned GPU acceleration method for homomorphic encryption technology when called by a processor. That is, the present invention is materialized on a carrier to become a computer program product.

[0095] The present invention also provides a GPU acceleration device for homomorphic encryption technology, the device comprising at least one processor and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the above-mentioned GPU acceleration method for homomorphic encryption technology.

[0096] Various implementations of the systems and techniques described herein can be realized in digital electronic circuit systems, integrated circuit systems, dedicated ASICs (application specific integrated circuits), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0097] The computer programs (also referred to as programs, software, software applications, or codes) of the present invention include machine instructions for programmable processors, and these computer programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, device, and / or device (e.g., disk, optical disk, memory, programmable logic device PLD) for providing machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as machine-readable signals. The term "machine-readable signal" refers to any signal for providing machine instructions and / or data to a programmable processor.

[0098] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in the present application can be executed in parallel, sequentially or in different orders, as long as the expected results of the technical solutions disclosed in the present application can be achieved, they are all within the scope of protection of the present invention. Although the present invention is described according to a limited number of embodiments, it is understood by those skilled in the art with the benefit of the above description that other embodiments can be envisioned within the scope of the present invention described thereby. The disclosure of the present invention is illustrative and not restrictive with respect to the scope of the present invention, and the scope of the present invention is defined by the appended claims.

Claims

1. A GPU acceleration method for homomorphic encryption technology, characterized in that: include: The step of data encoding and encryption is to preprocess and encode the plaintext data in floating point form, convert the plaintext data into a polynomial form of homomorphic encryption, and encrypt the encoded data; The step of decomposing large number operations is to apply the Chinese Remainder Theorem (CRT) to decompose large number operations into multiple parallel operations under small moduli, so as to utilize the multi-threaded architecture of GPU to perform the decomposed small number operations; The steps of fast number theoretic transform, apply fast number theoretic transform (NTT) to perform multiplication operation, and convert polynomial convolution into point value multiplication; The basic operation steps use the parallel computing power of GPU to accelerate homomorphic addition, homomorphic multiplication, homomorphic rotation, key switching and rescaling operations in homomorphic encryption; The steps of advanced operations are to implement complex homomorphic operations based on basic operations, including matrix-vector multiplication and convolution in neural networks.

2. The GPU acceleration method for homomorphic encryption technology according to claim 1, characterized in that: The plaintext data in the data encoding encryption includes neural network convolution kernel parameters and fully connected layer parameters.

3. A GPU acceleration method for homomorphic encryption technology according to claim 1 or 2, characterized in that: The steps of large number operation decomposition include: In the decomposition stage, the coefficients of the polynomial are moduli-reduced by different moduli, and the remainders are stored in different addresses; In the synthesis stage, multiple residual numbers are synthesized using mixed radix conversion (MRC). These residual numbers are first stored in registers, and the thread bundle shuffle mechanism is used between different GPU threads to reduce communication overhead.

4. According to claim 3, a GPU acceleration method for homomorphic encryption technology is characterized in that: The fast number theory transformation comprises the following steps: Step 1: Convert the one-dimensional NTT to a two-dimensional NTT by first performing NTT on the columns and then on the rows. Each operation is implemented by a kernel function. Step 2: Each time the kernel function is started, the data in the global memory is copied to the shared memory, and the shared memory is used instead of the direct access to the global memory; Step 3: In the last five rounds of the butterfly transformation, data exchange within the same warp is achieved through warp shuffling to optimize communication efficiency.

5. A GPU acceleration method for homomorphic encryption technology according to claim 4, characterized in that: The basic operation is optimized through batch processing, and multiple operations under different moduli are executed in a single kernel function, thereby reducing the kernel function startup overhead.

6. A GPU acceleration method for homomorphic encryption technology according to claim 4 or 5, characterized in that: Based on the fact that key switching involves inner product calculation and NTT transformation, the kernel functions of the two are merged into one to reduce the communication between kernel functions and improve efficiency.

7. The GPU acceleration method for homomorphic encryption technology according to claim 1, characterized in that: The advanced operation uses the big-step small-step method (BSGS) when performing matrix-vector multiplication to reduce the reliance on homomorphic rotation operations.

8. The GPU acceleration method for homomorphic encryption technology according to claim 7, further characterized in that: The advanced computing divides computing tasks without data conflicts into different computing streams for execution through stream processing technology to improve the efficiency of parallel computing.

9. A GPU acceleration system for homomorphic encryption technology, characterized in that: include: The system has a program module corresponding to the steps of claim 1, and executes the steps of the GPU acceleration method for homomorphic encryption technology during operation; The data encoding and encryption module preprocesses and encodes the plaintext data in floating point form, converts the plaintext data into a polynomial form of homomorphic encryption, and encrypts the encoded data; Large number operation decomposition module (Chinese remainder theorem module), which applies the Chinese remainder theorem (CRT) to decompose large number operations into multiple parallel operations under small moduli, so as to utilize the multi-threaded architecture of GPU to perform the decomposed small number operations; The fast number theoretic transform module applies the fast number theoretic transform (NTT) to perform multiplication operations and convert polynomial convolution into point value multiplication; Basic computing module, which uses the parallel computing power of GPU to accelerate homomorphic addition, homomorphic multiplication, homomorphic rotation, key switching and rescaling operations in homomorphic encryption; Advanced computing module, which implements complex homomorphic operations based on basic operations, including matrix-vector multiplication and convolution in neural networks.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is configured to implement the steps of a GPU acceleration method for homomorphic encryption technology described in any one of claims 1 to 8 when called by a processor.

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