A GPU-accelerated method and system for homomorphic encryption

Abstract

A GPU acceleration method and system for homomorphic encryption technology, related to homomorphic encryption and GPU acceleration technology, in order to solve the problem that complex coefficient polynomial calculation with long bit number is required to realize homomorphic encryption and GPU lacks the ability to process such data, the technical points of the present application include: an optimization technology based on thread bundle shuffling is adopted to eliminate synchronization overhead; kernel fusion is used to solve the imbalance problem between memory access and calculation; for neural network inference application, different encoding methods are designed for different scenarios: for small batch data, a full connection layer calculation method based on large step small step algorithm is adopted, which reduces the number of rotation keys required for data transmission. For large batch data, a flow-based calculation method is introduced to improve GPU utilization. Through thread bundle shuffling, kernel fusion and neural network inference optimization, the present application realizes 256 times acceleration compared with homomorphic encryption open source library SEAL, and provides millisecond and sub-millisecond inference speed for small batch and large batch data on convolutional neural network respectively.

Description

Technical Field

[0001] This invention relates to the fields of homomorphic encryption and GPU acceleration technology, and specifically to a GPU acceleration method for homomorphic encryption technology. Background Technology

[0002] Homomorphic encryption (HE) is an encryption technique that allows direct computation on ciphertext, yielding the correct result after decryption. This characteristic makes it widely used in privacy protection and data security, especially in cloud computing. However, traditional homomorphic encryption computation often involves huge computational overhead, making it difficult to meet the performance requirements of practical applications. Early homomorphic encryption schemes required a large amount of computing resources during encryption and decryption, resulting in low efficiency in practical applications. Although these methods can perform computations while ensuring data privacy, their high computational cost and slow processing speed make them difficult to promote in applications requiring real-time processing.

[0003] To address this issue, GPU-accelerated homomorphic encryption schemes have emerged in recent years. By leveraging the parallel computing capabilities of GPUs, these methods can significantly improve the speed of homomorphic encryption computation, thereby achieving sufficiently fast execution efficiency while ensuring data privacy. This approach can be effectively applied in cloud computing, satisfying privacy protection requirements while significantly reducing computational latency. However, implementing homomorphic encryption requires complex polynomial calculations with long coefficients, and GPUs lack the capability to process this type of data. Furthermore, in machine learning applications using privacy-preserving data, homomorphic encryption (HE) faces challenges from complex operations in deep learning algorithms (such as convolution and pooling). Current fully homomorphic encryption (FHE) only supports addition and multiplication, and cross-slot operations introduce additional overhead, limiting its efficiency and scalability.

[0004] For example, patent document CN118690414A discloses a privacy information retrieval method and system based on GPU fast response, which includes: preprocessing database data to obtain preprocessed database data; storing the preprocessed database data in the GPU of a server; the CPU acquiring query data from the user client, sending the query data to the GPU, and the GPU expanding the query data using a homomorphic encryption algorithm to obtain expanded query data; the GPU matching the expanded query data in the preprocessed database data to obtain a ciphertext response result; the GPU sending the ciphertext response result to the CPU; the CPU sending the ciphertext response result to the user client, and the user client decrypting the response result to obtain the decrypted response result. This prior art provides a GPU acceleration solution with fewer data transfers and higher execution efficiency. Summary of the Invention

[0005] The technical problem to be solved by this invention is:

[0006] Given that existing GPU-accelerated homomorphic encryption schemes have the following problems: implementing homomorphic encryption requires complex polynomial calculations with long coefficients, GPUs lack the ability to process such data, and current fully homomorphic encryption (FHE) only supports addition and multiplication and cannot perform complex convolution and pooling operations, and cross-slot operations introduce additional overhead, limiting its efficiency and scalability, this invention provides a GPU-accelerated method and system for homomorphic encryption technology.

[0007] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows:

[0008] According to one aspect of the present invention, a GPU acceleration method for homomorphic encryption technology is proposed, comprising:

[0009] The data encoding and encryption steps involve preprocessing and encoding plaintext data in floating-point form, converting the plaintext data into a homomorphic encrypted polynomial form, and then encrypting the encoded data.

[0010] The steps of large number decomposition are to apply the Chinese Remainder Theorem (CRT) to decompose large number operations into parallel operations under multiple small moduli, so as to utilize the multi-threaded architecture of the GPU to execute the decomposed fractional operations.

[0011] The steps of the Fast Number Theory Transform (NTT) are to perform multiplication operations by applying the NTT to convert polynomial convolution into point-value multiplication.

[0012] The basic computation steps utilize the parallel computing capabilities of GPUs to accelerate homomorphic addition, homomorphic multiplication, homomorphic rotation, key switching, and rescaling operations in homomorphic encryption.

[0013] Advanced computation steps, based on basic operations to implement complex homomorphic operations, including matrix-vector multiplication and convolution in neural networks.

[0014] Optionally, the plaintext data in the data encoding and encryption module includes neural network convolution kernel parameters and fully connected layer parameters.

[0015] Furthermore, the Chinese Remainder Theorem module includes:

[0016] In the decomposition stage, the coefficients of the polynomial are moduloed by different moduli, and the remainders are stored in different addresses.

[0017] During the synthesis phase, multiple residuals are synthesized using Mixed Radix Conversion (MRC). These residuals are first stored in registers, and communication overhead is reduced between different GPU threads through a thread bundle shuffling mechanism.

[0018] Furthermore, the fast number theory transformation module includes the following steps:

[0019] Step 1: Convert the one-dimensional NTT to a two-dimensional NTT. First, perform NTT on the columns and then on the rows. Each operation is implemented by a kernel function.

[0020] Step 2: Each time the kernel function is started, the data in global memory is copied to shared memory, and shared memory is used instead of direct access to global memory;

[0021] Step 3: In the last five rounds of the butterfly transformation, data exchange within the same thread bundle is achieved through thread bundle shuffling to optimize communication efficiency.

[0022] Furthermore, the basic operation module uses batch processing optimization technology to execute operations under multiple different moduli in a single kernel function, reducing the kernel function startup overhead.

[0023] Furthermore, the key switching operation involves inner product calculation and NTT transformation. To improve efficiency, the kernel functions for these two operations are merged into one, reducing communication between kernel functions.

[0024] Furthermore, the advanced computation module employs Big Step Small Step (BSGS) when performing matrix-vector multiplication to reduce reliance on homomorphic rotation operations.

[0025] Furthermore, the advanced computing module uses stream processing technology to divide computing tasks without data conflicts into different computing streams for execution, thereby further improving the efficiency of parallel computing.

[0026] A GPU acceleration system for homomorphic encryption technology includes: the system having a program module corresponding to the steps of the above-described technical solution, and executing the steps in the GPU acceleration method for homomorphic encryption technology described above during runtime;

[0027] The data encoding and encryption module preprocesses and encodes plaintext data in floating-point form, transforms the plaintext data into a homomorphic encrypted polynomial form, and encrypts the encoded data.

[0028] The large number decomposition module (Chinese Remainder Theorem module) applies the Chinese Remainder Theorem (CRT) to decompose large number operations into parallel operations under multiple small moduli, so as to utilize the multi-threaded architecture of the GPU to execute the decomposed fractional operations;

[0029] The Fast Number Theory Transform (NTT) module applies the NTT to perform multiplication operations, converting polynomial convolution into point-value multiplication.

[0030] The basic computing module utilizes the parallel computing capabilities of the GPU to accelerate homomorphic addition, homomorphic multiplication, homomorphic rotation, key switching, and rescaling operations in homomorphic encryption.

[0031] The advanced computation module implements complex homomorphic operations based on basic computations, including matrix-vector multiplication and convolution in neural networks.

[0032] The technical features further defining the various modules in a GPU acceleration system for homomorphic encryption are consistent with the steps in a GPU acceleration method for homomorphic encryption.

[0033] A computer-readable storage medium storing a computer program configured to implement the steps of the GPU-accelerated method for homomorphic encryption described above when invoked by a processor.

[0034] The beneficial technical effects of this invention are:

[0035] This invention employs an optimization technique based on thread bundle shuffling to eliminate synchronization overhead; it utilizes kernel fusion to address the imbalance between memory access and computation; and for neural network inference applications, different encoding methods are designed for different scenarios (i.e., small batches and large batches): for small batches of data, a fully connected layer computation method based on a big-step-small-step algorithm is used to reduce the number of rotation keys required for data transmission. For large batches of data, a stream-based computation method is introduced to improve GPU utilization. Through thread bundle shuffling, kernel fusion, and neural network inference optimization, this invention achieves a 256x speedup compared to the homomorphic encryption open-source library SEAL, providing millisecond and sub-millisecond inference speeds on convolutional neural networks for small and large batches of data, respectively.

[0036] This invention employs an optimization technique based on thread bundle shuffling to mitigate synchronization overhead in homomorphic encryption. Specifically, during the Inverse Chinese Remainder Theorem (ICRT) phase, multiple threads within the same thread bundle are used to compute the mixed radix representation, thereby improving GPU utilization. By ensuring that the number of polynomials factored is less than the maximum number of threads in the thread bundle, synchronization overhead is effectively eliminated.

[0037] The imbalance between memory access and computation is addressed by fusing the NTT kernel with the inner product kernel. This fusion of the two kernels achieves a relative balance between memory and computational demands.

[0038] For neural network inference applications, different encoding methods are designed for different scenarios (i.e., small batches and large batches). For small batches of data, a fully connected layer computation method based on the Baby-Step Giant-Step (BSGS) algorithm is proposed, which effectively reduces the number of rotation keys required for data transmission. For large batches of data, a stream-based computation method is introduced to improve GPU utilization.

[0039] Through thread bundle shuffling, kernel fusion, and neural network inference optimization, this invention achieves a 256x speedup compared to the homomorphic encryption open-source library SEAL. Furthermore, this invention provides millisecond and sub-millisecond inference speeds for convolutional neural network (CNN) models on mini-batch and large-batch MNIST datasets, respectively.

[0040] This invention enables GPU homomorphic encryption to process complex polynomials (with long coefficients) for computational purposes. Furthermore, in machine learning applications involving privacy-preserving data, HE faces challenges from complex deep learning algorithm operations (such as convolution and pooling). This invention supports convolution and pooling operations without introducing additional overhead through slot cross-operations, offering excellent efficiency and scalability. Attached Figure Description

[0041] The present invention can be better understood by referring to the description given below in conjunction with the accompanying drawings, which together with the following detailed description are included in and form part of this specification, and are used to further illustrate preferred embodiments of the invention and explain the principles and advantages of the invention.

[0042] Figure 1 This is a flowchart of large number synthesis as described in the embodiment;

[0043] Figure 2 This is a schematic diagram of data grouping for the fast number theory transform described in the embodiment;

[0044] Figure 3 This is a flowchart of the BSGS algorithm described in the embodiment;

[0045] Figure 4 This is a schematic diagram of the stream processing technology described in the embodiment;

[0046] Figure 5 This is a comparison chart of SM utilization before and after kernel fusion optimization in an embodiment of the present invention;

[0047] Figure 6 This is a comparison chart of memory utilization before and after kernel fusion optimization in an embodiment of the present invention. Detailed Implementation

[0048] To enable those skilled in the art to better understand the present invention, exemplary embodiments or examples of the present invention will be described below in conjunction with the accompanying drawings. Obviously, the described embodiments or examples are merely some, not all, of the embodiments or examples of the present invention. All other embodiments or examples obtained by those skilled in the art based on the embodiments or examples of the present invention without inventive effort should fall within the scope of protection of the present invention.

[0049] The system described in this invention includes the following modules:

[0050] The data encoding and encryption module preprocesses and encodes plaintext data in floating-point form, transforms the plaintext data into a homomorphic encrypted polynomial form, and encrypts the encoded data.

[0051] The large number decomposition module (Chinese Remainder Theorem module) applies the Chinese Remainder Theorem (CRT) to decompose large number operations into parallel operations under multiple small moduli, so as to utilize the multi-threaded architecture of the GPU to execute the decomposed fractional operations;

[0052] The Fast Number Theory Transform (NTT) module applies the NTT to perform multiplication operations, converting polynomial convolution into point-value multiplication.

[0053] The basic computing module utilizes the parallel computing capabilities of the GPU to accelerate homomorphic addition, homomorphic multiplication, homomorphic rotation, key switching, and rescaling operations in homomorphic encryption.

[0054] The advanced computation module implements complex homomorphic operations based on basic computations, including matrix-vector multiplication and convolution in neural networks.

[0055] In this embodiment, optionally, the plaintext data in the data encoding and encryption module includes neural network convolutional kernel parameters and fully connected layer parameters. Specifically, different encoding methods are designed for large-batch and small-batch user input. In the scenario of large-batch data, image pixels at the same position in a batch are packaged into a single ciphertext, and the corresponding convolutional kernel parameters and fully connected layer parameters encode an element, which is used to broadcast the operation to all batches; in the scenario of small-batch data, all data is packaged into a single ciphertext, and the corresponding convolutional kernel parameters and fully connected layer parameters encode all elements. The large-batch encoding method is suitable for scenarios with high effective bandwidth requirements, while the small-batch encoding method is suitable for scenarios with latency requirements.

[0056] In this embodiment, optionally, the Chinese Remainder Theorem module includes:

[0057] In the decomposition stage, the coefficients of the polynomial are moduloed by different moduli, and the remainders are stored in different addresses.

[0058] During the synthesis phase, multiple residuals are synthesized using Mixed Radix Conversion (MRC). These residuals are first stored in registers, and communication overhead is reduced between different GPU threads through a thread bundle shuffling mechanism.

[0059] Figure 1 The diagram illustrates an MRC data dependency graph, with the remainder representation at the top and the mixed radix representation at the bottom. To fully utilize the parallel computing capabilities of GPUs, this invention assigns a thread to each vertical data stream in the graph, while communication between horizontal data streams employs a thread bundle shuffling mechanism. Considering the characteristics of thread bundle execution—that threads within a bundle perform the same operation simultaneously—synchronization is unnecessary as long as the size of the thread bundle exceeds the number of radixes in the mixed radix representation. Since the number of moduli required for homomorphic encryption is generally smaller than the thread bundle size, synchronization operations are avoided.

[0060] In this embodiment, optionally, the fast number theory transformation module includes the following steps:

[0061] Step 1: Convert the one-dimensional NTT to a two-dimensional NTT. First, perform NTT on the columns and then on the rows. Each operation is implemented by a kernel function.

[0062] Step 2: Each time the kernel function is started, the data in global memory is copied to shared memory, and shared memory is used instead of direct access to global memory;

[0063] Step 3: In the last five rounds of the butterfly transformation, data exchange within the same thread bundle is achieved through thread bundle shuffling to optimize communication efficiency.

[0064] The N-point NTT is divided into log N stages by the butterfly transformation. In the basic GPU implementation of the NTT algorithm, each thread requires O(log N) global memory accesses, which leads to significant memory access overhead. A common optimization strategy is to transfer data from global memory to shared memory. However, the scope of shared memory is limited to the thread block level, and current GPU architectures limit the number of threads per thread block to a maximum of 1024. Therefore, only Radix-2 NTTs with a maximum of 2048 points can be processed. For NTTs with higher point counts, multiple kernel functions must be used, resulting in significant global memory access overhead. Therefore, before executing step two, this invention divides the one-dimensional NTT into a two-dimensional NTT, where the number of points in each dimension is less than 2048, so that in step two, all data in one dimension can be accessed using shared memory. The grouping method is as follows: Figure 2 As shown.

[0065] Similar to the optimization of the large number arithmetic decomposition module, this invention again uses thread bundle shuffling optimization to improve memory access efficiency and reduce synchronization. Another benefit of this optimization is the avoidance of bank conflicts. Bank conflicts refer to the conflict that occurs when multiple threads within a thread bundle simultaneously access the same bank, as the shared memory is divided into 32 banks, each storing a consecutive 32 bits of data. During NTT execution, all threads in the thread bundle simultaneously read the elements of the butterfly transform. Bank conflicts do not occur when the step size in a round is greater than or equal to 32 (the bank size); however, when the step size is less than 32, conflicts occur because only 16 banks are used. To solve this problem, registers are used instead of shared memory in the last five stages of NTT, thereby eliminating bank conflicts.

[0066] To reduce synchronization overhead, this invention utilizes implicit synchronization within a thread bundle. In the last five stages of NTT, it can be decomposed into multiple 64-point NTT transformations, limiting data dependencies to within a single thread bundle and enabling intra-thread communication through thread bundle shuffling. Given that the NTT point range in homomorphic encryption is typically 2... 11 Up to 2 15 This implicit synchronization is highly advantageous. By optimizing the last five stages of NTT through thread bundle shuffling, this invention eliminates most of the synchronization.

[0067] In this embodiment, optionally, the basic operation module uses batch processing optimization technology to execute operations under multiple different moduli in a single kernel function, reducing the kernel function startup overhead. Specifically, this means that data under different moduli are converted into one thread and optimized using loop unrolling.

[0068] In this embodiment, optionally, the key switching operation involves inner product calculation and NTT transformation. To improve efficiency, the kernel functions for these two operations are merged into one, reducing communication between kernel functions. Specifically, key switching first requires switching the ciphertext from the NTT domain to the polynomial coefficient domain, then performing a modulo switch on the ciphertext, and finally switching the ciphertext back to the NTT domain to perform an inner product with the key. After the modulo switch, the data expands to several times the input size. To reduce the cost of data transmission, the data switched to the NTT domain is directly read by the inner product kernel function, thus reducing data transmission.

[0069] In this embodiment, optionally, the advanced computation module employs Big Step Small Step (BSGS) when performing matrix-vector multiplication to reduce reliance on homomorphic rotation operations. For example... Figure 3 As shown, specifically, in matrix-vector multiplication, the operation is decomposed into multiple multiplications of plaintext and rotated ciphertext. During rotation, only the ciphertext with a small step size is rotated, and the calculation results are accumulated before a larger step size rotation is performed.

[0070] In this embodiment, optionally, the advanced computing module uses stream processing technology to divide computational tasks without data conflicts into different computational streams for execution, thereby further improving the efficiency of parallel computing. For example... Figure 4 As shown, specifically, CUDA streaming optimizes batch encoding by parallelizing independent kernel functions across different streams. In fully connected layers and convolutional layers, the kernel functions associated with each result element are merged into a single stream to mask kernel startup latency.

[0071] The technical effects of the present invention were further verified through experiments. The experiments consisted of four parts, each verifying the following:

[0072] The optimization effect of thread-beam shuffling technology on the Chinese Remainder Theorem module and NTT module.

[0073] The optimization effect of batch processing and kernel fusion optimization method on basic computing module.

[0074] Performance comparison of this invention with other open-source libraries.

[0075] Performance comparison of this invention in neural network inference applications.

[0076] This invention compares the Chinese Remainder Theorem module and the Fast Number Theory Transformation module with baselines, both of which benefit from optimizations based on thread bundle shuffling. Table 1 shows a comparison between the implementation of the inverse Chinese Remainder Theorem and HE-Booster, which processes all residues in a single thread. Experimental results demonstrate the significant advantages of the method presented in this invention, particularly with smaller parameters, namely the polynomial length N and the number of moduli L. This indicates substantial room for improvement in GPU utilization. This method enhances computational efficiency by improving GPU utilization. Although this method requires additional synchronization operations, this invention eliminates the overhead of synchronization through implicit thread synchronization within the thread bundle.

[0077] Table 1 Performance of the Chinese Remainder Theorem Module

[0078]

[0079] As shown in Table 2, in Scheme I, this invention uses shared memory instead of global memory, restricting global memory access to the beginning and end of each kernel function. This contrasts with the baseline method, which requires interaction with global memory on each iteration. Therefore, the advantages of this optimization become increasingly apparent as the number of NTT points and iterations increases. In Scheme II, this invention further introduces a 2D NTT transition, reducing the number of kernel startups and further reducing global memory accesses, thereby significantly improving performance. In Scheme III, this invention further uses registers instead of shared memory and uses thread bundle shuffling for communication, reducing synchronization operation time and avoiding memory bank conflicts.

[0080] Figure 5 and Figure 6 The unoptimized inner product (IP), kernel 1 (K1), and kernel 2 (K2) were analyzed, along with the batch-optimized kernel (K1-Opt) and kernel fusion (K2-Opt). The optimized kernels showed a significant improvement in utilization, primarily due to batch processing. The unoptimized inner product exhibited a large imbalance in memory usage, which was mitigated by kernel fusion, achieving a balance between memory and stream processor (SM) utilization.

[0081] As shown in Table 3, GPU acceleration does not significantly improve homomorphic addition because these operations are independent of NTT and INTT and are not affected by NTT optimization. However, relinearization and rotation operations show significant acceleration due to frequent transitions between the NTT and INTT domains. Kernel fusion and batch processing methods further reduce the computational overhead of these operations. As shown in Table 3, the method of this invention exhibits superior performance under the same GPU model.

[0082] Table 2 Performance of the Fast Number Theory Transform Module

[0083]

[0084] Table 3 Comparison of homomorphic encryption operation performance

[0085]

[0086]

[0087] Table 4. Performance of Convolutional Neural Networks in Different Batches

[0088]

[0089] To evaluate the practical usability of the proposed algorithm, this invention implements a Convolutional Neural Network (CNN) and designs a CNN based on the Cryptotonet architecture. The CNN of this invention comprises one convolutional layer and two fully connected layers, using a squared function as the activation function. The convolutional layer uses zero padding, a stride of 1, and a filter size of (5×5,1). The fully connected layers are configured as (784,64) and (64,10). The model is pre-trained using PyTorch on the MNIST dataset, and experiments on inference applications of this invention are conducted for different batch sizes.

[0090] In large-batch scenarios, this invention encapsulates one pixel of 4096 images into a single ciphertext, with a transmitted ciphertext size of 367.5 MB (28*28*2*8192*240 bits). In small-batch scenarios, this invention encapsulates eight data blocks into a single ciphertext, with a transmitted ciphertext size of 1.56 MB (2*16384*400 bits). The results show that for smaller input data sizes, small-batch processing effectively reduces the number of homomorphic operations (HOPs). Table 4 provides a comparative analysis with existing methods. For small-batch encoding, the average inference time is 1.88 milliseconds per inference. In large-batch processing, streaming processing significantly improves efficiency, reducing the inference time for a batch of data to less than one second.

[0091] In summary, the method proposed in this invention significantly improves stream processing efficiency for large-scale batch processing. Simulation experiments and practical applications have verified the technical effects and practicality claimed by this invention.

[0092] The algorithm (method) proposed in this invention is the underlying technical core of this invention, and various products can be derived based on the algorithm.

[0093] Based on the algorithm (method) proposed in this invention, a GPU acceleration system for homomorphic encryption technology is developed using a programming language. This system has program modules corresponding to the steps of the above-mentioned technical solution, and executes the steps in the above-mentioned GPU acceleration method for homomorphic encryption technology when running.

[0094] The developed system (software) computer program is stored on a computer-readable storage medium, and the computer program is configured to implement the steps of the aforementioned GPU-accelerated method for homomorphic encryption when invoked by a processor. In other words, the invention is materialized on a carrier, becoming a computer program product.

[0095] The present invention also provides a GPU acceleration device for homomorphic encryption technology, the device comprising at least one processor and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to execute the aforementioned GPU acceleration method for homomorphic encryption technology.

[0096] Various implementations of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, application-specific integrated circuits (ASICs), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include: implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0097] The computational programs (also referred to as programs, software, software applications, or code) of this invention include machine instructions of a programmable processor and can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, device, and / or apparatus (e.g., disk, optical disk, memory, programmable logic device PLD) for providing machine instructions and / or data to a programmable processor, including machine-readable media that receive machine instructions as machine-readable signals. The term "machine-readable signal" refers to any signal for providing machine instructions and / or data to a programmable processor.

[0098] It should be understood that the various processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, all of which are within the protection scope of this invention. Although the invention has been described with respect to a limited number of embodiments, those skilled in the art will understand from the above description that other embodiments can be conceived within the scope of the invention described herein. The disclosure of the invention is illustrative and not restrictive, and the scope of the invention is defined by the appended claims.

Claims

1. A GPU-accelerated method for homomorphic encryption technology, characterized in that, include: The data encoding and encryption steps involve preprocessing and encoding plaintext data in floating-point form, converting the plaintext data into a homomorphic encrypted polynomial form, and then encrypting the encoded data. The steps of large number decomposition are to apply the Chinese Remainder Theorem (CRT) to decompose large number operations into parallel operations under multiple small moduli, so as to utilize the multi-threaded architecture of the GPU to execute the decomposed fractional operations. The steps of the Fast Number Theory Transform (NTT) are to perform multiplication operations by applying the NTT to convert polynomial convolution into point-value multiplication. The fast number theory transformation includes the following steps: Step 1: Convert the one-dimensional NTT to a two-dimensional NTT. First, perform NTT on the columns and then on the rows. Each operation is implemented by a kernel function. Step 2: Each time the kernel function is started, the data in global memory is copied to shared memory, and shared memory is used instead of direct access to global memory; Step 3: In the last five rounds of the butterfly transformation, data exchange within the same thread bundle is achieved through thread bundle shuffling to optimize communication efficiency; The basic computation steps utilize the parallel computing capabilities of GPUs to accelerate homomorphic addition, homomorphic multiplication, homomorphic rotation, key switching, and rescaling operations in homomorphic encryption. Since key switching involves inner product calculation and NTT transformation, the kernel functions of these two are merged into one to reduce communication between kernel functions and improve efficiency. Advanced computation steps, based on basic operations to implement complex homomorphic operations, including matrix-vector multiplication and convolution in neural networks; The advanced operations employ big-small-big-steps (BSGS) when performing matrix-vector multiplication to reduce reliance on homomorphic rotation operations.

2. The GPU acceleration method for homomorphic encryption technology according to claim 1, characterized in that, The number The plaintext data in the encoding encryption includes neural network convolution kernel parameters and fully connected layer parameters.

3. A GPU acceleration method for homomorphic encryption technology according to claim 1 or 2, characterized in that, The steps of large number arithmetic decomposition include: In the decomposition stage, the coefficients of the polynomial are moduloed by different moduli, and the remainders are stored in different addresses. During the synthesis phase, multiple residuals are synthesized using Mixed Radix Conversion (MRC). These residuals are first stored in registers, and communication overhead is reduced between different GPU threads through a thread bundle shuffling mechanism.

4. The GPU acceleration method for homomorphic encryption technology according to claim 1, characterized in that, The basic operations are optimized through batch processing, which executes multiple operations under different moduli in a single kernel function, reducing the kernel function startup overhead.

5. The GPU acceleration method for homomorphic encryption technology according to claim 1, further characterized in that, The advanced computation uses stream processing technology to divide computational tasks without data conflicts into different computational streams for execution, thereby improving the efficiency of parallel computing.

6. A GPU-accelerated system for homomorphic encryption technology, characterized in that, include: The system has a program module corresponding to the steps in claim 1 above, and executes the steps in the GPU acceleration method for homomorphic encryption technology described above when running; The data encoding and encryption module preprocesses and encodes plaintext data in floating-point format, converting the plaintext data into... Homomorphic encryption in polynomial form, and encrypting the encoded data; The large number decomposition module applies the Chinese Remainder Theorem (CRT) to decompose large number operations into parallel operations under multiple small moduli, so as to utilize the multi-threaded architecture of the GPU to execute the decomposed fractional operations; The Fast Number Theory Transform (NTT) module applies the NTT to perform multiplication operations, converting polynomial convolution into point-value multiplication. The basic computing module utilizes the parallel computing capabilities of the GPU to accelerate homomorphic addition, homomorphic multiplication, homomorphic rotation, key switching, and rescaling operations in homomorphic encryption. The advanced computation module implements complex homomorphic operations based on basic computations, including matrix-vector multiplication and convolution in neural networks.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program configured to, when invoked by a processor, implement the steps of any one of claims 1-5, a GPU-accelerated method for homomorphic encryption.

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