Transistor layout method, device, storage medium and electronic device

Abstract

The present application discloses a transistor layout method, device, storage medium and electronic device, wherein the transistor layout method includes obtaining a standard cell layout; grouping transistors in the standard cell layout to obtain a number of initial transistor groups; using an intra-group layout algorithm to adjust the positions of transistors in each initial transistor group to obtain a number of target transistor groups; using an inter-group layout algorithm to adjust the positions of the target transistor groups to obtain a target transistor layout of the standard cell layout. This solution can improve the efficiency of transistor layout.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit technology, and specifically to a transistor layout method, device, storage medium, and electronic device. Background Art

[0002] At present, the design of application-specific integrated circuits (ASICs) generally adopts a method based on standard cell libraries to improve design efficiency and reliability. However, with the increasing complexity of integrated circuits and technological advances, the number of required standard cells has increased significantly, resulting in frequent and complex updates to the cell library, especially when the process size is reduced, and the cell layout needs to be redesigned. This makes it unrealistic to manually maintain a large and constantly changing cell library.

[0003] To solve this problem, standard cell layout automatic generation technology came into being, which can automatically generate layout based on transistor-level netlist and design rules, ensure correctness and compactness, and reduce manual intervention. This automated tool greatly shortens the design time and ensures compliance with design rules. However, the optimization of cell layout, especially when considering area optimization, is still challenging.

[0004] The automatic generation process of standard cell layout is usually divided into three main steps: transistor layout, cell internal wiring and layout compression. Each step aims to achieve efficient layout and optimization that meets design requirements. Among them, transistor layout is the first link in the design process, which directly affects the smooth progress of subsequent steps and the performance of the final product. Therefore, how to improve the efficiency of transistor layout is an urgent problem to be solved in this field. Summary of the invention

[0005] The embodiments of the present application provide a transistor layout method, device, storage medium and electronic device, which can improve the efficiency of transistor layout.

[0006] In a first aspect, an embodiment of the present application provides a transistor layout method, including:

[0007] Get the standard cell layout;

[0008] Grouping transistors in the standard cell layout to obtain a number of initial transistor groups;

[0009] Using an intra-group layout algorithm to adjust the positions of the transistors in each of the initial transistor groups to obtain a plurality of target transistor groups;

[0010] The positions of the target transistor groups are adjusted by using an inter-group layout algorithm to obtain a target transistor layout of the standard cell layout.

[0011] In the transistor layout method provided in the embodiment of the present application, the position of the transistors in each of the initial transistor groups is adjusted by using the intra-group layout algorithm to obtain a plurality of target transistor groups, including:

[0012] Initializing the positions of the transistors in each of the initial transistor groups to obtain an initial transistor layout for each of the initial transistor groups;

[0013] A simulated annealing algorithm is used to adjust each of the initial transistor layouts to obtain a plurality of target transistor groups.

[0014] In the transistor layout method provided in the embodiment of the present application, the position of the transistors in each of the initial transistor groups is adjusted by using the intra-group layout algorithm to obtain a plurality of target transistor groups, including:

[0015] Based on the transistors in each of the initial transistor groups, a decision tree is constructed using a branch and bound algorithm;

[0016] Each node of the decision tree is traversed to gradually determine the position of each transistor in each initial transistor group to obtain a plurality of target transistor groups.

[0017] In the transistor layout method provided in the embodiment of the present application, traversing each node of the decision tree includes:

[0018] Based on the pruning strategy, each node of the decision tree is traversed.

[0019] In the transistor layout method provided in the embodiment of the present application, the positions of the target transistor groups are adjusted by using an inter-group layout algorithm to obtain the target transistor layout of the standard cell layout, including:

[0020] Constructing a cost function, the cost function comprising a layout width function, a routability function, and a pin accessibility function;

[0021] generating an initial layout between the groups according to the connection relationship between the target transistor groups;

[0022] The initial layout between the groups is adjusted using a Pareto optimal algorithm so that the value of the cost function is an optimal solution, thereby obtaining a target transistor layout of the standard cell layout.

[0023] In the transistor layout method provided in the embodiment of the present application, the use of the Pareto optimal algorithm to adjust the initial layout between groups includes:

[0024] The Pareto optimal algorithm is combined with a dynamic programming algorithm and a pruning strategy to adjust the initial layout between the groups.

[0025] In the transistor layout method provided in the embodiment of the present application, the transistors in the standard cell layout are grouped to obtain a plurality of initial transistor groups, including:

[0026] Scanning the standard cell layout to identify electrical connection relationships among a plurality of transistors in the standard cell layout;

[0027] The transistors are grouped according to the electrical connection relationship to obtain a plurality of initial transistor groups.

[0028] In a second aspect, an embodiment of the present application provides a transistor layout device, including:

[0029] A layout acquisition unit, used to acquire a standard cell layout;

[0030] A layout grouping unit, used for grouping transistors in the standard cell layout to obtain a plurality of initial transistor groups;

[0031] An intra-group layout unit, used for adjusting the positions of the transistors in each of the initial transistor groups by using an intra-group layout algorithm to obtain a plurality of target transistor groups;

[0032] The inter-group layout unit is used to adjust the positions of the target transistor groups by using an inter-group layout algorithm to obtain the target transistor layout of the standard cell layout.

[0033] In a third aspect, the present application provides a storage medium storing a plurality of instructions, wherein the instructions are suitable for loading by a processor to execute any of the above-mentioned transistor layout methods.

[0034] In a fourth aspect, the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above-described transistor layout methods when executing the computer program.

[0035] In summary, the transistor layout method provided in the embodiment of the present application includes obtaining a standard cell layout; grouping the transistors in the standard cell layout to obtain a number of initial transistor groups; using an intra-group layout algorithm to adjust the positions of the transistors in each of the initial transistor groups to obtain a number of target transistor groups; using an inter-group layout algorithm to adjust the positions of the target transistor groups to obtain a target transistor layout of the standard cell layout. This solution first groups the transistors in the standard cell layout, then optimizes the positions of the transistors in each initial transistor group by an intra-group layout algorithm, and optimizes the positions of the target transistor groups by an inter-group layout algorithm, automatically generates a target transistor layout of the standard cell layout, reduces manual intervention, and thus improves the efficiency of transistor layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 It is a schematic diagram of an application scenario of the transistor layout method provided in an embodiment of the present application.

[0038] Figure 2 It is a flow chart of the transistor layout method provided in an embodiment of the present application.

[0039] Figure 3 It is a structural schematic diagram of a transistor layout device provided in an embodiment of the present application.

[0040] Figure 4 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0042] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0043] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0044] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application, and have no specific meanings. Therefore, "module", "component" or "unit" can be used in a mixed manner.

[0045] In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, terms such as "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0046] The automatic generation process of standard cell layout is usually divided into three main steps: transistor layout, cell internal wiring and layout compression. Each step aims to achieve efficient layout and optimization that meets design requirements. Among them, transistor layout is the first link in the design process, which directly affects the smooth progress of subsequent steps and the performance of the final product. Therefore, how to improve the accuracy and efficiency of transistor layout is an urgent problem to be solved in this field.

[0047] Based on this, the embodiments of the present application provide a transistor layout method, device, storage medium and electronic device. Specifically, the transistor layout device can be integrated in an electronic device, and the electronic device can be a server or a terminal. Among them, the terminal can include a mobile phone, a wearable smart device, a tablet computer, a laptop computer, and a personal computer (PC), etc.; the server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0048] For example, Figure 1 As shown, after obtaining the standard cell layout, the electronic device can first group the transistors in the standard cell layout to obtain several initial transistor groups; then use the intra-group layout algorithm to adjust the positions of the transistors in each of the initial transistor groups to obtain several target transistor groups; finally, use the inter-group layout algorithm to adjust the positions of the several target transistor groups to obtain the target transistor layout of the standard cell layout.

[0049] The technical solutions shown in the present application will be described in detail below through specific embodiments. It should be noted that the description order of the following embodiments is not intended to limit the priority order of the embodiments.

[0050] See also Figure 2 , Figure 2 : is a schematic diagram of a flow chart of a transistor layout method provided in an embodiment of the present application. The specific flow of the transistor layout method can be as follows:

[0051] 101. Obtain the standard cell layout.

[0052] Standard cell layout is a basic building block commonly used in integrated circuit design, mainly used for the implementation of digital circuits. Each standard cell usually contains a logic function (such as an AND gate, an OR gate, a trigger, etc.), and these standard cells have a uniform size and interface in the physical layout, so as to facilitate efficient arrangement and connection on the chip.

[0053] 102. Group the transistors in the standard cell layout to obtain a number of initial transistor groups.

[0054] Specifically, the standard cell layout is scanned to identify the electrical connection relationship of a number of transistors in the standard cell layout; the number of transistors are grouped according to the electrical connection relationship to obtain a number of initial transistor groups.

[0055] In some embodiments, a depth-first search (DFS) or breadth-first search (BFS) algorithm may be used to traverse the standard cell layout, identify the electrical connection relationship of several transistors in the standard cell layout, and obtain several interconnected transistor blocks. These interconnected transistor blocks may be referred to as CCBs (Channel Connected Blocks).

[0056] Afterwards, the transistors are grouped according to the CCB to obtain a number of initial transistor groups. In some embodiments, the transistors in each CCB can be grouped as a group to form a number of initial transistor groups.

[0057] It can be understood that the transistors of each initial transistor group are connected to each other, and there may be a connection relationship between the initial transistor groups.

[0058] 103. Use an intra-group layout algorithm to adjust the positions of transistors in each initial transistor group to obtain a plurality of target transistor groups.

[0059] The intra-group layout algorithm may be a simulated annealing algorithm. In some embodiments, the positions of transistors in each initial transistor group may be initialized to obtain an initial transistor layout for each initial transistor group; and then each initial transistor layout may be adjusted using a simulated annealing algorithm to obtain a number of target transistor groups.

[0060] A cost function may be constructed first. It should be noted that the cost function may be constructed according to actual conditions, including but not limited to the following cost function.

[0061] For example, the cost function Cost can be as follows:

[0062] Cost=α·Width+β·Height+γ·Routing Difficulty

[0063] Among them, Width is the width of the layout, and the goal is to minimize it. Height is the height of the layout, and the goal is to minimize it. Routing Difficulty is the routing difficulty, expressed as the distance between network terminals, and the goal is to minimize it. α, β, and γ are weight coefficients that can be adjusted according to design requirements.

[0064] Then, the positions of all transistors in the initial transistor group are randomly arranged to obtain the initial transistor layout, and the cost function value of the initial transistor layout is calculated. Then, based on the initial transistor layout, the transistor positions are perturbed to generate a new transistor layout. In actual application, the perturbation of the transistor positions can be achieved through moving operations, swapping operations, and direction adjustments. For example, you can randomly select a transistor and change its position, or randomly select two transistors, swap their positions, or change the direction of the transistor (such as rotating 180 degrees). It should be noted that each time a new transistor layout is generated, its cost function value needs to be calculated. Afterwards, the cost function value of the initial transistor layout is compared with the cost function value of the new transistor layout. Determine whether to accept the new solution based on the Metropolis criterion. If the cost of the new solution is lower than the current solution, it is directly accepted. If the cost of the new solution is higher, it is accepted with a certain probability, and the probability is determined by the annealing temperature: P = e -ΔE / T , where ΔE is the cost increase and T is the current annealing temperature.

[0065] As the algorithm iterates, the temperature is gradually lowered to reduce large disturbances. When the maximum number of iterations is reached or the temperature is lower than the threshold, the algorithm is stopped and the optimal solution is returned. The Metropolis criterion achieves a dynamic balance between global search and local convergence by judging ΔE and combining the acceptance mechanism of random probability. It effectively avoids falling into the local optimum and finds the global optimal solution.

[0066] The intra-group layout algorithm may be a branch and bound algorithm. In some embodiments, a decision tree may be constructed based on transistors in each initial transistor group using a branch and bound algorithm; each node of the decision tree is then traversed to gradually determine the position of each transistor in each initial transistor group to obtain a number of target transistor groups.

[0067] In some embodiments, each node of the decision tree may be traversed based on a pruning strategy.

[0068] In this decision tree, each node represents a layout state, and each layer represents the layout selection of a transistor. The root node represents the initial state, and the child node represents the layout result of adding a transistor in the current state. In actual application, the cost function (width cost function) of the current layout can be calculated at each node separately. If the cost value of the current node is higher than the optimal solution currently found, it is directly pruned and further search for the branch is stopped to avoid in-depth search. After the traversal is completed, the layout solution with the lowest cost value is returned to obtain the target transistor group.

[0069] 104. Use an inter-group layout algorithm to adjust the positions of several target transistor groups to obtain a target transistor layout of a standard cell layout.

[0070] Specifically, a cost function can be constructed first, which includes a layout width function, a routability function, and a pin accessibility function. Then, an initial layout between groups is generated according to the connection relationship between several target transistor groups; finally, the initial layout between groups is adjusted using a Pareto Optimality algorithm so that the value of the cost function is the optimal solution, and the target transistor layout of the standard cell layout is obtained.

[0071] The layout width function is the lateral distance between the leftmost transistor and the rightmost transistor in the standard cell layout. A smaller width can effectively reduce the area of ​​the standard cell.

[0072] Among them, the routability function can be as follows:

[0073]

[0074] Among them, NETS: represents all the networks (Net) in the standard cell. Each network consists of multiple transistor endpoints (network terminals) connected together. n∈NETS: represents traversing all networks n. M n : represents the set of all terminals in network n. and They respectively represent the horizontal position coordinates of terminal i and terminal j in network n.

[0075] The routability function indicates that for each network n, the maximum horizontal span in its terminal is calculated, and then the maximum spans of all networks are summed to measure the overall routing cost. Good routability can effectively reduce the difficulty of subsequent routing steps, optimize network connections between groups, reduce long lines and crossovers, and reduce routing complexity.

[0076] Among them, the pin access function can be as follows:

[0077]

[0078] Where, PINS: represents all pins in the standard unit. n∈PINS: represents traversing all pins n. n : Indicates the standard unit where pin n is located. Indicates the horizontal position coordinate of pin n. left: Indicates the left boundary coordinate of the standard cell. right: Indicates the right boundary coordinate of the standard cell.

[0079] The pin accessibility function indicates that for each pin, the shortest distance to the left and right boundaries of the standard cell is calculated, and then the minimum distances of all pins are summed to measure the access convenience cost of the pin layout.

[0080] The Pareto optimal solution algorithm can optimize layout width, routability and pin access simultaneously, finding a balance between multiple goals to ensure that no improvement in one goal will lead to a significant deterioration in other goals.

[0081] In some embodiments, the Pareto optimal algorithm may be combined with a dynamic programming algorithm and a pruning strategy to adjust the initial layout between groups.

[0082] For example, an initial layout between groups can be generated based on the connection relationship between several target transistor groups. Then the cost function value of the initial layout between groups is calculated. Then the dynamic programming algorithm is used to recursively optimize the position of each target transistor group to improve the layout cost. Convergence occurs when the maximum number of iterations or cost function is reached.

[0083] It should be noted that during the iteration process, if the current layout cost exceeds the known optimal solution, it will be directly pruned to avoid further search. The dynamic programming algorithm refers to storing intermediate calculation results to avoid repeated calculations. For example, if k groups of layouts have been completed, the optimal position of the k+ group can be calculated based on the layout of the first k groups.

[0084] In summary, the transistor layout method provided by the embodiment of the present application includes obtaining a standard cell layout; grouping the transistors in the standard cell layout to obtain several initial transistor groups; using the intra-group layout algorithm to adjust the positions of the transistors in each initial transistor group respectively to obtain several target transistor groups; using the inter-group layout algorithm to adjust the positions of several target transistor groups to obtain the target transistor layout of the standard cell layout. This scheme first groups the transistors in the standard cell layout, then optimizes the positions of the transistors in each initial transistor group by the intra-group layout algorithm, optimizes the positions of several target transistor groups by the inter-group layout algorithm, automatically generates the target transistor layout of the standard cell layout, reduces manual intervention, and thus improves the efficiency of transistor layout. In addition, through the multi-objective optimization method (Pareto optimal solution), the layout compactness, wiring feasibility and pin accessibility are optimized, the standard cell area is reduced, and the wiring success rate is improved. The layout results are highly consistent with the design rules and manufacturing requirements, significantly reducing manual intervention, and improving production yield and manufacturing reliability.

[0085] In order to better implement the transistor layout method provided in the embodiment of the present application, the embodiment of the present application also provides a transistor layout device, wherein the meanings of the terms are the same as those in the above transistor layout method, and the specific implementation details can refer to the description in the method embodiment.

[0086] See also Figure 3 , Figure 3 2 is a schematic diagram of the structure of a transistor layout device provided in an embodiment of the present application. The transistor layout device may include a layout acquisition unit 201, a layout grouping unit 202, an intra-group layout unit 203, and an inter-group layout unit 204.

[0087] A layout acquisition unit 201 is used to acquire a standard cell layout;

[0088] A layout grouping unit 202 is used to group transistors in the standard cell layout to obtain a number of initial transistor groups;

[0089] An intra-group layout unit 203, used to adjust the positions of transistors in each initial transistor group respectively by using an intra-group layout algorithm to obtain a plurality of target transistor groups;

[0090] The inter-group layout unit 204 is used to adjust the positions of several target transistor groups by using an inter-group layout algorithm to obtain a target transistor layout of a standard cell layout.

[0091] The specific implementation of each of the above units can refer to the above-mentioned embodiment of the transistor layout method, which will not be described one by one here.

[0092] In summary, the transistor layout device provided in the embodiment of the present application can obtain the standard cell layout through the layout acquisition unit 201; the layout grouping unit 202 groups the transistors in the standard cell layout to obtain a number of initial transistor groups; the intra-group layout unit 203 uses the intra-group layout algorithm to adjust the positions of the transistors in each initial transistor group respectively to obtain a number of target transistor groups; the inter-group layout unit 204 uses the inter-group layout algorithm to adjust the positions of the several target transistor groups to obtain the target transistor layout of the standard cell layout. This solution first groups the transistors in the standard cell layout, then optimizes the positions of the transistors in each initial transistor group through the intra-group layout algorithm, and optimizes the positions of the several target transistor groups through the inter-group layout algorithm, automatically generates the target transistor layout of the standard cell layout, reduces manual intervention, and thus improves the efficiency of transistor layout.

[0093] The present application also provides an electronic device, in which the transistor layout device of the present application can be integrated, such as Figure 4 As shown, it shows a schematic diagram of the structure of the electronic device involved in the embodiment of the present application, specifically:

[0094] The electronic device may include one or more processors 301 of processing cores and one or more computer-readable storage media memories 302 and other components. Those skilled in the art will appreciate that Figure 4 The electronic device structure shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0095] The processor 301 is the control center of the electronic device, which uses various interfaces and lines to connect various parts of the entire electronic device, and executes various functions of the electronic device and processes data by running or executing the software program and / or the present application stored in the memory 302, and calling the data stored in the memory 302, so as to monitor the electronic device as a whole. Optionally, the processor 301 may include one or more processing cores; preferably, the processor 301 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operation storage medium, user interface and application program, etc., and the modem processor mainly processes wireless communication. It is understandable that the above-mentioned modem processor may not be integrated into the processor 301.

[0096] The memory 302 can be used to store software programs and the present application. The processor 301 executes various functional applications and data processing by running the software programs and the present application stored in the memory 302. The memory 302 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating storage medium, an application required for at least one function, etc.; the data storage area may store data created according to the use of the electronic device, etc. In addition, the memory 302 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices. Accordingly, the memory 302 may also include a memory controller to provide the processor 301 with access to the memory 302.

[0097] Although not shown, the electronic device may further include a display unit, an input unit, a power supply, etc., which will not be described in detail herein. Specifically in this embodiment, the processor 301 in the electronic device will load the executable files corresponding to the processes of one or more application programs into the memory 302 according to the following instructions, and the processor 301 will run the application programs stored in the memory 302, thereby realizing various functions, as follows:

[0098] Get the standard cell layout;

[0099] Grouping transistors in the standard cell layout to obtain a number of initial transistor groups;

[0100] Using an intra-group placement algorithm to adjust the positions of transistors in each initial transistor group respectively, to obtain a plurality of target transistor groups;

[0101] The positions of several target transistor groups are adjusted by using an inter-group placement algorithm to obtain a target transistor layout of a standard cell layout.

[0102] A person of ordinary skill in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be completed by instructions, or by controlling related hardware through instructions. The instructions may be stored in a computer-readable storage medium and loaded and executed by a processor.

[0103] To this end, an embodiment of the present application provides a storage medium in which a plurality of instructions are stored, and the instructions can be loaded by a processor to execute the steps in any one of the generation methods provided in the embodiment of the present application. For example, the instructions can execute the following steps:

[0104] Get the standard cell layout;

[0105] Grouping transistors in the standard cell layout to obtain a number of initial transistor groups;

[0106] Using an intra-group placement algorithm to adjust the positions of transistors in each initial transistor group respectively, to obtain a plurality of target transistor groups;

[0107] The positions of several target transistor groups are adjusted by using an inter-group placement algorithm to obtain a target transistor layout of a standard cell layout.

[0108] The specific implementation of the above operations can be found in the previous embodiments, which will not be described in detail here.

[0109] The storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0110] Since the instructions stored in the storage medium can execute the steps in any method provided in the embodiments of the present application, the beneficial effects that can be achieved by any method provided in the embodiments of the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0111] The transistor layout method, device, storage medium and electronic device provided by the present application are respectively introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the core idea of ​​the present application; at the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A transistor layout method, characterized in that: include: Get the standard cell layout; Grouping transistors in the standard cell layout to obtain a number of initial transistor groups; Using an intra-group layout algorithm to adjust the positions of the transistors in each of the initial transistor groups to obtain a plurality of target transistor groups; The positions of the target transistor groups are adjusted by using an inter-group layout algorithm to obtain a target transistor layout of the standard cell layout.

2. The transistor layout method according to claim 1, wherein: The adopting of the intra-group layout algorithm to adjust the positions of the transistors in each of the initial transistor groups to obtain a plurality of target transistor groups includes: Initializing the positions of the transistors in each of the initial transistor groups to obtain an initial transistor layout for each of the initial transistor groups; A simulated annealing algorithm is used to adjust each of the initial transistor layouts to obtain a plurality of target transistor groups.

3. The transistor layout method according to claim 1, wherein: The adopting of the intra-group layout algorithm to adjust the positions of the transistors in each of the initial transistor groups to obtain a plurality of target transistor groups includes: Based on the transistors in each of the initial transistor groups, a decision tree is constructed using a branch and bound algorithm; Each node of the decision tree is traversed to gradually determine the position of each transistor in each initial transistor group to obtain a plurality of target transistor groups.

4. The transistor layout method according to claim 3, characterized in that: The traversing each node of the decision tree comprises: Based on the pruning strategy, each node of the decision tree is traversed.

5. The transistor layout method according to claim 1, wherein: The step of adjusting the positions of the target transistor groups by using an inter-group layout algorithm to obtain a target transistor layout of the standard cell layout includes: Constructing a cost function, the cost function comprising a layout width function, a routability function, and a pin accessibility function; generating an initial layout between the groups according to the connection relationship between the target transistor groups; The initial layout between the groups is adjusted using a Pareto optimal algorithm so that the value of the cost function is an optimal solution, thereby obtaining a target transistor layout of the standard cell layout.

6. The transistor layout method according to claim 5, characterized in that: The using of the Pareto optimal algorithm to adjust the initial layout between the groups includes: The Pareto optimal algorithm is combined with a dynamic programming algorithm and a pruning strategy to adjust the initial layout between the groups.

7. The transistor layout method according to claim 1, wherein: The transistors in the standard cell layout are grouped to obtain a plurality of initial transistor groups, including: Scanning the standard cell layout to identify electrical connection relationships among a plurality of transistors in the standard cell layout; The transistors are grouped according to the electrical connection relationship to obtain a plurality of initial transistor groups.

8. A transistor layout device, characterized in that: include: A layout acquisition unit, used to acquire a standard cell layout; A layout grouping unit, used for grouping transistors in the standard cell layout to obtain a plurality of initial transistor groups; An intra-group layout unit, used for adjusting the positions of the transistors in each of the initial transistor groups by using an intra-group layout algorithm to obtain a plurality of target transistor groups; The inter-group layout unit is used to adjust the positions of the target transistor groups by using an inter-group layout algorithm to obtain the target transistor layout of the standard cell layout.

9. A storage medium, characterized in that: The storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor to execute the transistor layout method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the transistor layout method according to any one of claims 1 to 7 is implemented.

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