Control Circuit of Resistive Random Access Memory Array and Resistive Random Access Memory

Abstract

The present application relates to a control circuit for a resistive random access memory (RRAM) array and a resistive random access memory. The control circuit includes a gating module, a controller, and a readout circuit. The gating module includes a logic control circuit and a multi-stage transmission gate circuit connected to each other. The logic control circuit, based on a plurality of read / write control signals and an address signal output by the controller, sends corresponding secondary switch signal pairs to the multi-stage transmission gate circuit, and controls the connection or disconnection between a target memory cell corresponding to the address signal and the readout circuit. The multi-stage transmission gate circuit, based on the secondary switch signal pairs and the plurality of read / write control signals, applies a corresponding input voltage to the target memory cell, and the input voltage is determined from a plurality of preset voltages received by the multi-stage transmission gate circuit. The readout circuit, when connected to the target memory cell, reads the current value output by the target memory cell, thereby solving the problem of a relatively large occupied area of the peripheral circuit.

Description

Technical Field

[0001] This application relates to the field of microelectronics technology, and particularly to a control circuit for a resistive random access memory array and a resistive random access memory. Background Art

[0002] As a new type of computing device that integrates memory and computing, a resistive random access memory (RRAM) has the advantages of low power consumption, high speed, and compatibility with complementary metal oxide semiconductor (CMOS) processes. Its resistance value can be programmed by voltage, and after the excitation voltage is removed, its resistance value is still stored for a long time, showing non-volatile characteristics. RRAM also has the advantages of small size and high integration density, showing significant advantages compared with other new types of computing devices that integrate memory and computing. The peripheral circuit of the resistive random access memory is relatively complex. For a 1T1R type memory array, it is necessary to control the reading and writing of each memory cell in the memory array through word lines, bit lines, and source lines respectively. As the scale of the memory array expands, its peripheral circuit occupies a large area, reducing the storage density per unit area.

[0003] Aiming at the problem of large area occupied by the peripheral circuit in the prior art, no effective solution has been proposed yet. Summary of the Invention

[0004] In this embodiment, a control circuit for a resistive random access memory array and a resistive random access memory are provided to solve the problem of large area occupied by the peripheral circuit in the related art.

[0005] In the first aspect, in this embodiment, a control circuit for a resistive random access memory array is provided. The control circuit includes a gating module connected to the resistive random access memory array, a controller, and a readout circuit connected to the gating module. The resistive random access memory array includes a plurality of memory cells. The gating module includes a logic control circuit and a multi-stage transmission gate circuit connected to each other.

[0006] Based on a plurality of read / write control signals and an address signal output by the controller, the logic control circuit sends corresponding pairs of secondary switch signals to the multi-stage transmission gate circuit, and controls the connection or disconnection between the target memory cell corresponding to the address signal and the readout circuit.

[0007] Based on the pairs of secondary switch signals and the plurality of read / write control signals, the multi-stage transmission gate circuit applies a corresponding input voltage to the target memory cell, and the input voltage is determined from a plurality of preset voltages received by the multi-stage transmission gate circuit.

[0008] When connected to the target memory cell, the readout circuit reads the current value output by the target memory cell.

[0009] In some embodiments, the multi-level transmission gate circuit includes a word line first-level transmission gate circuit and a word line second-level transmission gate circuit, the plurality of read / write control signals include a read control signal and a write control signal, and the word line first-level transmission gate circuit includes a first transmission gate and a second transmission gate.

[0010] Based on the write control signal, the word line first-level transmission gate circuit generates a pair of first-level switching signals for the first transmission gate to control the connection or disconnection of a preset word line write voltage signal to / from the word line second-level transmission gate circuit; and

[0011] Based on the read control signal, the word line first-level transmission gate circuit generates a pair of first-level switching signals for the second transmission gate to control the connection or disconnection of a preset word line read voltage signal to / from the word line second-level transmission gate circuit.

[0012] In some embodiments, the logic control circuit includes a word line logic control circuit, and the plurality of read / write control signals include an enable signal.

[0013] When the enable signal is at a low level, based on the pair of second-level switching signals, the word line second-level transmission gate circuit disconnects from the word line terminal of the target memory cell; and based on the pair of second-level switching signals, the word line logic control circuit controls the word line terminal of the target memory cell to be grounded.

[0014] When the enable signal and the address signal are both at a high level, based on the pair of second-level switching signals, the word line second-level transmission gate circuit resumes connection to the word line terminal of the target memory cell.

[0015] In some embodiments, the multi-level transmission gate circuit includes a bit line first-level transmission gate circuit and a bit line second-level transmission gate circuit, the plurality of read / write control signals include a set control signal and a reset control signal, and the bit line first-level transmission gate circuit includes a fourth transmission gate and a fifth transmission gate.

[0016] Based on the set control signal, the bit line first-level transmission gate circuit generates a pair of first-level switching signals for the fourth transmission gate to control the connection or disconnection of a preset bit line set voltage signal to / from the bit line second-level transmission gate circuit; and

[0017] Based on the reset control signal, the bit line first-level transmission gate circuit generates a pair of first-level switching signals for the fifth transmission gate to control the bit line second-level transmission gate circuit to be grounded or disconnected.

[0018] In some of these embodiments, the logic control circuit includes a bit line logic control circuit, and the multiple read / write control signals include an enable signal and a read control signal.

[0019] The bit line logic control circuit controls the connection or disconnection of a preset bit line read voltage signal to the bit line terminal of the target memory cell based on the read control signal, the enable signal, and the address signal.

[0020] The bit line logic control circuit generates the secondary switch signal pair based on the enable signal and the address signal.

[0021] In some of these embodiments, the multi-level transmission gate circuit includes a source line primary transmission gate circuit and a source line secondary transmission gate circuit. The multiple read / write control signals include a set control signal and a reset control signal. The source line primary transmission gate circuit includes a seventh transmission gate and an eighth transmission gate.

[0022] The source line primary transmission gate circuit generates a primary switch signal pair for the seventh transmission gate based on the set control signal to control the grounding or disconnection of the source line secondary transmission gate circuit; and

[0023] The source line primary transmission gate circuit generates a primary switch signal pair for the eighth transmission gate based on the reset control signal to control the connection or disconnection of a preset source line reset voltage signal to the source line secondary transmission gate circuit.

[0024] In some of these embodiments, the logic control circuit includes a source line logic control circuit, and the multiple read / write control signals include an enable signal, a read control signal, a set signal, and a reset signal.

[0025] The source line logic control circuit controls the connection or disconnection of the readout circuit to the source line terminal of the target memory cell based on the read control signal, the enable signal, and the address signal.

[0026] The source line logic control circuit generates the secondary switch signal pair based on the set signal, the reset signal, the enable signal, and the address signal.

[0027] In some of these embodiments, the control circuit further includes a digital-to-analog conversion circuit.

[0028] The digital-to-analog conversion circuit is configured to convert the voltage value output by the controller into a corresponding word line write voltage signal and output it to the multi-level transmission gate circuit.

[0029] In some of these embodiments, the readout circuit includes a current-to-voltage conversion circuit and an analog-to-digital conversion circuit.

[0030] The current-to-voltage circuit converts the current value output by the target storage unit into a corresponding voltage signal, and the analog-to-digital conversion circuit converts the voltage signal into a voltage value and sends it to the controller.

[0031] In a second aspect, a resistive random access memory is provided in this embodiment. The resistive random access memory includes a resistive memory array and a control circuit of the resistive memory array as described in the first aspect.

[0032] Compared with the related art, in the control circuit of the resistive memory array provided in this embodiment, the logic control circuit sends a corresponding pair of secondary switch signals to the multi-level transmission gate circuit based on multiple read / write control signals and address signals output by the controller. The multi-level transmission gate circuit applies a corresponding input voltage to the target storage unit based on the pair of secondary switch signals and the multiple read / write control signals to implement the read / write operation corresponding to the input voltage. The logic control circuit controls the connection or disconnection between the corresponding target storage unit and the readout circuit based on multiple read / write control signals and address signals. When the readout circuit is connected to the target storage unit, the readout circuit reads the current value output by the target storage unit, and the data read result is obtained through the current value when implementing the read operation. The control circuit realizes the gating of the word line, bit line, and source line, and the corresponding voltage input and current readout through the gating module, reducing the occupied area of the peripheral circuit and solving the problem of the large occupied area of the peripheral circuit.

[0033] The details of one or more embodiments of the present application are set forth in the following drawings and description, so that the other features, objects, and advantages of the present application become more comprehensible. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:

[0035] Figure 1 is a schematic structural diagram of the control circuit of the resistive memory array in some embodiments of the present application;

[0036] Figure 2 is a schematic connection diagram of the resistive memory array in some embodiments of the present application;

[0037] Figure 3 is a schematic connection diagram of the word line multi-level transmission gate circuit in some embodiments of the present application;

[0038] Figure 4 is a schematic connection diagram of the word line multi-level transmission gate circuit and the word line logic control circuit in some embodiments of the present application;

[0039] Figure 5 It is a connection schematic diagram of the bit line multi-level transmission gate circuit according to some embodiments of the present application;

[0040] Figure 6 It is a connection schematic diagram of the bit line multi-level transmission gate circuit and the bit line logic control circuit according to some embodiments of the present application;

[0041] Figure 7 It is a connection schematic diagram of the source line multi-level transmission gate circuit according to some embodiments of the present application;

[0042] Figure 8 It is a connection schematic diagram of the source line multi-level transmission gate circuit and the source line logic control circuit according to some embodiments of the present application;

[0043] Figure 9 It is a circuit connection schematic diagram of the digital-to-analog conversion circuit according to some embodiments of the present application;

[0044] Figure 10 It is a connection schematic diagram of the readout circuit according to some embodiments of the present application. Detailed implementation manners

[0045] To understand the purpose, technical solution and advantages of the present application more clearly, the present application will be described and explained below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0046] Unless otherwise defined, technical or scientific terms used in this application shall have the ordinary meanings as understood by those of ordinary skill in the technical field to which this application belongs. In this application, words such as "a", "an", "one", "the", "these", etc. do not indicate a limitation in quantity, and they can be singular or plural. The terms "including", "comprising", "having" and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent in these processes, methods, products or devices. The terms "connected", "coupled", etc. used in this application do not limit to physical or mechanical connections, but may include electrical connections, whether directly or indirectly. The term "plurality" used in this application means two or more. "And / or" describes the association relationship of associated objects and indicates that there can be three relationships. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. Usually, the character " / " indicates that the objects associated before and after are in an "or" relationship. The terms "first", "second", "third", etc. used in this application only distinguish similar objects and do not represent a specific order for the objects.

[0047] Figure 1 is a schematic structural diagram of a control circuit of a resistive random access memory (RRAM) array according to some embodiments of the present application. As Figure 1 shown, the control circuit of the RRAM array includes a gating module 20 connected to the RRAM array 40, and a controller 10 and a readout circuit 30 connected to the gating module 20; the RRAM array 40 includes a plurality of memory cells, and the gating module 20 includes a logic control circuit 22 and a multi-stage transmission gate circuit 24 connected to each other. Those of ordinary skill in the art can understand that Figure 1 the structure shown is only schematic and does not limit the structure of the control circuit of the RRAM array described above. For example, the control circuit may further include more or fewer components than Figure 1 shown, or may have a different configuration from Figure 1 shown.

[0048] Based on multiple read / write control signals and address signals output by the controller 10, the logic control circuit 22 sends corresponding secondary switch signal pairs to the multi-level transmission gate circuit 24, and controls the connection or disconnection between the target storage unit 401 corresponding to the address signal and the readout circuit 30. Based on the secondary switch signal pairs and the multiple read / write control signals, the multi-level transmission gate circuit 24 applies a corresponding input voltage to the target storage unit 401, and the input voltage is determined from multiple preset voltages received by the multi-level transmission gate circuit 24; when connected to the target storage unit 401, the readout circuit 30 reads the current value output by the target storage unit 401.

[0049] The resistive random access memory (RRAM) array in this embodiment may be a single-transistor single-resistance (1T1R) array. Figure 2 It is a connection schematic diagram of the RRAM array in some embodiments of the present application. As Figure 2 shown, the 1T1R array includes a total of (m + 1) × (n + 1) storage units. Each storage unit includes a transistor and a resistor. The transistor can isolate the selected storage unit from other unselected storage units. The word lines WL[0:m] are connected to the gates of the transistors, and adjusting the voltage of WL[0:m] can control the threshold current transmitted to the storage units. The drains of the transistors are connected to the bit lines BL[0:n] through resistors, and the sources of the transistors are connected to the source lines SL[0:n]. The operations on the 1T1R array generally include write operations and read operations, and the write operations include Set and Reset. Setting is setting to "1", and resetting is setting to "0".

[0050] In some embodiments, when performing the Set operation, the corresponding row is selected through the word lines WL[0:m] to turn on the corresponding transistors, and the corresponding Set voltage is applied to the bit lines BL[0:n] of the corresponding column while SL[0:n] is grounded; when performing the Reset operation, the corresponding row is selected through the word lines WL[0:m] to turn on the corresponding transistors, the bit lines BL[0:n] of the corresponding column are grounded, and the corresponding Reset voltage is applied to SL[0:n] of the corresponding column. For the unselected rows and columns, the corresponding WL, BL, and SL can all be grounded. The WL voltages corresponding to the Reset and Set operations can be the same. When performing the read operation, the corresponding row is selected through the word lines WL[0:m] to turn on the corresponding transistors, the corresponding read voltage is applied to BL[0:n] of the corresponding column, and at the same time SL[0:n] of the corresponding column is grounded. The current value is read by connecting the readout circuit to SL[0:n] of the corresponding column, and this current value can correspond to a high resistance state or a low resistance state.

[0051] The read / write control signals in this embodiment may include an enable signal, a read control signal during a read operation, and a write control signal, a set control signal, and a reset control signal during a write operation. The address signals may include a row address signal and a column address signal. Specifically, the read / write control signals and the address signals may be set to be active high. The pair of secondary switch signals is a pair of control signals, where one is at a high level and the other is at a low level.

[0052] When performing a read operation or a write operation, the controller 10 sends corresponding read / write control signals and address signals to the logic control circuit 22 and the multi-stage transmission gate circuit 24. The logic control circuit 22 determines the target memory cell 401 according to the read / write control signals and the address signals, and outputs a corresponding pair of secondary switch signals, which are sent to the multi-stage transmission gate circuit 24. The multi-stage transmission gate circuit 24 determines the input voltages of the WL, BL, and SL corresponding to the target memory cell 401 from the received multiple preset voltages according to the pair of secondary switch signals and the read / write control signals, and applies the input voltages to the WL, BL, and SL corresponding to the target memory cell 401 respectively, so as to complete the read operation or the write operation.

[0053] When performing a read operation, the logic control circuit 22 also controls the connection between the target memory cell 401 and the readout circuit 30 according to the read / write control signals and the address signals. When the readout circuit 30 is connected to the target memory cell 401, the readout circuit 30 reads the current value of the SL to obtain a data readout result. When not performing a read operation, the readout circuit 30 is in a disconnected state from the target memory cell 401.

[0054] The control circuit of the resistive memory array in this embodiment, through the logic control circuit, based on multiple read / write control signals and address signals output by the controller, sends a corresponding pair of secondary switch signals to the multi-stage transmission gate circuit. Through the multi-stage transmission gate circuit, based on the pair of secondary switch signals and the multiple read / write control signals, corresponding input voltages are applied to the target memory cell to implement the read / write operation corresponding to the input voltages; through the logic control circuit, based on multiple read / write control signals and address signals, the connection or disconnection between the corresponding target memory cell and the readout circuit is controlled. When the readout circuit is connected to the target memory cell, the readout circuit reads the current value output by the target memory cell, and when performing a read operation, the current value of the target memory cell is read by the readout circuit, and the data readout result is obtained through the current value; the control circuit realizes the gating of the word line, bit line, and source line and the corresponding voltage input and current readout through the gating module, reducing the occupied area of the peripheral circuit and solving the problem of the large occupied area of the peripheral circuit.

[0055] In some embodiments, Figure 3 is a connection schematic diagram of the word line multi-stage transmission gate circuit in some embodiments of the present application. As Figure 3As shown, the multi-level transmission gate circuit includes a first-level word line transmission gate circuit 2411 and a second-level word line transmission gate circuit 2412. The multiple read / write control signals include a read control signal READ and a write control signal WRITE. The first-level word line transmission gate circuit 2411 includes a first transmission gate T1 and a second transmission gate T2.

[0056] Based on the write control signal WRITE, the first-level word line transmission gate circuit 2411 generates a pair of first-level switch signals for the first transmission gate T1 to control the connection or disconnection between a preset word line write voltage signal VWLDAC and the second-level word line transmission gate circuit 2412. Based on the read control signal READ, the first-level word line transmission gate circuit 2411 generates a pair of first-level switch signals for the second transmission gate T2 to control the connection or disconnection between a preset word line read voltage signal VWLREAD and the second-level word line transmission gate circuit 2412.

[0057] Furthermore, the multi-level word line transmission gate circuit may further include a level shifter circuit. The level shifter circuit is used to perform voltage conversion on the input high-level signal or low-level signal to drive the first transmission gate T1 and the second transmission gate T2, but does not change the relative high and low levels of the signals. The second-level word line transmission gate circuit 2412 may include a transmission gate T3. Specifically, T1, T2, and T3 may be CMOS transmission gates. Specifically, when the first control terminal (positive phase terminal) of the CMOS transmission gate is at a high level and the second control terminal (inverse phase terminal) is at a low level, the input terminal and the output terminal are conducting; when the first control terminal (positive phase terminal) of the transmission gate is at a low level and the second control terminal (inverse phase terminal) is at a high level, the input terminal and the output terminal are disconnected.

[0058] Among them, the write control signal WRITE and the read control signal READ cannot be valid at the same time. When a write operation is performed, the write control signal WRITE is at a high level. After the write control signal WRITE and the corresponding inverse signal are level-shifted, they are used as the control signal for T1. The input terminal and the output terminal of T1 are conducting, and the word line write voltage signal VWLDAC is sent to the input terminal of the second-level word line transmission gate circuit 2412. At this time, the input terminal and the output terminal of T2 are disconnected.

[0059] Similarly, when a read operation is performed, the read control signal READ is at a high level. The input terminal and the output terminal of T2 are conducting, and the word line read voltage signal VWLREAD is sent to the input terminal of the second-level word line transmission gate circuit 2412. At this time, the input terminal and the output terminal of T1 are disconnected.

[0060] Further, the transmission gate T3 controls the conduction or disconnection between its input terminal and output terminal according to the pair of secondary switch signals sent by the word line logic control circuit, so as to control the application of the word line read voltage signal VWLREAD or the word line write voltage signal VWLDAC to the word line terminal of the target memory cell, realizing the selection of the target memory cell for read operation or write operation; and disconnecting the connection with the word line terminal of the memory cell when the memory cell is not selected.

[0061] The control circuit of the resistive memory array in this embodiment sends the corresponding word line read voltage signal or word line write voltage signal to the word line secondary transmission gate circuit during read operation and write operation respectively through the word line primary transmission gate circuit; and applies the word line read voltage signal or word line write voltage signal to the word line terminal of the target memory cell through the word line secondary transmission gate circuit, realizing the selection of the target memory cell for read operation or write operation, and realizing the selection and output of the word line voltage corresponding to different operations.

[0062] In some embodiments, Figure 4 is a schematic connection diagram of the word line multi-level transmission gate circuit and the word line logic control circuit in some embodiments of the present application. As Figure 4 shown, the multiple read / write control signals further include an enable signal BANK_EN. When the enable signal BANK_EN is at a low level, the word line secondary transmission gate circuit 2412 disconnects the connection with the word line terminal of the target memory cell based on the pair of secondary switch signals S1 / S2; the word line logic control circuit 221 grounds the word line terminal of the target memory cell based on the pair of secondary switch signals S1 / S2.

[0063] When the enable signal BANK_EN and the word line address signal LW_WL <m:1>When both are at high level, the word line two - level transmission gate circuit 2412 restores the connection with the word line terminal of the target memory cell based on the two - level switch signals S1 / S2.

[0064] Specifically, the enable signal BANK_EN and the word line address signal LW_WL <m:1>is active high. When the enable signal BANK_EN or the word line address signal LW_WL <m:1>When it is at a low level, S1 is at a low level, S2 is at a high level, the input and output ends of T3 are disconnected, the switching transistor Q1 conducts, and the word line end of the target storage unit is grounded.

[0065] When the enable signal BANK_EN and the word line address signal LW_WL <m:1>When it is at a high level, S1 is at a high level, S2 is at a low level, the input terminal and the output terminal of T3 are conducting, and the switching transistor Q1 is turned off. Among them, the word line address signal LW_WL <m:1>There are m address signals, the address signal of the row where the target memory cell is located is at a high level, and the rest are at a low level.

[0066] The control circuit of the resistive memory array in this embodiment realizes the control of the voltage input to the word line terminal of the target memory cell through the word line logic control circuit, and outputs the corresponding word line voltage under different operating conditions, ensuring the correctness of the word line voltage.

[0067] In some embodiments, Figure 5 is a connection schematic diagram of the bit line multi-stage transmission gate circuit in some embodiments of the present application. As Figure 5 shown, the multi-stage transmission gate circuit includes a bit line first-stage transmission gate circuit 2421 and a bit line second-stage transmission gate circuit 2422. The multiple read / write control signals include a set control signal SET and a reset control signal RESET. The bit line first-stage transmission gate circuit 2421 includes a fourth transmission gate T4 and a fifth transmission gate T5.

[0068] The bit line first-stage transmission gate circuit 2421 generates a pair of first-stage switch signals for the fourth transmission gate T4 based on the set control signal SET to control the connection or disconnection of the preset bit line set voltage signal VBLSET and the bit line second-stage transmission gate circuit 2422; the bit line first-stage transmission gate circuit 2421 generates a pair of first-stage switch signals for the fifth transmission gate T5 based on the reset control signal RESET to control the grounding or disconnection of the bit line second-stage transmission gate circuit 2422. The bit line set voltage signal VBLSET can provide a set voltage SET and a forming voltage FORMING.

[0069] Similar to the word line multi-stage transmission gate circuit in the above embodiment, the bit line multi-stage transmission gate circuit may further include a level shift circuit. The level shift circuit is used to perform voltage conversion on the input high-level signal or low-level signal to drive the fourth transmission gate T4 and the fifth transmission gate T5, but does not change the relative high and low levels of the signals. The bit line second-stage transmission gate circuit 2422 may include a transmission gate T6. Specifically, T4, T5, and T6 may be CMOS transmission gates. The relationship between the high and low levels of the first control terminal and the second control terminal and the on / off state will not be elaborated here.

[0070] Among them, the set control signal SET and the reset control signal RESET cannot be valid at the same time. When a set operation is performed, the set control signal SET is at a high level. After the set control signal SET and the corresponding inverted signal are level-shifted, they are used as the control signal of T4. The input terminal and the output terminal of T4 are conducted, and the bit line set voltage signal VBLSET is sent to the input terminal of the bit line second-stage transmission gate circuit 2422. At this time, the input terminal and the output terminal of T5 are disconnected.

[0071] Similarly, when a reset operation is performed, the reset control signal RESET is at a high level, the input and output ends of T5 are conducted, and the input end of the bit line secondary transmission gate circuit 2422 is grounded. At this time, the input and output ends of T4 are disconnected.

[0072] Furthermore, the transmission gate T6 controls the conduction or disconnection of its input and output ends according to the pair of secondary switch signals sent by the bit line logic control circuit, so as to control the bit line set voltage signal VBLSET or 0V grounded to be applied to the bit line end of the target storage cell, and realize the set operation or the reset operation.

[0073] The control circuit of the resistive memory array in this embodiment connects the corresponding bit line set voltage signal or ground signal to the bit line secondary transmission gate circuit respectively during the set operation and the reset operation through the bit line primary transmission gate circuit; and applies the bit line set voltage or ground voltage to the bit line end of the target storage cell through the bit line secondary transmission gate circuit to realize the set operation or the reset operation, thus realizing the selection and output of the bit line voltage corresponding to different operations.

[0074] In some embodiments, Figure 6 is a schematic connection diagram of the bit line transmission gate circuit and the bit line logic control circuit in some embodiments of the present application. As Figure 6 shown, the logic control circuit includes a bit line logic control circuit 222, and the multiple read / write control signals include an enable signal BANK_EN and a read control signal READ. The bit line logic control circuit 222 is based on the read control signal READ, the enable signal BANK_EN, and the bit line address signal LW_BL <n:1>, control the connection or disconnection of the preset bit line read voltage signal VBLREAD to / from the bit line terminal of the target memory cell; the bit line logic control circuit 222 is based on the enable signal BANK_EN and the bit line address signal LW_BL <n:1>, generate the secondary switch signal pair S3 / S4.

[0075] In this embodiment, any two of the read control signal READ, the set control signal SET, and the reset control signal RESET cannot be valid at the same time. The enable signal BANK_EN and the bit line address signal LW_BL <n:1>It is active high.

[0076] When the enable signal BANK_EN and the bit line address signal LW_BL <n:1>When it is at a high level, transmission gate T6 conducts. Further, when the read control signal READ is at a high level, switch transistor Q2 conducts, and transmission gates T4 and T5 turn off, and the bit line terminal of the target memory cell is applied with the bit line read voltage signal VBLREAD. Similarly, when the enable signal BANK_EN and the bit line address signal LW_BL <n:1>is at a high level, and when the set control signal SET is at a high level, the switching transistor Q2 is turned off, the transmission gates T4 and T6 are turned on, the transmission gate T5 is turned off, and the bit line terminal of the target storage cell is applied with the bit line set voltage signal VBLSET. Similarly, when the enable signal BANK_EN and the bit line address signal LW_BL <n:1>is at a high level, and when the reset control signal RESET is at a high level, the bit line terminal of the target storage unit is grounded.

[0077] When the enable signal BANK_EN or the bit line address signal LW_BL <n:1>When it is at a low level, the transmission gate T6 is turned off, the switching transistor Q2 is turned off, and the bit line terminal of the target storage unit is disconnected from the gating module.

[0078] The control circuit of the resistive memory array in this embodiment controls the connection or disconnection between the target storage unit and the gating module through the bit line logic control circuit; through the bit line logic control circuit and the bit line transmission gate circuit, when the target storage unit is connected to the gating module, the input voltage of the bit line terminal of the target storage unit is controlled, and the corresponding bit line voltage is output under different operating conditions, ensuring the correctness of the bit line voltage.

[0079] In some embodiments, Figure 7 is a connection schematic diagram of the source line multi-stage transmission gate circuit in some embodiments of the present application. As Figure 7 shown, the multi-stage transmission gate circuit includes a source line first-stage transmission gate circuit 2431 and a source line second-stage transmission gate circuit 2432. The multiple read / write control signals include a set control signal SET and a reset control signal RESET. The source line first-stage transmission gate circuit 2431 includes a seventh transmission gate T7 and an eighth transmission gate T8. The source line first-stage transmission gate circuit 2431 generates a first-stage switch signal pair of the seventh transmission gate T7 based on the set control signal SET to control the source line second-stage transmission gate circuit 2432 to be grounded or disconnected; the source line first-stage transmission gate circuit 2431 generates a first-stage switch signal pair of the eighth transmission gate T8 based on the reset control signal RESET to control the connection or disconnection between the preset source line reset voltage signal VSLRESET and the source line second-stage transmission gate circuit 2432.

[0080] Similar to the word line multi-stage transmission gate circuit in the above embodiment, the source line multi-stage transmission gate circuit may further include a level shift circuit. The level shift circuit is used to perform voltage conversion on the input high-level signal or low-level signal to drive the seventh transmission gate T7 and the eighth transmission gate T8, but does not change the relative high and low levels of the signal. The source line second-stage transmission gate circuit 2432 may include a transmission gate T9. Specifically, T7, T8, and T9 may be CMOS transmission gates. The relationship between the high and low levels of the first control terminal and the second control terminal and the on / off state will not be elaborated here.

[0081] Among them, the set control signal SET and the reset control signal RESET cannot be valid at the same time. When a set operation is performed, the set control signal SET is at a high level. After the set control signal SET and the corresponding inverted signal are level-shifted, they are used as the control signal of T7. The input terminal and the output terminal of T7 are conducted, and the input terminal of the source line second-stage transmission gate circuit 2432 is grounded. At this time, the input terminal and the output terminal of T8 are disconnected.

[0082] Similarly, when a reset operation is performed, the reset control signal RESET is at a high level, the input and output terminals of T8 are conducting, and the source line reset voltage signal VSLRESET is sent to the input terminal of the source line secondary transmission gate circuit 2432. At this time, the input and output terminals of T7 are disconnected.

[0083] Furthermore, the transmission gate T9 controls the conduction or disconnection of its input and output terminals according to the pair of secondary switch signals sent by the source line logic control circuit, so as to control the source line terminal of the target memory cell to be grounded or to apply the source line reset voltage signal VSLRESET, thereby implementing the set operation or the reset operation.

[0084] The control circuit of the resistive memory array in this embodiment connects the corresponding ground signal or source line reset voltage signal to the source line secondary transmission gate circuit through the source line primary transmission gate circuit during the set operation and the reset operation respectively; and applies the ground voltage or the source line reset voltage to the source line terminal of the target memory cell through the source line secondary transmission gate circuit, so as to implement the set operation or the reset operation, and realizes the selection and output of the source line voltage corresponding to different operations.

[0085] In some embodiments, Figure 8 is a schematic connection diagram of the source line multi-stage transmission gate circuit and the source line logic control circuit in some embodiments of the present application. As Figure 8 shown, the logic control circuit includes a source line logic control circuit 223, and the plurality of read / write control signals include an enable signal BANK_EN, a read control signal READ, a set signal SET, and a reset signal RESET. The source line logic control circuit 223 is based on the read control signal READ, the enable signal BANK_EN, and the source line address signal LW_SL <n:1>, control the connection or disconnection between the readout circuit and the source line terminal of the target memory cell; the source line logic control circuit 223 is based on the set signal SET, the reset signal RESET, the enable signal BANK_EN, and the source line address signal LW_SL <n:1>, generate the secondary switch signal pair S5 / S6.

[0086] Similar to the above embodiments, any two of the read control signal READ, the set control signal SET, and the reset control signal RESET cannot be valid at the same time. The enable signal BANK_EN and the source line address signal LW_SL <n:1>It is active high.

[0087] When the enable signal BANK_EN and the source line address signal LW_SL <n:1>is at a high level, and when the read control signal READ is at a high level, the switching transistor Q3 conducts, and the source line terminal of the target memory cell is connected to the readout circuit. When the enable signal BANK_EN and the source line address signal LW_SL <n:1>is at a high level, and when the set control signal SET is at a high level, the switching transistor Q3 is turned off, the transmission gates T7 and T9 are turned on, the transmission gate T8 is turned off, and the source line terminal of the target memory cell is grounded. Similarly, when the enable signal BANK_EN and the source line address signal LW_SL <n:1>When the word line voltage signal WL is at a high level and the reset control signal RESET is at a high level, the switching transistor Q3 is turned off, the transmission gates T8 and T9 are turned on, the transmission gate T7 is turned off, and the source line terminal of the target memory cell is connected to the source line reset voltage signal VSLRESET.

[0088] When the enable signal BANK_EN or the bit line address signal LW_BL <n:1>When it is at a low level, the transmission gate T9 is turned off, the switching transistor Q3 is turned off, and the source line terminal of the target storage cell is disconnected from the gating module.

[0089] The control circuit of the resistive memory array in this embodiment controls the connection or disconnection between the target storage cell and the gating module through the source line logic control circuit; through the source line logic control circuit and the source line transmission gate circuit, when the target storage cell is connected to the gating module, the input voltage of the source line terminal of the target storage cell is controlled, and the corresponding source line voltage is output under different operating conditions, ensuring the correctness of the bit line voltage; and when the read control signal is valid, it controls the source line terminal of the target storage cell to be connected to the readout circuit, and the data readout result is obtained by reading the current value of the source line terminal.

[0090] In some embodiments, the control circuit further includes a digital-to-analog conversion circuit, and the digital-to-analog conversion circuit is used to convert the voltage value output by the controller into a corresponding word line write voltage signal and output it to the multi-level transmission gate circuit. Figure 9 It is a circuit connection diagram of the digital-to-analog conversion circuit in some embodiments of the present application. As Figure 9 shown, the digital-to-analog conversion circuit includes a capacitor array 41 and a rail-to-rail input / output operational amplifier 42. The capacitor array includes 9 capacitors and 9 switches (6 capacitors and 6 switches are shown in the figure), and the capacitance values of the 9 capacitors are C, C / 2, C / 4, C / 8, C / 16, C / 32, C / 64, C / 128, C / 128 respectively. The upper plates of the 9 capacitors are connected to the non-inverting input terminal of the rail-to-rail input / output operational amplifier 42. The lower plate of one capacitor with a capacitance value of C / 128 is connected to GND, and the lower plates of the other 8 capacitors are connected to the reference voltage VREF through switches. The upper plates of all capacitors are connected to GND through the clock switch DAC_CLK. According to the input digital voltage value and the reference voltage VREF, an analog voltage is generated as the word line write voltage signal VWLDAC.

[0091] When using this digital-to-analog conversion circuit, first ground the clock switch DAC_CLK and the switches D0 to D7, so that both ends of all capacitors are grounded, then disconnect DAC_CLK, and the capacitor array connects the lower plates of the capacitors to the reference voltage VREF. According to the law of conservation of charge, its output voltage satisfies:

[0092]

[0093] In some embodiments, Figure 10 It is a connection diagram of the readout circuit in some embodiments of the present application. As Figure 10 shown, the readout circuit includes a current-to-voltage conversion circuit 51 and an analog-to-digital conversion circuit 52. The current-to-voltage conversion circuit 51 converts the current value I output by the target storage cell IN It is converted into a corresponding voltage signal, and the analog-to-digital conversion circuit 52 converts the voltage signal into a digital voltage value D<7:0> and sends it to the controller. Specifically, the analog-to-digital conversion circuit 52 can be an 8-bit successive approximation analog-to-digital converter.

[0094] The input end of the current-to-voltage circuit 51 is connected to the source line logic control circuit, and the output end is connected to the input end of the analog-to-digital conversion circuit 52. The function of the current-to-voltage circuit 51 is to convert the source line current I from the resistive random access memory array IN scale it and generate a voltage. The function of the analog-to-digital conversion circuit 52 is to perform analog-to-digital conversion on the voltage generated by the current-to-voltage circuit 51.

[0095] The current-to-voltage circuit 51 can include an operational amplifier clamping circuit and a current scaling circuit. Among them, the function of the operational amplifier clamping circuit is to clamp the source line SL of the resistive random access memory array to a fixed voltage, that is, the source line read voltage VSLREAD, and the function of the current scaling circuit is to scale the current I of the source line SL IN scale it and generate a voltage at the input end of the analog-to-digital conversion circuit 52. The flow direction of the SL current is controlled by the digital control signal COMPUTE_OC. When COMPUTE_OC is at a high level, the current flows out of the chip for chip testing; when COMPUTE_OC is at a low level, the current flows to the operational amplifier clamping circuit.

[0096] The analog-to-digital conversion circuit 52 is composed of a sample-and-hold circuit SH, a comparator COMP, two P-DAC capacitor arrays, and a successive approximation register SAR module. When its enable signal ENA is at a high level, the analog-to-digital conversion circuit 52 works normally. When ENA is at a low level, the input of the comparator COMP is pulled to GND, and the output of the analog-to-digital conversion circuit 52 is 0.

[0097] In some embodiments, the present application also provides a resistive random access memory, which includes a resistive random access memory array and a control circuit of the resistive random access memory array as described in the above embodiments.

[0098] For the resistive random access memory of this embodiment, a corresponding input voltage is applied to a target storage unit in the resistive random access memory array through the control circuit of the resistive random access memory array to implement read and write operations corresponding to the input voltage; the connection or disconnection between the target storage unit and the readout circuit is controlled. When the readout circuit is connected to the target storage unit, the current value output by the target storage unit is read. When implementing the read operation, the current value of the target storage unit is read through the readout circuit, and the data readout result is obtained through the current value; the gating of the word line, bit line, and source line and the corresponding voltage input and current readout are realized, reducing the occupied area of the peripheral circuit and solving the problem of the large occupied area of the peripheral circuit.

[0099] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation manners, and will not be elaborated herein.

[0100] It should be understood that the specific embodiments described herein are only used to explain this application, rather than to limit it. All other embodiments obtained by those of ordinary skill in the art according to the embodiments provided in this application without creative efforts shall fall within the protection scope of this application.

[0101] Obviously, the accompanying drawings are only some examples or embodiments of this application. For those of ordinary skill in the art, this application can also be applied to other similar situations based on these drawings without creative efforts. Additionally, it can be understood that although the work done during this development process may be complex and time-consuming, for those of ordinary skill in the art, certain design, manufacturing, or production changes based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient disclosure of this application.

[0102] The term "embodiment" in this application means that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of this application. The phrase appears in various positions in the specification does not necessarily mean the same embodiment, nor does it mean being independent or alternative to other embodiments and mutually exclusive. Those of ordinary skill in the art can clearly or implicitly understand that the embodiments described in this application can be combined with other embodiments without conflict.

[0103] The above-described embodiments only represent several implementation manners of this application, and their descriptions are relatively specific and detailed, but should not be construed as a limitation on the scope of patent protection. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of this application shall be subject to the appended claims.

Claims

1. A control circuit of a resistive memory array, the control circuit comprising a gating module connected to the resistive memory array, and a controller and a readout circuit connected to the gating module; the resistive memory array comprises a plurality of memory cells, characterized in that: The gating module includes a logic control circuit and a multi-stage transmission gate circuit connected to each other. The logic control circuit sends a corresponding pair of secondary switch signals to the multi-stage transmission gate circuit based on a plurality of read / write control signals and address signals output by the controller, and controls the target storage unit corresponding to the address signal to be connected or disconnected from the readout circuit; The multi-stage transmission gate circuit applies a corresponding input voltage to the target memory cell based on the secondary switch signal pair and the plurality of read / write control signals, wherein the input voltage is determined from a plurality of preset voltages received by the multi-stage transmission gate circuit; The readout circuit reads the current value output by the target memory cell when connected to the target memory cell; The multi-stage transmission gate circuit includes a word line primary transmission gate circuit and a word line secondary transmission gate circuit, the multiple read and write control signals include a read control signal and a write control signal, and the word line primary transmission gate circuit includes a first transmission gate and a second transmission gate. The word line primary transmission gate circuit generates a primary switch signal pair of the first transmission gate based on the write control signal to control a preset word line write voltage signal to be connected or disconnected with the word line secondary transmission gate circuit; and The word line primary transmission gate circuit generates a primary switch signal pair of the second transmission gate based on the read control signal to control a preset word line read voltage signal to be connected or disconnected with the word line secondary transmission gate circuit.

2. The circuit according to claim 1, characterized in that The logic control circuit includes a word line logic control circuit, the multiple read and write control signals include an enable signal, When the enable signal is at a low level, the word line secondary transmission gate circuit disconnects the word line terminal of the target memory cell based on the secondary switch signal pair; the word line logic control circuit controls the word line terminal of the target memory cell to be grounded based on the secondary switch signal pair; In the case that both the enable signal and the address signal are at a high level, the word line secondary transmission gate circuit restores the connection with the word line terminal of the target memory cell based on the secondary switch signal pair.

3. The circuit according to claim 1, characterized in that The multi-stage transmission gate circuit includes a bit line primary transmission gate circuit and a bit line secondary transmission gate circuit, the multiple read and write control signals include a set control signal and a reset control signal, and the bit line primary transmission gate circuit includes a fourth transmission gate and a fifth transmission gate, The bit line primary transmission gate circuit generates a primary switch signal pair of the fourth transmission gate based on the setting control signal to control the connection or disconnection of a preset bit line setting voltage signal with the bit line secondary transmission gate circuit; and The bit line primary transmission gate circuit generates a primary switch signal pair of the fifth transmission gate based on the reset control signal to control the bit line secondary transmission gate circuit to be grounded or disconnected.

4. The circuit according to claim 3, characterized in that The logic control circuit includes a bit line logic control circuit, the multiple read and write control signals include an enable signal and a read control signal, The bit line logic control circuit controls a preset bit line read voltage signal to be connected or disconnected with a bit line terminal of the target memory cell based on the read control signal, the enable signal and the address signal; The bit line logic control circuit generates the secondary switch signal pair based on the enable signal and the address signal.

5. The circuit according to claim 1, characterized in that The multi-stage transmission gate circuit includes a source line primary transmission gate circuit and a source line secondary transmission gate circuit, the multiple read and write control signals include a set control signal and a reset control signal, the source line primary transmission gate circuit includes a seventh transmission gate and an eighth transmission gate, The source line primary transmission gate circuit generates a primary switch signal pair of the seventh transmission gate based on the set control signal to control the source line secondary transmission gate circuit to be grounded or disconnected; and The source line primary transmission gate circuit generates a primary switch signal pair of the eighth transmission gate based on the reset control signal to control the connection or disconnection of a preset source line reset voltage signal with the source line secondary transmission gate circuit.

6. The circuit according to claim 5, characterized in that The logic control circuit includes a source line logic control circuit, the multiple read and write control signals include an enable signal, a read control signal, a set signal and a reset signal, The source line logic control circuit controls the readout circuit to connect or disconnect with the source line terminal of the target memory cell based on the read control signal, the enable signal and the address signal; The source line logic control circuit generates the secondary switch signal pair based on the set signal, the reset signal, the enable signal and the address signal.

7. The circuit according to claim 1, characterized in that The control circuit also includes a digital-to-analog conversion circuit, The digital-to-analog conversion circuit is used to convert the voltage value output by the controller into a corresponding word line write voltage signal, and output it to the multi-stage transmission gate circuit.

8. The circuit according to claim 1, characterized in that The readout circuit includes a current-to-voltage conversion circuit and an analog-to-digital conversion circuit. The current-to-voltage circuit converts the current value output by the target storage unit into a corresponding voltage signal, and the analog-to-digital conversion circuit converts the voltage signal into a voltage value and sends it to the controller.

9. A resistive random access memory, characterized in that: The resistive memory comprises a resistive memory array and a control circuit of the resistive memory array as claimed in any one of claims 1 to 8.

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