Packaging structure and manufacturing method
By setting stress relief grooves on the edge area of the packaging layer, the wafer warping problem caused by different thermal expansion coefficients is solved, and the effect of effectively releasing thermal stress is achieved. It is suitable for a variety of packaging types.
Patent Information
- Application Number
- CN202411673515.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-21
- Publication Date
- 2025-04-01
AI Technical Summary
In chip packaging on wafers, due to the different thermal expansion coefficients of the packaging layer and wafer, the wafer is prone to warping or even lobes during the heating process, and the prior art is difficult to effectively solve this problem.
Annular stress relief grooves are provided in the edge area of the encapsulation layer, and these grooves are formed by cutting the side walls of the encapsulation layer by cutting the cutting tool to release stresses caused by different coefficients of thermal expansion.
Effectively release thermal stress between the packaging layer and the wafer to avoid wafer warping and lobes. It is suitable for different types of packaging, with simple operation and significantly improves wafer warping problems caused by different thermal expansion coefficients.
Smart Images
Figure CN119742239A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of packaging, and relates to a packaging structure and a manufacturing method. Background Art
[0002] As the current process requirements for thin wafers increase, how to control the warpage problem in chip on wafer (COW) packaging has become the key. In COW packaging, the chips are first stacked on a thin wafer, and then a packaging layer covering the chips is formed. Due to the extreme differences in the coefficient of thermal expansion (CTE) between various materials, warpage of varying degrees is likely to occur during the subsequent heating process, making some process operations difficult and even causing chip cracking.
[0003] The current solution is to fine-tune the thermal expansion stress by adjusting various machine parameters. However, for wafers of different thicknesses, different chip stacking methods, and packaging layers of different materials, the machine parameters need to be readjusted, and the problem cannot be fundamentally solved. It can only reduce the probability of warping.
[0004] Therefore, how to provide a packaging structure and a manufacturing method to avoid wafer warping or even wafer cracking due to different thermal expansion coefficients has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention
[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a packaging structure and a manufacturing method for solving the problem of wafer warping or even wafer cracking caused by different thermal expansion coefficients between the packaging layer and the wafer in the prior art.
[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a packaging structure, comprising the following steps:
[0007] Providing a wafer, the wafer comprising a first surface and a second surface arranged opposite to each other, wherein a plurality of chips and a packaging layer covering the chips are formed on the first surface of the wafer;
[0008] A stress release groove is formed in the packaging layer. The stress release groove is an annular structure and extends from the side wall of the packaging layer to the inside of the packaging layer to release the stress generated by the different thermal expansion coefficients between the wafer and the packaging layer.
[0009] Optionally, the step of forming a stress release groove in the packaging layer includes:
[0010] Providing a carrier, fixing the second surface of the wafer to the carrier through an adhesive layer, wherein the carrier can drive the wafer to rotate;
[0011] A cutting tool is provided to cut the side wall of the packaging layer to form the stress release groove, wherein the cutting direction is perpendicular to the direction in which the wafer points to the packaging layer.
[0012] Optionally, a pressure sensor is further included, and the pressure sensor is connected to the cutting tool to detect the cutting pressure of the cutting tool when forming the stress release groove.
[0013] Optionally, after forming the stress release groove, the following steps are further included:
[0014] separating the wafer from the carrier;
[0015] The package body separated from the carrier is diced to form a plurality of package structures.
[0016] Optionally, the depth of the stress release groove is 2 mm to 5 mm, and the width of the stress release groove is 1 mm to 2 mm.
[0017] Optionally, the chip is fixed to the first surface of the wafer by a wafer adhesive film.
[0018] Optionally, the chip is fixed to the first surface of the wafer by welding through a welding layer.
[0019] Optionally, the number of the stress relief groove is one.
[0020] Optionally, there are multiple stress release grooves, and in the direction from the wafer to the packaging layer, the multiple stress release grooves are arranged in sequence at intervals.
[0021] The present invention also provides a packaging structure, and the packaging structure is manufactured by any of the above-mentioned packaging structure manufacturing methods.
[0022] As described above, in the packaging structure and manufacturing method of the present invention, a stress release groove is set in the edge area of the packaging layer to provide deformation space for the material deformation of the packaging layer, so that the stress is effectively released and the wafer warping is avoided; and it is suitable for different types of packaging, simple to operate, and significantly improves the wafer warping problem caused by different thermal expansion coefficients. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 A schematic diagram of a package is shown.
[0024] Figure 2 Display as Figure 1 The package shown is a schematic diagram after undergoing a high temperature process.
[0025] Figure 3Shown is a process flow chart of a method for manufacturing a packaging structure in an embodiment of the present invention.
[0026] Figure 4 It is a schematic diagram showing a chip and a packaging layer formed on a first surface of a wafer according to an embodiment of the present invention.
[0027] Figure 5 It is a schematic diagram showing a stress release groove formed on the side wall of the packaging layer according to an embodiment of the present invention.
[0028] Figure 6 It is a schematic diagram showing a package body after undergoing a high temperature process according to an embodiment of the present invention.
[0029] Component number description
[0030] 01 Wafer
[0031] 02 Chip
[0032] 03 Encapsulation layer
[0033] 1 Wafer
[0034] 2 Wafer adhesive film
[0035] 3 Chips
[0036] 4 Encapsulation layer
[0037] 5 Stress relief slot
[0038] 6 Carrier
[0039] 7 Adhesion layer
[0040] 8 Cutting tools
[0041] 9 Rotating structure
[0042] 10. Pressure sensor
[0043] Steps S1 to S2 DETAILED DESCRIPTION
[0044] like Figure 1 As shown, it is a schematic diagram of a package body, in which a first surface of a wafer 01 is formed with a plurality of chips 02 and a packaging layer 03 covering the chips 02. Figure 2 As shown, it is shown as Figure 1 The schematic diagram of the package body after undergoing a high temperature process shows that thermal stress is generated due to the large difference in CTE between the package layer 03 and the wafer 01, and the stress is transmitted to the edge, causing warping in the edge area of the wafer 01. Therefore, the purpose of this application is to solve the problem of wafer warping or even cracking due to different thermal expansion coefficients.
[0045] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0046] See also Figures 3 to 6 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0047] This embodiment provides a method for manufacturing a packaging structure. Figure 3 The method for manufacturing the packaging structure comprises the following steps:
[0048] S1: providing a wafer, wherein the wafer comprises a first surface and a second surface arranged opposite to each other, wherein a plurality of chips and a packaging layer covering the chips are formed on the first surface of the wafer;
[0049] S2: forming a stress release groove in the packaging layer, wherein the stress release groove is an annular structure and extends from the side wall of the packaging layer to the inside of the packaging layer to release the stress generated by the different thermal expansion coefficients between the wafer and the packaging layer.
[0050] The method for manufacturing the packaging structure in this embodiment is described in detail below with reference to the specific drawings.
[0051] First, see Figure 4 , perform step S1: provide a wafer 1, the wafer 1 includes a first surface and a second surface arranged opposite to each other, and a plurality of chips 2 and a packaging layer covering the chips 2 are formed on the first surface of the wafer 1.
[0052] As an example, the wafer 1 is a thinned wafer. The thinned wafer can reduce the packaging mounting height, increase the integration level and improve the electrical performance, etc., and is suitable for advanced packaging technology.
[0053] As an example, the wafer 1 may be any suitable wafer, such as a silicon wafer, a gallium arsenide wafer, a silicon carbide wafer, a gallium nitride wafer, etc. In this embodiment, the wafer 1 is a silicon wafer.
[0054] As an example, the number of the chips 3 is multiple, and the chip 3 is fixed to the first surface of the wafer 1 through a die attach film 2 (Die Attach Film); in another example, the chip 3 can also be fixed to the first surface of the wafer 1 through welding of a welding layer, which is selected according to needs.
[0055] As an example, Figure 1 The chip 3 is merely provided with a single layer as an example. In another example, the chip 3 may also be provided with multiple layers, which is selected according to the requirements.
[0056] As an example, after the chip 3 is formed on the first surface of the wafer 1 , the packaging layer 4 is formed on the first surface of the wafer 1 by a spin coating process or other suitable processes, and the packaging layer 4 covers the chip 3 .
[0057] As an example, the material of the encapsulation layer 4 is a polymer, such as epoxy resin, polyimide, etc., which is selected according to actual needs.
[0058] Next, see Figure 5 , execute step S2: forming a stress release groove 5 in the packaging layer 4, the stress release groove 5 has a ring-shaped structure, and the stress release groove 5 extends from the side wall of the packaging layer 4 to the inside of the packaging layer 4 to release the stress caused by the different thermal expansion coefficients between the wafer 1 and the packaging layer 4.
[0059] As an example, the step of forming the stress release groove 5 in the packaging layer 4 includes:
[0060] (i) providing a carrier 6, and fixing the second surface of the wafer 1 to the carrier 6 via an adhesive layer 7, wherein the carrier 6 can drive the wafer 1 to rotate;
[0061] (ii) providing a cutting tool 8 to cut the side wall of the packaging layer 4 to form the stress release groove 5, wherein the cutting direction is perpendicular to the direction from the wafer 1 to the packaging layer 4;
[0062] As an example, the carrier 6 may be any suitable carrier, such as a metal carrier, a semiconductor carrier, a glass carrier, a polymer carrier, etc., which is not limited here.
[0063] As an example, the adhesive layer 7 may be made of materials such as tape or polymer, and is used to temporarily bond the wafer 1 and the carrier 6 , and subsequently debond the wafer 1 and the carrier 6 based on the adhesive layer 7 .
[0064] As an example, the carrier 6 is fixed to the rotating structure 9, and the rotating structure 9 drives the carrier 6 to rotate, so that the carrier 6 drives the wafer 1 to rotate. For example, the rotating structure 9 uses a vacuum suction cup, and the vacuum suction cup adsorbs and fixes the carrier 6 and drives the carrier 6 to rotate. In the cutting process, the wafer 1 rotates at a constant speed along the central axis to form the annular stress release groove 5 on the side wall of the packaging layer 4.
[0065] As an example, the direction in which the wafer 1 points to the packaging layer 4 is defined as the vertical direction, and the cutting tool 8 is placed horizontally and rotated at high speed to cut the packaging layer 4 to form the stress release groove 5; the depth of the stress release groove 5 is 2mm to 5mm, for example, it can be 2mm, 3mm, 4mm, 5mm, etc., and the width of the stress release groove 5 is 1mm to 2mm, for example, it can be 1mm, 1.5mm, 2mm, etc.
[0066] As an example, after the stress release groove 5 is formed, the wafer 1 and the carrier 6 are debonded according to the type of the adhesion layer 7. For example, when the adhesion layer 7 adopts a photothermal conversion material, the adhesion layer 7 can be irradiated with a laser to reduce its viscosity, thereby peeling off the wafer 1 and the carrier 6; when the adhesion layer 7 adopts a high-temperature thermal peeling glue, the wafer 1 and the carrier 6 can be peeled off through a high-temperature process.
[0067] As an example, since the wafer 1 is a thinned wafer, its mechanical strength is weak and it is easy to break during the transfer and process operation of different processes. Therefore, in this embodiment, before the chip 3 and the packaging layer 4 are formed on the first side of the wafer 1, the second side of the wafer 1 is first fixed to the carrier 6 through the adhesion layer 7 to improve the mechanical strength of the wafer 1, and then the chip 3 and the packaging layer 4 are formed on the first side of the wafer 1. That is, before the packaging layer 4 is formed, the carrier 6 provides mechanical support for the wafer 1, and after the carrier 6 and the wafer 1 are peeled off, the packaging layer 4 provides mechanical support for the wafer 1.
[0068] As an example, a pressure sensor 10 is also included, and the pressure sensor 10 is connected to the cutting tool 8 to detect the cutting pressure of the cutting tool 8 when forming the stress release groove 5. Since the Mohs hardness difference between the packaging layer 4 and the chip 3 is large, when the pressure detected by the pressure sensor 10 has a large deviation, it means that the chip 3 is cut to the edge area, and the cutting tool 8 stops immediately to avoid damaging the chip 3.
[0069] As an example, see Figure 6, which is a schematic diagram showing the package body after undergoing a high temperature process in an embodiment of the present invention. When the stress is transmitted to the edge area, since the edge area of the packaging layer 4 is provided with the stress release groove 5, a deformation space is provided for the material deformation of the packaging layer 4, so that the stress is effectively released and the wafer is prevented from warping.
[0070] As an example, in this embodiment, for wafers 1 with different thicknesses, different chip 3 stacking methods, and packaging layers 4 with different materials, the thermal stress generated by the difference in material CTE can be released through the stress release groove 5. There is no need for excessive process parameter adjustments, the operation is simple, and the wafer warping problem caused by different thermal expansion coefficients can be significantly improved.
[0071] As an example, in this embodiment, the number of the stress release groove 5 is one. In other examples, a plurality of the stress release grooves 5 may also be provided. In the direction from the wafer 1 to the packaging layer 4, the plurality of stress release grooves 5 are arranged in sequence at intervals, and the selection is made according to actual needs.
[0072] As an example, after the wafer 1 and the carrier 6 are separated, the method further includes dicing the package body separated from the carrier 6 to form a plurality of package structures.
[0073] This embodiment also provides a packaging structure, which is manufactured by the above-mentioned manufacturing method.
[0074] In summary, in the packaging structure and manufacturing method of the present invention, a stress release groove is set in the edge area of the packaging layer to provide deformation space for the material deformation of the packaging layer, so that the stress is effectively released and the wafer is prevented from warping; and it is applicable to different types of packaging, simple to operate, and significantly improves the problem of wafer warping caused by different thermal expansion coefficients. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0075] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a packaging structure, characterized in that: The following steps are involved: Providing a wafer, the wafer comprising a first surface and a second surface arranged opposite to each other, wherein a plurality of chips and a packaging layer covering the chips are formed on the first surface of the wafer; A stress release groove is formed in the packaging layer. The stress release groove is an annular structure and extends from the side wall of the packaging layer to the inside of the packaging layer to release the stress generated by the different thermal expansion coefficients between the wafer and the packaging layer.
2. The method for manufacturing a packaging structure according to claim 1, characterized in that: The step of forming the stress release groove in the packaging layer includes: Providing a carrier, fixing the second surface of the wafer to the carrier through an adhesive layer, wherein the carrier can drive the wafer to rotate; A cutting tool is provided to cut the side wall of the packaging layer to form the stress release groove, wherein the cutting direction is perpendicular to the direction in which the wafer points to the packaging layer.
3. The method for manufacturing a packaging structure according to claim 2, characterized in that: A pressure sensor is also included, and the pressure sensor is connected to the cutting tool to detect the cutting pressure of the cutting tool when forming the stress release groove.
4. The method for manufacturing a packaging structure according to claim 2, characterized in that: After forming the stress release groove, the following steps are also included: separating the wafer from the carrier; The package body separated from the carrier is diced to form a plurality of package structures.
5. The method for manufacturing a packaging structure according to claim 1, wherein: The depth of the stress release groove is 2 mm to 5 mm, and the width of the stress release groove is 1 mm to 2 mm.
6. The method for manufacturing a packaging structure according to claim 1, wherein: The chip is fixed to the first surface of the wafer through a wafer adhesive film.
7. The method for manufacturing a packaging structure according to claim 1, wherein: The chip is fixed to the first surface of the wafer by welding through a welding layer.
8. The method for manufacturing a packaging structure according to claim 1, wherein: The number of the stress release groove is one.
9. The method for manufacturing a packaging structure according to claim 1, wherein: There are multiple stress release grooves, and in the direction from the wafer to the packaging layer, the multiple stress release grooves are arranged in sequence at intervals.
10. A packaging structure, characterized in that: The packaging structure is manufactured by the packaging structure manufacturing method according to any one of claims 1 to 9.