Semiconductor device, manufacturing method, and electronic device

Abstract

The application relates to a semiconductor device, a preparation method and an electronic device. The semiconductor device comprises a substrate, a source pad and a gate pad, the source pad comprises a first layer source pad and a second layer source pad, the first layer source pad covers a gate structure and an active region, and the second layer source pad covers part of the top surface of the first layer source pad. The gate pad comprises a first layer gate pad and a second layer gate pad, the first layer gate pad covers part of the top surface of the substrate, and the second layer gate pad covers part of the top surface of the first layer gate pad and the first layer source pad, wherein the source pad and the gate pad are insulated. By making the covering area of the first layer gate pad smaller than the covering area of the second layer gate pad, space can be saved, the area of the active region can be increased, the specific on-resistance value of the device can be reduced, and the reliability and electrical properties of the semiconductor device can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device, a preparation method and an electronic equipment. BACKGROUND

[0002] Compared with the traditional silicon insulated gate bipolar field effect transistor, the silicon carbide metal oxide field effect transistor has higher working temperature, lower switching loss and higher switching frequency in the same high voltage environment.

[0003] However, in the traditional technology, the gate pad and the source pad occupy a large area of the chip, resulting in a decrease in the area of the active region, an increase in the value of the specific on-resistance, and a decrease in the reliability and electrical properties of the device. SUMMARY

[0004] The purpose of the present application is to provide a semiconductor device, a preparation method and an electronic equipment, which can increase the area of the active region, reduce the specific on-resistance value of the device, and improve the reliability and electrical properties of the device. To achieve the purpose of the present application, the present application provides the following technical solutions:

[0005] In a first aspect, the present application provides a semiconductor device, comprising:

[0006] a substrate, the substrate comprising a plurality of active regions and a plurality of gate structures, the plurality of active regions being spaced apart in the substrate along a first direction, the plurality of gate structures being distributed on the top surface of the substrate along the first direction, the gate structure covering part of the active region, and the gate structure and the active region being staggered distributed;

[0007] a source pad, comprising a first layer source pad and a second layer source pad, the first layer source pad covering the gate structure and the active region, and the second layer source pad covering part of the top surface of the first layer source pad;

[0008] a gate pad, comprising a first layer gate pad and a second layer gate pad, the first layer gate pad covering part of the top surface of the substrate, and the second layer gate pad covering part of the top surface of the first layer gate pad and the first layer source pad, wherein the source pad and the gate pad are insulated.

[0009] The semiconductor device of the present application includes a substrate, a source pad, and a gate pad. The substrate includes multiple active areas and multiple gate structures. The multiple active areas are spaced apart along a first direction within the substrate. The multiple gate structures are spaced apart along the first direction on the top surface of the substrate. The gate structures cover portions of the active areas, and the gate structures and the active areas are staggered. The gate pads include a first layer of gate pads and a second layer of gate pads. The first layer of gate pads covers a portion of the top surface of the substrate and can provide an electrical connection point for the electrical lead-out of the gate. The second layer of gate pads covers a portion of the top surface of the first layer of gate pads and the first layer of source pads and can connect the first layer of gate pads to a circuit, thereby achieving electrical connection of the gate in the circuit. The coverage area of ​​the first layer of gate pads is smaller than that of the second layer of gate pads, which can save space at the bottom of the second layer of gate pads. Cells can then be formed at the bottom of the second layer of gate pads, increasing the area of ​​the active area, reducing the device's specific on-resistance, and improving the reliability and electrical performance of the semiconductor device. The coverage area of ​​the first-layer source pad is larger than the coverage area of ​​the second-layer source pad. It is possible to provide an electrical connection point of the source for the increased active area through the first-layer source pad without changing the coverage area of ​​the gate pad and the source pad, and to connect to the circuit through the second-layer source pad, thereby realizing the electrical connection of the source.

[0010] In one embodiment,

[0011] The size of the first layer gate pad in the first direction is smaller than the size of the first layer source pad in the first direction;

[0012] A size of the first-layer source pad in the first direction is smaller than a size of the second-layer source pad in the first direction.

[0013] In one embodiment, the semiconductor device further includes:

[0014] a first dielectric layer, the first dielectric layer covering the first source pad and the first gate pad, and the first dielectric layer being located between the first gate pad and the second gate pad, and between the first source pad and the second gate pad;

[0015] The first dielectric layer includes a first notch and a second notch, the first layer gate pad is connected to the second layer gate pad through the first notch, and the first layer source pad is connected to the second layer source pad through the second notch.

[0016] In one embodiment, the semiconductor device further includes:

[0017] A second dielectric layer covers the gate structure.

[0018] In a second aspect, the present application further provides an electronic device, comprising:

[0019] A semiconductor device as described in any of the above.

[0020] The electronic device of the present application includes any of the semiconductor devices described above, including a substrate, a source pad, and a gate pad. The substrate includes multiple active regions and multiple gate structures, the multiple active regions being spaced apart along a first direction within the substrate, the multiple gate structures being spaced apart along the first direction on the top surface of the substrate, the gate structures covering portions of the active regions, and the gate structures and the active regions being staggered. The gate pads include a first layer of gate pads and a second layer of gate pads. The first layer of gate pads covers a portion of the top surface of the substrate and can provide an electrical connection point for electrical lead-out of the gate. The second layer of gate pads covers a portion of the top surface of the first layer of gate pads and the first layer of source pads and can connect the first layer of gate pads to a circuit, thereby achieving electrical connection of the gate in the circuit. The first layer of gate pads has a smaller coverage area than the second layer of gate pads, which can save space at the bottom of the second layer of gate pads, thereby forming a cell at the bottom of the second layer of gate pads, increasing the area of ​​the active region, reducing the device's specific on-resistance, and improving the reliability and electrical performance of the semiconductor device. The coverage area of ​​the first-layer source pad is larger than the coverage area of ​​the second-layer source pad. It is possible to provide an electrical connection point of the source for the increased active area through the first-layer source pad without changing the coverage area of ​​the gate pad and the source pad, and to connect to the circuit through the second-layer source pad, thereby realizing the electrical connection of the source.

[0021] In a third aspect, the present application further provides a method for preparing a semiconductor device, comprising:

[0022] Providing a substrate, the substrate comprising a gate structure and an active area;

[0023] Providing a substrate, the substrate comprising a plurality of active regions and a plurality of gate structures, the plurality of active regions being spaced apart along a first direction within the substrate, the plurality of gate structures being spaced apart along the first direction on a top surface of the substrate, the gate structures covering portions of the active regions, and the gate structures and the active regions being staggered;

[0024] A source pad and a gate pad are formed on the top surface of the substrate, wherein the source pad includes a first layer of source pads and a second layer of source pads, the first layer of source pads covers the gate structure and the active area, and the second layer of source pads covers a portion of the top surface of the first layer of source pads, and the gate pad includes a first layer of gate pads and a second layer of gate pads, the first layer of gate pads covers a portion of the top surface of the substrate, and the second layer of gate pads covers a portion of the top surface of the first layer of gate pads and the first layer of source pads, wherein the source pad and the gate pad are insulated.

[0025] The method for preparing a semiconductor device of the present application includes providing a substrate, the substrate including multiple active areas and multiple gate structures, the multiple active areas being spaced apart along a first direction within the substrate, the multiple gate structures being spaced apart along the first direction on the top surface of the substrate, the gate structures covering portions of the active areas, and the gate structures and the active areas being staggered. A source pad and a gate pad are then formed on the top surface of the substrate, wherein the source pad includes a first layer of source pads and a second layer of source pads, the first layer of source pads covering the gate structures and the active areas, the second layer of source pads covering portions of the top surface of the first layer of source pads, and the gate pad includes a first layer of gate pads and a second layer of gate pads, the first layer of gate pads covering portions of the top surface of the substrate, the second layer of gate pads covering portions of the top surfaces of the first layer of gate pads and the first layer of source pads, wherein the source pads and the gate pads are insulated from each other. The first layer of gate pads provides an electrical connection point for the electrical lead-out of the gate, and the second layer of gate pads connects the first layer of gate pads to the circuit, thereby achieving electrical connection of the gate in the circuit. The coverage area of ​​the first-layer gate pad is smaller than that of the second-layer gate pad, which can save space at the bottom of the second-layer gate pad. This allows the formation of a cell at the bottom of the second-layer gate pad, increasing the area of ​​the active area, reducing the device's specific on-resistance, and improving the reliability and electrical performance of the semiconductor device. The coverage area of ​​the first-layer source pad is larger than that of the second-layer source pad. This allows the first-layer source pad to provide an electrical connection point for the increased active area through the increased active area without changing the coverage area of ​​the gate and source pads, and connects to the circuit through the second-layer source pad, thereby achieving electrical connection of the source.

[0026] In one embodiment, forming a source pad and a gate pad on the top surface of the substrate includes:

[0027] forming a first metal layer on the top surface of the substrate;

[0028] Etching the first metal layer to form the first gate pad and the first source pad;

[0029] forming a second metal layer on top surfaces of the first layer of gate pads and the first layer of source pads;

[0030] The second metal layer is etched to form the second gate pad and the second source pad.

[0031] In one embodiment, after etching the first metal layer and before forming the second metal layer on the top surfaces of the first gate pad and the second gate pad, the method further includes:

[0032] forming a first dielectric material layer on top surfaces of the first layer of gate pads and the first layer of source pads;

[0033] The first dielectric material layer is etched to form a first dielectric layer, wherein the first dielectric layer includes a first notch and a second notch, the first layer gate pad is connected to the second layer gate pad through the first notch, and the first layer source pad is connected to the second layer source pad through the second notch.

[0034] In one embodiment,

[0035] The size of the first layer gate pad in the first direction is smaller than the size of the first layer source pad in the first direction;

[0036] A size of the first-layer source pad in the first direction is smaller than a size of the second-layer source pad in the first direction.

[0037] In one embodiment, after providing the substrate and before forming the source pad and the gate pad on the top surface of the substrate, the method further includes:

[0038] A second dielectric layer is formed, where the second dielectric layer covers the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0040] Figure 1 is a schematic cross-sectional structural diagram of a semiconductor device provided in one embodiment;

[0041] Figure 2 is a flow chart of a method for preparing a semiconductor device provided in another embodiment;

[0042] Figure 3 is a schematic cross-sectional view of a structure obtained in step S11 of a method for manufacturing a semiconductor device provided in another embodiment;

[0043] Figure 4 is a flow chart of steps S151 to S156 in a method for manufacturing a semiconductor device provided in another embodiment;

[0044] Figure 5 is a schematic cross-sectional view of a structure obtained in step S151 of a method for manufacturing a semiconductor device provided in another embodiment;

[0045] Figure 6is a flow chart of steps S153 and S154 in a method for manufacturing a semiconductor device provided in another embodiment;

[0046] Figure 7 It is a schematic cross-sectional view of a structure obtained in step S154 in a method for preparing a semiconductor device provided in another embodiment.

[0047] Description of Reference Numerals

[0048] 10. Substrate; 101. Active area; 102. Gate structure; 20. Source pad; 201. First-layer source pad; 202. Second-layer source pad; 30. Gate pad; 301. First-layer gate pad; 302. Second-layer gate pad; 40. First dielectric layer; 50. Second dielectric layer; 60. First metal layer. DETAILED DESCRIPTION

[0049] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0051] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0052] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0053] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0055] In the performance evaluation of power devices such as silicon carbide metal oxide field effect transistors, the specific on-resistance value is an important indicator for evaluating the performance of unipolar power devices. The smaller the value of the specific on-resistance, the better the performance of the device. Among them, the value of the specific on-resistance is negatively correlated with the area of ​​the active region.

[0056] However, in conventional technology, the gate pad and the source pad occupy a large area of ​​the chip, resulting in a smaller active area, which in turn increases the value of the on-resistance and reduces the reliability and electrical performance of the device.

[0057] The present invention provides a semiconductor device. Figure 1 The semiconductor device may include: a substrate 10, a source pad 20, and a gate pad 30. The substrate 10 includes multiple active regions 101 and multiple gate structures 102. The multiple active regions 101 are spaced apart along a first direction within the substrate 10. The multiple gate structures 102 are spaced apart along the first direction on the top surface of the substrate 10. The gate structures 102 cover portions of the active regions 101, and the gate structures 102 and the active regions 101 are staggered. The source pad 20 includes a first layer of source pads 201 and a second layer of source pads 202. The first layer of source pads 201 covers the gate structures 102 and the active regions 101, and the second layer of source pads 202 covers portions of the top surface of the first layer of source pads 201. The gate pad 30 includes a first-layer gate pad 301 and a second-layer gate pad 302, wherein the first-layer gate pad 301 covers a portion of the top surface of the substrate 10, and the second-layer gate pad 302 covers a portion of the top surface of the first-layer gate pad 301 and the first-layer source pad 201, wherein the source pad 20 and the gate pad 30 are insulated.

[0058] By way of example, the substrate 10 may include, but is not limited to, a silicon carbide (SiC) substrate.

[0059] Exemplarily, the gate structure 102 can include a gate conductive layer, a gate oxide layer and a gate electrode. The material of the gate conductive layer can include but is not limited to a conductive layer, for example, a doped polysilicon gate conductive layer. The size of the gate conductive layer in the second direction can be 30 nm to 50 nm, for example, the size of the gate conductive layer in the second direction can be 30 nm, 40 nm or 50 nm. The gate oxide layer can include but is not limited to an oxide layer, for example, a silicon dioxide layer. The gate electrode can include but is not limited to a metal gate electrode. The size of the gate oxide layer in the second direction can be 300 nm to 500 nm, for example, the size of the gate oxide layer in the second direction can be 300 nm, 400 nm or 500 nm, etc.

[0060] Exemplarily, the first direction is the OX direction as shown in Figure 1 Exemplarily, the second direction is the OY direction as shown in Figure 1 Exemplarily, the second direction is the OY direction as shown in

[0061] Exemplarily, the active region 101 includes a source region and a drain region and a well region at the bottom of the source region and the drain region. It should be noted that the semiconductor device can further include a source electrode and a drain electrode, the source electrode covers the top surface of the source region, and the drain electrode is located on the top surface of the drain region.

[0062] Exemplarily, the material of the source pad 20 can include but is not limited to copper or other conductive materials. The material of the gate pad 30 can include but is not limited to copper or other conductive materials.

[0063] The semiconductor device of the present application includes a substrate 10, a source pad 20, and a gate pad 30. The substrate 10 includes multiple active areas 101 and multiple gate structures 102. The multiple active areas 101 are spaced apart along a first direction within the substrate 10. The multiple gate structures 102 are spaced apart along the first direction on the top surface of the substrate 10. The gate structures 102 cover portions of the active areas 101, and the gate structures 102 and the active areas 101 are staggered. The gate pad 30 includes a first layer of gate pads 301 and a second layer of gate pads 302. The first layer of gate pads 301 covers a portion of the top surface of the substrate 10 and can provide an electrical connection point for the electrical extraction of the gate. The second layer of gate pads 302 covers a portion of the top surface of the first layer of gate pads 301 and the first layer of source pads 201, and can connect the first layer of gate pads 301 to a circuit, thereby achieving electrical connection of the gate in the circuit. The coverage area of ​​the first-layer gate pad 301 is smaller than that of the second-layer gate pad 302, which can save space at the bottom of the second-layer gate pad 302. This allows the formation of a cell at the bottom of the second-layer gate pad 302, thereby increasing the area of ​​the active area 101, reducing the device's specific on-resistance, and improving the reliability and electrical performance of the semiconductor device. The coverage area of ​​the first-layer source pad 201 is larger than that of the second-layer source pad 202. This allows the first-layer source pad 201 to provide an electrical connection point for the source electrode for the increased active area 101 without changing the coverage area of ​​the gate pad 30 and source pad 20, and connects to the circuit through the second-layer source pad 202, thereby achieving electrical connection of the source electrode.

[0064] In some embodiments, please refer to Figure 1 The size of the first layer gate pad 301 in the first direction is smaller than the size of the first layer source pad 201 in the first direction. The size of the first layer source pad 201 in the first direction is smaller than the size of the second layer source pad 202 in the first direction.

[0065] In the semiconductor device provided in the embodiments of the present application, by setting the size of the first-layer gate pad 301 in the first direction to be smaller than the size of the first-layer source pad 201 in the first direction, the first-layer gate pad 301 can save space, thereby increasing the coverage area of ​​the first-layer source pad 201, and thus allowing more cells to be arranged below the first-layer source pad 201, thereby increasing the area of ​​the active area 101, reducing the device's specific on-resistance value, and improving the electrical performance of the semiconductor device. By setting the size of the first-layer source pad 201 in the first direction to be smaller than the size of the second-layer source pad 202 in the first direction, the first-layer source pad 201 can be electrically guided out using the second-layer source pad 202 while the first-layer source pad 201 completely covers the active area 101, thereby connecting the source to the circuit and achieving electrical connection of the source.

[0066] In some embodiments, please refer to Figure 1 The semiconductor device further includes: a first dielectric layer 40, the first dielectric layer 40 covering the first-layer source pad 201 and the first-layer gate pad 301, and the first dielectric layer 40 is located between the first-layer gate pad 301 and the second-layer gate pad 302, and between the first-layer source pad 201 and the second-layer gate pad 302; wherein the first dielectric layer 40 includes a first notch and a second notch, the first-layer gate pad 301 and the second-layer gate pad 302 are connected through the first notch, and the first-layer source pad 201 and the second-layer source pad 202 are connected through the second notch.

[0067] As an example, the material of the first dielectric layer 40 may include but is not limited to silicon oxide (SiO2), silicon nitride (SiN x ), aluminum oxide (Al2O3), low dielectric constant (Low-k) materials, high dielectric constant (High-k) materials, etc.

[0068] As an example, the dimensions of the first notch and the second notch in the first direction can be set according to the actual usage requirements of the semiconductor device to ensure electrical connection between the first layer gate pad 301 and the second layer gate pad 302, and between the first layer source pad 201 and the second layer source pad 202.

[0069] The semiconductor device provided in the embodiments of the present application, by providing a first dielectric layer 40, can separate the source pad 20 and the gate pad 30, thereby achieving electrical isolation of the semiconductor device and enabling efficient signal transmission in a multi-layer interconnect structure. Providing a first notch and a second notch in the first dielectric layer 40 can achieve electrical connection between the first-layer gate pad 301 and the second-layer gate pad 302, and between the first-layer source pad 201 and the second-layer source pad 202, thereby achieving efficient signal transmission.

[0070] In some embodiments, please refer to Figure 1 The semiconductor device further includes a second dielectric layer 50 , and the second dielectric layer 50 covers the gate structure 102 .

[0071] As an example, the material of the second dielectric layer 50 may include but is not limited to silicon oxide (SiO2), silicon nitride (SiN x ), aluminum oxide (Al2O3), low dielectric constant (Low-k) materials, high dielectric constant (High-k) materials, etc. The thickness of the second dielectric layer 50 can be 800nm~1100nm, for example, the thickness of the second dielectric layer 50 can be 800nm, 900nm, 1000nm or 1100nm, etc.

[0072] The semiconductor device provided in the embodiments of the present application can realize electrical isolation between the gate structure 102 and other film layers by arranging the second dielectric layer 50, so as to realize signal transmission.

[0073] It should be noted that the semiconductor device in the embodiments of the present application can further include a metal silicide layer, which is located between the active region 101 and the first layer source pad 201, so as to reduce the contact resistance of the device.

[0074] It should be noted that the semiconductor device in the embodiments of the present application can further include a passivation layer, which covers the gate pad 30, the source pad 20 and the first dielectric layer 40, and the passivation layer can protect the device in the packaging process.

[0075] The embodiments of the present application provide an electronic device including the semiconductor device in any of the above embodiments.

[0076] The electronic device of the present application includes a substrate, a source pad and a gate pad. The substrate includes a plurality of active regions and a plurality of gate structures. The plurality of active regions are spaced apart in the substrate along a first direction. The plurality of gate structures are spaced apart on the top surface of the substrate along the first direction. The gate structure covers part of the active region, and the gate structure and the active region are staggered. The gate pad includes a first layer gate pad and a second layer gate pad. The first layer gate pad covers part of the top surface of the substrate, and can provide an electrical connection point for electrical lead-out of the gate. The second layer gate pad covers part of the top surface of the first layer gate pad and the first layer source pad, and can connect the first layer gate pad to a circuit, thereby realizing electrical connection of the gate in the circuit. The coverage area of the first layer gate pad is smaller than that of the second layer gate pad, which can save space and increase the area of the active region, thereby reducing the specific on-resistance of the device and improving the reliability and electrical properties of the semiconductor device. The coverage area of the first layer source pad is larger than that of the second layer source pad, which can provide an electrical connection point for the increased active region through the first layer source pad without changing the coverage area of the gate pad and the source pad, and the second layer source pad is connected to the circuit, thereby realizing electrical connection of the source.

[0077] The embodiments of the present application provide a preparation method of a semiconductor device, please refer to Figure 2 The preparation method of the semiconductor device can include:

[0078] S11: providing a substrate, the substrate includes a plurality of active regions and a plurality of gate structures, the plurality of active regions are spaced apart in the substrate along a first direction, the plurality of gate structures are spaced apart on the top surface of the substrate along the first direction, the gate structure covers part of the active region, and the gate structure and the active region are staggered.

[0079] As an example, please refer to Figure 3 The substrate 10 may include but is not limited to a silicon carbide (SiC) substrate.

[0080] As an example, see Figure 3 The gate structure 102 may include a gate conductive layer, a gate oxide layer, and a gate electrode. The gate conductive layer may include, but is not limited to, a conductive layer, such as a doped polysilicon gate conductive layer or a metal gate conductive layer. Specifically, in this embodiment, the gate conductive layer is a doped polysilicon gate conductive layer. The size of the gate conductive layer in the second direction may be 30nm~50nm, such as, the size of the gate conductive layer in the second direction may be 30nm, 40nm or 50nm. The gate oxide layer may include, but is not limited to, an oxide layer, such as a silicon dioxide layer. The gate electrode may include, but is not limited to, a metal gate electrode. The size of the gate oxide layer in the second direction may be 300nm~500nm, such as, the size of the gate oxide layer in the second direction may be 300nm, 400nm or 500nm, etc.

[0081] As an example, see Figure 3 The active region 101 includes a source region, a drain region, and a well region located at the bottom of the source and drain regions. The active region can be formed by, but is not limited to, ion implantation. It should be noted that the semiconductor device also includes a source electrode and a drain electrode. The source electrode covers the top surface of the source region, and the drain electrode is located on the top surface of the drain region.

[0082] As an example, the first direction is as follows Figure 3 The second direction is as shown in Figure 3 The OY direction is shown in .

[0083] S15: forming a source pad and a gate pad on the top surface of the substrate, wherein the source pad comprises a first layer of source pad and a second layer of source pad, the first layer of source pad covers the gate structure and the active area, the second layer of source pad covers a portion of the top surface of the first layer of source pad, the gate pad comprises a first layer of gate pad and a second layer of gate pad, the first layer of gate pad covers a portion of the top surface of the substrate, the second layer of gate pad covers a portion of the top surface of the first layer of gate pad and the first layer of source pad, wherein the source pad and the gate pad are insulated.

[0084] As an example, see Figure 1 The material of the source pad 20 may include, but is not limited to, copper or other conductive materials. The material of the gate pad 30 may include, but is not limited to, copper or other conductive materials.

[0085] The method for manufacturing the semiconductor device of the present application comprises the following steps: providing a substrate, the substrate comprising a plurality of active regions and a plurality of gate structures, the plurality of active regions being spaced apart in the substrate along a first direction, the plurality of gate structures being distributed on the top surface of the substrate along the first direction, the gate structures covering part of the active regions, and the gate structures and the active regions being staggered. A source pad and a gate pad are formed on the top surface of the substrate, wherein the source pad comprises a first layer of source pads and a second layer of source pads, the first layer of source pads covering the gate structures and the active regions, the second layer of source pads covering part of the top surface of the first layer of source pads, the gate pad comprises a first layer of gate pads and a second layer of gate pads, the first layer of gate pads covering part of the top surface of the substrate, the second layer of gate pads covering part of the top surface of the first layer of gate pads and the first layer of source pads, and the source pad and the gate pad being insulated. The first layer of gate pads provides an electrical connection point for the electrical lead-out of the gate, and the second layer of gate pads connects the first layer of gate pads to a circuit, thereby realizing the electrical connection of the gate in the circuit. The coverage area of the first layer of gate pads is smaller than that of the second layer of gate pads, thereby saving space, increasing the area of the active regions, reducing the specific on-resistance of the device, and improving the reliability and electrical properties of the semiconductor device. The coverage area of the first layer of source pads is larger than that of the second layer of source pads, thereby providing an electrical connection point for the source of the added active regions through the first layer of source pads without changing the coverage area of the gate pad and the source pad, and connecting to the circuit through the second layer of source pads, thereby realizing the electrical connection of the source.

[0086] In some embodiments, referring to Figure 4 forming the source pad and the gate pad on the top surface of the substrate comprises:

[0087] S151: forming a first metal layer on the top surface of the substrate.

[0088] As an example, referring to Figure 5 the first metal layer 60 can be formed on the top surface of the substrate by, but not limited to, a molecular beam epitaxy (MBE), a physical vapor deposition (PVD), a chemical vapor deposition (CVD), or an atomic layer deposition (ALD). Specifically, in the present embodiment, the first metal layer 60 is formed by a physical vapor deposition. The material of the first metal layer can include, but is not limited to, copper.

[0089] S152: etching the first metal layer to form a first layer of gate pads and a first layer of source pads.

[0090] As an example, see Figure 1 The first metal layer 60 may be etched using, but not limited to, a photolithography process to form a first-layer gate pad 301 and a first-layer source pad 201 .

[0091] S155: forming a second metal layer on top surfaces of the first-layer gate pad and the first-layer source pad.

[0092] As an example, a second metal layer (not shown) may be formed on the top surfaces of the first gate pad and the first source pad using, but not limited to, a molecular beam epitaxy process, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. Specifically, in this embodiment, the second metal layer is formed using a physical vapor deposition process. The material of the second metal layer may include, but is not limited to, copper.

[0093] S156: Etching the second metal layer to form a second gate pad and a second source pad.

[0094] As an example, see Figure 1 The second metal layer may be etched using, but not limited to, a photolithography process to form a second-layer gate pad 302 and a second-layer source pad 202 .

[0095] The method for fabricating a semiconductor device in an embodiment of the present application forms a first metal layer on the top surface of a substrate and then etches the first metal layer to form a first gate pad and a first source pad. The first source pad can be formed simultaneously with the first gate pad, simplifying the process steps and flow. The first metal layer can be etched according to the actual use requirements of the semiconductor device to obtain first gate pads and first source pads of different sizes, thereby enhancing the applicability of the semiconductor device. Furthermore, a second metal layer is formed on the top surface of the first gate pad and the first source pad, and then the second metal layer is etched to form second gate pads and second source pads. The second source pad can be formed simultaneously with the second gate pad, simplifying the process steps and process of the semiconductor device. The second metal layer can be etched according to the actual use requirements of the semiconductor device to obtain second gate pads and second source pads of different sizes, further enhancing the applicability of the semiconductor device.

[0096] In some embodiments, see Figure 6 After etching the first metal layer and before forming the second metal layer on top of the first gate pad and the second gate pad, the method for preparing the semiconductor device further includes:

[0097] S153: forming a first dielectric material layer on top surfaces of the first layer of gate pads and the first layer of source pads.

[0098] As an example, a first dielectric material layer (not shown) may be formed on the top surfaces of the first gate pad 301 and the first source pad 201 using, but not limited to, a molecular beam epitaxy process, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The material of the first dielectric material layer may include, but is not limited to, silicon oxide, silicon nitride, aluminum oxide, a low-k dielectric constant material, a high-k dielectric constant material, and the like.

[0099] S154: Etching the first dielectric material layer to form a first dielectric layer, the first dielectric layer including a first notch and a second notch, the first layer gate pad and the second layer gate pad are connected through the first notch, and the first layer source pad and the second layer source pad are connected through the second notch.

[0100] As an example, see Figure 7 The first dielectric material layer may be etched using, but is not limited to, a photolithography process.

[0101] As an example, the dimensions of the first notch and the second notch in the first direction can be set according to the actual usage requirements of the semiconductor device to ensure electrical connection between the first layer gate pad 301 and the second layer gate pad 302, and between the first layer source pad 201 and the second layer source pad 202.

[0102] The method for fabricating a semiconductor device provided in an embodiment of the present application forms a first dielectric material layer on the top surfaces of the first-layer gate pad and the first-layer source pad, and then etches the first dielectric material layer to form a first dielectric layer. This layer can electrically isolate the first-layer gate pad from the first-layer source pad. Furthermore, etching to form a first notch and a second notch can achieve electrical connections between the first-layer gate pad and the second-layer gate pad, and between the first-layer source pad and the second-layer source pad.

[0103] In some embodiments, see Figure 1 The size of the first layer gate pad 301 in the first direction is smaller than the size of the first layer source pad 201 in the first direction. The size of the first layer source pad 201 in the first direction is smaller than the size of the second layer source pad 202 in the first direction.

[0104] The method for manufacturing a semiconductor device provided in an embodiment of the present application saves space by setting the size of the first-layer gate pad in the first direction to be smaller than the size of the first-layer source pad in the first direction, thereby increasing the coverage area of ​​the first-layer source pad. This allows more cells to be arranged below the first-layer source pad, thereby increasing the area of ​​the active area, reducing the device's specific on-resistance, and improving the electrical properties of the semiconductor device. By setting the size of the first-layer source pad in the first direction to be smaller than the size of the second-layer source pad in the first direction, the first-layer source pad can be electrically guided out using the second-layer source pad while the first-layer source pad completely covers the active area, thereby connecting the source electrode to the circuit and achieving electrical connection of the source electrode.

[0105] In some embodiments, after providing the substrate and before forming the source pad and the gate pad on the top surface of the substrate, the method further includes:

[0106] S12: forming a second dielectric layer, where the second dielectric layer covers the gate structure.

[0107] As an example, see Figure 1 The second dielectric layer 50 can be formed using, but is not limited to, molecular beam epitaxy, physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The material of the second dielectric layer 50 can include, but is not limited to, silicon oxide, silicon nitride, aluminum oxide, a low-k material, a high-k material, etc. The thickness of the second dielectric layer 50 can be 800 nm to 1100 nm. For example, the thickness of the second dielectric layer 50 can be 800 nm, 900 nm, 1000 nm, or 1100 nm.

[0108] The method for preparing a semiconductor device provided in an embodiment of the present application forms a second dielectric layer, and the second dielectric layer covers the gate structure, thereby achieving electrical isolation between the gate structure and other structures, thereby improving the electrical properties of the semiconductor device.

[0109] It should be noted that, after forming the second dielectric layer, the method for preparing the semiconductor device in the embodiment of the present application may further include:

[0110] S13: Etching the second dielectric layer to expose the active area.

[0111] As an example, see Figure 1 The second dielectric layer 50 may be etched using, but not limited to, a photolithography process.

[0112] S14: forming a metal silicide layer, wherein the metal silicide layer covers the exposed surface of the active region.

[0113] As an example, but not limited to, a metal silicide layer (not shown) is formed by a molecular beam epitaxy process, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The metal silicide layer can reduce the contact resistance of the device.

[0114] It should be noted that the method for preparing the semiconductor device in the embodiment of the present application may also include the step of forming a passivation layer, which covers the gate pad, the source pad and the first dielectric layer. The passivation layer can protect the device during the packaging process.

[0115] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that: include: a substrate comprising a plurality of active regions and a plurality of gate structures, wherein the plurality of active regions are spaced apart along a first direction within the substrate, the plurality of gate structures are spaced apart along the first direction on a top surface of the substrate, the gate structures partially covering the active regions, and the gate structures and the active regions are staggered; A source pad, comprising a first layer of source pads and a second layer of source pads, wherein the first layer of source pads covers the gate structure and the active area, and the second layer of source pads covers a portion of a top surface of the first layer of source pads; A gate pad, comprising a first layer of gate pads and a second layer of gate pads, wherein the first layer of gate pads covers a portion of the top surface of the substrate, and the second layer of gate pads covers a portion of the top surface of the first layer of gate pads and the first layer of source pads, wherein the source pads and the gate pads are insulated; The size of the first layer gate pad in the first direction is smaller than the size of the first layer source pad in the first direction; The size of the first layer source pad in the first direction is smaller than the size of the second layer source pad in the first direction; The coverage area of ​​the first layer gate pad is smaller than the coverage area of ​​the second layer gate pad, and the coverage area of ​​the first layer source pad is larger than the coverage area of ​​the second layer source pad.

2. The semiconductor device according to claim 1, wherein Also includes: a first dielectric layer, the first dielectric layer covering the first source pad and the first gate pad, and the first dielectric layer being located between the first gate pad and the second gate pad, and between the first source pad and the second gate pad; The first dielectric layer includes a first notch and a second notch, the first layer gate pad is connected to the second layer gate pad through the first notch, and the first layer source pad is connected to the second layer source pad through the second notch.

3. The semiconductor device according to claim 1, wherein Also includes: A second dielectric layer covers the gate structure.

4. An electronic device, characterized in that: include: The semiconductor device according to any one of claims 1 to 3.

5. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a plurality of active regions and a plurality of gate structures, the plurality of active regions being spaced apart along a first direction within the substrate, the plurality of gate structures being spaced apart along the first direction on a top surface of the substrate, the gate structures covering portions of the active regions, and the gate structures and the active regions being staggered; forming a source pad and a gate pad on the top surface of the substrate, wherein the source pad includes a first layer of source pads and a second layer of source pads, the first layer of source pads covers the gate structure and the active area, the second layer of source pads covers a portion of the top surface of the first layer of source pads, and the gate pad includes a first layer of gate pads and a second layer of gate pads, the first layer of gate pads covers a portion of the top surface of the substrate, and the second layer of gate pads covers a portion of the top surface of the first layer of gate pads and the first layer of source pads, wherein the source pad and the gate pad are insulated; The size of the first layer gate pad in the first direction is smaller than the size of the first layer source pad in the first direction; The size of the first layer source pad in the first direction is smaller than the size of the second layer source pad in the first direction; The coverage area of ​​the first layer gate pad is smaller than the coverage area of ​​the second layer gate pad, and the coverage area of ​​the first layer source pad is larger than the coverage area of ​​the second layer source pad.

6. The method for preparing a semiconductor device according to claim 5, wherein: The forming of a source pad and a gate pad on the top surface of the substrate includes: forming a first metal layer on the top surface of the substrate; Etching the first metal layer to form the first gate pad and the first source pad; forming a second metal layer on top surfaces of the first layer of gate pads and the first layer of source pads; The second metal layer is etched to form the second gate pad and the second source pad.

7. The method for preparing a semiconductor device according to claim 6, wherein: After etching the first metal layer and before forming the second metal layer on the top surfaces of the first gate pad and the second gate pad, the method further includes: forming a first dielectric material layer on top surfaces of the first layer of gate pads and the first layer of source pads; The first dielectric material layer is etched to form a first dielectric layer, wherein the first dielectric layer includes a first notch and a second notch, the first layer gate pad is connected to the second layer gate pad through the first notch, and the first layer source pad is connected to the second layer source pad through the second notch.

8. The method for preparing a semiconductor device according to claim 5, wherein: After providing the substrate and before forming the source pad and the gate pad on the top surface of the substrate, the method further includes: A second dielectric layer is formed, where the second dielectric layer covers the gate structure.

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