Semiconductor device and method of manufacturing the same, electronic device

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, and an electronic device, and relates to the technical field of semiconductors, and aims to improve the reliability of the semiconductor device. The semiconductor device comprises a substrate, an epitaxial layer located on one side of the substrate, a channel part and a gate semiconductor layer located on the side of the epitaxial layer away from the substrate, a source contact layer located on the side of the channel part away from the substrate, and a drain located on the side of the substrate away from the epitaxial layer. The channel part comprises a first channel subpart and a second channel subpart connected to each other, and the first channel subpart is located between the epitaxial layer and the second channel subpart. The gate semiconductor layer surrounds the first channel subpart. The source contact layer is located on the second channel subpart, and the second channel subpart separates the source contact layer and the gate semiconductor layer. The drain is located on the side of the substrate away from the epitaxial layer. The semiconductor device is applied to a power electronic device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and particularly relates to a semiconductor device and a preparation method thereof, and an electronic device. BACKGROUND

[0002] A junction field-effect transistor (JFET) has the advantages of simple structure and reliable performance, and is widely used as an electrically controlled switch structure in traditional silicon (Si) and wide-bandgap semiconductor (such as silicon carbide (SiC), gallium nitride (GaN), etc.) electronic devices. The JFET is a unipolar electronic device, that is, in the case that the JFET is in an open state, only one type of carrier flows in the channel of the JFET to form a conduction current between the source and the drain. The gate and the channel of the JFET form a PN junction, and in the case of a normally open JFET, by applying a voltage to the gate, the PN junction can be reversely biased to the channel pinch-off voltage to turn off the JFET.

[0003] The JFET mainly includes a vertical JFET, a channel of the vertical JFET extending along the thickness direction of the substrate, and the source and the drain being located on the upper and lower sides of the channel, which is beneficial to reduce the area of the vertical JFET and improve the integration of the device to which the vertical JFET is applied.

[0004] However, the vertical JFET has the problem of low breakdown voltage between the gate and the source, which reduces the reliability of the vertical JFET. SUMMARY

[0005] Embodiments of the present disclosure provide a semiconductor device and a preparation method thereof, and an electronic device, aiming to improve the reliability of the semiconductor device.

[0006] To achieve the above object, embodiments of the present disclosure adopt the following technical solutions:

[0007] In a first aspect, a semiconductor device is provided, the semiconductor device comprising: a substrate, an epitaxial layer, a channel portion, a gate semiconductor layer, a source contact layer, and a drain. The epitaxial layer is located on one side of the substrate. The channel portion is located on a side of the epitaxial layer away from the substrate, the channel portion comprising a first channel sub-portion and a second channel sub-portion connected in series, the first channel sub-portion being located between the epitaxial layer and the second channel sub-portion. The gate semiconductor layer is located on a side of the epitaxial layer away from the substrate, and surrounds the first channel sub-portion. The source contact layer is located on a side of the second channel sub-portion away from the substrate. The second channel sub-portion separates the source contact layer and the gate semiconductor layer. The drain is located on a side of the substrate away from the epitaxial layer.

[0008] The semiconductor device provided by some embodiments of the present disclosure divides the channel portion into the first channel sub-portion and the second channel sub-portion, and arranges the first channel sub-portion between the epitaxial layer and the second channel sub-portion, and adjusts the arrangement between the gate semiconductor layer and the channel portion, so that the gate semiconductor layer surrounds the first channel sub-portion, and the second channel sub-portion separates the gate semiconductor layer and the second channel sub-portion. That is, by adjusting the structure included in the semiconductor device itself, the distance between the gate semiconductor layer and the second channel sub-portion is increased. The adjustment of the structure is ingenious, which can effectively improve the breakdown voltage between the gate and the source and enhance the reliability of the semiconductor device without adding additional structures.

[0009] In some embodiments, a normal projection of an end of the first channel sub-portion contacting the second channel sub-portion on the substrate is within a normal projection of an end of the second channel sub-portion contacting the first channel sub-portion on the substrate.

[0010] In some embodiments, the first channel sub-portion includes the first part and the second part connected to each other, and the first part is between the epitaxial layer and the second part. A normal projection of the second part on the substrate is within a normal projection of the first part on the substrate.

[0011] In some embodiments, a distance between a normal projection boundary of the second part on the substrate and a normal projection boundary of the first part on the substrate ranges from 0.1 μm to 1 μm.

[0012] In some embodiments, a normal projection of the second channel sub-portion on the substrate coincides with a normal projection of the first part on the substrate.

[0013] In some embodiments, the semiconductor device further includes a current diffusion layer. The current diffusion layer is between the epitaxial layer and the first channel sub-portion and contacts the first channel sub-portion. A normal projection of the first channel sub-portion on the substrate is within a normal projection of the current diffusion layer on the substrate.

[0014] In some embodiments, the current diffusion layer and the first channel sub-portion are in an integrated structure.

[0015] In some embodiments, the number of channel portions is a plurality, and the gate semiconductor layer surrounds the first channel sub-portion of the plurality of channel portions. The second channel sub-portion of each channel portion is provided with a source contact layer away from the side of the substrate, and at least two source contact layers are electrically connected.

[0016] In some embodiments, the semiconductor device further includes a source, a first ohmic contact layer, a gate, and a second ohmic contact layer. The source is located away from the side of the substrate of the source contact layer. The first ohmic contact layer is located between the source contact layer and the source. The gate is located away from the side of the substrate of the gate semiconductor layer. The second ohmic contact layer is located between the gate semiconductor layer and the gate.

[0017] In some embodiments, the semiconductor device further comprises: a plurality of annular protrusions and a field-limiting ring. The plurality of annular protrusions are located on a side of the epitaxial layer away from the substrate and are arranged in a ring-like manner. The plurality of annular protrusions surround the channel portion and the gate semiconductor layer. The field-limiting ring is located on a side of the epitaxial layer away from the substrate and is located between two adjacent annular protrusions.

[0018] In some embodiments, the gate semiconductor layer includes a first gate layer and a second gate layer connected to each other. The first gate layer surrounds the first channel sub-portion, and a surface of the second gate layer on a side remote from the substrate is lower than a surface of the first gate layer on a side remote from the substrate. The second gate layer is made of the same material as the field limiting ring and is disposed on the same layer.

[0019] In some embodiments, the annular protrusion includes a first annular sub-protrusion and a second annular sub-protrusion connected to each other, wherein the first annular sub-protrusion is located between the epitaxial layer and the second annular sub-protrusion. The first annular sub-protrusion and the first channel sub-portion are disposed in the same layer. The second annular sub-protrusion and the second channel sub-portion are made of the same material and disposed in the same layer.

[0020] In a second aspect, a method for fabricating a semiconductor device is provided, the method comprising: providing a substrate. Forming an epitaxial layer, a channel portion, a gate semiconductor layer, and a source contact layer on one side of the substrate; the channel portion is located on a side of the epitaxial layer away from the substrate; the channel portion includes a first channel sub-portion and a second channel sub-portion connected to each other, with the first channel sub-portion located between the epitaxial layer and the second channel sub-portion; the gate semiconductor layer is located on a side of the epitaxial layer away from the substrate and surrounds the first channel sub-portion; the source contact layer is located on a side of the second channel sub-portion away from the substrate; the second channel sub-portion separates the source contact layer and the gate semiconductor layer; and forming a drain on a side of the substrate away from the epitaxial layer.

[0021] In some embodiments, forming an epitaxial layer, a channel portion, a gate semiconductor layer, and a source contact layer on one side of a substrate includes: forming an epitaxial thin film on one side of the substrate. Performing a first ion implantation from a side of the epitaxial thin film away from the substrate to form a first doped region. Forming a first mask pattern on a side of the epitaxial thin film away from the substrate, the first mask pattern covering a portion of the first doped region and exposing another portion of the first doped region. Based on the first mask pattern, performing a second ion implantation from a side of the epitaxial thin film away from the substrate to form a second doped region; the portion of the first doped region opposite the second doped region constitutes a second portion of the first channel sub-portion, and the second doped region is used to constitute the gate semiconductor layer. Forming a second channel sub-portion and a source contact layer on a side of the epitaxial thin film away from the substrate; the second channel sub-portion covers the first doped region and a portion of the second doped region.

[0022] In some embodiments, the forming the epitaxial layer, the channel portion, the gate semiconductor layer and the source contact layer on one side of the substrate further comprises: etching and thinning the second doped region based on the second channel sub-portion and the source contact layer; forming a third doped region by performing a third ion implantation on the epitaxial film away from the one side of the substrate based on the second channel sub-portion and the source contact layer, the third doped region being connected with the second doped region to form the gate semiconductor layer.

[0023] In some embodiments, the epitaxial film has a termination region surrounding an active region, and the channel portion and the gate semiconductor layer are located in the active region. In the process of forming the second channel sub-portion and the source contact layer on the epitaxial film away from the one side of the substrate, a second annular sub-bump is also formed on the epitaxial film away from the one side of the substrate, and the second annular sub-bump is located in the termination region. In the process of etching and thinning the second doped region based on the second channel sub-portion and the source contact layer, a portion of the epitaxial film located in the termination region is also thinned based on the second channel sub-portion and the source contact layer. In the process of forming the third doped region, a field limiting ring is also formed by performing a third ion implantation on the portion of the epitaxial film located in the termination region based on the second annular sub-bump, and a portion located between the second annular sub-bump and the substrate and in contact with the field limiting ring forms a first annular sub-bump.

[0024] In some embodiments, before forming the drain on the side of the substrate away from the epitaxial layer, the preparation method further comprises: forming a first ohmic contact layer on the side of the source contact layer away from the substrate, and forming a second ohmic contact layer on the side of the gate semiconductor layer away from the substrate. A dielectric layer covering the first ohmic contact layer and the second ohmic contact layer is formed. The source and the gate are formed; the source penetrates through the dielectric layer to the first ohmic contact layer, and the gate penetrates through the dielectric layer to the second ohmic contact layer.

[0025] In a third aspect, an electronic device is provided, which includes: a semiconductor device and a circuit board, the circuit board being electrically connected with the semiconductor device. The semiconductor device is the semiconductor device according to any one of the first aspect.

[0026] The technical effects brought by any one of the embodiments of the second aspect to the third aspect can refer to the technical effects brought by different embodiments of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure.

[0028] Figure 1 The structural diagram of the electronic device according to some embodiments;

[0029] Figure 2 The structure of the semiconductor device according to some embodiments Figure 1 ;

[0030] Figure 3 Structure of a semiconductor device according to some embodiments Figure 2 ;

[0031] Figure 4 Simulated electric field distribution between gate and source of a semiconductor device according to some embodiments

[0032] Figure 5 Simulated electric field strength along a sampling line of a semiconductor device according to some embodiments Figure 4 along the Y-axis shown

[0033] Figure 6 Structure of a semiconductor device according to some embodiments Figure 3 ;

[0034] Figure 7 Structure of a semiconductor device according to some embodiments Figure 4 ;

[0035] Figure 8 Structure of a semiconductor device according to some embodiments Figure 5 ;

[0036] Figure 9 Structure of a semiconductor device according to some embodiments Figure 6 ;

[0037] Figure 10 Flow chart of a method of manufacturing a semiconductor device according to some embodiments

[0038] Figures 11a-11l Structure corresponding to each step of a method of manufacturing a semiconductor device according to some embodiments Figure 1 ;

[0039] Figures 12a-12c Structure corresponding to each step of a method of manufacturing a semiconductor device according to some embodiments Figure 2 ;

[0040] Figure 13a Transfer characteristic curve of a semiconductor device shown in Figure 2 ;

[0041] Figure 13b Transfer characteristic curve of a semiconductor device according to some embodiments

[0042] Figure 14a Off-state breakdown current voltage curve of a semiconductor device shown in Figure 2 ;

[0043] Figure 14bA graph of an off-state breakdown current versus voltage for a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. It should be apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0045] In the description of the present disclosure, unless the context requires otherwise, throughout the specification and claims, the term "comprising" is interpreted to mean "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "exemplarily" or "some examples" are intended to mean that the specific feature, structure, material or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0046] Hereinafter, the terms "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0047] In describing some embodiments, "connected" and variations thereof can be used. For example, the term "connected" can be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0048] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0049] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0050] In addition, the use of "based on" means open and inclusive, because the process, step, calculation or other action "based on" one or more stated conditions or values can be based on additional conditions or values beyond those stated in practice.

[0051] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0052] In the context of this disclosure, the meaning of "on the side away from..." should be interpreted in the broadest manner, so that "on the side away from..." not only means "directly on the side of something away from...", but also includes the meaning of "on the side of something away from..." with intervening features or layers in between.

[0053] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0054] Some embodiments of the present application provide an electronic device. The electronic device may be a power electronic device, that is, a device with a power electronic device (also referred to as a semiconductor device or a power semiconductor device) as a main functional element. For example, the electronic device may be a converter, an electronic switch, an electronic AC power controller, a power factor correction (PFC) circuit, etc. Among them, the converter includes but is not limited to a DC chopper (DC / DC, or a DC to DC power supply), a rectifier (AC / DC, or an AC-DC converter), an inverter (DC / AC, or a DC-AC converter), etc., and the electronic switch includes but is not limited to a power switching power supply circuit, etc. The embodiments of the present application do not impose any special restrictions on the specific type of the electronic device.

[0055] Figure 1 1 shows a schematic structural diagram of an electronic device 1000. The electronic device 1000 includes a semiconductor device 100 and a circuit board 200. The circuit board 200 is electrically connected to the semiconductor device 100, and the circuit board 200 is used to provide the semiconductor device 100 with required electrical signals.

[0056] It is understood that the structures illustrated in the embodiments of the present application do not constitute a specific limitation on the electronic device 1000. In other embodiments of the present application, the electronic device 1000 may include more components than shown, or may combine or separate certain components, or may have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0057] Some embodiments of the present disclosure also provide a semiconductor device. This semiconductor device can be used in the above-mentioned electronic device 1000. Optionally, the semiconductor device provided in the embodiments of the present application can be used as the semiconductor device in the above-mentioned electronic device 1000. Of course, the specific application scenarios of the above-mentioned semiconductor device are not limited to this. It is understandable that any electronic device that requires the use of a power semiconductor device falls within the application scenarios of the embodiments of the present application. Alternatively, the semiconductor device provided in the embodiments of the present application can be used alone.

[0058] Figure 2 A structural diagram of a semiconductor device is shown. In some examples, such as Figure 2 As shown, the semiconductor device may include a substrate 1, an epitaxial layer 2, a channel portion 3, a gate semiconductor layer 4, a source contact layer 5, a gate 6, a source electrode 7, and a drain electrode 8. The channel portion 3, the gate semiconductor layer 4, the source contact layer 5, the gate 6, the source electrode 7, and the drain electrode 8 may constitute a JFET.

[0059] Continue reading Figure 2 , epitaxial layer 2 is located on one side of substrate 1. Exemplarily, the materials of substrate 1 and epitaxial layer 2 both include wide bandgap semiconductor materials, including but not limited to silicon carbide, gallium nitride, diamond, etc. Optionally, the materials of substrate 1 and epitaxial layer 2 are the same, for example, both substrate 1 and epitaxial layer 2 are made of silicon carbide.

[0060] Exemplarily, the substrate 1 is an N+ substrate, meaning that the substrate 1 has been subjected to an N-type high-doping treatment (or heavy doping treatment), which can reduce the resistivity of the substrate 1. The epitaxial layer 2 is an N-epitaxial layer, meaning that the epitaxial layer 2 has been subjected to an N-type lightly doping treatment. The epitaxial layer 2 can also be referred to as an N-drift region.

[0061] The channel portion 3 and gate semiconductor layer 4 are both located on the side of the epitaxial layer 2 away from the substrate 1, and the gate semiconductor layer 4 surrounds the channel portion 3. The source contact layer 5 is located on the side of the channel portion 3 away from the substrate 1 and is in contact with the channel portion 3. The gate 6 is located on the side of the gate semiconductor layer 4 away from the substrate 1 and is in contact with the gate semiconductor layer 4; the source electrode 7 is located on the side of the source contact layer 5 away from the substrate 1 and is in contact with the source contact layer 5; and the drain electrode 8 is located on the side of the substrate 1 away from the epitaxial layer 2.

[0062] Exemplarily, the material of the gate 6 and the source 7 is the same. Alternatively, the material of any one of the gate 6 and the source 7 includes but is not limited to metal materials such as titanium, aluminum, gold, silver, copper and alloy materials thereof, or conductive materials such as heavily doped polysilicon, titanium nitride, indium tin oxide, etc. The material of the drain 8 includes but is not limited to metal materials such as nickel, aluminum, titanium, tungsten and alloy materials thereof.

[0063] In the case that the above semiconductor device is in the on state, the gate 6 can receive a suitable voltage, which can be distributed on the gate semiconductor layer 4 to control the semiconductor device to be on, and the current can flow out from the source 7 and conduct downward through the source contact layer 5, the channel part 3, the epitaxial layer 2 and the substrate 1 to the drain 8.

[0064] In some possible implementations, the channel part 3 is formed by ion implantation on the semiconductor structure protruding from the epitaxial layer 2, the source contact layer 5 is formed by ion implantation on the top of the channel part 3, the gate semiconductor layer 4 is formed by ion implantation on the sidewall and bottom of the channel part 3, and the doping type of the channel part 3 and the source contact layer 5 is the same, and the doping type of the channel part 3 is opposite to that of the gate semiconductor layer 4. Alternatively, the doping type of the channel part 3 and the source contact layer 5 is N type, and the doping type of the gate semiconductor layer 4 is P type.

[0065] In order to form the gate semiconductor layer 4, the ion implantation is performed in a tilted manner, that is, the angle of ion implantation is at a certain angle with the extension direction of the channel part 3. Therefore, the angle, depth and dose of ion implantation need to be accurately controlled, which increases the difficulty of preparation of the semiconductor device. Moreover, the tilted ion implantation for forming the gate semiconductor layer 4 results in a very small spacing between the gate semiconductor layer 4 and the source contact layer 5, and further results in a low breakdown voltage between the gate 6 and the source 7, which reduces the reliability of the semiconductor device.

[0066] Based on this, some embodiments of the present disclosure improve the above semiconductor device 100, wherein, Figure 3 A structural diagram of a semiconductor device is shown.

[0067] In some embodiments, as Figure 3 shown, the semiconductor device 100 can include a substrate 1, an epitaxial layer 2, a channel part 3, a gate semiconductor layer 4, a source contact layer 5, a gate 6, a source 7 and a drain 8. As to the substrate 1, the epitaxial layer 2, the gate 6, the source 7 and the drain 8, the related descriptions are provided above, which will not be repeated here.

[0068] In some examples, the channel portion 3 is located on a side of the epitaxial layer 2 away from the substrate 1. The channel portion 3 extends along a thickness direction of the substrate 1. The thickness direction of the substrate 1 refers to a stacking direction of the substrate 1, the epitaxial layer 2, and the channel portion 3.

[0069] With reference to the accompanying drawings being continued, Figure 3 wherein the channel portion 3 includes a first channel sub-portion 31 and a second channel sub-portion 32 connected to each other, and the first channel sub-portion 31 is located between the epitaxial layer 2 and the second channel sub-portion 32. The first channel sub-portion 31 and the second channel sub-portion 32 directly contact each other, for example, the first channel sub-portion 31 and the second channel sub-portion 32 are two independent structures, and there is a clear interface between the two.

[0070] In some examples, as shown in Figure 3 , the gate semiconductor layer 4 is located on a side of the epitaxial layer 2 away from the substrate 1, and surrounds the first channel sub-portion 31. For example, relative to the substrate 1, a side surface of the gate semiconductor layer 4 away from the substrate 1 is flush with a side surface of the first channel sub-portion 31 away from the substrate 1. The gate semiconductor layer 4 does not surround the second channel sub-portion 32; in a direction perpendicular to the thickness direction of the substrate 1, the gate semiconductor layer 4 and the second channel sub-portion 32 do not overlap.

[0071] For example, the first channel sub-portion 31 and the gate semiconductor layer 4 are both formed by doping a semiconductor material, and the doping type of the first channel sub-portion 31 is opposite to the doping type of the gate semiconductor layer 4. Optionally, the doping type of the first channel sub-portion 31 is N-type, and the doping type of the gate semiconductor layer 4 is P-type.

[0072] In some examples, as shown in Figure 3 , the source contact layer 5 is located on a side of the second channel sub-portion 32 away from the substrate 1. Wherein, the gate semiconductor layer 4 is located below the second channel sub-portion 32, the second channel sub-portion 32 separates the source contact layer 5 and the gate semiconductor layer 4, and the source contact layer 5 and the gate semiconductor layer 4 do not directly contact each other.

[0073] Correspondingly, the distance between the source contact layer 5 and the gate semiconductor layer 4 is increased. In this way, the breakdown voltage between the gate 6 and the source 7 can be effectively improved.

[0074] The embodiments of the present disclosure respectively simulate the semiconductor devices shown in Figure 2 and Figure 3 , and the simulation results are shown in Figure 4 . Among them, Figure 4 (a) in Figure 2 is an electric field distribution diagram between the gate 6 and the source 7 in the semiconductor device shown in Figure 4 (b) in Figure 3The electric field distribution between the gate 6 and the source 7 in the semiconductor device shown. Figure 5 To Figure 2 And Figure 3 The simulated electric field of the semiconductor device shown along Figure 4 The sampling line distribution curve of the Y-axis shown.

[0075] As Figure 4 (a) and Figure 5 (b) in the figure show, when the voltage difference (V GS ) between the gate 6 and the source 7 is -20V, the semiconductor device is off, at this time, Figure 2 The semiconductor device shown has a high field (about 3.2MV / cm) between the gate 6 and the source 7. This means that the PN junction formed between the gate 6 and the source 7 has been reverse breakdown. And under the same V GS , as Figure 4 (a) and Figure 5 (b) in the figure show, Figure 3 The semiconductor device shown has a PN junction electric field between the gate 6 and the source 7 less than 1.5MV / cm, less than the breakdown field. This means that Figure 3 The gate voltage range of the semiconductor device shown has been improved, and the breakdown voltage range between the gate 6 and the source 7 has been improved.

[0076] Thus, the semiconductor device 100 provided by some embodiments of the present disclosure, by dividing the channel part 3 into the first channel subpart 31 and the second channel subpart 32 connected to each other, so that the first channel subpart 31 is located between the epitaxial layer 2 and the second channel subpart 32, and adjusting the arrangement between the gate semiconductor layer 4 and the channel part 3, so that the gate semiconductor layer 4 surrounds the first channel subpart 31, the second channel subpart 32 can be used to separate the gate semiconductor layer 4 and the second channel subpart 32. That is, by adjusting the structure included in the semiconductor device 100 itself, the distance between the gate semiconductor layer 4 and the second channel subpart 32 is increased. The adjustment of the structure is ingenious, which can effectively improve the breakdown voltage between the gate 6 and the source 7 without adding additional structures, and enhance the reliability of the semiconductor device 100.

[0077] Moreover, this also makes the semiconductor device 100 more suitable for high-voltage normally-on JFET, and the cascode device commonly used by high-voltage normally-on JFET, and is conducive to reducing or even preventing the semiconductor device 100 from being damaged by transient gate voltage spikes when applied to cascode devices.

[0078] In some embodiments, the interval between the source contact layer 5 and the gate semiconductor layer 4 along the thickness direction of the substrate 1 is, for example, the same as the thickness of the second channel sub-portion 32. Accordingly, by adjusting the thickness of the second channel sub-portion 32, the breakdown voltage range between the gate electrode 6 and the source electrode 7 of the semiconductor device 100 can be adjusted so that the breakdown voltage between the gate electrode 6 and the source electrode 7 is more appropriate. Here, the thickness of the second channel sub-portion 32 can be selected according to actual design requirements.

[0079] In some embodiments, as shown in Figure 3 and Figure 6 , the orthogonal projection of the end of the first channel sub-portion 31 that is in contact with the second channel sub-portion 32 on the substrate 1 is located within the range of the orthogonal projection of the end of the second channel sub-portion 32 that is in contact with the first channel sub-portion 31 on the substrate 1. Accordingly, the orthogonal projection area of the end of the first channel sub-portion 31 that is in contact with the second channel sub-portion 32 on the substrate 1 is less than the orthogonal projection area of the end of the second channel sub-portion 32 that is in contact with the first channel sub-portion 31 on the substrate 1.

[0080] It can be understood that the semiconductor device 100 has a first direction that is perpendicular to the thickness direction of the substrate 1. Accordingly, the first direction can be any one of the directions parallel to the contact surface between the substrate 1 and the epitaxial layer 2. As shown in Figure 3 and Figure 6 , along the first direction, the end of the first channel sub-portion 31 that is in contact with the second channel sub-portion 32 is arranged inwardly relative to the end of the second channel sub-portion 32 that is in contact with the first channel sub-portion 31.

[0081] For example, as shown in Figure 6 , along the first direction, the size of the end of the first channel sub-portion 31 that is in contact with the second channel sub-portion 32 is D1, and the size of the end of the second channel sub-portion 32 that is in contact with the first channel sub-portion 31 is D2, where D1 < D2. The edge of the end of the second channel sub-portion 32 that is in contact with the first channel sub-portion 31 exceeds the end of the first channel sub-portion 31 that is in contact with the second channel sub-portion 32. The end of the second channel sub-portion 32 that is in contact with the first channel sub-portion 31 and the end of the first channel sub-portion 31 that is in contact with the second channel sub-portion 32 form a T-shaped structure.

[0082] This can make the end of the gate semiconductor layer 4 that is away from the substrate 1 be located below the side surface of the second channel sub-portion 32 that is close to the substrate 1 and be in contact with the side surface of the second channel sub-portion 32 that is close to the substrate 1, ensuring that the second channel sub-portion 32 can cover the end of the gate semiconductor layer 4 that is away from the substrate 1, and further ensuring that the second channel sub-portion 32 has a better spacing effect on the gate semiconductor layer 4 and the source contact layer 5, effectively ensuring that the breakdown voltage between the gate electrode 6 and the source electrode 7 is higher.

[0083] In some examples, such as Figure 3 and Figure 6 As shown, the first channel sub-section 31 includes a first portion 311 and a second portion 312 that are connected. For example, the first portion 311 and the second portion 312 form an integral structure. The first portion 311 is located between the epitaxial layer 2 and the second portion 312. The second portion 312 contacts the second channel sub-section 32. Accordingly, the orthographic projection of the second portion 312 on the substrate 1 is located within the orthographic projection of the second channel sub-section 32 on the substrate 1. Along the first direction, the second portion 312 is recessed relative to the end of the second channel sub-section 32 that contacts the first channel sub-section 31.

[0084] Furthermore, the orthographic projection of the second portion 312 on the substrate 1 is located within the orthographic projection range of the first portion 311 on the substrate 1. Along the first direction, the second portion 312 is set inward relative to the first portion 311. For example, Figure 6 As shown, along the first direction, the second portion 312 has a dimension D1, and the first portion 311 has a dimension D3, where D1 < D3. The edge of the first portion 311 extends beyond the second portion 312. The first channel sub-portion 31 is generally stepped, and the channel portion 3 is generally in the shape of an "I."

[0085] It is understandable that when the JFET is turned off, the narrower portion of the channel is pinched off first. Accordingly, when the semiconductor device 100 is turned off, the first channel sub-portion 31 of the channel portion 3 is pinched off first, and further, the second portion 312 of the first channel sub-portion 31 is pinched off first. However, the second portion 312 is relatively small in the first direction, which can easily increase the channel resistance of the semiconductor device 100.

[0086] By dividing the first channel sub-portion 31 into two parts, and making the size of the first part 311 away from the first channel sub-portion 31 in the first direction larger than the size of the second part 312 in the first direction, the second part 312 can be used to reduce the channel resistance of the semiconductor device 100, avoid affecting or even improve the conduction characteristics of the semiconductor device 100.

[0087] Exemplarily, the distance between the orthographic projection boundary of the second portion 312 on the substrate 1 and the orthographic projection boundary of the first portion 311 on the substrate 1 is in the range of 0.1 μm to 1 μm. That is, along the first direction, the minimum distance between the sidewall of the second portion 312 and the sidewall of the first portion 311 is in the range of 0.1 μm to 1 μm; and the difference between the dimension D3 of the first portion 311 and the dimension D1 of the second portion 312 is in the range of 0.2 μm to 2 μm.

[0088] Optionally, the spacing between the projection boundary on the substrate 1 of the second portion 312 and the projection boundary on the substrate 1 of the first portion 311 can be 0.1 μm, 0.2 μm, 0.4 μm, 0.6 μm, 0.8 μm, or 1 μm, etc.

[0089] With the above size range, on the one hand, the difficulty of preparing the first portion 311, the second portion 312 and the gate semiconductor layer 4 can be reduced, and the gate parasitic resistance can be reduced; on the other hand, the situation that the drain 8 cannot pinch off the first channel sub-portion 31 in the channel portion 3 under high voltage can be avoided, and the withstand voltage capability between the source 7 and the drain 8 can be avoided.

[0090] In some examples, as shown in Figure 3 and Figure 6 , the projection on the substrate 1 of the second channel sub-portion 32 coincides with the projection on the substrate 1 of the first portion 311 of the first channel sub-portion 31. Correspondingly, along the first direction, the size D2 of the second channel sub-portion 32 is equal to the size D3 of the first portion 311 of the first channel sub-portion 31. The projection area on the substrate 1 of the second channel sub-portion 32 is equal to the projection area on the substrate 1 of the first portion 311 of the first channel sub-portion 31.

[0091] In this way, the area occupied by the channel portion 3 on the substrate 1 can be reduced, the area occupied by the JFET in the semiconductor device 100 can be reduced, and the integration of the semiconductor device 100 can be improved.

[0092] In some embodiments, as shown in Figure 7 , in the semiconductor device 100, the number of channel portions 3 is multiple, and the number of source contact layers 5 is multiple. The multiple channel portions 3 and the multiple source contact layers 5 are one-to-one corresponding. The second channel sub-portion 32 of each channel portion 3 is provided with one source contact layer 5, for example, on the side away from the substrate 1. The multiple channel portions 3 can be arranged at intervals along the first direction. Each channel portion 3 can correspond to a JFET, for example.

[0093] For example, continuing to refer to Figure 7 , the gate semiconductor layer 4 surrounds the first channel sub-portion 31 of the multiple channel portions 3, and at least two source contact layers 5 are electrically connected. Correspondingly, the gates of the multiple JFETs are electrically connected together, and the sources of at least two JFETs are electrically connected together, so that at least two JFETs can constitute a common-source common-gate device.

[0094] Here, the way of electrically connecting the at least two source contact layers 5 includes various ways. Optionally, continuing to refer to Figure 7The source 7, which is located at the side of the at least two source contact layers 5 away from the substrate 1, is connected, i.e., the at least two source contact layers 5 are electrically connected together through the source 7. For example, the source 7, which is located at the side of the at least two source contact layers 5 away from the substrate 1, is in an integral structure.

[0095] It can be understood that the semiconductor device 100 can further include other structures, which will be described below in conjunction with the accompanying drawings.

[0096] In some embodiments, as shown in Figure 6 and Figure 7 , the semiconductor device 100 can further include a current diffusion layer 9. The current diffusion layer 9 is located between the epitaxial layer 2 and the first channel sub-portion 31 and is in contact with the first channel sub-portion 31. The orthographic projection of the first channel sub-portion 31 on the substrate 1 is located within the orthographic projection range of the current diffusion layer 9 on the substrate 1. Correspondingly, along the first direction, the edge of the current diffusion layer 9 exceeds the first channel sub-portion 31.

[0097] For example, the area of the orthographic projection of the first channel sub-portion 31 on the substrate 1 is smaller than the area of the orthographic projection of the current diffusion layer 9 on the substrate 1. Along the first direction, the size of the first channel sub-portion 31 is smaller than the size of the current diffusion layer 9.

[0098] In this way, the current diffusion layer 9 can be used to further reduce the channel resistance of the semiconductor device 100, avoid affecting or even improve the conduction characteristics of the semiconductor device 100.

[0099] In some examples, the current diffusion layer 9 and the first channel sub-portion 31 are in an integral structure. That is, the current diffusion layer 9 and the first channel sub-portion 31 are of the same or substantially the same material, and are continuous and not disconnected between each other.

[0100] In this way, during the process of preparing and forming the semiconductor device 100, the current diffusion layer 9 and the first channel sub-portion 31 can be prepared and formed synchronously, which is beneficial to simplify the preparation process of the semiconductor device 100.

[0101] For example, as shown in Figure 6 and Figure 7 , the current diffusion layer 9 can also be located between the gate semiconductor layer 4 and the epitaxial layer 2 and be in contact with the side surface of the gate semiconductor layer 4 close to the substrate 1. Alternatively, the current diffusion layer 9 can be recessed into the gate semiconductor layer 4, i.e., the side surface of the gate semiconductor layer 4 close to the substrate 1 is lower than the side surface of the current diffusion layer 9 close to the substrate 1.

[0102] In some embodiments, as shown in Figure 7 , Figure 8 and Figure 9As shown, the semiconductor device 100 can further include a first ohmic contact layer 10 and a second ohmic contact layer 11.

[0103] The first ohmic contact layer 10 is located between and directly contacts the source contact layer 5 and the source 7. This is advantageous to reduce the contact resistance between the source contact layer 5 and the source 7. The source contact layer 5 can further reduce the contact resistance between the channel 3 and the source 7.

[0104] The second ohmic contact layer 11 is located between and directly contacts the gate semiconductor layer 4 and the gate 6. This is advantageous to reduce the contact resistance between the gate semiconductor layer 4 and the gate 6.

[0105] In some embodiments, as shown in Figure 8 and Figure 9 The semiconductor device 100 can further include a plurality of ring-shaped protrusions 12 and a field limiting ring 13. The field limiting ring 13 can also be referred to as a terminal field limiting ring.

[0106] The plurality of ring-shaped protrusions 12 are located on the side of the epitaxial layer 2 away from the substrate 1, and are sequentially arranged in a ring shape. Exemplarily, the orthographic projection shape of the plurality of ring-shaped protrusions 12 on the substrate 1 includes but is not limited to a circular ring, a square ring, etc. The orthographic projection shape of each ring-shaped protrusion 12 on the substrate 1 can be the same or different. For example, along the first direction, the inner diameters of the plurality of ring-shaped protrusions 12 are different, and at least one ring-shaped protrusion 12 surrounds another ring-shaped protrusion 12. Alternatively, the plurality of ring-shaped protrusions 12 are concentric and arranged at intervals.

[0107] The field limiting ring 13 is located on the side of the epitaxial layer 2 away from the substrate 1, and is located between two adjacent ring-shaped protrusions 12. For example, along the first direction, the ring-shaped protrusions 12 and the field limiting ring 13 are arranged alternately. The number of the field limiting ring 13 can be one or more.

[0108] Further, the plurality of ring-shaped protrusions 12 surround the channel 3 and the gate semiconductor layer 4. The channel 3 and the gate semiconductor layer 4, and the source contact layer 5, the source 7, etc. located on the side of the channel 3 away from the substrate 1, are located in the area surrounded by the plurality of ring-shaped protrusions 12.

[0109] The ring-shaped protrusion 12 with the smallest inner diameter in the plurality of ring-shaped protrusions 12, for example, contacts the gate semiconductor layer 4 and separates the gate semiconductor layer 4 and the field limiting ring 13 with the smallest inner diameter.

[0110] By arranging the field limiting ring 13, the problem of electric field concentration at the edge of the semiconductor device 100 can be alleviated or even eliminated, and the breakdown voltage of the semiconductor device 100 is further improved.

[0111] In some examples, asFigure 9 As shown, the gate semiconductor layer 4 includes a first gate layer 41 and a second gate layer 42 connected to each other. The first gate layer 41 surrounds the first channel sub-portion 31. Compared to the substrate 1, the second gate layer 42 has a surface farther from the substrate 1 and is lower than the surface of the first gate layer 41 farther from the substrate 1. Accordingly, the cross-section of the first gate layer 41 and the second gate layer 42 is L-shaped.

[0112] Furthermore, the second gate layer 42 and the field limiting ring 13 are made of the same material and are provided in the same layer.

[0113] In this article, "same layer" refers to a layer structure formed using the same film-forming process to form a specific pattern, followed by a single patterning process using the same mask. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching steps, and the specific pattern within the resulting layer structure may be continuous or discontinuous, at varying heights or thicknesses.

[0114] In this way, the second gate layer 42 and the field limiting ring 13 can be simultaneously formed in the same fabrication process, thereby avoiding the increase of process steps due to the provision of the field limiting ring 13 , and simplifying the fabrication process of the semiconductor device 100 .

[0115] In some examples, such as Figure 9 As shown, the annular protrusion 12 includes a first annular sub-protrusion 121 and a second annular sub-protrusion 122 connected to each other. The first annular sub-protrusion 121 is located between the epitaxial layer 2 and the second annular sub-protrusion 122. The first annular sub-protrusion 121 and the first channel sub-portion 31 are provided in the same layer, and the second annular sub-protrusion 122 and the second channel sub-portion 32 are made of the same material and provided in the same layer.

[0116] In this way, the first annular sub-protrusion 121 and the first channel sub-portion 31 can be simultaneously prepared and formed in the same preparation process, and the second annular sub-protrusion 122 and the second channel sub-portion 32 can be simultaneously prepared and formed in the same preparation process. This can avoid adding process steps due to the setting of the annular protrusion 12, which is conducive to simplifying the preparation process of the semiconductor device 100.

[0117] Some embodiments of the present application also provide a method for preparing a semiconductor device, which is used, for example, to prepare the semiconductor device 100 in some of the above embodiments. Figure 10 A flow chart of a method for preparing a semiconductor device is shown; Figures 11a-11l and Figures 12a-12c The following diagrams respectively illustrate the structural diagrams corresponding to each step in a method for preparing a semiconductor device. It should be understood that Figure 10 The steps shown are not exclusive and can also be Figure 10Other steps may be performed before, after or between any of the steps shown. In addition, some of the steps may be performed simultaneously, or may be performed in different order. Figure 10 Executed in the order shown.

[0118] The following is a schematic illustration of the method for preparing a semiconductor device with reference to the accompanying drawings. Figure 10 As shown, the preparation method includes: S100-S300.

[0119] S100 , providing a substrate.

[0120] Regarding the substrate, please refer to the relevant description above and will not be repeated here.

[0121] S200, combined Figures 11a-11i An epitaxial layer 2, a channel portion 3, a gate semiconductor layer 4, and a source contact layer 5 are formed on one side of a substrate 1. The channel portion 3 is located on the side of the epitaxial layer 2 away from the substrate 1. The channel portion 3 includes a first channel sub-portion 31 and a second channel sub-portion 32 that are connected, with the first channel sub-portion 31 located between the epitaxial layer 2 and the second channel sub-portion 32. The gate semiconductor layer 4 is located on the side of the epitaxial layer 2 away from the substrate 1 and surrounds the first channel sub-portion 31. The source contact layer 5 is located on the side of the second channel sub-portion 32 away from the substrate 1. The second channel sub-portion 32 separates the source contact layer 5 from the gate semiconductor layer 4.

[0122] Illustratively, the embodiments of the present disclosure may adopt an epitaxial process, an ion implantation process, an etching process, etc. to prepare and form the epitaxial layer 2 , the channel portion 3 , the gate semiconductor layer 4 and the source contact layer 5 .

[0123] S300, such as Figure 11l As shown, a drain 8 is formed on a side of the substrate 1 away from the epitaxial layer 2 .

[0124] For example, embodiments of the present disclosure may utilize a deposition process to deposit a conductive material on the side of substrate 1 away from epitaxial layer 2 to form drain electrode 8. Drain electrode 8 is then treated with a high-temperature annealing process to form an ohmic contact with substrate 1. Alternatively, the material of drain electrode 8 includes, but is not limited to, metal materials such as nickel, aluminum, titanium, tungsten, and their alloys. Along the thickness direction of substrate 1, the thickness of drain electrode 8 may range from 0.02 μm to 2 μm, for example.

[0125] In the method for preparing a semiconductor device provided by some embodiments of the present disclosure, during the process of preparing and forming the epitaxial layer 2, the channel portion 3, the gate semiconductor layer 4 and the source contact layer 5, the preparation processes of the four can be adjusted, so that the prepared channel portion 3 includes a first channel sub-portion 31 and a second channel sub-portion 32 that are connected, and the first channel sub-portion 31 is located between the epitaxial layer 2 and the second channel sub-portion 32, so that the gate semiconductor layer 4 surrounds the first channel sub-portion 31. In this way, the second channel sub-portion 32 can be used to separate the gate semiconductor layer 4 and the second channel sub-portion 32, thereby increasing the distance between the gate semiconductor layer 4 and the second channel sub-portion 32, and thus, on the basis of avoiding adding additional structures, effectively improving the breakdown voltage between the gate 6 and the source 7, thereby enhancing the reliability of the prepared semiconductor device 100.

[0126] In some embodiments, in the above S200 , forming the epitaxial layer 2 , the channel portion 3 , the gate semiconductor layer 4 and the source contact layer 5 on one side of the substrate 1 includes: S210 - S250 .

[0127] S210, such as Figure 11a As shown, an epitaxial thin film 2a is formed on one side of a substrate 1.

[0128] For example, the embodiment of the present disclosure may adopt an epitaxial process to grow an epitaxial film 2a. The thickness of the epitaxial film 2a is, for example, in the range of 1 μm to 100 μm. The epitaxial film 2a is, for example, treated with an N-type light doping process, and its doping concentration is, for example, in the range of 1×10 14 cm -3 to 1×10 17 cm -3 .

[0129] The material of the epitaxial thin film 2a includes wide bandgap semiconductor materials, which include but are not limited to silicon carbide, gallium nitride, diamond, etc.

[0130] S220, such as Figure 11b As shown, a first ion implantation is performed from a side of the epitaxial film 2a away from the substrate 1 to form a first doping region A1.

[0131] For example, Figure 11b As shown, before performing the first ion implantation, a mask film can be formed on the side of the epitaxial film 2a away from the substrate 1. This mask film is then etched using a photolithography process to form a second mask layer M2. The second mask layer M2 has multiple openings spaced apart, each of which exposes a portion of the epitaxial film 2a. The position of each opening corresponds to the location of the channel portion to be formed. The first ion implantation can then be performed on the epitaxial film 2a based on the second mask layer M2 to form multiple first doped regions A1. The second mask layer M2 can then be removed.

[0132] For example, the implanted ions are N-type ions, including but not limited to nitrogen ions, phosphorus ions, etc. The depth range of the first doped region A1 is for example 0.1 μm-4 μm, and the doping concentration range of the first doped region A1 is for example 1 x 1018 cm-3-1 x 1020 cm-3. 14 cm -3 -1 x 1018 cm-3 20 cm -3

[0133] S230, as shown in the figure, a first mask pattern 14 is formed on the side of the epitaxial film 2a away from the substrate 1, the first mask pattern 14 covers a part of the first doped region A1, and exposes another part of the first doped region A1. Figure 11c

[0134] For example, a dielectric material such as silicon oxide (SiO2), silicon nitride (SiNx), etc. or a photoresist can be used to form a mask film on the side of the epitaxial film 2a away from the substrate 1, and then a photolithography process is used to etch the mask film to obtain a first mask layer M1, which includes a plurality of first mask patterns 14 arranged in intervals, and each first mask pattern 14 is in a block shape.

[0135] For example, the first mask pattern 14 and the first doped region A1 are arranged in one-to-one correspondence, and each first mask pattern 14 covers a part of the corresponding first doped region A1 and exposes another part of the first doped region A1. The exposed part of the first doped region A1 is for example in a ring shape.

[0136] S240, as shown in the figure, based on the first mask pattern 14, a second ion implantation is performed from the side of the epitaxial film 2a away from the substrate 1 to form a second doped region A2. The part of the first doped region A1 opposite to the second doped region A2 constitutes a second part of the first channel sub-portion 31, and the second doped region A2 is used to constitute a gate semiconductor layer. Figure 11c

[0137] For example, the second doped region A2 surrounds each first doped region A1. For example, the implanted ions of the second doped region A2 are P-type ions, including but not limited to aluminum ions, boron ions, etc. Correspondingly, the second doped region A2 can also be referred to as a P-type region. The depth range of the second doped region A2 is for example 0.1 μm-4 μm, and the doping concentration range of the second doped region A2 is for example 1 x 1018 cm-3-1 x 1020 cm-3. 16 cm -3 -1 x 1018 cm-3 20 cm -3 In the first direction, the size range of the part of the first doped region A1 opposite to the second doped region A2 (i.e. the second part of the first channel sub-portion 31) is for example 0.5 μm-5 μm. ​​

[0138] The second ion implantation is, for example, vertical ion implantation, and the ion implantation direction is parallel or substantially parallel to the thickness direction of the substrate 1 .

[0139] Here, after the second doping region A2 is formed, the first mask layer M1 may be removed, and the surface of the epitaxial film 2 a away from the substrate 1 may be cleaned.

[0140] S250, such as Figure 11e As shown, a second channel sub-portion 32 and a source contact layer 5 are formed on the side of the epitaxial film 2a away from the substrate 1. The second channel sub-portion 32 covers the first doping region A1 and a portion of the second doping region A2.

[0141] For example, combined Figure 11d and Figure 11e The method for forming the second channel sub-portion 32 and the source contact layer 5 includes: using an epitaxial process to grow a channel film 32a on the side of the epitaxial film 2a away from the substrate 1, and then, epitaxially growing or ion implanting the channel film 32a on the side away from the substrate 1 to form a source contact film 5a; thereafter, using a photolithography process to form a third mask layer M3 on the side of the source contact film 5a away from the substrate 1, the third mask layer M3 includes a plurality of second mask patterns in a block shape, and the plurality of second mask patterns and the plurality of first doping regions A1 are arranged one-to-one correspondingly, and each second mask pattern covers the first doping region A1 and a portion of the second doping region A2; then, based on the third mask layer M3, a dry etching process can be used to etch the source contact film 5a and the channel film 3a to obtain a plurality of second channel sub-portions 32 and a plurality of source contact layers 5.

[0142] For example, the thickness of the channel film 32a is in the range of 0.2 μm to 2 μm. The channel film 32a is, for example, subjected to N-type doping treatment, and its doping concentration is, for example, in the range of 1×10 16 cm -3 -1×10 20 cm -3 The thickness of the source contact film 5a is, for example, in the range of 0.1 μm to 0.5 μm. The source contact film 5a is, for example, heavily N-type doped, and its doping concentration is, for example, in the range of 1×10 17 cm -3 -1×10 20 cm -3 Along the first direction, the size of the second channel sub-portion 32 is smaller than or equal to the size of a portion of the first doping region A1 that is not opposite to the second doping region A2.

[0143] It can be understood that the second channel sub-portion 32 and the source contact layer 5 are etched in the same patterning process and are formed by using a preparation process independent of the first channel sub-portion 31. The second channel sub-portion 32 can be used to separate the source contact layer 5 and the second doped region A2, and correspondingly, separate the source contact layer 5 and the gate semiconductor layer to be formed. The process is relatively simple, and the breakdown voltage between the source and the gate of the semiconductor device can be effectively increased.

[0144] Further, in the above S200, the epitaxial layer 2, the channel portion 3, the gate semiconductor layer 4 and the source contact layer 5 are formed on one side of the substrate 1, and the process can further include S260-S270.

[0145] S260, as shown in the figure, the second doped region A2 is etched and thinned based on the second channel sub-portion 32 and the source contact layer 5. Figure 11e

[0146] Specifically, the second doped region A2 is etched and thinned based on the third mask layer M3 located on the side of the second channel sub-portion 32 and the source contact layer 5 away from the substrate 1.

[0147] Optionally, the etching of the source contact film 5a and the channel film 32a, and the etching of the second doped region A2, can be performed in the same etching process. Here, the etching depth is in the range of, for example, 0.3 μm-4.5 μm.

[0148] S270, as shown in the figure, the third ion implantation is performed from the side of the epitaxial film 2a away from the substrate 1 based on the second channel sub-portion 32 and the source contact layer 5, to form the third doped region A3, which is connected with the second doped region A2 and constitutes the gate semiconductor layer 4. Figure 11f Specifically, the third ion implantation is performed based on the third mask layer M3 located on the side of the second channel sub-portion 32 and the source contact layer 5 away from the substrate 1. For example, the implanted ions are P-type ions, and the depth of the third doped region A3 is in the range of, for example, 0.1 μm-2 μm, and the doping concentration of the third doped region A3 is in the range of, for example, 1×10 16 cm -3 -1×10 20 cm -3 -1×10

[0149] The part of the first doped region A1 opposite to the third doped region A3 constitutes the first part 311 of the first channel sub-portion 31. As shown in the figure, by controlling the depth of the third doped region A3, the bottom of the first doped region A1 can constitute a current diffusion layer 9.

[0150] Figure 11f

[0151] ​​​Here, the spacing between the edge of the third doped region A3 and the edge of the second doped region A2 in the first direction is, for example, in the range of 0.1 μm to 1 μm. In this way, on the one hand, the second doped region A2 can be prevented from being removed too much, so that the overlay accuracy of the process can be controlled, and the gate parasitic resistance can be prevented from being increased. On the other hand, the size of the sidewall of the third doped region A3 in the first direction can be prevented from being too large, so that the first channel sub-portion 31 cannot be pinched off under high voltage of the drain, and the withstand voltage between the source and the drain of the semiconductor device can be reduced.

[0152] It can be understood that, in the above channel portion 3, the size of the second portion 312 in the first direction is the smallest, and accordingly, the threshold voltage of the channel portion 3 is controlled in the above S240. The third ion implantation in the above S270 and the formation of the second channel sub-portion 32 in the S250 are not related to the size of the second portion 312 in the first direction, and will not affect the size of the second portion 312 in the first direction.

[0153] In Figure 2 In the semiconductor device shown in FIG. 1, the material of the channel portion 3 includes a wide-bandgap semiconductor material, and generally, a dry etching process is required to etch the wide-bandgap semiconductor material to form a groove, and then the channel portion 3 is obtained. The etching of the wide-bandgap semiconductor material is relatively difficult, and a hard mask and a relatively large power etching device need to be used, so that the size of the channel portion 3 in the first direction obtained by etching is difficult to control accurately, and then the uniformity of the size of different channel portions 3 in the first direction obtained by etching is poor. The channel portion 3 has a relatively high carrier concentration, and thus the change of the size of the channel portion 3 in the first direction obtained by etching in the preparation process will cause a great change of the threshold voltage and the withstand voltage of the semiconductor device finally obtained.

[0154] In the embodiment of the present disclosure, the threshold voltage of the semiconductor device is determined by the second portion 312 of the channel portion 3. In the process of forming the second portion 312, the first mask layer M1 can also be referred to as an ion implantation mask, and the material of the ion implantation mask is generally relatively easy to etch, and accordingly, the etching size is easy to control, and the process uniformity is relatively high. Accordingly, the size accuracy of the first mask pattern 14 is high, and the size accuracy of the second portion 312 obtained by preparation is high. In this way, the adverse effects on the threshold voltage and the breakdown voltage between the source and the drain caused by directly etching the channel portion are avoided.

[0155] In addition, the third doped region A3 is formed by the third ion implantation, so that the withstand voltage of the semiconductor device can be improved, and the threshold voltage of the semiconductor device can be prevented from being affected.

[0156] The embodiments of the present disclosure are respectively used for Figure 2 and the semiconductor device (for example, the semiconductor device 1 shown in FIG. 1) prepared by using the preparation method provided by the embodiments of the present disclosure.Figure 11l The transfer characteristic curve and off-state breakdown current-voltage curve (as shown in the figure) were simulated.

[0157] from Figure 13a and Figure 13b It can be seen that Figure 2 In the semiconductor device shown, when the size of the channel portion 3 in the first direction changes from 1.2μm to 1.6μm, the threshold voltage drifts greatly; while in the semiconductor device shown in the embodiment of the present disclosure, when the size of the second part 312 of the first channel sub-portion 31 in the first direction changes from 1.2μm to 1.6μm, the threshold voltage is stable and basically stable at around -9V.

[0158] from Figure 14a and Figure 14b It can be seen that Figure 2 In the semiconductor device shown, when the size of the channel portion 3 in the first direction changes from 1.2μm to 1.6μm, the off-state drain breakdown voltage is greatly degraded, and breakdown occurs before the rated voltage; while in the semiconductor device shown in the embodiment of the present disclosure, when the size of the second part 312 of the first channel sub-portion 31 in the first direction changes from 1.2μm to 1.6μm, the off-state drain breakdown voltage is not degraded.

[0159] That is to say, the preparation method of the channel portion 3 in the semiconductor device provided in the embodiment of the present disclosure can achieve the decoupling between the size of the second part 312 of the first channel sub-portion 31 in the first direction and the threshold voltage and the off-state drain breakdown voltage, effectively improving the problems of threshold voltage drift and off-state drain breakdown voltage degradation caused by the change in the size of the second part 312 of the first channel sub-portion 31 in the first direction.

[0160] In some embodiments, before the above S300, the above preparation method further includes: S281-S283.

[0161] S281, such as Figure 11i As shown, a first ohmic contact layer 10 is formed on a side of the source contact layer 5 away from the substrate 1 , and a second ohmic contact layer 11 is formed on a side of the gate semiconductor layer 4 away from the substrate 1 .

[0162] For example, Figure 11g As shown, before forming the first ohmic contact layer 10 and the second ohmic contact layer 11, a dielectric material can be deposited on the side of the gate semiconductor layer 4 and the source contact layer 5 away from the substrate 1 to form a dielectric film 15a. The dielectric film 15a also covers the sidewalls of the gate semiconductor layer 4, the sidewalls of the second channel sub-portion 32, and the sidewalls of the source contact layer 5. Then, in combination with Figure 11g and Figure 11hFor example, an anisotropic dry etching process is used to etch the dielectric film 15a, removing the portion of the dielectric film 15a located on the side of the gate semiconductor layer 4 and the source contact layer 5 away from the substrate 1, and retaining the portion of the dielectric film 15a covering the sidewalls of the gate semiconductor layer 4, the sidewalls of the second channel sub-portion 32, and the sidewalls of the source contact layer 5 to form the sidewall spacer 15. Figure 11i As shown, an ohmic metal material is deposited on the side of the gate semiconductor layer 4 and the source contact layer 5 away from the substrate 1 , and annealed using a high-temperature annealing process to obtain a first ohmic contact layer 10 and a second ohmic contact layer 11 .

[0163] Optionally, the dielectric film 15a may have a thickness ranging from 0.02 μm to 2 μm, and the material of the dielectric film 15a includes, but is not limited to, dielectric materials such as silicon oxide and silicon nitride. The first ohmic contact layer 10 and the second ohmic contact layer 11 may have the same thickness, for example, ranging from 0.02 μm to 0.2 μm, and the first ohmic contact layer 10 and the second ohmic contact layer 11 may be made of the same material, for example, including, but not limited to, metal materials such as nickel, aluminum, titanium, tungsten, and alloys thereof.

[0164] The first ohmic contact layer 10 and the second ohmic contact layer 11 are simultaneously prepared and formed in the same preparation process, which is beneficial to simplifying the preparation process of the semiconductor device.

[0165] S282, such as Figure 11j As shown, a dielectric layer 16 is formed to cover the first ohmic contact layer 10 and the second ohmic contact layer 11 .

[0166] For example, a deposition process may be used to deposit dielectric material on the side of the first ohmic contact layer 10 and the second ohmic contact layer 11 away from the substrate 1 to form the dielectric layer 16 . The dielectric layer 16 also covers the sidewall spacer 15 .

[0167] S283, such as Figure 11k As shown, a source electrode 7 and a gate electrode 6 are formed. The source electrode 7 penetrates the dielectric layer 16 to the first ohmic contact layer 10 , and the gate electrode 6 penetrates the dielectric layer 16 to the second ohmic contact layer 11 .

[0168] For example, before forming the source electrode 7 and the gate electrode 6, a first via hole and a second via hole can be formed in the dielectric layer 16. The first via hole penetrates the dielectric layer 16 and exposes the first ohmic contact layer 10. The second via hole penetrates the dielectric layer 16 and exposes the second ohmic contact layer 11. Then, a conductive material is deposited on the first and second via holes and on the side of the dielectric layer 16 away from the substrate 1 to form the source electrode 7 and the gate electrode 6. The source electrode 7 contacts the first ohmic contact layer 10 through the first via hole, and the gate electrode 6 contacts the second ohmic contact layer 11 through the second via hole. A certain distance is provided between the source electrode 7 and the gate electrode 6 to prevent leakage between the source electrode 7 and the gate electrode 6.

[0169] As to the materials of the source 7 and the gate 6, refer to the relevant description above, which will not be repeated here.

[0170] In some embodiments, as shown in FIG. 2B, the epitaxial film 2a has a termination region B1 and an active region B2. The termination region B1, for example, is annular and surrounds the active region B2. The channel portion 3 and the gate semiconductor layer 4 are located in the active region B2. Figures 12a-12c In some examples, as shown in FIG. 2C, in the process of forming the second channel sub-portion 32 and the source contact layer 5 on the side of the epitaxial film 2a away from the substrate 1 in S250, a second annular sub-bump 122 is also formed on the side of the epitaxial film 2a away from the substrate 1, and the second annular sub-bump 122 is located in the termination region B1.

[0171] Figure 12a In some examples, as shown in FIG. 2C, in the process of forming the second channel sub-portion 32 and the source contact layer 5 on the side of the epitaxial film 2a away from the substrate 1 in S250, a second annular sub-bump 122 is also formed on the side of the epitaxial film 2a away from the substrate 1, and the second annular sub-bump 122 is located in the termination region B1.

[0172] Specifically, the channel film 3a and the source contact film 5a are not only located in the active region B2 but also located in the termination region B1; part of the second mask pattern in the third mask layer M3 is also located in the termination region B1, and the part of the second mask pattern located in the termination region B1 is annular. In the process of etching the part of the source contact film 5a and the channel film 3a located in the active region B2 based on the third mask layer M3, the part of the source contact film 5a and the channel film 3a located in the termination region B1 is also etched, obtaining the second annular sub-bump 122.

[0173] In some examples, as shown in FIG. 2D, in the process of etching and thinning the second doped region A2 based on the second channel sub-portion 32 and the source contact layer 5 in S260, the part of the epitaxial film 2a located in the termination region B1 is also thinned based on the second channel sub-portion 32 and the source contact layer 5. Figure 12b Specifically, the part of the epitaxial film 2a is etched and thinned based on the part of the second mask pattern in the third mask layer M3 located in the termination region B1.

[0174] In some examples, as shown in FIG. 2D, in the process of etching and thinning the second doped region A2 based on the second channel sub-portion 32 and the source contact layer 5 in S260, the part of the epitaxial film 2a located in the termination region B1 is also thinned based on the second channel sub-portion 32 and the source contact layer 5.

[0175] Figure 12c In some examples, as shown in FIG. 2E, in the process of forming the third doped region A3 in S270, the part of the epitaxial film 2a located in the termination region B1 is also subjected to the third ion implantation based on the second annular sub-bump 122, forming a field limiting ring 13; the part located between the second annular sub-bump 122 and the substrate 1 and in contact with the field limiting ring 13 constitutes a first annular sub-bump 121. The first annular sub-bump 121 and the second annular sub-bump 122 constitute the annular bump 12.

[0176] ​​Specifically, based on the part of the second mask pattern in the third mask layer M3 located in the termination region B1, the third ion implantation is performed on the epitaxial film 2a. Then, in the process of removing the third mask layer M3, for example, the part of the source contact film away from the substrate 1 on the side of the second annular sub-protrusion 122 is also removed. The subsequently formed dielectric layer 16 also covers the annular protrusion 12 and the field limiting ring 13.

[0177] By synchronously preparing the annular protrusion 12 and the field limiting ring 13 in the process of preparing the second channel sub-portion 32, the source contact layer 5 and the gate semiconductor layer 4, it is beneficial to simplify the preparation process of the semiconductor device.

[0178] Of course, the annular protrusion 12 and the field limiting ring 13 can also be prepared independently of the preparation process of the second channel sub-portion 32, the source contact layer 5 and the gate semiconductor layer 4, and are prepared separately, which is not limited in the embodiments of the present disclosure.

[0179] The above merely describes the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: substrate; an epitaxial layer, located on one side of the substrate; a channel portion located on a side of the epitaxial layer away from the substrate; the channel portion includes a first channel sub-portion and a second channel sub-portion connected to each other, the first channel sub-portion being located between the epitaxial layer and the second channel sub-portion; a gate semiconductor layer, located on a side of the epitaxial layer away from the substrate and surrounding the first channel sub-portion; a source contact layer, located on a side of the second channel sub-portion away from the substrate; the second channel sub-portion separates the source contact layer and the gate semiconductor layer; The drain is located on a side of the substrate away from the epitaxial layer.

2. The semiconductor device according to claim 1, wherein An orthographic projection of one end of the first channel sub-portion in contact with the second channel sub-portion on the substrate is located within a range of an orthographic projection of one end of the second channel sub-portion in contact with the first channel sub-portion on the substrate.

3. The semiconductor device according to claim 2, wherein The first channel sub-portion includes a first portion and a second portion connected to each other, the first portion being located between the epitaxial layer and the second portion; The orthographic projection of the second portion on the substrate is located within the orthographic projection range of the first portion on the substrate.

4. The semiconductor device according to claim 3, wherein A distance between an orthographic projection boundary of the second portion on the substrate and an orthographic projection boundary of the first portion on the substrate is in a range of 0.1 μm to 1 μm.

5. The semiconductor device according to claim 3, wherein An orthographic projection of the second channel sub-portion on the substrate coincides with an orthographic projection of the first portion on the substrate. The semiconductor device according to claim 1 , wherein: The semiconductor device further includes: a current diffusion layer, the current diffusion layer being located between the epitaxial layer and the first channel sub-portion and in contact with the first channel sub-portion; The orthographic projection of the first channel sub-portion on the substrate is located within the orthographic projection range of the current diffusion layer on the substrate.

7. The semiconductor device according to claim 6, wherein: The current diffusion layer and the first channel sub-portion are in an integrated structure.

8. The semiconductor device according to claim 1, wherein There are multiple channel portions, and the gate semiconductor layer surrounds the first channel sub-portions of the multiple channel portions; The source contact layer is provided on a side of the second channel sub-portion of each channel portion away from the substrate, and at least two source contact layers are electrically connected.

9. The semiconductor device according to claim 1, wherein The semiconductor device further includes: a source electrode, located on a side of the source contact layer away from the substrate; a first ohmic contact layer, located between the source contact layer and the source electrode; a gate electrode, located on a side of the gate semiconductor layer away from the substrate; The second ohmic contact layer is located between the gate semiconductor layer and the gate.

10. The semiconductor device according to claim 1, wherein The semiconductor device further includes: a plurality of annular protrusions, located on a side of the epitaxial layer away from the substrate, and arranged in a ring-shaped manner; the plurality of annular protrusions surround the channel portion and the gate semiconductor layer; The field limiting ring is located on a side of the epitaxial layer away from the substrate and between two adjacent annular protrusions.

11. The semiconductor device according to claim 10, wherein: The gate semiconductor layer includes a first gate layer and a second gate layer connected to each other; the first gate layer surrounds the first channel sub-portion, and a surface of the second gate layer is farther from the substrate than the substrate and is lower than a surface of the first gate layer is farther from the substrate; The second gate layer and the field limiting ring are made of the same material and are provided in the same layer.

12. The semiconductor device according to claim 10, wherein: The annular protrusion includes a first annular sub-protrusion and a second annular sub-protrusion connected to each other, and the first annular sub-protrusion is located between the epitaxial layer and the second annular sub-protrusion; The first annular sub-protrusion and the first channel sub-portion are arranged in the same layer; The second annular sub-protrusion and the second channel sub-portion are made of the same material and are arranged in the same layer.

13. A method for preparing a semiconductor device, characterized in that: The preparation method comprises: providing a substrate; An epitaxial layer, a channel portion, a gate semiconductor layer, and a source contact layer are formed on one side of the substrate; the channel portion is located on a side of the epitaxial layer away from the substrate; the channel portion includes a first channel sub-portion and a second channel sub-portion connected to each other, the first channel sub-portion being located between the epitaxial layer and the second channel sub-portion; the gate semiconductor layer is located on a side of the epitaxial layer away from the substrate and surrounds the first channel sub-portion; the source contact layer is located on a side of the second channel sub-portion away from the substrate; the second channel sub-portion separates the source contact layer and the gate semiconductor layer; A drain is formed on a side of the substrate away from the epitaxial layer.

14. The preparation method according to claim 13, characterized in that The step of forming an epitaxial layer, a channel portion, a gate semiconductor layer, and a source contact layer on one side of the substrate comprises: forming an epitaxial thin film on one side of the substrate; Performing a first ion implantation from a side of the epitaxial film away from the substrate to form a first doped region; forming a first mask pattern on a side of the epitaxial film away from the substrate, wherein the first mask pattern covers a portion of the first doped region and exposes another portion of the first doped region; Based on the first mask pattern, performing a second ion implantation from a side of the epitaxial thin film away from the substrate to form a second doped region; a portion of the first doped region opposite to the second doped region constitutes a second portion of the first channel sub-portion, and the second doped region is used to constitute the gate semiconductor layer; The second channel sub-portion and the source contact layer are formed on a side of the epitaxial thin film away from the substrate; the second channel sub-portion covers the first doping region and a portion of the second doping region.

15. The preparation method according to claim 14, characterized in that The epitaxial layer, the channel portion, the gate semiconductor layer and the source contact layer are formed on one side of the substrate, further comprising: Based on the second channel sub-portion and the source contact layer, etching and thinning the second doped region; Based on the second channel sub-portion and the source contact layer, a third ion implantation is performed from a side of the epitaxial film away from the substrate to form a third doped region, which is connected to the second doped region to constitute the gate semiconductor layer.

16. The preparation method according to claim 15, characterized in that The epitaxial thin film has a termination region and an active region, wherein the termination region surrounds the active region; the channel portion and the gate semiconductor layer are located in the active region; In the process of forming the second channel sub-portion and the source contact layer on the side of the epitaxial film away from the substrate, a second annular sub-protrusion is also formed on the side of the epitaxial film away from the substrate; the second annular sub-protrusion is located in the termination area; In the process of etching and thinning the second doped region based on the second channel sub-portion and the source contact layer, a portion of the epitaxial thin film located in the termination region is also thinned based on the second channel sub-portion and the source contact layer; In the process of forming the third doped region, the third ion implantation is also performed on the portion of the epitaxial film located in the termination region based on the second annular sub-protrusion to form a field limiting ring; the portion located between the second annular sub-protrusion and the substrate and in contact with the field limiting ring constitutes the first annular sub-protrusion.

17. The preparation method according to claim 13, characterized in that Before forming the drain on the side of the substrate away from the epitaxial layer, the preparation method further includes: forming a first ohmic contact layer on a side of the source contact layer away from the substrate, and forming a second ohmic contact layer on a side of the gate semiconductor layer away from the substrate; forming a dielectric layer covering the first ohmic contact layer and the second ohmic contact layer; A source electrode and a gate electrode are formed; the source electrode penetrates the dielectric layer to the first ohmic contact layer, and the gate electrode penetrates the dielectric layer to the second ohmic contact layer.

18. An electronic device, characterized in that: The electronic device comprises: The semiconductor device is a semiconductor device according to any one of claims 1 to 12; A circuit board is electrically connected to the semiconductor device.

Images