A solar cell intermediate, a solar cell and a preparation method thereof

Abstract

The invention discloses a solar cell intermediate, a solar cell and a preparation method. The solar cell intermediate of the invention adopts a dielectric buffer layer with a square resistance of more than 2000Ω / sq in a local passivation contact structure, and the dielectric buffer layer is controlled to be arranged on the entire back surface. The structure not only overcomes the problems of large metal composite and contact resistance in contact with doped polysilicon or doped emitter after the use of traditional "base" metal slurry, but also achieves unexpected improvements in short-circuit current, metal composite, interface contact and other aspects. The structure is suitable for preparing solar cells and is beneficial to reducing costs and increasing efficiency.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and in particular to a solar cell intermediate, a solar cell and a preparation method thereof. Background Art

[0002] The concept of tunneling oxide / heavily doped polysilicon passivated contact (TOPCon) cells has received widespread attention since it was proposed. As the production capacity of TOPCon cells has reached several hundred GW, it is particularly important to further reduce costs and improve efficiency of TOPCon cells. In terms of efficiency improvement, how to reduce the free carrier absorption of heavily doped polysilicon film layer to increase the short-circuit current of the battery is a current research and development hotspot; in terms of cost reduction, facing the industry trend of large demand for silver paste and rising prices of silver paste, how to reduce the consumption of silver paste is urgent. At present, it is usually to directly reduce the number of electrode grid lines or narrow the width of electrode grid lines, but directly reducing the number of grid lines will directly lead to a decrease in battery efficiency. The narrowing of electrode grid line width is subject to the existing electrode preparation technology and the consumption reduction is limited. Using "cheap" metal paste instead of silver paste is also a solution to reduce the consumption of silver paste. "Cheap" metals such as aluminum and copper are cheaper than silver, which can effectively reduce non-silicon costs; but practice has found that after the use of "cheap" metal paste, there are problems such as large metal composite and large contact resistance when it comes into contact with doped polysilicon or doped emitter, resulting in the current industrialized TOPCon batteries basically using 100% silver paste. Summary of the invention

[0003] The purpose of the present invention is to overcome one or more deficiencies in the prior art and to provide an improved solar cell intermediate. The passivation contact structure formed by the solar cell intermediate can improve short-circuit current, reduce metal composites, improve interface contact and thereby improve battery efficiency while also achieving the replacement of silver materials with "base" metals, reducing silver paste consumption and thereby reducing battery costs, thereby achieving the function of both cost reduction and efficiency improvement.

[0004] The present invention also provides a method for preparing the solar cell intermediate.

[0005] The present invention also provides a method for preparing a solar cell and a solar cell made therefrom. The solar cell can use relatively cheap metal slurry to prepare a back metal electrode, thereby improving the cell conversion efficiency and reducing the production cost.

[0006] In order to achieve the above object, a technical solution adopted by the present invention is:

[0007] A solar cell intermediate, comprising:

[0008] A silicon wafer having a back surface, the back surface comprising a first region and a second region;

[0009] In the first region, a tunnel dielectric layer, a phosphorus-doped polysilicon layer, a first dielectric buffer layer, and a main back side fine gate electrode are sequentially arranged along a direction perpendicular to the first region;

[0010] In the second region, a main back passivation layer and a second dielectric buffer layer are sequentially arranged along a direction perpendicular to the second region;

[0011] The first dielectric buffer layer is in contact with the second dielectric buffer layer, and the first dielectric buffer layer and the second dielectric buffer layer are respectively film layers formed of metal compounds with a square resistance of more than 2000Ω / sq.

[0012] In some embodiments of the present invention, the thickness of the first dielectric buffer layer and the second dielectric buffer layer are respectively 10-100 nm.

[0013] In some embodiments of the present invention, the sheet resistance of the first dielectric buffer layer and the sheet resistance of the second dielectric buffer layer are 2000-15000Ω / sq respectively.

[0014] In some embodiments of the present invention, the metal compound is selected from ML x wherein M is a combination of one or more selected from Ti, Li, Ta, Mg, Hf, Sc, W, Mo and V, L is a combination of one or more selected from O, C and N, and x is the coordination number of L.

[0015] Furthermore, the metal compound is selected from TiO x 、TaO x MgO x A combination of one or more of .

[0016] Furthermore, x can be 1 or 2.

[0017] In some embodiments of the present invention, the solar cell intermediate further includes a secondary back passivation layer, which is arranged on the peripheral side of the surface of the phosphorus-doped polycrystalline silicon layer and forms a hole in the middle, and the first dielectric buffer layer has a portion passing through the hole and contacting the phosphorus-doped polycrystalline silicon layer, and the contact is direct contact or indirect contact, and the orthographic projection of the secondary back passivation layer is located within the orthographic projection range of the phosphorus-doped polycrystalline silicon layer.

[0018] In some embodiments of the present invention, the secondary back passivation layer is integrally formed with the primary back passivation layer.

[0019] In some embodiments of the present invention, the first dielectric buffer layer and the second dielectric buffer layer are integrally formed.

[0020] According to the present invention, the total area of ​​the first dielectric buffer layer and the second dielectric buffer layer is equal to the area of ​​the back surface.

[0021] In some embodiments of the present invention, the solar cell intermediate further includes a metal silicon compound layer, wherein the metal silicon compound layer is located between the phosphorus-doped polycrystalline silicon layer and the first dielectric buffer layer, and the material of the metal silicon compound layer is an alloy formed by Z and Si, wherein Z is a combination of one or more selected from Ti, Li, Ta, Mg, Hf, Sc, W, Mo and V.

[0022] In some embodiments of the present invention, the metal in the metal silicon compound layer is the same as the metal of the metal compound in the first dielectric buffer layer.

[0023] In some embodiments of the present invention, the metal material in the main back side fine gate electrode is aluminum and / or copper.

[0024] In some embodiments of the present invention, the solar cell intermediate further comprises a secondary back side fine grid electrode, which together with the primary back side fine grid electrode constitutes a whole surface electrode covering more than 90% of the first region and the second region.

[0025] Furthermore, the metal material of the secondary back side fine gate electrode is aluminum and / or copper.

[0026] Furthermore, the main back side fine gate electrode and the auxiliary back side fine gate electrode are integrally formed.

[0027] In some embodiments of the present invention, the thickness of the tunnel dielectric layer is 1-3 nm, and the thickness of the phosphorus-doped polysilicon layer is 100-200 nm.

[0028] Another technical solution provided by the present invention is a method for preparing a solar cell intermediate, the method comprising:

[0029] Providing a silicon wafer having a back surface, wherein the back surface includes a first region and a second region;

[0030] sequentially disposing a tunnel oxide layer and a phosphorus-doped polysilicon layer on the back surface; and then removing the partial structures of the tunnel oxide layer and the phosphorus-doped polysilicon layer respectively located in the second region;

[0031] Disposing a back passivation layer on the back surface, and then completely or partially removing a portion of the back passivation layer located in the first region to expose a portion of the surface of the phosphorus-doped polysilicon layer located in the first region;

[0032] Disposing metal film layers on the first region and the second region respectively, wherein the metal film layer located in the first region is in contact with the exposed surface of the phosphorus-doped polysilicon layer;

[0033] Performing a heat treatment in an oxygen environment; wherein, after the heat treatment, the metal film layer located in the first region is transformed into a first dielectric buffer layer composed of a metal oxide with a square resistance of more than 2000Ω / sq, or a portion of the metal film layer located in the first region is transformed into a first dielectric buffer layer composed of a metal oxide with a square resistance of more than 2000Ω / sq, and the silicon in the phosphorus-doped polysilicon layer in contact with the remaining portion reacts to generate a metal silicon compound and forms a metal silicon compound layer; the metal film layer located in the second region is transformed into a second dielectric buffer layer composed of a metal oxide with a square resistance of more than 2000Ω / sq;

[0034] A back side fine gate electrode is provided at least on the first dielectric buffer layer.

[0035] In some embodiments of the present invention, the temperature of the heat treatment is 600-1000° C., and the treatment time is 1-10 min.

[0036] Another technical solution provided by the present invention is: a solar cell intermediate made by the above-mentioned method for preparing the solar cell intermediate.

[0037] Another technical solution provided by the present invention is: a solar cell, which includes the solar cell intermediate described above.

[0038] Another technical solution provided by the present invention is a method for preparing a solar cell, the method comprising:

[0039] Step (1) provides a silicon wafer, and performs boron diffusion treatment on the silicon wafer to form emitters on the front surface and the back surface of the silicon wafer respectively;

[0040] Step (2) removing the emitter on the back surface of the silicon wafer;

[0041] Step (3) The back surface includes a first region and a second region;

[0042] sequentially disposing a tunnel oxide layer and a phosphorus-doped polysilicon layer on the back surface; and then removing the partial structures of the tunnel oxide layer and the phosphorus-doped polysilicon layer respectively located in the second region;

[0043] Disposing a back passivation layer on the back surface, and then completely or partially removing a portion of the back passivation layer located in the first region to expose a portion of the surface of the phosphorus-doped polysilicon layer located in the first region;

[0044] Performing a heat treatment in an oxygen environment; wherein, after the heat treatment, the metal film layer located in the first region is transformed into a first dielectric buffer layer composed of a metal oxide with a square resistance of more than 2000Ω / sq, or a portion of the metal film layer located in the first region is transformed into a first dielectric buffer layer composed of a metal oxide with a square resistance of more than 2000Ω / sq, and the silicon in the phosphorus-doped polysilicon layer in contact with the remaining portion reacts to generate a metal silicon compound and forms a metal silicon compound layer; the metal film layer located in the second region is transformed into a second dielectric buffer layer composed of a metal oxide with a square resistance of more than 2000Ω / sq;

[0045] A back side fine gate electrode is provided at least on the first dielectric buffer layer.

[0046] In some embodiments of the present invention, in the step (3), when the back side fine gate electrode is provided in an area of ​​more than 90% of the back surface, a connection base point of a back side silver material is first printed, and then the back side fine gate electrode surrounding the connection base point and / or having a partial overlap with the connection base point is provided.

[0047] Another technical solution provided by the present invention is a solar cell manufactured by the above-mentioned method for manufacturing a solar cell.

[0048] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art:

[0049] Based on the problem of high cost pressure caused by excessive demand for silver paste in existing TOPCon batteries, the present invention innovatively provides a new type of solar cell intermediate that can use "base" metal paste instead of silver paste in the back fine grid electrode. The passivation contact structure formed by the solar cell intermediate overcomes the problems of large metal composite and contact resistance when the traditional "base" metal paste is used in contact with doped polysilicon or doped emitter, and unexpected improvements are achieved in short-circuit current, metal composite, interface contact and other aspects, which significantly improves cost reduction and efficiency improvement. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 This is a schematic diagram of the structure of a solar cell prepared in Comparative Example 1 of the present invention;

[0051] Figure 1 In the reference numerals: 11, silicon wafer; 12, boron diffused emitter; 13, AlO x Thin film; 14, front passivation layer; 15, front fine-grid silver electrode; 16, tunnel dielectric layer; 17, phosphorus-doped polysilicon layer; 18, back passivation layer; 19, back fine-grid silver electrode;

[0052] Figure 2is a schematic structural diagram of a solar cell according to Embodiment 1 of the present invention;

[0053] Figure 2 In the reference numerals: 21, silicon wafer; 22, boron diffused emitter; 23, AlO x Thin film; 24, front passivation layer; 25, front fine gate silver electrode; 26, tunnel dielectric layer; 27, phosphorus-doped polysilicon layer; 280, metal silicon compound layer; 281, first dielectric buffer layer; 282, second dielectric buffer layer; 291, main back passivation layer; 292, secondary back passivation layer; 293, main back fine gate electrode;

[0054] Figure 3 is a schematic structural diagram of a solar cell according to Embodiment 2 of the present invention;

[0055] Figure 3 In the reference numerals: 31, silicon wafer; 32, boron diffused emitter; 33, AlO x Thin film; 34, front passivation layer; 35, front fine gate silver electrode; 36, tunnel dielectric layer; 37, phosphorus-doped polysilicon layer; 381, first dielectric buffer layer; 382, ​​second dielectric buffer layer; 391, main back passivation layer; 392, secondary back passivation layer; 393, main back fine gate electrode;

[0056] Figure 4 is a schematic structural diagram of a solar cell according to Embodiment 3 of the present invention;

[0057] Figure 4 In the reference numerals: 41, silicon wafer; 42, boron diffused emitter; 43, AlO x Thin film; 44, front passivation layer; 45, front fine gate silver electrode; 46, tunnel dielectric layer; 47, phosphorus-doped polysilicon layer; 480, metal silicon compound layer; 481, first dielectric buffer layer; 482, second dielectric buffer layer; 491, main back passivation layer; 492, secondary back passivation layer; 493, main back fine gate electrode; 494, secondary back fine gate electrode;

[0058] Figure 5 This is a schematic diagram of the connection between the back silver pad point and the back field electrode in Example 3 of the present invention;

[0059] Figure 5 In the figure marks: 590, back side back field electrode; 593, silver pad point; 594, overlapping area. DETAILED DESCRIPTION

[0060] The main concept of the present invention is: on the one hand, the present invention adopts a localized passivation contact structure on the back of the solar cell, that is, the passivation contact structure is not evenly distributed on the entire back surface of the cell, but only exists in the area around the metal grid line, while ensuring that the metal grid line is located on the passivation contact structure. Since the passivation metal structure is localized, most of the long-wave photons reaching the back surface of the silicon wafer will not be absorbed by the heavily doped polysilicon layer, but can be reflected back to the silicon wafer substrate by the back surface passivation film, and be reabsorbed and utilized, thereby increasing the photogenerated current value; on the other hand, the present invention adopts a whole-surface dielectric buffer layer in the local passivation contact structure, and unexpectedly found that it can overcome the problems of large metal composite and large contact resistance when the traditional "base" metal slurry is used in contact with doped polysilicon or doped emitter. After a large number of experimental studies, it is analyzed that the metal oxide used in the dielectric buffer layer itself does not have conductivity, but it can have a similar conduction band / valence band step with the phosphorus-doped polysilicon layer, so it can achieve selective collection of electrons / holes, play a certain role in interface passivation and interface carrier transport, and thus unexpected improvements have been achieved in short-circuit current, metal composite, interface contact and other aspects.

[0061] Based on this, the present invention provides a solar cell intermediate, a solar cell and a preparation method.

[0062] Specifically, the solar cell intermediate comprises:

[0063] A silicon wafer having a back surface, the back surface comprising a first region and a second region;

[0064] In the first region, a tunnel dielectric layer, a phosphorus-doped polysilicon layer, a first dielectric buffer layer, and a main back side fine gate electrode are sequentially arranged along a direction perpendicular to the first region;

[0065] In the second region, a main back passivation layer and a second dielectric buffer layer are sequentially arranged along a direction perpendicular to the second region;

[0066] The first dielectric buffer layer is in contact with the second dielectric buffer layer, and the first dielectric buffer layer and the second dielectric buffer layer are respectively film layers formed of metal compounds with a square resistance of more than 2000Ω / sq.

[0067] Furthermore, the preparation method of the solar cell intermediate includes:

[0068] Providing a silicon wafer having a back surface, wherein the back surface includes a first region and a second region;

[0069] sequentially disposing a tunnel oxide layer and a phosphorus-doped polysilicon layer on the back surface; and then removing the partial structures of the tunnel oxide layer and the phosphorus-doped polysilicon layer respectively located in the second region;

[0070] Disposing a back passivation layer on the back surface, and then completely or partially removing a portion of the back passivation layer located in the first region to expose a portion of the surface of the phosphorus-doped polysilicon layer located in the first region;

[0071] Disposing metal film layers on the first region and the second region respectively, wherein the metal film layer located in the first region is in contact with the exposed surface of the phosphorus-doped polysilicon layer;

[0072] Performing a heat treatment in an oxygen environment; wherein, after the heat treatment, the metal film layer located in the first region is transformed into a first dielectric buffer layer composed of a metal oxide with a square resistance of more than 2000Ω / sq, or a portion of the metal film layer located in the first region is transformed into a first dielectric buffer layer composed of a metal oxide with a square resistance of more than 2000Ω / sq, and the silicon in the phosphorus-doped polysilicon layer in contact with the remaining portion reacts to generate a metal silicon compound and forms a metal silicon compound layer; the metal film layer located in the second region is transformed into a second dielectric buffer layer composed of a metal oxide with a square resistance of more than 2000Ω / sq;

[0073] A back side fine gate electrode is provided at least on the first dielectric buffer layer.

[0074] Specifically, the preparation method of the solar cell intermediate of the present invention is further introduced below. The preparation method comprises:

[0075] (1) providing a single crystal silicon wafer as a substrate, and performing pre-cleaning, interface morphology modification, and subsequent cleaning on the single crystal silicon wafer;

[0076] (2) depositing a tunnel dielectric layer, a polysilicon layer or an amorphous silicon layer on the back surface of the substrate in sequence and subjecting the layer to high temperature treatment, so that the latter is transformed into a doped polysilicon layer and a doped silicon glass phase is generated on the outer surface;

[0077] (3) The back surface of the substrate is laser treated and wet etched to

[0078] The doped polysilicon layer and the tunnel dielectric layer corresponding to the second area (non-contact area) are completely removed and cleaned;

[0079] (4) depositing a passivation layer on the back surface of the substrate, and laser opening the film in the vertical projection area of ​​the doped polysilicon layer in the first area of ​​the substrate and removing the local passivation layer;

[0080] (5) depositing a dielectric buffer layer on the entire back surface of the silicon wafer;

[0081] (6) A "base" metal electrode is provided on the dielectric buffer layer at least in the first region.

[0082] Specifically, the single crystal silicon wafer in step (1) is an N-type silicon wafer, and the resistivity of the silicon wafer is 0.5-3Ω·cm;

[0083] Specifically, the purpose of pre-cleaning in step (1) is to remove surface damage and organic matter, and the specific cleaning process is to use an aqueous solution containing H2O2, NaOH, and a pre-cleaning auxiliary additive (commercially available conventional product) at a certain temperature to treat the silicon wafer;

[0084] Specifically, the interface morphology modification in step (1) can be divided into surface texturing and surface polishing. The specific process is to use an aqueous solution containing NaOH and auxiliary additives (commercially available conventional texturing additives, polishing additives, etc. can be selected, which can be purchased from Changzhou Shichuang Energy Co., Ltd., etc.) at a certain temperature to treat the silicon wafer. After the surface texturing treatment, a random small-sized pyramid morphology is formed on the surface of the silicon wafer; after the surface polishing, the surface forms a flat surface morphology.

[0085] Specifically, the tunnel dielectric layer in step (2) can be a tunnel oxide layer, or one or more selected from silicon oxide and silicon oxynitride. The overall thickness of the tunnel dielectric layer is 1-3 nm. The specific tunnel dielectric layer preparation method can include silicon oxide preparation method (thermal oxidation method, nitric acid oxidation method, ozone method, ALD method, PE method, etc.), silicon oxynitride preparation method (such as PE method). The role of the tunnel dielectric layer: chemical passivation of the interface while blocking phosphorus atoms from diffusing to the substrate surface to inhibit Auger recombination.

[0086] Specifically, the doped polysilicon layer in step (2) is specifically a heavily doped polysilicon layer, which is obtained by a first approach, i.e., depositing intrinsic amorphous silicon or intrinsic polysilicon and then subjecting it to a high-temperature phosphorus diffusion treatment, or by a second approach, i.e., depositing doped amorphous silicon and then subjecting it to a high-temperature crystallization annealing treatment. The first approach uses LPCVD, PECVD, PVD and other methods to deposit intrinsic amorphous silicon or intrinsic polysilicon, and the second approach uses PECVD or PVD to deposit doped amorphous silicon. Furthermore, the thickness of the doped polysilicon layer is 100-200nm, and the doping concentration is 1×10 20 -6×10 20 / cm 3 The role of the doped polysilicon layer: it plays a role in field passivation and interface band bending, inducing effective carrier transmission. At the same time, the carrier mobility of the film layer is high, which is conducive to the lateral transmission of carriers.

[0087] Specifically, the doped silica glass phase in step (2) is a phosphorus silicate glass layer, and its thickness is generally about 30-50 nm. The doped silica glass phase is a substance that is inevitably formed by high temperature treatment.

[0088] Specifically, the laser treatment in step (3) includes laser oxidation and laser film opening, and different laser treatments correspond to different ones. Further, the laser oxidation process: first remove the doped silicon glass phase on the surface by cleaning, then use laser to perform patterning scanning in an oxygen atmosphere to form a patterned oxide mask, and then perform wet etching to etch a certain thickness of the doped polysilicon layer in the area without the oxide mask, wherein the laser oxidation uses a laser as an ultraviolet light source, the pulse width is nanoseconds or picoseconds, the laser spot width is 100-200μm, and the thickness of the patterned oxide mask is 1-10nm.

[0089] Furthermore, the laser film opening process: no need for cleaning, directly use the laser to perform graphic scanning on the back surface of the substrate to remove the doped silicon glass phase in the scanning area, and then perform wet etching to allow the doped polysilicon layer in the area not covered by the doped silicon glass phase to be etched to a certain thickness. The laser film opening uses a green light or ultraviolet light source with a pulse width of picoseconds. The width of the film opening laser spot is 100-400μm. The laser film opening process will inevitably cause a certain thickness of the doped polysilicon layer to be removed.

[0090] Specifically, the wet etching process in step (3) is to treat the silicon wafer substrate with an aqueous solution containing NaOH and etching auxiliary additives at a certain temperature, so that the doped polysilicon layer directly exposed to the solution reacts with NaOH, thereby reducing the thickness of the doped polysilicon layer.

[0091] Specifically, the cleaning process in step (3) is to first use an aqueous solution containing H2O2 and NaOH at a certain temperature to clean to remove surface additive residues, and then use a mixed aqueous solution of HF and HCl to clean to remove alkali residues and remove the patterned oxide mask or doped silicon glass phase.

[0092] Specifically, the method of completely removing the doped polysilicon layer and the tunnel dielectric layer corresponding to the second region may be performed by referring to the above method or other prior arts.

[0093] Specifically, after the step (3) is carried out, the selective Poly-Si structure is prepared.

[0094] Specifically, the passivation layer described in step (4) is one of silicon nitride film, aluminum oxide + silicon nitride laminated film, silicon nitride + silicon oxynitride laminated film, aluminum oxide + silicon nitride + silicon oxynitride laminated film, wherein the preparation method of silicon nitride is PECVD method, the preparation method of aluminum oxide is ALD or PEALD method, and the preparation method of silicon oxynitride is PECVD method. The thickness of the passivation layer is 20-80nm. The function of the passivation layer is to provide hydrogen passivation.

[0095] Specifically, the laser light source used to remove the passivation layer in step (4) is an ultraviolet light source with a pulse width of picoseconds. The laser spot size is smaller than the vertical projection width of the first doped polysilicon layer, and the laser spot size is 30-100 μm.

[0096] Specifically, in step (5), the sheet resistance of the dielectric buffer layer is above 2000Ω / sq, the dielectric buffer layer is specifically a metal oxide, and the metal compound is selected from ML x wherein M is a combination of one or more selected from Ti, Li, Ta, Mg, Hf, Sc, W, Mo and V, L is a combination of one or more selected from O, C and N, and x is the coordination number of L. Further, a selected from TiO x 、TaO x MgO x A combination of one or more of the above. The dielectric buffer layer as a whole is not conductive, and has a similar conduction band step to silicon. At the same time, the oxygen vacancy defects in the film layer have the ability to migrate electrons, so it can have the ability to transport electrons. The role of the dielectric buffer layer: isolate the "base" metal electrode from the doped polysilicon layer to avoid direct contact; at the same time, it plays an electron transport role. Furthermore, the thickness of the dielectric buffer layer is 10-100nm.

[0097] Specifically, the preparation method of the dielectric buffer layer in step (5) includes the following methods: first, a pure metal film is first deposited by a PVD method, and then oxidized and modified at a certain temperature, so that a metal oxide is formed on the surface of the metal film; and second, a method of directly depositing a metal oxide film by an ALD method or a PVD method. The first method includes the following situations: (1) After high-temperature treatment and a long treatment time, the pure metal film is completely converted into a metal oxide; (2) After high-temperature treatment, a certain thickness of metal on the surface is oxidized into a metal oxide, and the bottom metal layer reacts with the doped polysilicon layer in direct contact (the passivation layer is opened and exposed) to form a metal silicide; (3) When the temperature is low and the treatment time is short, the surface metal is oxidized into a metal oxide, while the bottom metal film is not completely oxidized, and due to the low temperature, the metal does not react with the polysilicon. The above situations ultimately depend on the thickness of the pure metal film, the high-temperature modification temperature, the high-temperature treatment time, and the oxygen concentration. The PVD method in the second method includes depositing a sputtered metal oxide target or introducing oxygen while depositing a pure metal film. The metal oxide prepared by the second method is an amorphous phase, and has more crystal defects than the first method. It is possible to choose to perform high-temperature treatment after depositing the metal oxide film to reduce defects in the film and improve the crystal structure distribution.

[0098] Specifically, in step (5), a dielectric buffer layer is deposited on the entire back surface, and the dielectric buffer layer is distributed on the entire surface. The first dielectric buffer layer located in the first area can directly contact the doped polysilicon layer in the laser opening area, and the second dielectric buffer layer located in the second area is located on the passivation layer in the second area.

[0099] Specifically, the "base" metal slurry used for the "base" metal electrode in step (6) includes aluminum paste and copper paste, and the setting method of the "base" metal electrode includes screen printing or laser transfer, and the high-temperature sintering peak temperature is 600-800°C. The graphic design of the "base" metal slurry electrode includes electrode grid line design and full-surface electrode design. Furthermore, the local grid line covers the vertical projection area of ​​the passivation layer film opening area.

[0100] Specifically, during the high temperature sintering process in step (6), the "base" metal slurry deposited on the dielectric buffer layer will burn through a certain thickness of the dielectric buffer layer, and stay in the dielectric buffer layer during sintering cooling. Furthermore, the thickness of the dielectric buffer layer retained under the "base" metal slurry is 5-20nm. The "base" metal slurry will not damage the passivation layer.

[0101] In some embodiments, the method for preparing a solar cell comprising a solar cell intermediate of the present invention comprises:

[0102] Step 1: Take an N-type monocrystalline silicon wafer, pre-clean it to remove organic matter and particulate matter on the surface of the wafer, and then perform a texturing process to obtain a small-sized random pyramid morphology on the surface of the battery. Then perform an alkali and hydrogen peroxide cleaning to remove residual additives on the surface, and finally perform a hydrofluoric acid and hydrochloric acid mixed acid solution cleaning to remove surface alkali residues and inorganic and metal impurities.

[0103] Step 2: Insert the silicon wafer horizontally into the quartz boat and send it into the quartz furnace tube, heat it to 840-880℃, introduce a boron doping source (for example, boron trichloride) for surface source deposition, the amount introduced is 300-400sccm, then stop the source, and heat it up and push it forward, the push temperature is 900-940℃, and the push atmosphere gas is nitrogen. After the push is completed, continue to heat it up to 1020-1060℃ and keep the temperature constant, the atmosphere gas is oxygen. The boron diffusion square resistance is 200-300Ω / sq, and the surface doping concentration is 2×10 18 -8×10 18 / cm 3 The boron-doped layer on the front and back surfaces of the silicon wafer forms a borosilicate glass layer with a thickness of 80-120nm.

[0104] Step 3: Use a chain machine to perform single-sided HF treatment, with the back surface facing downward and the front surface facing upward, so that the back surface and edge borosilicate glass layer are removed.

[0105] Step 4: Pre-clean the silicon wafer and then polish it to achieve a flat tower base morphology on the back of the battery, with a tower base size of 10-15μm. Then use alkali and hydrogen peroxide to remove residual additives on the surface, and finally use a mixed acid solution of hydrofluoric acid and hydrochloric acid to remove surface alkali residues and inorganic and metal impurities.

[0106] Step 5: Insert the silicon wafer horizontally into the quartz boat and send it into the quartz furnace tube, and prepare the tunnel oxide layer by thermal oxidation, nitric acid oxidation, ozone, ALD, PE, etc., or prepare the silicon oxynitride tunnel dielectric layer by PE, and then prepare intrinsic amorphous silicon or intrinsic polycrystalline silicon. Since the silicon wafer adopts single insertion, the tunnel dielectric layer and intrinsic amorphous silicon or intrinsic polycrystalline silicon are deposited on both the front and back sides.

[0107] Step 6: Insert the silicon wafer into the phosphorus diffusion quartz boat and send it into the phosphorus diffusion furnace tube, heat it to 770-810℃ and then introduce phosphorus oxychloride for surface source deposition. The amount of phosphorus oxychloride introduced is 1500-1700sccm. After the deposition is completed, start heating and advancing, only nitrogen gas is introduced, and the advancement temperature is 860-900℃. After the advancement is completed, the temperature begins to drop, and oxygen is introduced during the cooling process to accelerate surface oxidation. Finally, exit the tube and take out the sample. After step 6, a phosphorus silicon glass layer is generated on the outer surface of the silicon wafer.

[0108] Step 7:

[0109] Use a green picosecond laser to pattern the back surface of the silicon wafer. The pattern is a plurality of parallel straight lines with the same spacing. The light spot is a square spot, and the spots do not overlap. Then use a chain machine to perform single-sided HF treatment, with the front surface facing down and the back surface facing up, so that the phosphosilicate glass layer on the front surface and edge is removed. Then perform the RCA cleaning process, first perform the de-plating treatment, the purpose of this step is to remove the polysilicon and tunnel dielectric layer on the front surface and edge and the back surface opening area. Then perform alkali and hydrogen peroxide cleaning to remove residual additives on the surface, and finally perform a mixed acid solution of hydrofluoric acid and hydrochloric acid to clean and remove alkali residues, as well as the borosilicate glass layer and the phosphosilicate glass layer. After step 7, the tunnel dielectric layer and phosphorus-doped polysilicon layer located in the second area are removed.

[0110] Step 8: Insert the silicon wafer into the ALD metal boat and send it into the ALD metal chamber, raise the temperature to 270-310°C, control the reaction pressure to 30-50Pa, and then pass trimethylaluminum (TMA) and high-purity water in turn for atomic layer deposition cycle reaction, the number of cycles is 20-40. After step 8, AlO is generated on the front surface of the silicon wafer. x film.

[0111] Step 9: Insert the silicon wafer into the graphite boat with the front surface facing outward, and send it into the PECVD furnace tube, heat it to 400-500℃, and control the pressure in the tube at 100-300Pa, then introduce different proportions of silane, ammonia and nitrous oxide in sequence to form a multi-layer front passivation layer structure.

[0112] Step 10: Insert the silicon wafer into the graphite boat with the back surface facing outward, and send it into the PECVD furnace tube, heat it to 400-500℃, and control the pressure in the tube at 100-300Pa, then introduce different proportions of silane and ammonia in sequence to form a back passivation layer structure.

[0113] Step 11: Use an ultraviolet picosecond laser to perform laser film opening in the vertical projection area of ​​the phosphorus-doped polysilicon layer in the first area. The laser scanning pattern for film opening is a plurality of parallel straight lines with the same spacing distribution, the light spot is a square light spot, and the light spot overlap rate is 0%. The back passivation layer in the laser scanning area is removed.

[0114] Step 12: Use magnetron sputtering to bombard a metal target (such as Ti, Li, Ta, Mg, Hf, Sc, W, Mo and V) with argon gas, and sputter deposit on the entire back surface. After sputtering, heat and oxidize in an oxygen atmosphere.

[0115] The thickness of the sputtered deposited metal film, the heated oxidation temperature, the heated oxidation processing time and the oxygen concentration determine whether the metal film is completely converted into metal oxide, or partially converted into metal oxide and partially reacts with the directly contacting doped polysilicon layer (the passivation layer is opened and exposed) to form metal silicide.

[0116] Step 13:

[0117] (Method 1) Use printing to print the back main grid, back fine grid, front main grid, and front fine grid in sequence. After printing the back main grid, back fine grid, and front main grid, they all need to be dried at low temperature to remove most of the organic matter and solidify the electrode. The drying temperature is 200-300°C. The back main grid, front main grid, and front fine grid are all different types of silver pastes. The solid content of the main grid is 80-85%, the solid content of the silver paste is 90-95%, and the back fine grid is aluminum paste or copper paste. The shape of the main grid and the fine grid are both grid lines, and the main grid and the fine grid overlap and intersect to form an H-type electrode structure. The back fine grid completely covers the vertical projection area of ​​the laser film opening area in step 11, and is all on the surface of the metal film.

[0118] (Method 2) Use printing to print the back silver pad points (interconnection base points of silver material), back back field electrode, front main grid, and front fine grid in sequence. After printing the back silver pad points, back back field electrode, and front main grid, they all need to be dried at low temperature to remove most of the organic matter and solidify the electrode. The drying temperature is 200-300°C. The back main grid, front main grid, and front fine grid are all different types of silver paste. The solid content of the main grid is 80-85%, the solid content of the silver paste is 90-95%, and the back back field electrode is a corrosive aluminum paste. The shape of the main grid and the fine grid are both grid lines, and the main grid and the fine grid overlap and intersect to form an H-type electrode structure. The back silver pads are orderly distributed on the back, and the back back field electrode covers the entire back and overlaps with the silver pad points.

[0119] The above scheme is further described below in conjunction with specific embodiments; it should be understood that these embodiments are used to illustrate the basic principles, main features and advantages of the present invention, and the present invention is not limited to the scope of the following embodiments; the implementation conditions adopted in the embodiments can be further adjusted according to specific requirements, and the implementation conditions not specified are usually the conditions in conventional experiments.

[0120] Unless otherwise specified in the following examples, all raw materials are commercially available or prepared by conventional methods in the art. Comparative Example 1: This comparative example provides a solar cell and a method for preparing the same

[0121] The preparation method comprises:

[0122] Step 1: Take an N-type single crystal silicon wafer with a resistivity of 1Ω·cm, pre-clean the wafer to remove organic matter and particulate matter on the surface of the wafer. The pre-cleaning conditions are: temperature 68°C, time 120s, H2O2:NaOH:DI Water (deionized water) = 32:8:690 (volume ratio), and then perform texturing treatment to obtain a small-sized random pyramid morphology on the surface of the battery, with a pyramid size of about 1.5μm. The texturing conditions are: temperature 82°C, time 420s, additives: NaOH:DI Water = 2.7:9.5:680 (volume ratio). Then perform alkali and hydrogen peroxide cleaning to remove residual additives on the surface, and finally perform hydrofluoric acid and hydrochloric acid mixed acid solution cleaning to remove surface alkali residues and inorganic and metal impurities.

[0123] Step 2: Insert the silicon wafer horizontally into the quartz boat and send it into the quartz furnace tube. Heat it to 860℃, introduce the boron trichloride doping source for surface source deposition, and the amount of introduction is 350sccm. Then stop the source and heat it up. The pushing temperature is 920℃, and the pushing atmosphere is nitrogen. After the pushing is completed, continue to heat it up to 1040℃ and keep the temperature constant. The atmosphere is oxygen. The boron diffusion square resistance is about 250Ω / sq, and the surface doping concentration is about 4×10 18 / cm 3A borosilicate glass layer with a thickness of about 100nm is generated on the surface of the boron-dopant layer on the front and back surfaces of the silicon wafer.

[0124] Step 3: Use a chain machine to perform single-sided HF treatment, with the back surface facing downward and the front surface facing upward, so that the back surface and edge borosilicate glass layer are removed.

[0125] Step 4: Pre-clean the silicon wafer under the following conditions: temperature 65°C, time 120s, H2O2:NaOH:DIWater=8.4:3.6:670 (volume ratio), and then polish to achieve a flat tower base morphology on the back of the battery, with a tower base size of about 7μm. Then, use alkali and hydrogen peroxide to remove residual additives on the surface, and finally use a mixed acid solution of hydrofluoric acid and hydrochloric acid to remove surface alkali residues, inorganic matter, and metal impurities.

[0126] Step 5: Insert the silicon wafer horizontally into the quartz boat and send it into the quartz furnace tube, heat it to 600°C and then introduce oxygen for constant temperature oxidation (i.e. thermal oxidation method), then evacuate the oxygen and purge it with nitrogen, then heat it to 610°C and reduce the pressure to 32Pa, introduce silane (SiH4) for intrinsic polysilicon deposition, evacuate the silane and purge it with nitrogen after deposition, finally cool it down and take out the sample. Since the silicon wafer adopts single insertion, the tunneling oxide layer and the intrinsic polysilicon layer are deposited on both the front and back sides. The thickness of the tunneling oxide layer is about 1.7nm, and the thickness of the intrinsic polysilicon layer is about 120nm.

[0127] Step 6: Insert the silicon wafer into the phosphorus diffusion quartz boat and send it into the phosphorus diffusion furnace tube. Heat it to 790°C and then introduce phosphorus oxychloride for surface source deposition. The amount of phosphorus oxychloride introduced is 1600sccm. After the deposition is completed, start heating and advance. Only nitrogen gas is introduced. The advancement temperature is 880°C. After the advancement is completed, the temperature begins to drop. During the cooling process, oxygen is introduced to accelerate surface oxidation. Finally, exit the tube and take out the sample. After step 6, a phosphorus silicon glass layer is generated on the outer surface of the silicon wafer. The square resistance of the phosphorus diffusion test is about 45Ω / sq, and the doping concentration of the polysilicon layer is 3×10 20 / cm 3 , the thickness of the phosphosilicate glass layer is about 30nm.

[0128] Step 7: Use a chain machine to perform single-sided HF treatment, with the front surface facing down and the back surface facing up, so that the front surface and the edge phosphosilicate glass layer are removed. Then perform the RCA cleaning process, first perform the de-wrap treatment, the specific conditions are as follows: de-wrap auxiliary additives (commercially available conventional products): NaOH: DI water = 6.8: 32: 650 (volume ratio), temperature 65 ° C, time 300s, the purpose of this step is to remove the front surface and edge polysilicon. Then perform alkali and hydrogen peroxide cleaning to remove residual additives on the surface, and finally perform hydrofluoric acid and hydrochloric acid mixed acid solution cleaning to remove alkali residues and borosilicate glass layer and phosphosilicate glass layer.

[0129] Step 8: Insert the silicon wafer into the ALD metal boat and send it into the ALD metal chamber, raise the temperature to 290°C, control the reaction pressure to 40Pa, and then pass TMA and high-purity water in turn for atomic layer deposition cycle reaction, the number of cycles is 28. After step 8, AlO is generated on the front surface of the silicon wafer. x film.

[0130] Step 9: Insert the silicon wafer into the graphite boat with the front surface facing outward, and send it into the PECVD furnace tube, heat it to 450℃, and control the pressure in the tube at 200Pa, then introduce different proportions of silane, ammonia, and laughing gas in sequence to form a multi-layer front passivation layer structure. The thickness of the front passivation layer is about 75nm.

[0131] Step 10: Insert the silicon wafer into the graphite boat with the back surface facing outward, and send it into the PECVD furnace tube, heat it to 450°C, and control the pressure in the tube at 200Pa, then introduce different proportions of silane and ammonia in sequence to form a back passivation layer structure. The thickness of the back passivation layer is about 80nm.

[0132] Step 11: Use printing to print the back main grid, back fine grid, front main grid, and front fine grid in sequence. After printing the back main grid, back fine grid, and front main grid, they all need to be dried at low temperature to remove most of the organic matter and solidify the electrode. The drying temperature is 275±10°C. The printing of the front fine grid requires high-temperature sintering. The sintering peak upper temperature zone temperature is 730°C, and the lower temperature zone is 700°C. The back main grid, back fine grid, front main grid, and front fine grid are all different types of silver pastes. The solid content of the main grid is about 2%, and the solid content of the silver paste is about 92%. The shape of the main grid and the fine grid are both grid lines, and the main grid and the fine grid overlap and intersect to form an H-type electrode structure. The width of the back fine grid is 30μm, the number of back fine grid lines is 200, the width of the back main grid is 60μm, and the total wet weight of the back electrode is about 45mg. The final battery structure corresponding to Comparative Example 1 is shown in Figure 1 The boron diffused emitter 12, AlO x The film 13, the front passivation layer 14, and the AlO x A front fine-gate silver electrode 15 is provided on the back surface of the silicon wafer 11 through a thin film 13 and in contact with the boron-diffused emitter 12. A tunnel dielectric layer 16, a phosphorus-doped polysilicon layer 17, a back passivation layer 18, and a back fine-gate silver electrode 19 passing through the back passivation layer 18 and in contact with the phosphorus-doped polysilicon layer 17 are sequentially arranged.

[0133] Embodiment 1:

[0134] This example provides a method for preparing a solar cell including a solar cell intermediate and a solar cell made therefrom.

[0135] Specifically: Steps 1 to 6 of this example are consistent with Steps 1 to 6 of Comparative Example 1;

[0136] Step 7: Use a green picosecond laser to pattern the back of the silicon wafer. The pattern is a plurality of parallel straight lines with the same spacing. The spot is a square spot with a size of 200μm, and the spots do not overlap. Then use a chain machine to perform single-sided HF treatment, with the front side facing down and the back side facing up, so that the front and edge phosphorus silicon glass layers are removed. Then perform the RCA process, first perform the de-plating treatment, the specific conditions are as follows: additives: NaOH: DI water = 6.8: 32: 650, temperature 65 ° C, time 300s, the purpose of this step is to remove the polysilicon on the front and edge and back film opening areas. Then perform alkali and hydrogen peroxide cleaning to remove residual additives on the surface, and finally perform hydrofluoric acid and hydrochloric acid mixed acid solution cleaning to remove alkali residues, as well as borosilicate glass layer and phosphorus silicon glass layer.

[0137] Step 8-Step 9 are the same as Step 8-Step 9 of Comparative Example 1;

[0138] Step 10: Insert the silicon wafer into the graphite boat with the back side facing outwards, and send it into the PECVD furnace tube, heat it to 450°C, and control the pressure in the tube at 200Pa, then introduce silane and ammonia in sequence (the volume ratio of silane to ammonia is 1:6) to form a back passivation layer structure. The thickness of the back passivation layer is about 40nm.

[0139] Step 11: Use an ultraviolet picosecond laser to perform laser film opening in the vertical projection area of ​​the phosphorus-doped polysilicon layer in the first area (corresponding to the metal contact area). The laser scanning pattern for film opening is a plurality of parallel straight lines with the same spacing distribution. The spot is a square spot with a size of 30μm, a spot overlap rate of 0%, and a power of 11% of the maximum power. The back passivation layer in the laser scanning area is removed.

[0140] Step 12: Use magnetron sputtering method to bombard titanium target with argon gas, expose the back of silicon wafer and fix it in the deposition position. The reaction pressure of magnetron sputtering is 1-2Pa, the temperature is set to room temperature, the sputtering power is 10kw, and the thickness of titanium film deposition is 20nm. Then oxidize at 800℃ in oxygen atmosphere for 3min. Titanium forms titanium silicide metal silicide with doped polysilicon in the open film area of ​​passivation dielectric film at high temperature, that is, metal silicon compound layer with a thickness of 5nm; the titanium metal film deposited in the non-open film area of ​​passivation dielectric film is completely oxidized into titanium dioxide film with a square resistance of 4500Ω / sq and a thickness of about 38nm.

[0141] Step 13: Use printing to print the back main grid, back fine grid, front main grid, and front fine grid in sequence. After printing the back main grid, back fine grid, and front main grid, they all need to be dried at low temperature to remove most of the organic matter and solidify the electrode. The drying temperature is 275±10°C. The back main grid, front main grid, and front fine grid are all different types of silver pastes. The solid content of the main grid is about 82%, the solid content of the silver paste is about 92%, and the back fine grid is a non-burn-through aluminum paste (a conventional product on the market). The shapes of the main grid and the fine grid are both grid lines, and the main grid and the fine grid overlap and intersect to form an H-shaped electrode structure. The back fine grid completely covers the vertical projection area of ​​the laser film opening area in step 11, and is all on the surface of the titanium dioxide film. The width of the back fine grid is 100μm, the number of back fine grid lines is 200, the width of the back main grid is 60μm, the wet weight of the back fine grid is 240mg, and the wet weight of the back main grid is 8mg.

[0142] The battery structure made in this example can be Figure 2 As shown, a boron diffused emitter 22, an AlO x The film 23, the front passivation layer 24, and the AlO x The thin film 23 and the front fine-grid silver electrode 25 in contact with the boron-diffused emitter 22 are on the back surface of the silicon wafer 21, and the back surface includes a first area (corresponding to the metal contact area) and a second area (corresponding to the non-metal contact area);

[0143] In the first region, a tunnel dielectric layer 26, a phosphorus-doped polysilicon layer 27, a metal silicon compound layer 280, a first dielectric buffer layer 281, and a main back side fine gate electrode 293 are sequentially arranged along a direction perpendicular to the first region;

[0144] In the second region, a main back passivation layer 291 and a second dielectric buffer layer 282 are sequentially arranged along a direction perpendicular to the second region;

[0145] At the same time, in the first region, a secondary back passivation layer 292 is also provided. The secondary back passivation layer 292 is provided on the peripheral side of the surface of the phosphorus-doped polysilicon layer 27 and a hole is formed in the middle. The first dielectric buffer layer 281 has a portion passing through the hole and in contact with the phosphorus-doped polysilicon layer 27 through the metal silicon compound layer 280. The secondary back passivation layer 292 and the main back passivation layer 291 are integrally formed, and the first dielectric buffer layer 281 and the second dielectric buffer layer 282 are integrally formed.

[0146] Embodiment 2:

[0147] This example provides a method for preparing a solar cell including a solar cell intermediate and a solar cell made therefrom.

[0148] Specifically: Step 1 to Step 11 and Step 13 of this example are the same as Step 1 to Step 11 and Step 13 of Example 1. Step 12: Use a magnetron sputtering method to bombard the titanium dioxide target with argon gas, place the back of the silicon wafer facing the target and fix it on a carrier, the reaction pressure is 1-2Pa, the temperature is set to 250°C, the sputtering power is 20kw, and the thickness of the obtained titanium dioxide film is about 38nm, and the square resistance is 2700Ω / sq.

[0149] For the corresponding battery structure, see Figure 3 As shown, a boron diffused emitter 32, an AlO x The film 33, the front passivation layer 34, and the AlO x The front fine-grid silver electrode 35 of the thin film 33 and in contact with the boron-diffused emitter 32 is on the back surface of the silicon wafer 31, and the back surface includes a first area (corresponding to the metal contact area) and a second area (corresponding to the non-metal contact area);

[0150] In the first region, a tunnel dielectric layer 36, a phosphorus-doped polysilicon layer 37, a first dielectric buffer layer 381, and a main back side fine gate electrode 393 are sequentially arranged along a direction perpendicular to the first region;

[0151] In the second region, a main back passivation layer 391 and a second dielectric buffer layer 382 are sequentially arranged along a direction perpendicular to the second region;

[0152] At the same time, in the first region, a secondary back passivation layer 392 is also provided. The secondary back passivation layer 392 is provided on the peripheral side of the surface of the phosphorus-doped polysilicon layer 37 and a hole is formed in the middle. The first dielectric buffer layer 381 has a portion passing through the hole and contacting the phosphorus-doped polysilicon layer 37. The secondary back passivation layer 392 and the main back passivation layer 391 are integrally formed, and the first dielectric buffer layer 381 and the second dielectric buffer layer 382 are integrally formed.

[0153] Embodiment 3:

[0154] This example provides a method for preparing a solar cell including a solar cell intermediate and a solar cell made therefrom.

[0155] Specifically: Steps 1-12 of this example are the same as steps 1-12 of Example 1. Step 13 of this example is as follows:

[0156] Step 13: Step 13: Use printing to print the back silver pad points, back back field electrode, front main grid, and front fine grid in sequence. After printing the back silver pad points, back back field electrode, and front main grid, they all need to be dried at low temperature to remove most of the organic matter and solidify the electrode. The drying temperature is. The back main grid, front main grid, and front fine grid are all different types of silver pastes. The solid content of the main grid is about 82%, the solid content of the silver paste is about 92%, and the back back field electrode is a non-burn-through aluminum paste. The main grid and the fine grid are both in the shape of grid lines, and the main grid and the fine grid overlap and intersect to form an H-type electrode structure. The back silver pads are orderly distributed on the back, and the back back field electrode covers the entire back and overlaps with the silver pad points. The wet weight of the back back field electrode is 400mg, and the wet weight of the back silver pad points is 18mg.

[0157] The battery structure corresponding to this example is shown in Figure 4 As shown, a boron diffused emitter 42, an AlO x The film 43, the front passivation layer 44, and the AlO x The front fine-grid silver electrode 45 of the thin film 43 and in contact with the boron-diffused emitter 42 is on the back surface of the silicon wafer 41, and the back surface includes a first area (corresponding to the metal contact area) and a second area (corresponding to the non-metal contact area);

[0158] In the first region, a tunnel dielectric layer 46, a phosphorus-doped polysilicon layer 47, a metal silicon compound layer 480, a first dielectric buffer layer 481, and a main back side fine gate electrode 493 are sequentially arranged along a direction perpendicular to the first region;

[0159] In the second region, a main back passivation layer 491 and a second dielectric buffer layer 482 are sequentially arranged along a direction perpendicular to the second region;

[0160] At the same time, in the first region, a secondary back passivation layer 492 is also provided. The secondary back passivation layer 492 is provided on the peripheral side of the surface of the phosphorus-doped polysilicon layer 47 and a hole is formed in the middle. The first dielectric buffer layer 481 has a portion passing through the hole and contacting the phosphorus-doped polysilicon layer 47. The secondary back passivation layer 492 and the main back passivation layer 491 are integrally formed, and the first dielectric buffer layer 481 and the second dielectric buffer layer 482 are integrally formed.

[0161] At the same time, in the second region, a secondary back fine gate electrode 494 is also provided, and the secondary back fine gate electrode 494 and the main back fine gate electrode 493 together constitute a whole surface electrode (i.e., a back back field electrode) covering the entire area of ​​the first region and the second region, forming a Figure 5 As shown, the entire back surface is basically covered, with only the area where the silver pad point is left uncovered, and the back back field electrode 590 surrounds the silver pad point 593 and has a partial overlap with the silver pad point 593 to form an overlapping area 594.

[0162] Performance Test:

[0163] The batteries obtained in the above-mentioned Examples 1-3 and Comparative Example 1 were subjected to the following performance tests, and the test method was: using an IV tester to test the battery photoelectric conversion efficiency and related electrical performance parameters under standard light power under a simulated solar light source. The specific test results are shown in Table 1 (Eta: conversion efficiency, Voc: open circuit voltage, Jsc: short circuit current density, FF: fill factor).

[0164] Table 1

[0165]

[0166] As can be seen from Table 1, the conversion efficiency of the battery of the present invention has been significantly improved. Compared with the comparative example 1, the conversion efficiency of Example 1 is improved by 0.16%. For crystalline silicon solar cells, a change of 0.1% is usually a huge improvement. It can be seen that the improved battery structure of the present invention can optimize the short-circuit current density, open-circuit voltage, and fill factor, and promote a significant improvement in battery efficiency under the synergistic effect. It can also replace silver paste with "cheap" metal paste in the back fine grid electrode, which greatly reduces the cost.

[0167] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

[0168] The endpoints and any values ​​of the ranges disclosed in this article are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article.

Claims

1. A solar cell intermediate, characterized in that: The solar cell intermediate comprises: A silicon wafer having a back surface, the back surface comprising a first region and a second region; In the first region, a tunnel dielectric layer, a phosphorus-doped polysilicon layer, a first dielectric buffer layer, and a main back side fine gate electrode are sequentially arranged along a direction perpendicular to the first region; In the second region, a main back passivation layer and a second dielectric buffer layer are sequentially arranged along a direction perpendicular to the second region; The first dielectric buffer layer is in contact with the second dielectric buffer layer, and the first dielectric buffer layer and the second dielectric buffer layer are respectively film layers formed by metal compounds with a square resistance of more than 2000Ω / sq.

2. The solar cell intermediate according to claim 1, characterized in that: The thickness of the first dielectric buffer layer and the second dielectric buffer layer are respectively 10-100 nm.

3. The solar cell intermediate according to claim 1, characterized in that: The sheet resistance of the first dielectric buffer layer and the sheet resistance of the second dielectric buffer layer are 2000-15000Ω / sq respectively.

4. The solar cell intermediate according to claim 1, characterized in that: The metal compound is selected from ML x wherein M is a combination of one or more selected from Ti, Li, Ta, Mg, Hf, Sc, W, Mo and V, L is a combination of one or more selected from O, C and N, and x is the coordination number of L.

5. The solar cell intermediate according to claim 4, characterized in that: The metal compound is selected from TiO x 、TaO x MgO x A combination of one or more of .

6. The solar cell intermediate according to claim 1, characterized in that: The solar cell intermediate also includes a secondary back passivation layer, which is arranged on the peripheral side of the surface of the phosphorus-doped polysilicon layer and forms a hole in the middle. The first dielectric buffer layer has a portion that passes through the hole and contacts the phosphorus-doped polysilicon layer, and the contact is direct contact or indirect contact. The orthographic projection of the secondary back passivation layer is located within the orthographic projection range of the phosphorus-doped polysilicon layer.

7. The solar cell intermediate according to claim 6, characterized in that: The secondary back passivation layer is integrally formed with the primary back passivation layer.

8. The solar cell intermediate according to claim 1, characterized in that: The first dielectric buffer layer and the second dielectric buffer layer are integrally formed.

9. The solar cell intermediate according to claim 1, characterized in that: The solar cell intermediate also includes a metal silicon compound layer, which is located between the phosphorus-doped polycrystalline silicon layer and the first dielectric buffer layer. The material of the metal silicon compound layer is an alloy formed by Z and Si, and Z is a combination of one or more selected from Ti, Li, Ta, Mg, Hf, Sc, W, Mo and V.

10. The solar cell intermediate according to claim 9, characterized in that: The metal in the metal silicon compound layer is the same as the metal of the metal compound in the first dielectric buffer layer.

11. The solar cell intermediate according to claim 1, characterized in that: The metal material in the main back fine gate electrode is aluminum and / or copper; and / or, the solar cell intermediate also includes a secondary back fine gate electrode, and the secondary back fine gate electrode and the main back fine gate electrode together constitute a full-surface electrode covering more than 90% of the first area and the second area; and / or, the thickness of the tunneling dielectric layer is 1-3nm, and the thickness of the phosphorus-doped polysilicon layer is 100-200nm.

12. A method for preparing a solar cell intermediate, characterized in that: The preparation method comprises: Providing a silicon wafer having a back surface, wherein the back surface includes a first region and a second region; sequentially disposing a tunnel oxide layer and a phosphorus-doped polysilicon layer on the back surface; and then removing the partial structures of the tunnel oxide layer and the phosphorus-doped polysilicon layer respectively located in the second region; Disposing a back passivation layer on the back surface, and then completely or partially removing a portion of the back passivation layer located in the first region to expose a portion of the surface of the phosphorus-doped polysilicon layer located in the first region; Disposing metal film layers on the first region and the second region respectively, wherein the metal film layer located in the first region is in contact with the exposed surface of the phosphorus-doped polysilicon layer; Performing a heat treatment in an oxygen environment; wherein, after the heat treatment, the metal film layer located in the first region is transformed into a first dielectric buffer layer composed of a metal oxide with a square resistance of more than 2000Ω / sq, or a portion of the metal film layer located in the first region is transformed into a first dielectric buffer layer composed of a metal oxide with a square resistance of more than 2000Ω / sq, and the silicon in the phosphorus-doped polysilicon layer in contact with the remaining portion reacts to generate a metal silicon compound and forms a metal silicon compound layer; the metal film layer located in the second region is transformed into a second dielectric buffer layer composed of a metal oxide with a square resistance of more than 2000Ω / sq; A back side fine gate electrode is provided at least on the first dielectric buffer layer.

13. The method for preparing a solar cell intermediate according to claim 12, characterized in that: The temperature of the heating treatment is 600-1000° C., and the treatment time is 1-10 minutes.

14. A solar cell, characterized in that: The solar cell comprises the solar cell intermediate according to any one of claims 1 to 11.

15. A method for preparing a solar cell, characterized in that: The preparation method comprises: Step (1) provides a silicon wafer, and performs boron diffusion treatment on the silicon wafer to form emitters on the front surface and the back surface of the silicon wafer respectively; Step (2) removing the emitter on the back surface of the silicon wafer; Step (3) The back surface includes a first region and a second region; sequentially disposing a tunnel oxide layer and a phosphorus-doped polysilicon layer on the back surface; and then removing the partial structures of the tunnel oxide layer and the phosphorus-doped polysilicon layer respectively located in the second region; Disposing a back passivation layer on the back surface, and then completely or partially removing a portion of the back passivation layer located in the first region to expose a portion of the surface of the phosphorus-doped polysilicon layer located in the first region; Performing a heat treatment in an oxygen environment; wherein, after the heat treatment, the metal film layer located in the first region is transformed into a first dielectric buffer layer composed of a metal oxide with a square resistance of more than 2000Ω / sq, or a portion of the metal film layer located in the first region is transformed into a first dielectric buffer layer composed of a metal oxide with a square resistance of more than 2000Ω / sq, and the silicon in the phosphorus-doped polysilicon layer in contact with the remaining portion reacts to generate a metal silicon compound and forms a metal silicon compound layer; the metal film layer located in the second region is transformed into a second dielectric buffer layer composed of a metal oxide with a square resistance of more than 2000Ω / sq; A back side fine gate electrode is provided at least on the first dielectric buffer layer.

16. The method for preparing a solar cell according to claim 15, characterized in that: In the process (3), when the back side fine gate electrode is set in an area of ​​more than 90% of the back surface, a connection base point made of silver material on the back side is first printed, and then the back side fine gate electrode is set to surround the connection base point and / or partially overlap with the connection base point.

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