Broadband voltage on-line measuring device based on FPGA + ARM architecture

Abstract

The invention discloses a broadband voltage on-line measuring device based on an FPGA + ARM framework. The broadband voltage on-line measuring device comprises a power supply system, a secondary side voltage monitoring module, a high-speed data transmission module and a broadband voltage inversion module. The power supply system supplies power to the secondary side output voltage monitoring module, the high-speed data transmission module and the broadband voltage inversion module; the secondary side voltage monitoring module monitors the secondary side output voltage of the voltage transformer, preprocesses the secondary side output voltage, and then transmits the preprocessed secondary side output voltage to the broadband voltage inversion module through the high-speed data transmission module; the broadband voltage inversion module performs inversion on the secondary side output voltage to obtain the primary side voltage of the voltage transformer; according to the method, inversion calculation of the power grid voltage is completed only through the secondary side output waveform of the CVT, the electrical structure of the CVT does not need to be changed, additional measuring equipment does not need to be additionally arranged in the CVT, safety is high, and economic benefits are remarkable.

Description

Technical Field

[0001] The invention relates to the field of broadband voltage measurement, and in particular to a broadband voltage online measurement device based on FPGA+ARM architecture. Background Art

[0002] At present, the power system is facing a very serious disturbance problem. The electromagnetic energy between system equipment will dynamically interact and rebalance, resulting in electromagnetic transient processes such as voltage and current changes, including ferromagnetic resonance and other working conditions. Under the action of low-frequency overvoltage, the magnetic coupling performance of the voltage transformer decreases due to core saturation, and the magnetic leakage flux surges, causing secondary voltage waveform distortion. However, it is currently impossible to measure the broadband voltage of the power grid through voltage transformers, and the existing online monitoring device needs to modify the original structure of the CVT, which will destroy the original electrical isolation of the CVT to a certain extent, and safety cannot be guaranteed.

[0003] Therefore, a reasonable and effective device is needed to monitor the voltage waveform distortion caused by voltage disturbance in real time and obtain an accurate primary voltage waveform. Summary of the invention

[0004] The purpose of the present invention is to provide a broadband voltage online measurement device based on FPGA+ARM architecture, including a power supply system, a secondary side voltage monitoring module, a high-speed data transmission module, and a broadband voltage inversion module;

[0005] The power supply system supplies power to the secondary side output voltage monitoring module, the high-speed data transmission module, and the broadband voltage inversion module;

[0006] The secondary side voltage monitoring module monitors the secondary side output voltage of the voltage transformer and performs preprocessing, and then transmits the preprocessed secondary side output voltage to the broadband voltage inversion module through the high-speed data transmission module;

[0007] The broadband voltage inversion module inverts the secondary side output voltage to obtain the primary side voltage of the voltage transformer, and the steps include:

[0008] 1) The measured discrete complex frequency domain data is fitted into a transfer function form of a rational fraction and by using the vector matching method, namely:

[0009]

[0010] In the formula, H CVT -1 (s) is the transmission characteristic curve function; s is the complex frequency domain parameter; r k 、p k d is H CVT -1 (s) residues, poles and constant terms; N Fis the number of discrete complex frequency domain data;

[0011] 2) Use discrete state space equations to express the inverse function H of the voltage transformer's transmission characteristic curve -1 cvt(s), that is:

[0012] H CVT -1 (s) = C (sI-A) -1 B+D (2)

[0013] In the formula, A is N F The diagonal matrix of N is a matrix of N, whose diagonal elements are the residues in formula (1); B is N F ×1-order column vector, and all element values ​​are 1; C is 1×N F The order row vector, the element value is the formula error! The reference source was not found. The middle pole; D = d, and it is a linear term; I is a unit vector;

[0014] 3) Define parameters α and β, namely:

[0015]

[0016] Where Δt is the time interval;

[0017] 4) Calculate the primary voltage of the voltage transformer, that is:

[0018] v p (k) = Cx′ k +Gv s (k) (4)

[0019] x′ k =αx′ k-1 +B′v s (k-1) (5)

[0020]

[0021] In the formula, v p (k) is the primary voltage of the voltage transformer; v s (k) is the secondary side output voltage; x′ k , x′ k-1 is the state variable; G is a matrix; B′ is a matrix; v s (k-1) is the secondary side output voltage monitored for the k-1th time.

[0022] Further, the power supply system includes a power supply, a synchronous buck rectifier;

[0023] The power supply output amplitude is V FB Voltage;

[0024] The synchronous buck rectifier steps down the voltage output by the power supply to meet the voltage supply requirements of different levels;

[0025] The synchronous buck rectifier realizes different levels of voltage output by changing the resistance value of the grounding resistor;

[0026] Among them, the relationship between the grounding resistance and the output voltage of the synchronous buck rectifier is as follows:

[0027]

[0028] Where, R2 is the grounding resistance; V out is the synchronous buck rectifier output voltage; V FB is the output voltage of the power supply; R1 is the resistance value of the synchronous buck rectifier except the grounding resistance.

[0029] Further, the secondary side voltage monitoring module includes a step-down module and a fully differential amplifier;

[0030] The step-down module steps down the secondary output voltage. V o is the ground resistance of the buck module, V all It is the sum of the total resistance of the buck module;

[0031] The fully differential amplifier performs differential amplification on the stepped-down secondary output voltage to achieve a differential tracking function.

[0032] Furthermore, the high-speed data transmission module uses a Gigabit Ethernet chip.

[0033] Furthermore, the secondary side voltage monitoring module stores a voltage signal threshold range, and generates an error signal if the received voltage signal exceeds the voltage signal threshold range.

[0034] Furthermore, the high-speed data transmission module is integrated with Bar2Stream IP core and FIFO module;

[0035] After the secondary side voltage monitoring module generates and processes the secondary side output voltage, the start signal of the Bar2Stream IP core is activated;

[0036] Under the control of the start signal, the high-speed data transmission module receives the pre-processed voltage signal through the DATA0 to DATA3 interface input and writes it into the data_back array;

[0037] Subsequently, the Bar2Stream IP core successfully communicates with the FIFO module by handshaking, and the data in the data_back array is transmitted to the broadband voltage inversion module through the stream_data_out interface;

[0038] The FIFO module is used to adjust the transmission rate so that the transmission rate of the high-speed data transmission module matches the data rate generated by the secondary side voltage monitoring module.

[0039] Furthermore, the secondary side voltage monitoring module calls the uart_rx_over function to monitor the status of the two serial port receive buffers to determine whether a new data packet has arrived;

[0040] When the data reception is detected to be completed, the rx_flag flag of the corresponding buffer is cleared to 0, and the message status is set to 1, and the data length in the ART receiving buffer of the U secondary side voltage monitoring module is recorded;

[0041] When AD_Trigger_on of the secondary side voltage monitoring module = 0, the secondary side voltage monitoring module is in the cache state;

[0042] When AD_Trigger_on=1, the secondary side voltage monitoring module is in the waiting trigger state. At this time, the key state is detected to identify whether there is a manual trigger event; if so, it immediately enters the trigger state, if not, it automatically enters the trigger state after t time;

[0043] When AD_Trigger_on=2, the secondary side voltage monitoring module is in a triggered state, performs voltage monitoring, and records the exact time of triggering.

[0044] Furthermore, when monitoring the secondary side output voltage, the secondary side voltage monitoring module also calibrates the secondary side output voltage through zero point calibration and full offset calibration to eliminate offset error and gain error;

[0045] The steps of zero point calibration are: when there is no input signal, sample multiple sampled data, calculate the average value, and store the data to ensure that the output of the AD chip is 0 when there is no input signal;

[0046] The full-bias calibration steps are as follows: test input is performed at 10% and 90% of the full scale of the secondary side voltage monitoring module chip to obtain the ADC offset and gain error, calculate the transfer function slope and save it, thereby eliminating the gain error.

[0047] The transfer function slope k is given by:

[0048]

[0049] Where V 90％real is the actual voltage value at 90% full-scale output, V 10％real The actual voltage value at 10% full-scale output, V 90％ideal is the ideal voltage value at 90% full-scale output, V10％ideal It is the ideal voltage value at 10% full-scale output.

[0050] Further, it also includes a control module;

[0051] The control module generates a control command KEYWORD=value1, value2, ..., valueN, and sends it to the secondary side voltage monitoring module in the form of a character string;

[0052] The control command KEYWORD includes sampling frequency, sampling time, real time, model parameters, and voltage signal threshold range. The model parameters include matrices A, B, C, and constant D in the discrete state space equation.

[0053] Further, a visualization module is included;

[0054] The visualization module includes a component trigger interface, a real-time monitoring interface and a parameter configuration interface;

[0055] The trigger interface is used to start online measurement of broadband voltage;

[0056] The real-time monitoring interface is used to display the secondary side output voltage and the primary side voltage;

[0057] The parameter configuration interface is used to configure the parameters of the control command.

[0058] The technical effect of the present invention is unquestionable. The present invention completes the inversion calculation of the grid voltage only through the output waveform of the CVT secondary side. There is no need to change the electrical structure of the CVT, nor to install additional measuring equipment inside the CVT. It has high safety and significant economic benefits. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 This is a design flow chart of a wide-band voltage online measurement device based on FPGA+ARM architecture provided by the present invention.

[0060] Figure 2 This is a physical picture of the wide-band voltage online measurement device based on FPGA+ARM architecture proposed in the present invention.

[0061] Figure 3 This is the schematic diagram of the buck module circuit.

[0062] Figure 4 This is the THS4521IDR differential amplifier circuit design schematic.

[0063] Figure 5 It is a Gigabit network circuit design schematic.

[0064] Figure 6 This is the Gigabit Ethernet port hardware connection diagram.

[0065] Figure 7 This is the schematic diagram of the AD control module.

[0066] Figure 8 This is a schematic diagram of the Bar2Stream module.

[0067] Fig. 9 This is a schematic diagram of the FIFO module.

[0068] Fig.10 This is a schematic diagram of the DMA module.

[0069] Fig.11 It is the main program design flow chart of ARM-side software.

[0070] Fig.12 This is a schematic diagram of the host computer event trigger interface.

[0071] Fig.13 It is a schematic diagram of the real-time monitoring interface of the host computer.

[0072] Fig.14 It is a schematic diagram of the host computer parameter configuration interface. DETAILED DESCRIPTION

[0073] The present invention is further described below in conjunction with the embodiments, but it should not be understood that the above subject matter of the present invention is limited to the following embodiments. Without departing from the above technical ideas of the present invention, various substitutions and changes are made according to the common technical knowledge and customary means in the art, which should all be included in the protection scope of the present invention.

[0074] Embodiment 1:

[0075] See also Figures 1 to 14 , a broadband voltage online measurement device based on FPGA+ARM architecture, including a power supply system, a secondary side voltage monitoring module, a high-speed data transmission module, and a broadband voltage inversion module;

[0076] The power supply system supplies power to the secondary side output voltage monitoring module, the high-speed data transmission module, and the broadband voltage inversion module;

[0077] The secondary side voltage monitoring module monitors the secondary side output voltage of the voltage transformer and performs preprocessing, and then transmits the preprocessed secondary side output voltage to the broadband voltage inversion module through the high-speed data transmission module;

[0078] The broadband voltage inversion module inverts the secondary side output voltage to obtain the primary side voltage of the voltage transformer, and the steps include:

[0079] 1) The measured discrete complex frequency domain data is fitted into a transfer function form of a rational fraction and by using the vector matching method, namely:

[0080]

[0081] In the formula, H CVT -1 (s) is the transmission characteristic curve function; s is the complex frequency domain parameter; r k 、p k d is H CVT -1 (s) residues, poles and constant terms; N F is the number of discrete complex frequency domain data;

[0082] 2) Use discrete state space equations to express the inverse function H of the voltage transformer's transmission characteristic curve -1 cvt(s), that is:

[0083] H CVT -1 (s) = C (sI-A) -1 B+D (2)

[0084] In the formula, A is N F The diagonal matrix of N is a matrix of N, whose diagonal elements are the residues in formula (1); B is N F ×1-order column vector, and all element values ​​are 1; C is 1×N F The order row vector, the element value is the formula error! The reference source was not found. The middle pole; D = d, and it is a linear term; I is a unit vector;

[0085] 3) Define parameters α and β, namely:

[0086]

[0087] Where Δt is the time interval;

[0088] 4) Calculate the primary voltage of the voltage transformer, that is:

[0089] v p (k) = Cx′ k +Gv s (k) (4)

[0090] x′ k =αx′ k-1 +B′v s (k-1) (5)

[0091]

[0092] In the formula, v p (k) is the primary voltage of the voltage transformer; v s (k) is the secondary side output voltage; x′ k , x′ k-1is the state variable; G is a matrix; B′ is a matrix; v s (k-1) is the secondary side output voltage monitored for the k-1th time.

[0093] The power supply system includes a power supply and a synchronous buck rectifier;

[0094] The power supply output amplitude is V FB Voltage;

[0095] The synchronous buck rectifier steps down the voltage output by the power supply to meet the voltage supply requirements of different levels;

[0096] The synchronous buck rectifier realizes different levels of voltage output by changing the resistance value of the grounding resistor;

[0097] Among them, the relationship between the grounding resistance and the output voltage of the synchronous buck rectifier is as follows:

[0098]

[0099] Where, R2 is the grounding resistance; V out is the synchronous buck rectifier output voltage; V FB is the output voltage of the power supply; R1 is the resistance value of the synchronous buck rectifier except the grounding resistance.

[0100] The secondary side voltage monitoring module includes a step-down module and a fully differential amplifier;

[0101] The step-down module steps down the secondary output voltage. V o is the ground resistance of the buck module, V all It is the sum of the total resistance of the buck module;

[0102] The fully differential amplifier performs differential amplification on the stepped-down secondary output voltage to achieve a differential tracking function.

[0103] The high-speed data transmission module uses a Gigabit Ethernet chip.

[0104] The secondary side voltage monitoring module stores a voltage signal threshold range, and generates an error signal if the received voltage signal exceeds the voltage signal threshold range.

[0105] The high-speed data transmission module is integrated with Bar2Stream IP core and FIFO module;

[0106] After the secondary side voltage monitoring module generates and processes the secondary side output voltage, the start signal of the Bar2Stream IP core is activated;

[0107] Under the control of the start signal, the high-speed data transmission module receives the pre-processed voltage signal through the DATA0 to DATA3 interface input and writes it into the data_back array;

[0108] Subsequently, the Bar2Stream IP core successfully communicates with the FIFO module by handshaking, and the data in the data_back array is transmitted to the broadband voltage inversion module through the stream_data_out interface;

[0109] The FIFO module is used to adjust the transmission rate so that the transmission rate of the high-speed data transmission module matches the data rate generated by the secondary side voltage monitoring module.

[0110] The secondary side voltage monitoring module calls the uart_rx_over function to monitor the status of the two serial port receive buffers to determine whether new data packets have arrived;

[0111] When the data reception is detected to be completed, the rx_flag flag of the corresponding buffer is cleared to 0, and the message status is set to 1, and the data length in the ART receiving buffer of the U secondary side voltage monitoring module is recorded;

[0112] When AD_Trigger_on of the secondary side voltage monitoring module = 0, the secondary side voltage monitoring module is in the cache state;

[0113] When AD_Trigger_on=1, the secondary side voltage monitoring module is in the waiting trigger state. At this time, the key state is detected to identify whether there is a manual trigger event; if so, it immediately enters the trigger state, if not, it automatically enters the trigger state after t time;

[0114] When AD_Trigger_on=2, the secondary side voltage monitoring module is in a triggered state, performs voltage monitoring, and records the exact time of triggering.

[0115] When monitoring the secondary output voltage, the secondary voltage monitoring module also calibrates the secondary output voltage through zero point calibration and full offset calibration to eliminate offset error and gain error;

[0116] The steps of zero point calibration are: when there is no input signal, sample multiple sampled data, calculate the average value, and store the data to ensure that the output of the AD chip is 0 when there is no input signal;

[0117] The full-bias calibration steps are as follows: test input is performed at 10% and 90% of the full scale of the secondary side voltage monitoring module chip to obtain the ADC offset and gain error, calculate the transfer function slope and save it, thereby eliminating the gain error.

[0118] The transfer function slope k is given by:

[0119]

[0120] Where V 90％real is the actual voltage value at 90% full-scale output, V 10％real The actual voltage value at 10% full-scale output, V 90％ideal is the ideal voltage value at 90% full-scale output, V 10％ideal It is the ideal voltage value at 10% full-scale output.

[0121] The device also includes a control module;

[0122] The control module generates a control command KEYWORD=value1, value2, ..., valueN, and sends it to the secondary side voltage monitoring module in the form of a character string;

[0123] The control command KEYWORD includes sampling frequency, sampling time, real time, model parameters, and voltage signal threshold range. The model parameters include matrices A, B, C, and constant D in the discrete state space equation.

[0124] Also includes visualization modules;

[0125] The visualization module includes a component trigger interface, a real-time monitoring interface and a parameter configuration interface;

[0126] The trigger interface is used to start online measurement of broadband voltage;

[0127] The real-time monitoring interface is used to display the secondary side output voltage and the primary side voltage;

[0128] The parameter configuration interface is used to configure the parameters of the control command.

[0129] Embodiment 2:

[0130] A broadband voltage online measurement device based on FPGA+ARM architecture, including a power supply system, a secondary side voltage monitoring module, a high-speed data transmission module, and a broadband voltage inversion module;

[0131] The power supply system supplies power to the secondary side output voltage monitoring module, the high-speed data transmission module, and the broadband voltage inversion module;

[0132] The secondary side voltage monitoring module monitors the secondary side output voltage of the voltage transformer and performs preprocessing, and then transmits the preprocessed secondary side output voltage to the broadband voltage inversion module through the high-speed data transmission module;

[0133] The broadband voltage inversion module inverts the secondary side output voltage to obtain the primary side voltage of the voltage transformer, and the steps include:

[0134] 1) The measured discrete complex frequency domain data is fitted into a transfer function form of a rational fraction and by using the vector matching method, namely:

[0135]

[0136] In the formula, H CVT -1 (s) is the transmission characteristic curve function; s is the complex frequency domain parameter; r k 、p k d is H CVT -1 (s) residues, poles and constant terms;

[0137] 2) Use discrete state space equations to express the inverse function H of the voltage transformer's transmission characteristic curve -1 cvt(s), that is:

[0138] H CVT -1 (s) = C (sI-A) -1 B+D (2)

[0139] In the formula, A is N F The diagonal matrix of N is a matrix of N, whose diagonal elements are the residues in formula (1); B is N F ×1-order column vector, and all element values ​​are 1; C is 1×N F The order row vector, the element value is the formula error! The reference source was not found. The middle pole; D = d, and it is a linear term;

[0140] 3) Define parameters α and β, namely:

[0141]

[0142] 4) Calculate the primary voltage of the voltage transformer, that is:

[0143] v p (k) = Cx′ k +Gv s (k) (4)

[0144] x′ k =αx′ k-1 +B′v s (k-1) (5)

[0145]

[0146] In the formula, v p (k) is the primary voltage of the voltage transformer; v s (k) is the secondary side output voltage; x′ k is the defined state variable, x′k =αx k-1 +βBv s (k-1).

[0147] Embodiment 3:

[0148] A broadband voltage online measurement device based on FPGA+ARM architecture, the technical content is the same as that of embodiment 2, further, the power supply system includes a power supply and a synchronous buck rectifier;

[0149] The power supply output amplitude is V FB Voltage;

[0150] The synchronous buck rectifier steps down the voltage output by the power supply to meet the voltage supply requirements of different levels;

[0151] The synchronous buck rectifier realizes different levels of voltage output by changing the resistance value of the grounding resistor;

[0152] Among them, the relationship between the grounding resistance and the output voltage of the synchronous buck rectifier is as follows:

[0153]

[0154] Where, R2 is the grounding resistance; V out is the synchronous buck rectifier output voltage; V FB is the output voltage of the power supply; R1 is the resistance value of the synchronous buck rectifier except the grounding resistance.

[0155] Embodiment 4:

[0156] A broadband voltage online measurement device based on FPGA+ARM architecture, the technical content of which is the same as any one of Embodiments 2-3, and further, the secondary side voltage monitoring module includes a step-down module and a fully differential amplifier;

[0157] The step-down module steps down the secondary output voltage. V o is the ground resistance of the buck module, V all It is the sum of the total resistance of the buck module;

[0158] The fully differential amplifier performs differential amplification on the stepped-down secondary output voltage to achieve a differential tracking function.

[0159] Embodiment 5:

[0160] A broadband voltage online measurement device based on FPGA+ARM architecture, the technical content of which is the same as any one of Embodiments 2-4, and further, the high-speed data transmission module uses a Gigabit Ethernet chip.

[0161] Embodiment 6:

[0162] A wideband voltage online measurement device based on FPGA+ARM architecture, the technical content of which is the same as any one of Examples 2-5. Furthermore, the secondary side voltage monitoring module stores a voltage signal threshold range, and if the received voltage signal exceeds the voltage signal threshold range, an error signal is generated.

[0163] Embodiment 7:

[0164] A broadband voltage online measurement device based on FPGA+ARM architecture, the technical content is the same as any one of embodiments 2-6, further, the high-speed data transmission module is integrated with Bar2Stream IP core and FIFO module;

[0165] After the secondary side voltage monitoring module generates and processes the secondary side output voltage, the start signal of the Bar2Stream IP core is activated;

[0166] Under the control of the start signal, the high-speed data transmission module receives the pre-processed voltage signal through the DATA0 to DATA3 interface input and writes it into the data_back array;

[0167] Subsequently, the Bar2Stream IP core successfully communicates with the FIFO module by handshaking, and the data in the data_back array is transmitted to the broadband voltage inversion module through the stream_data_out interface;

[0168] The FIFO module is used to adjust the transmission rate so that the transmission rate of the high-speed data transmission module matches the data rate generated by the secondary side voltage monitoring module.

[0169] Embodiment 8:

[0170] A broadband voltage online measurement device based on FPGA+ARM architecture, the technical content is the same as any one of embodiments 2-7, further, the secondary side voltage monitoring module calls the uart_rx_over function to monitor the status of the two serial port receiving buffers to determine whether there is a new data packet arriving;

[0171] When the data reception is detected to be completed, the rx_flag flag of the corresponding buffer is cleared to 0, and the message status is set to 1, and the data length in the ART receiving buffer of the U secondary side voltage monitoring module is recorded;

[0172] When AD_Trigger_on of the secondary side voltage monitoring module = 0, the secondary side voltage monitoring module is in the cache state;

[0173] When AD_Trigger_on=1, the secondary side voltage monitoring module is in the waiting trigger state. At this time, the key state is detected to identify whether there is a manual trigger event; if so, it immediately enters the trigger state, if not, it automatically enters the trigger state after t time;

[0174] When AD_Trigger_on=2, the secondary side voltage monitoring module is in a triggered state, performs voltage monitoring, and records the exact time of triggering.

[0175] Embodiment 9:

[0176] A broadband voltage online measurement device based on FPGA+ARM architecture, the technical content of which is the same as any one of embodiments 2-8, and further, when monitoring the secondary side output voltage, the secondary side voltage monitoring module also calibrates the secondary side output voltage through zero point calibration and full offset calibration to eliminate offset error and gain error;

[0177] The steps of zero point calibration are: when there is no input signal, sample multiple sampled data, calculate the average value, and store the data to ensure that the output of the AD chip is 0 when there is no input signal;

[0178] The full-bias calibration steps are as follows: test input is performed at 10% and 90% of the full scale of the secondary side voltage monitoring module chip to obtain the ADC offset and gain error, calculate the transfer function slope and save it, thereby eliminating the gain error.

[0179] The transfer function slope k is given by:

[0180]

[0181] Where V 90％real is the actual voltage value at 90% full-scale output, V 10％real The actual voltage value at 10% full-scale output, V 90％ideal is the ideal voltage value at 90% full-scale output, V 10％ideal It is the ideal voltage value at 10% full-scale output.

[0182] Embodiment 10:

[0183] A broadband voltage online measurement device based on FPGA+ARM architecture, the technical content of which is the same as any one of Embodiments 2-9, and further includes a control module;

[0184] The control module generates a control command KEYWORD=value1, value2, ..., valueN, and sends it to the secondary side voltage monitoring module in the form of a character string;

[0185] The control command KEYWORD includes sampling frequency, sampling time, real time, model parameters, and voltage signal threshold range. The model parameters include matrices A, B, C, and constant D in the discrete state space equation.

[0186] Embodiment 11:

[0187] A broadband voltage online measurement device based on FPGA+ARM architecture, the technical content of which is the same as any one of Embodiments 2-10, and further includes a visualization module;

[0188] The visualization module includes a component trigger interface, a real-time monitoring interface and a parameter configuration interface;

[0189] The trigger interface is used to start online measurement of broadband voltage;

[0190] The real-time monitoring interface is used to display the secondary side output voltage and the primary side voltage;

[0191] The parameter configuration interface is used to configure the parameters of the control command.

[0192] Embodiment 12:

[0193] A design method for a broadband voltage online measurement device based on FPGA+ARM architecture, the steps are as follows:

[0194] S1: Design high-precision, high-speed hardware acquisition circuits that can meet the maximum sampling rate of 25MHz.

[0195] S2: Design a power supply system that can meet the dual-channel isolated output and meet the voltage supply requirements of different levels in the system.

[0196] S3: Design a high-speed data transmission module to achieve high-speed data transmission between the device and the host computer.

[0197] S4: Design high-speed sampling timing on the FPGA side to achieve accurate data transmission within the hardware.

[0198] S5: Design the high-speed data transmission timing on the FPGA side to achieve accurate data transmission within the hardware.

[0199] S6: Design the ARM main program control logic to complete the ARM logic control of the hardware.

[0200] S7: Use zero point calibration and full offset calibration to calibrate the signal collected by the data acquisition module to eliminate offset error and gain error.

[0201] S8: Design a broadband voltage inversion program and complete the inversion calculation of the secondary voltage through program call.

[0202] S9: Design the data communication protocol between the upper computer and the lower computer, complete the data transmission from the lower computer to the upper computer, and the command control from the upper computer to the lower computer,

[0203] S10: Develop a powerful host computer interface to complete the real-time display of voltage waveform calculation results and realize the functional control of the host computer over the slave computer.

[0204] Step S1 specifically uses AD9251-80 from ANALOG DEVICES as an analog-to-digital converter. First, the collected voltage signal needs to be stepped down. The schematic diagram of the step-down module used in this device is as follows: Figure 3 As shown in the figure, VIN1~3 are the signals supplied to the AD chip after passing through the step-down circuit. According to the principle of resistor voltage division, the step-down ratio k of this circuit is:

[0205]

[0206] Where V o is the ground resistance, V all It is the sum of the total resistance. In this device, k = 1 / 1001.

[0207] After the voltage signal is processed by the step-down circuit, a fully differential amplifier model THS4521IDR is selected to process the signal. The circuit design diagram is shown in the figure. Figure 4 As shown in the figure, VIN1 is the original voltage input terminal, IN0_P and IN0_N are the analog voltage outputs after the differential amplifier, and are also the analog voltage input terminals of the AD9251 chip, realizing the differential tracking function.

[0208] Step S2 specifically uses a TAS10-5-WH power supply that can meet dual-channel isolated output to stably output a 5V voltage for use on the circuit board. At the same time, an STI3472 synchronous buck rectifier is used to convert the 5V voltage into 1.8V and 3.3V voltages respectively to meet the different voltage level requirements of other modules in the circuit. The schematic diagram of the buck rectifier is shown in Figure 5 As shown, by changing the resistance of the grounding resistor, different levels of voltage output can be achieved. By using formula (2), it can be calculated that the values ​​of the resistor R2 corresponding to 1.8V and 3.3V are 15kΩ and 56.2kΩ.

[0209]

[0210] Step S3 specifically includes selecting RTL8211E-VB-CGT Gigabit Ethernet chip to build Ethernet circuit, selecting 3.3V external circuit power supply, and using Realtek's RTL8211E physical layer chip, HR911130C network port device and 25MHz crystal oscillator for the hardware circuit. The hardware connection block diagram is shown in the figure. Figure 6 As shown. Select a clock frequency of 125MHz

[0211] Step S4 specifically includes designing an IP core named AD_Control in the VIVADO software, such as Figure 7 As shown, it is used to process analog signals and generate corresponding trigger signals. In addition, the AD_Control module also integrates data monitoring functions. The upper 16 bits of the three limit signals are defined as high thresholds, while the lower 16 bits are defined as low thresholds. If the collected voltage signal exceeds these thresholds, the module will generate an error signal for real-time monitoring and exception handling.

[0212] Step S5 specifically includes integrating a Bar2Stream IP core into the Vivado development environment, such as Figure 8 As shown in the figure, the data processing is optimized. The IP core receives four 16-bit wide data streams, which are input through the DATA0 to DATA3 interfaces. The start signal is used as a trigger mechanism to indicate the start of data acquisition. M00_AXIS is a 64-bit wide parallel output interface, and the data block size for each transmission is set to 2 bytes. When the AD data acquisition is completed, the output signal done is pulled high, and at the same time, the start signal of the Bar2Stream IP core is activated. Under the control of the start signal, the data input through DATA0-DATA3 is written to the data_back array. Subsequently, when the Bar2Stream successfully handshakes with the FIFO module, the data in the data_back array is efficiently transmitted to the next module through the stream_data_out interface.

[0213] Considering that the data rate generated by the AD module may be similar to that of the direct memory access (DMA) module (such as Fig. 9 The transmission rate of the FIFO (First In First Out) module (as shown in Fig.10 The use of FIFO modules significantly reduces the risk of data transmission errors and data loss caused by rate mismatch. Within the maximum range allowed by FPGA resources, this paper increases the depth of FIFO as much as possible. In this design, the depth of FIFO is set to 16384, and the width of data signal TDATA is configured to 8 bits.

[0214] Step S6 is as follows: the design idea of ​​the main program of the project is as follows Fig.11 As shown in the figure, the system is started first, including serial communication initialization, message analysis initialization, TCP / IP protocol stack initialization and AD module initialization. After entering the main loop, the system calls the uart_rx_over function to monitor the status of the two serial port receive buffers to determine whether there are new data packets arriving. Once the data reception is detected to be completed, the system clears the rx_flag flag of the corresponding buffer to 0 and sets the message status to 1, indicating that the data is ready for subsequent processing. At the same time, the system records the data length in the UART receive buffer to prepare for message analysis.

[0215] Next, the system determines different trigger logics through the Switch statement according to the value of AD_Trigger_on. When AD_Trigger_on = 0, the system is in the cache state; when its value is 1, the system enters the waiting trigger state and detects the state of the key to identify whether there is a manual trigger event. Regardless of whether the key is pressed, the system will perform a timed trigger operation and calculate the RMS value of the recorded waveform; when AD_Trigger_on is 2, it means that the system has been triggered and data is recorded. At this time, the buzzer sounds and the exact moment of the trigger is recorded.

[0216] Step S7 specifically includes: performing bias calibration on the three A / D sampling channels, sampling 60 sampling data when there is no input signal and calculating the average value, and storing the data to ensure that the output of the AD chip is 0 when there is no input signal, thereby performing zero point calibration.

[0217] Test input is carried out at 10% and 90% of the full scale of the AD chip to obtain the ADC offset and gain errors, and its transfer function slope is calculated and saved, thereby eliminating the gain error.

[0218] Step S8 is specifically as follows: the voltage inversion calculation is completed through the state space equation, and its formula is as shown. Define a three-dimensional empty array x of size 2×n×2, where n is the dimension of the state space parameter matrix, and idx is used as the state switching parameter. Considering that A and C are both complex matrices, during the calculation process, the imaginary part and the real part of the matrix are split apart for calculation to simplify the calculation process. The idx parameter defined in the array x alternates between 0 and 1 according to the index i of the current sample, so that only half of the state variables need to be updated in each iteration, thereby effectively reducing the memory access frequency and the amount of calculation.

[0219] x′ k =αx′ k-1 +B′v s (k-1) (3)

[0220] vp (k) = Cx′ k +Gv s (k) (4)

[0221] in

[0222]

[0223] Step S9 is specifically as follows: the control command is sent to the ARM end in the form of a string, where KEYWORD is a specific keyword representing the sampling frequency, sampling time, real-time time, model parameters, threshold, AD calibration value and other parameters sent from the upper computer, and value1, value2, ..., valueN are the parameter values ​​set by the user. The lower computer parses the format string by calling the function, extracts the corresponding system value according to KEYWORD for setting, and formats a new string as a response.

[0224] KEYWORD=value1,value2,...,valueN (6)

[0225] The upper computer reads the lower computer parameters in the form of a string, where AT+GET is a fixed command prefix used to indicate a GET command, ID is a device identifier, and KEYWORD is a specific keyword, indicating the sampling frequency, sampling time, real-time time, model parameters, thresholds, AD calibration values ​​and other parameters from the hardware part.

[0226] AT+GET ID=xx,KEYWORD=value1,value2,...,valueN (7)

[0227] Step S10 is specifically: Use WPF (Windows Presentation Foundation) language to develop upper computer visualization software based on NET Framework platform. WPF technology separates interface display and logic control. The front-end uses XAML language to develop the interface, and the back-end uses C# language as the control language. The development platform used in this article is .NET, the programming language is C#, and the integrated development environment is Visual Studio 2022. The final designed upper computer system interface layout is as follows Figure 12-14 The system consists of three core interfaces: event trigger interface, real-time monitoring interface and parameter configuration interface.

[0228] According to the method proposed above, the design of a broadband voltage online monitoring device for a power grid can be realized.

Claims

1. A broadband voltage online measurement device based on FPGA+ARM architecture, characterized in that: It includes power supply system, secondary side voltage monitoring module, high-speed data transmission module and broadband voltage inversion module; The power supply system supplies power to the secondary side output voltage monitoring module, the high-speed data transmission module, and the broadband voltage inversion module; The secondary side voltage monitoring module monitors the secondary side output voltage of the voltage transformer and performs preprocessing, and then transmits the preprocessed secondary side output voltage to the broadband voltage inversion module through the high-speed data transmission module; The broadband voltage inversion module inverts the secondary side output voltage to obtain the primary side voltage of the voltage transformer, and the steps include: 1) The measured discrete complex frequency domain data is fitted into a transfer function form of a rational fraction and by using the vector matching method, namely: In the formula, H CVT -1 (s) is the transmission characteristic curve function; s is the complex frequency domain parameter; r k 、p k d is H CVT -1 (s) residues, poles and constant terms; N F is the number of discrete complex frequency domain data; 2) Use discrete state space equations to express the inverse function H of the voltage transformer's transmission characteristic curve -1 cvt(s), that is: H CVT -1 (s)=C(sI-A) -1 B+D (2) In the formula, A is N F The diagonal matrix of N is a matrix of N, whose diagonal elements are the residues in formula (1); B is N F ×1-order column vector, and all element values ​​are 1; C is 1×N F The order row vector, the element value is the formula error! The reference source was not found. The middle pole; D = d, and it is a linear term; I is a unit vector; 3) Define parameters α and β, namely: Where Δt is the time interval; 4) Calculate the primary voltage of the voltage transformer, that is: in p (k)=Cx k ′+Gv s (k) (4) x k ′=αx′ k-1 +B′v s (k-1) (5) In the formula, v p (k) is the primary voltage of the voltage transformer; v s (k) is the secondary side output voltage; x′ k , x′ k-1 is the state variable; G is a matrix; B′ is a matrix; v s (k-1) is the secondary side output voltage monitored for the k-1th time.

2. According to claim 1, a broadband voltage online measurement device based on F7PGA+ARM architecture is characterized in that: The power supply system includes a power supply and a synchronous buck rectifier; The power supply output amplitude is V FB Voltage; The synchronous buck rectifier steps down the voltage output by the power supply to meet the voltage supply requirements of different levels; The synchronous buck rectifier realizes different levels of voltage output by changing the resistance value of the grounding resistor; Among them, the relationship between the grounding resistance and the output voltage of the synchronous buck rectifier is as follows: Where, R2 is the grounding resistance; V out is the synchronous buck rectifier output voltage; V FB is the output voltage of the power supply; R1 is the resistance value of the synchronous buck rectifier except the grounding resistance.

3. The broadband voltage online measurement device based on FPGA+ARM architecture according to claim 1, characterized in that: The secondary side voltage monitoring module includes a step-down module and a fully differential amplifier; The step-down module steps down the secondary output voltage. V o is the ground resistance of the buck module, V all It is the sum of the total resistance of the buck module; The fully differential amplifier performs differential amplification on the stepped-down secondary output voltage to achieve a differential tracking function.

4. The broadband voltage online measurement device based on FPGA+ARM architecture according to claim 1, characterized in that: The high-speed data transmission module uses a Gigabit Ethernet chip.

5. The broadband voltage online measurement device based on FPGA+ARM architecture according to claim 1, characterized in that: The secondary side voltage monitoring module stores a voltage signal threshold range, and generates an error signal if the received voltage signal exceeds the voltage signal threshold range.

6. The broadband voltage online measurement device based on FPGA+ARM architecture according to claim 1, characterized in that: The high-speed data transmission module is integrated with Bar2Stream IP core and FIFO module; After the secondary side voltage monitoring module generates and processes the secondary side output voltage, the start signal of the Bar2Stream IP core is activated; Under the control of the start signal, the high-speed data transmission module receives the pre-processed voltage signal through the DATA0 to DATA3 interface input and writes it into the data_back array; Subsequently, the Bar2Stream IP core successfully communicates with the FIFO module by handshaking, and the data in the data_back array is transmitted to the broadband voltage inversion module through the stream_data_out interface; The FIFO module is used to adjust the transmission rate so that the transmission rate of the high-speed data transmission module matches the data rate generated by the secondary side voltage monitoring module.

7. The broadband voltage online measurement device based on FPGA+ARM architecture according to claim 1, characterized in that: The secondary side voltage monitoring module calls the uart_rx_over function to monitor the status of the two serial port receive buffers to determine whether new data packets have arrived; When the data reception is detected to be completed, the rx_flag flag of the corresponding buffer is cleared to 0, and the message status is set to 1, and the data length in the ART receiving buffer of the U secondary side voltage monitoring module is recorded; When AD_Trigger_on of the secondary side voltage monitoring module = 0, the secondary side voltage monitoring module is in the cache state; When AD_Trigger_on=1, the secondary side voltage monitoring module is in the waiting trigger state. At this time, the key state is detected to identify whether there is a manual trigger event; if so, it immediately enters the trigger state, if not, it automatically enters the trigger state after t time; When AD_Trigger_on=2, the secondary side voltage monitoring module is in a triggered state, performs voltage monitoring, and records the exact time of triggering.

8. The broadband voltage online measurement device based on FPGA+ARM architecture according to claim 1, characterized in that: When monitoring the secondary output voltage, the secondary voltage monitoring module also calibrates the secondary output voltage through zero point calibration and full offset calibration to eliminate offset error and gain error; The steps of zero point calibration are: when there is no input signal, sample multiple sampled data, calculate the average value, and store the data to ensure that the output of the AD chip is 0 when there is no input signal; The full-bias calibration steps are: test input at 10% and 90% of the full scale of the secondary voltage monitoring module chip to obtain the ADC offset and gain error, calculate the transfer function slope and save it, thereby eliminating the gain error; The transfer function slope k is given by: Among them, V 90％real is the actual voltage value at 90% full-scale output, V 10％real The actual voltage value at 10% full-scale output, V 90％ideal is the ideal voltage value at 90% full-scale output, V 10％ideal It is the ideal voltage value at 10% full-scale output.

9. The broadband voltage online measurement device based on FPGA+ARM architecture according to claim 1, characterized in that: Also includes a control module; The control module generates a control command KEYWORD=value1, value2, ..., valueN, and sends it to the secondary side voltage monitoring module in the form of a character string; The control command KEYWORD includes sampling frequency, sampling time, real time, model parameters, and voltage signal threshold range; the model parameters include matrices A, B, C, and constant D in the discrete state space equation.

10. The broadband voltage online measurement device based on FPGA+ARM architecture according to claim 9, characterized in that: Also includes visualization modules; The visualization module includes a component trigger interface, a real-time monitoring interface and a parameter configuration interface; The trigger interface is used to start online measurement of broadband voltage; The real-time monitoring interface is used to display the secondary side output voltage and the primary side voltage; The parameter configuration interface is used to configure the parameters of the control command.

Images