Bandgap reference circuit and semiconductor device

Abstract

A bandgap reference circuit (20) is provided with: a diode characteristic element group (22); the dynamic element matching circuit (23) performs the following operations in a certain period: changing the combination of the diode characteristic elements to be selected; an operation of repeatedly selecting, from among the diode characteristic element groups (22), a first diode characteristic element group (22a) comprising parallel connections of M diode characteristic elements and a second diode characteristic element group (22b) comprising parallel connections of N (> = M) diode characteristic elements; a reference voltage generation circuit (30) that generates a reference voltage (VBG) on the basis of the difference in current density between currents flowing through the first diode characteristic element group (22a) and the second diode characteristic element group (22b); and a secondary temperature coefficient adjustment circuit (37) that adjusts the secondary temperature coefficient of the generated reference voltage (VBG).

Description

Technical Field

[0001] The present invention relates to a bandgap reference circuit for generating a reference voltage and a semiconductor device including the bandgap reference circuit. Background Art

[0002] In the past, as a bandgap reference circuit for generating a reference voltage with excellent temperature characteristics, the following reference voltage generating circuit has been proposed, which comprises: a reference voltage generating circuit element that generates a reference voltage based on the difference between voltages applied to a first diode characteristic element and a second diode characteristic element whose current density of current flowing is different from that of the first diode characteristic element; a first adjustment circuit element that adjusts a primary temperature coefficient of the reference voltage; and a second adjustment circuit element that adjusts a secondary temperature coefficient of the reference voltage (for example, refer to patent document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent No. 5842164 Summary of the invention

[0006] Problems to be solved by the invention

[0007] However, according to the technology of Patent Document 1, although the temperature characteristics of the generated reference voltage are improved, there is a problem that characteristic deviation occurs between the plurality of reference voltage generating circuits produced depending on the characteristic deviation of the first diode characteristic element and the second diode characteristic element used. In addition, unless otherwise stated, characteristic deviation is the deviation of characteristics between individuals, also called manufacturing deviation.

[0008] Therefore, an object of the present disclosure is to provide a bandgap reference circuit with suppressed characteristic variation and a semiconductor device including such a bandgap reference circuit.

[0009] Means used to solve problems

[0010] In order to achieve the above-mentioned purpose, a bandgap reference circuit according to a technical solution of the present disclosure comprises: a diode characteristic element group, which is composed of a plurality of diode characteristic elements; a dynamic element matching circuit, which performs the following actions within a certain period, namely: while changing the combination of the M diode characteristic elements and the N diode characteristic elements to be selected, repeatedly performs the actions of selecting a first diode characteristic element group composed of the parallel connection of the M diode characteristic elements and a second diode characteristic element group composed of the parallel connection of the N diode characteristic elements from the diode characteristic element group, wherein the M is an integer greater than 1, and the N is an integer greater than 2 and greater than the M; a reference voltage generating circuit, which generates a reference voltage based on the difference between the current density of the current flowing through the first diode characteristic element group and the current density of the current flowing through the second diode characteristic element group; and a secondary temperature coefficient adjusting circuit, which adjusts the secondary temperature coefficient of the reference voltage generated by the reference voltage generating circuit.

[0011] Furthermore, in order to achieve the above-mentioned purpose, a semiconductor device according to a technical solution of the present disclosure comprises: the above-mentioned bandgap reference circuit; and a time-discrete filter, which receives the above-mentioned reference voltage outputted from the above-mentioned bandgap reference circuit; the above-mentioned dynamic element matching circuit repeatedly performs the above-mentioned action in synchronization with a clock signal; and the above-mentioned time-discrete filter performs time-discrete filtering processing in synchronization with the above-mentioned clock signal.

[0012] Effects of the Invention

[0013] According to the present disclosure, a bandgap reference circuit with suppressed characteristic variation and a semiconductor device including such a bandgap reference circuit are provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 : is a circuit block diagram showing the structure of a semiconductor device including a bandgap reference circuit according to an embodiment.

[0015] Figure 2 Yes means Figure 1 A block diagram of the functionality of the dynamic element matching circuit.

[0016] Figure 3 Yes means Figure 1 Diagram of the diode characteristic element group and switch group in .

[0017] Figure 4 Yes means Figure 3 The timing diagram of the operation example of the dynamic element matching circuit shown.

[0018] Figure 5 Yes Description Figure 4 A diagram showing the transitions of the selected states.

[0019] Fig. 6A It is a diagram showing a diode characteristic element group and a switch group according to a modified example.

[0020] Figure 6B Yes means Fig. 6A A timing chart showing an operation example of a dynamic element matching circuit according to a modified example shown.

[0021] Figure 6C Yes Description Figure 6B A diagram showing the transitions of the selected states.

[0022] Fig.6D It is a diagram for explaining the transition of the selection state of the reference example.

[0023] Figure 7 It means in Figure 6C The variation shown is similar to Fig.6D The reference examples shown are diagrams comparing simulation results of the variation (noise) of the reference voltage.

[0024] Figure 8 This is a circuit diagram showing a configuration example of a switch selection circuit that realizes a dynamic element matching circuit in accordance with a modification example incorporating randomness.

[0025] Fig.9A Yes means Figure 8 The timing diagram of the operation of the switch selection circuit is shown.

[0026] Fig. 9B It means being Figure 8 The switch selection circuit shown is a diagram for selecting a diode characteristic element of the first diode characteristic element group.

[0027] Fig.10 Yes Description Figure 8 The diagram shown is a diagram of the effect of the operation of the dynamic element matching circuit of the modified example incorporating randomness.

[0028] Fig.11 This is a diagram for explaining a configuration example of a switch selection circuit that realizes a dynamic element matching circuit according to a modification example combined with ΔΣ modulation.

[0029] Fig.12 It is a diagram showing a layout of a diode characteristic element group on a substrate according to a modification example.

[0030] Fig.13 This is a circuit block diagram showing a configuration of a semiconductor device according to a modified example in which a bipolar transistor included in a secondary temperature coefficient adjustment circuit is included in a diode characteristic element group as an object of dynamic element matching.

[0031] Fig.14 Yes means Fig.13 Circuit diagram of the detailed structure of the dynamic element matching circuit group.

[0032] Fig.15 Yes means Figure 1 A circuit diagram of a specific structural example of the first switch circuit and the second switch circuit.

[0033] Fig.16A Yes means Figure 1 A circuit diagram of a specific structural example of the time-discrete filter in FIG.

[0034] Fig. 16B Yes means Fig.16A The timing diagram of the operation of the time-discrete filter is shown.

[0035] Fig.17A This is a circuit block diagram showing a configuration of a semiconductor device according to a modification example including an averaging filter as an analog signal processing circuit instead of the time-discrete filter, AD converter, and averaging filter in the embodiment.

[0036] Fig. 17B Yes means Fig.17A The circuit diagram of the detailed structure of the averaging filter is shown.

[0037] Fig. 17C Yes means Fig.17A The diagram shows an example of one cycle of averaging processing performed by the averaging filter. DETAILED DESCRIPTION

[0038] Hereinafter, the embodiments of the present disclosure and its modified examples are described in detail using the accompanying drawings. In addition, the embodiments and its modified examples described below all represent a specific example of the present disclosure. The numerical values, shapes, materials, constituent elements, the configuration positions and connection forms of the constituent elements, the waveforms of signals, timing, etc. shown in the following embodiments and their modified examples are used as examples and are not intended to limit the present disclosure. In addition, the figures are not necessarily strictly illustrated. In each figure, the same mark is given to substantially the same structure, and repeated descriptions are omitted or simplified. In addition, "A is connected to B" means that A is electrically connected to B, which includes not only the case where A is directly connected to B, but also the case where A and B are indirectly connected in a state where other circuit elements are sandwiched between A and B.

[0039] Figure 1 1 is a circuit block diagram showing the structure of a semiconductor device 10 including a bandgap reference circuit 20 according to an embodiment of the present invention. The semiconductor device 10 includes the bandgap reference circuit 20 for generating a reference voltage VBG, a time-discrete filter 40 for performing a time-discrete filtering process on the generated reference voltage VBG to output a reference voltage VBG2, an AD converter 41 for converting the output reference voltage VBG2 into a digital signal, and an averaging filter 42 for averaging the output digital signal.

[0040] The bandgap reference circuit 20 includes a timing generation circuit 21 , a diode characteristic element group 22 , a dynamic element matching circuit 23 , a reference voltage generation circuit 30 , a primary temperature coefficient adjustment circuit 36 ​​, and a secondary temperature coefficient adjustment circuit 37 .

[0041] The timing generation circuit 21 generates a chopping clock 1 supplied to the first switch circuit 32 , a chopping clock 2 supplied to the second switch circuit 34 , a filter clock supplied to the time discrete filter 40 , and a DEM control clock supplied to the dynamic element matching circuit 23 based on a clock input from the outside.

[0042] The diode characteristic element group 22 is composed of a plurality of diode characteristic elements whose one end (cathode part) is commonly connected to the ground (here, to the ground potential). The diode characteristic element is an element that functionally has a diode characteristic composed of an anode part and a cathode part, such as a diode, an NPN bipolar transistor with a collector and a base connected, etc. In this embodiment, the base-emitter voltage of the NPN bipolar transistor with a collector and a base connected is used as the bandgap voltage.

[0043] The dynamic element matching circuit 23 is composed of: a switch group 25, which is composed of a plurality of switches connecting the anode parts of a plurality of diode characteristic elements constituting the diode characteristic element group 22 to a connection point V1 for generating a reference voltage V1 or a connection point V3 for generating a reference voltage V3; and a switch selection circuit 24, which outputs a DEM control signal for controlling the on and off of each switch constituting the switch group 25 according to the DEM control clock from the timing generation circuit 21.

[0044] The dynamic element matching circuit 23 has the following functions: Figure 2 As shown in the functional block diagram of the dynamic element matching circuit 23, the following actions are performed within a certain period: while changing the combination of the selected M diode characteristic elements and the N diode characteristic elements, the actions of repeatedly selecting from the diode characteristic element group 22 a, which is composed of a parallel connection of M diode characteristic elements, which is an integer greater than 1, and a parallel connection of N diode characteristic elements, which is an integer greater than 2 larger than M, from the diode characteristic element group 22 are performed.

[0045] The reference voltage generating circuit 30 is a circuit that generates a reference voltage VBG based on the difference between the current density of the current flowing through the first diode characteristic element group 22a and the current density of the current flowing through the second diode characteristic element group 22b (in other words, the difference in averaged diode characteristic voltages (i.e., bandgap voltages)), and has a first current source 31a, a second current source 31b, a first switching circuit 32, a first resistor element 33a, a second resistor element 33b, a second switching circuit 34 and a differential amplifier 35.

[0046] The first current source 31a and the second current source 31b are both variable current sources having one end connected to the power supply voltage VDD and outputting currents of the same magnitude according to the output voltage Vo of the differential amplifier 35. The first current source 31a and the second current source 31b output currents of magnitudes adjusted in the direction of applying negative feedback to the differential amplifier 35.

[0047] The first switch circuit 32 is a circuit that periodically switches between the first current source 31a and the second current source 31b based on the chopping clock 1 from the timing generation circuit 21 to supply current to the first diode characteristic element group 22a and the second diode characteristic element group 22b.

[0048] The first resistor element 33a and the second resistor element 33b have the same resistance value, and are current limiting elements inserted in a path in which current flows to the first diode characteristic element group 22a via the switch group 25 (hereinafter, this path will also be referred to as the "first path"), and are current limiting elements inserted in a path in which current flows to the second diode characteristic element group 22b via the switch group 25 and the primary temperature coefficient adjustment circuit 36 ​​(hereinafter, this path will also be referred to as the "second path").

[0049] The differential amplifier 35 is an amplifier having a non-inverting input terminal (first input terminal) and an inverting input terminal (second input terminal) to which a voltage V1 depending on the current density of the current flowing through the first diode characteristic element group 22a (i.e., a first voltage at a connection point V1 between the first resistor element 33a and the switch group 25) and a voltage V2 depending on the current density of the current flowing through the second diode characteristic element group 22b (i.e., a second voltage at a connection point V2 between the second resistor element 33b and the primary temperature coefficient adjustment circuit 36) are input via the second switch circuit 34, and amplifies the difference between the voltage input to the non-inverting input terminal and the voltage input to the inverting input terminal and outputs the difference as an output voltage Vo. In addition, the differential amplifier 35 switches the connection mode of the internal circuit 35a in synchronization with the switching operation of the second switch circuit 34 according to the chopping clock 2 from the timing generation circuit 21 so that the same amplification operation is performed when the non-inverting input terminal and the inverting input terminal are functionally switched and when they are not switched.

[0050] The second switch circuit 34 is a switch circuit that periodically switches the voltage input to the non-inverting input terminal of the differential amplifier 35 and the voltage input to the inverting input terminal of the differential amplifier 35 between the voltage V1 and the voltage V2 according to the chopping clock 2 from the timing generation circuit 21 .

[0051] The primary temperature coefficient adjustment circuit 36 ​​is a variable resistance element connected in series to the second resistance element 33 b , and is adjusted to a resistance value for bringing the primary temperature coefficient of the reference voltage VBG generated by the reference voltage generation circuit 30 close to zero.

[0052] The secondary temperature coefficient adjustment circuit 37 is a circuit for adjusting the secondary temperature coefficient of the reference voltage VBG generated by the reference voltage generation circuit 30, and is composed of two bipolar transistors 37b and 37c connected in series between the power supply voltage VDD and the ground potential, and a current mirror circuit 37a that takes the base current of the bipolar transistor 37b as an input (i.e., 1) and outputs a variable current with a current ratio of 1:k to the connection point V2. The current ratio 1:k of the current mirror circuit 37a is adjusted to a value for making the secondary temperature coefficient of the reference voltage VBG generated by the reference voltage generation circuit 30 close to zero.

[0053] Next, the operation of the semiconductor device 10 according to the present embodiment configured as described above will be described.

[0054] First, the overall operation will be described.

[0055] In the first path including the connection point V1, the current output from the first current source 31a or the second current source 31b flows through the first resistor element 33a via the first switch circuit 32, and then flows through the first diode characteristic element group 22a formed by the parallel connection of M diode characteristic elements selected by the switch group 25 of the dynamic element matching circuit 23.

[0056] On the other hand, in the second path including the connection point V2, the current output from the second current source 31b or the first current source 31a flows through the second resistor 33b and the primary temperature coefficient adjustment circuit 36 ​​via the first switch circuit 32, and further flows through the second diode characteristic element group 22b formed by the parallel connection of N diode characteristic elements selected by the switch group 25 of the dynamic element matching circuit 23. At the connection point V2, the current flows in and out between the secondary temperature coefficient adjustment circuit 37.

[0057] Here, the voltage V1 at the connection point V1 becomes the averaged diode characteristic voltage of the first diode characteristic element group 22a, and on the other hand, the voltage V2 at the connection point V2 becomes the voltage obtained by adding the reduced voltage in the primary temperature coefficient adjustment circuit 36 ​​to the averaged diode characteristic voltage of the second diode characteristic element group 22b (the third voltage at the connection point V3).

[0058] Such voltages V1 and V2 are input to the differential amplifier 35 via the second switch circuit 34, and the output voltage Vo from the differential amplifier 35 is negatively fed back to adjust the output currents of the first current source 31a and the second current source 31b.

[0059] The voltage at the connection point between the first switch circuit 32 and the second resistor element 33b is output from the reference voltage generating circuit 30 as the reference voltage VBG, and is input into the time-discrete filter 40. In the time-discrete filter 40, the voltage variation (noise) caused by the switching operation of the dynamic element matching circuit 23, the first switch circuit 32, and the second switch circuit 34 is suppressed, and is input into the AD converter 41 as the reference voltage VBG2.

[0060] In the AD converter 41 , the reference voltage VBG2 is converted into a digital signal, and the digital signal is averaged by performing digital signal processing such as moving average in the averaging filter 42 .

[0061] Next, the significance of the primary temperature coefficient adjustment circuit 36 ​​will be described.

[0062] In the reference voltage generating circuit 30, the currents outputted by the first current source 31a and the second current source 31b are equal in magnitude, the resistance values ​​of the first resistor element 33a and the second resistor element 33b are equal, and the non-inverting input terminal and the inverting input terminal are imaginary shorted due to the negative feedback of the differential amplifier 35, so that the voltage V1 is equal to the voltage V2, and further, the voltage obtained by adding the reduced voltage in the second resistor element 33b to the voltage V2 becomes the reference voltage VBG, so the first-order differential component dVBG / dT of the reference voltage VBG related to the temperature T is expressed by the following formula 1. dVBG / dT=dVf2 / dT+(k / q)·(ln(n)·(R2+R3) / R3) (Formula 1)

[0063] Here, Vf2 is the forward voltage of the second diode characteristic element group 22b, k is the Boltzmann constant, q is the basic charge, ln represents the natural logarithm, n is the current density ratio of the first diode characteristic element group 22a to the second diode characteristic element group 22b (here N / M), R2 is the resistance value of the second resistor element 33b, and R3 is the resistance value of the primary temperature coefficient adjustment circuit 36.

[0064] Thus, by adjusting the resistance value R3 of the primary temperature coefficient adjustment circuit 36 ​​so that the value of the above formula 1 becomes zero, the primary temperature coefficient of the reference voltage VBG can be set to zero. For example, when n=8, R2=90kΩ, and dVf2 / dT=-1.8mV / °C, the resistance value R3 of the primary temperature coefficient adjustment circuit 36 ​​becomes 10kΩ. In addition, k / q=86.17μV.

[0065] Next, the significance of the secondary temperature coefficient adjustment circuit 37 will be described.

[0066] The series expansion VBG0(T) of the bandgap voltage VBG0 of the second diode characteristic element group 22b for generating the reference voltage VBG with respect to temperature T can be approximated by performing a second-order differentiation with respect to t=ΔT / T0. 2 VBG0(t) / dt 2 =2·a2. In addition, the cubic terms and the following terms are ignored because they can be ignored in the assumed temperature range. Here, T0 is the reference temperature, ΔT is the temperature difference between temperature T and the reference temperature T0, and a2 is the constant of the quadratic term in the above series expansion.

[0067] The reference voltage generation circuit 30 outputs the reference voltage VBG(t) whose secondary temperature coefficient is canceled by adding the adjustment current Ic(t) from the secondary temperature coefficient adjustment circuit 37 to the band gap voltage VBG0(t). That is, since it can be expressed as VBG(t)=VBG0(t)-R2·Ic(t), the second-order differential d of the reference voltage VBG(t) with respect to the temperature t is 2 VBG(t) / dt 2 This becomes the following formula 2.

[0068] d 2 VBG(t) / dt 2 =2·a2-R2·d 2 Ic(t) / dt 2 (Formula 2)

[0069] Therefore, when t=0, that is, temperature T is the reference temperature T0 (for example, 27°C=300K), the secondary temperature coefficient of the reference voltage VBG can be made zero by adjusting the adjustment current Ic(t) output from the secondary temperature coefficient adjustment circuit 37 so that the above equation 2 becomes zero.

[0070] Specifically, when the adjustment current Ic(t) is a current expressed as Ic(t)=C·exp(-t) using a constant C, by setting the adjustment current Ic(t) to satisfy Ic(t)=2·a2 / (R2·C), the quadratic temperature coefficient of the reference voltage VBG can be made zero. Alternatively, the adjustment current Ic(t) may be a current expressed as Ic(t)=C / t using a constant C.

[0071] Next, an operation example of the dynamic element matching circuit 23 will be described.

[0072] Figure 3 Yes means Figure 1 FIG. 2 is a diagram of a diode characteristic element group 22 and a switch group 25 in FIG. The diode characteristic element group 22 is composed of eight NPN bipolar transistors whose collectors and bases are connected as a power of 2 (here, eight) diode characteristic elements Q1 to Q8. One end (cathode portion) of the eight diode characteristic elements Q1 to Q8 is connected to a common ground (here, to the ground potential).

[0073] The switch group 25 is composed of switches S1 to S8 for connecting the other ends (anode parts; collectors and bases of NPN bipolar transistors) of the eight diode characteristic elements Q1 to Q8 to the connection point V1, and switches T1 to T8 connected to the connection point V3. In the switch group 25, the switch selection circuit 24 controls the on-off of the switches S1 to S8 by the control signals S1 to S8 included in the DEM control signal, and controls the on-off of the switches T1 to T8 by the control signals T1 to T8 included in the DEM control signal. Thus, in the diode characteristic element group 22, a first diode characteristic element group 22a composed of M diode characteristic elements connected in parallel and a second diode characteristic element group 22b composed of N diode characteristic elements connected in parallel are determined.

[0074] In addition, the diode characteristic element group 22 is composed of a power of 2 number of diode characteristic elements Q1 to Q8. Therefore, in the diode characteristic element group 22, the frequency division circuit of the dynamic element matching circuit 23 (especially, the switch selection circuit 24 that outputs the DEM control signal to the switch group 25) for selecting the combination of the first diode characteristic element group 22a and the second diode characteristic element group 22b can be simplified, and averaging of the time discrete filter 40, the AD converter 41 and the averaging filter 42 becomes easy.

[0075] Figure 4 Yes means Figure 3 The timing diagram of the operation example of the dynamic element matching circuit 23 shown in FIG. Figure 1 , "S1" to "S8" represent control signals S1 to S8 for driving switches S1 to S8, "T1" to "T8" represent control signals T1 to T8 for driving switches T1 to T8, "first diode characteristic element group" represents diode characteristic elements selected as the first diode characteristic element group 22a, and "second diode characteristic element group" represents diode characteristic elements selected as the second diode characteristic element group 22b. In addition, in "S1" to "S8" and "T1" to "T8", the corresponding switch is turned on at the H level, and the corresponding switch is turned off at the L level.

[0076] As shown in the figure, the result of the control signals S1 to S8 and T1 to T8 controlling the on and off of the switches S1 to S8 and T1 to T8 constituting the switch group 25 is that at the first CLK, the diode characteristic element Q1 is selected as the first diode characteristic element group 22a, and the seven diode characteristic elements Q2 to Q8 other than the diode characteristic element Q1 are selected as the second diode characteristic element group 22b. At the second CLK, the diode characteristic element Q2 is selected as the first diode characteristic element group 22a, and the seven diode characteristic elements Q1 and Q3 to Q8 other than the diode characteristic element Q2 are selected as the second diode characteristic element group 22b, ... Similarly, at the eighth CLK, the diode characteristic element Q8 is selected as the first diode characteristic element group 22a, and the seven diode characteristic elements Q1 to Q7 other than the diode characteristic element Q8 are selected as the second diode characteristic element group 22b. In this way, the same selection state is repeated with the selection state of 8CLK as one cycle.

[0077] Figure 5 Yes Description Figure 4 A diagram showing the transitions of the selected states. Figure 5 (a) shows the arrangement positions of eight diode characteristic elements Q1 to Q8 constituting the diode characteristic element group 22 in the substrate 26 included in the semiconductor device 10 . Figure 5 (b) means Figure 4 The transition of the selection states of the diode characteristic elements Q1 to Q8 is shown.

[0078] according to Figure 5 As can be seen from (b), the state transition is repeated starting from "state 1" in which the diode characteristic element Q1 is selected as the first diode characteristic element group 22a and the seven diode characteristic elements Q2 to Q8 other than the diode characteristic element Q1 are selected as the second diode characteristic element group 22b, and then passing through "state 2", "state 3", ... until "state 8" in which the diode characteristic element Q8 is selected as the first diode characteristic element group 22a and the seven diode characteristic elements Q1 to Q7 other than the diode characteristic element Q8 are selected as the second diode characteristic element group 22b as one cycle.

[0079] Thus, according to this operation example, the one diode characteristic element selected as the first diode characteristic element group 22a and the seven diode characteristic elements selected as the second diode characteristic element group 22b are switched at each clock by the dynamic element matching circuit 23. Moreover, regardless of the selection state, the number M of diode characteristic elements selected as the first diode characteristic element group 22a and the number N of diode characteristic elements selected as the second diode characteristic element group 22b are constant (i.e., always 1 and 7, respectively). Furthermore, the number of times each of the diode characteristic elements Q1 to Q8 is selected as the first diode characteristic element group 22a and the number of times it is selected as the second diode characteristic element group 22b in one cycle are the same value (1 time and 7 times, respectively).

[0080] As a result, the variation in the characteristics of the first diode characteristic element group 22a and the second diode characteristic element group 22b caused by the manufacturing deviation of the diode characteristic elements Q1 to Q8 is suppressed and corrected at a certain period, so that the deviation between the semiconductor devices 10 of the reference voltage VBG generated based on the difference in current density of the current flowing through the first diode characteristic element group 22a and the current density of the current flowing through the second diode characteristic element group 22b is suppressed.

[0081] Furthermore, since the characteristic changes caused by the temperature of the first diode characteristic element group 22a and the second diode characteristic element group 22b are also suppressed, the adjustment range of the current ratio 1:k of the current mirror circuit 37a of the secondary temperature coefficient adjustment circuit 37 only needs to be smaller, or the adjustment of the secondary temperature coefficient is no longer required. By reducing the circuit scale of the secondary temperature coefficient adjustment circuit 37 or not providing the secondary temperature coefficient adjustment circuit 37, the circuit area of ​​the bandgap reference circuit 20 is reduced.

[0082] Next, a configuration and an operation example of a dynamic element matching circuit according to a modification of the present embodiment will be described.

[0083] Fig. 6A 2 is a diagram showing a diode characteristic element group 27 and a switch group 25a of a modified example. Figure 3 In the present modification, the diode characteristic element group 27 is composed of 16 diode characteristic elements Q1 to Q16. Furthermore, the switch group 25a is composed of switches S1 to S16 for connecting to the connection point V1 and switches T1 to T16 for connecting to the connection point V3 corresponding to the 16 diode characteristic elements Q1 to Q16.

[0084] Figure 6B Yes means Fig. 6A The timing diagram of the operation example of the dynamic element matching circuit of the modified example shown in FIG. Figure 4Corresponding to the figure, in this modification, the first diode characteristic element group 22a is composed of two diode characteristic elements selected from the 16 diode characteristic elements Q1 to Q16, and the second diode characteristic element group 22b is composed of 14 diode characteristic elements other than the selected two diode characteristic elements.

[0085] Figure 6C Yes Description Figure 6B A diagram showing the transitions of the selected states. Figure 6C (a) shows the configuration positions (layout) of 16 diode characteristic elements Q1 to Q16 constituting the diode characteristic element group 27 in the substrate 26 possessed by the semiconductor device 10, and a graph of the base-emitter voltage VBE (vertical axis) of the diode characteristic elements depending on the configuration position in the X-axis direction (configuration position in the direction from Q1 toward Q4, horizontal axis). Figure 6C (b) means Figure 6B The transition of the selection states of the diode characteristic elements Q1 to Q16 is shown.

[0086] like Figure 6C As shown in the layout of (a), in this modification, 16 diode characteristic elements Q1 to Q16 are formed in 4×4 rectangular locations on the substrate 26. Figure 6C As shown in FIG. 1 (a), depending on the manufacturing process of the semiconductor device 10, Figure 6C In the layout of (a), the base-emitter voltage VBE of each diode characteristic element increases from left to right.

[0087] As can be seen from this figure, in this modification, the configuration positions of the two diode characteristic elements selected as the first diode characteristic element group 22a in the substrate 26 are point symmetrical regardless of the selection state. For example, the configuration positions of the diode characteristic elements Q1 and Q13 selected in state 1 in the substrate 26 are point symmetrical, and the configuration positions of the diode characteristic elements Q2 and Q14 selected in state 2 in the substrate 26 are point symmetrical.

[0088] Similarly, the arrangement positions of the 14 diode characteristic elements selected as the second diode characteristic element group 22 b in the substrate 26 are point-symmetrical regardless of the selection state.

[0089] In this way, when the diode characteristic elements constituting the diode characteristic element group 27 have characteristic dependence based on the configuration position, according to the operation example of this variant, since both the first diode characteristic element group 22a and the second diode characteristic element group 22b are composed of diode characteristic elements in point-symmetrical configuration positions regardless of which selection state is used, the variation of the reference voltage VBG generated in each selection state is suppressed, and the noise accompanying the voltage variation between the selection states is reduced.

[0090] Fig.6D It is a diagram for explaining the transition of the selection state of the reference example. Fig.6D (a) and Figure 6C The same as (a). Fig.6D (b) and Figure 6C Unlike (b), the configuration positions of the two diode characteristic elements selected as the first diode characteristic element group 22a and the 14 diode characteristic elements selected as the second diode characteristic element group 22b on the substrate 26 are not point-symmetrical in any selection state.

[0091] In such a reference example, the generated reference voltage VBG varies in each selection state depending on the configuration positions of the diode characteristic elements selected as the first diode characteristic element group 22a and the second diode characteristic element group 22b on the substrate 26, resulting in voltage fluctuations between the selection states and generating noise.

[0092] Figure 7 is Figure 6C The variation shown is similar to Fig.6D The figure shows the simulation results obtained by comparing the variation (noise) of the reference voltage VBG between the reference examples shown in FIG. Figure 6C (a) and Fig.6D The time waveform of the variation (noise) of the reference voltage VBG when the arrangement positions of the diode characteristic elements Q1 to Q16 and the base-emitter voltage VBE are varied as shown in (a), and one cycle (period) of the selection state is set to 160 μs ( Figure 7 (a)) and spectrum ( Figure 7 (b)).

[0093] exist Figure 7 In (a) and (b), the solid line is Figure 6C In the case where the first diode characteristic element group 22a and the second diode characteristic element group 22b are configured in a point-symmetrical arrangement as in the modified example shown in FIG. Fig.6D As in the reference example shown in the figure, the first diode characteristic element group 22a and the second diode characteristic element group 22b are not composed of diode characteristic elements in a point-symmetrical arrangement position.

[0094] according to Figure 7 As can be seen from (b), in the case of the reference example, a noise spectrum having multiple peaks including the largest peak at 12.5 kHz is observed, whereas in the case of the modified example, almost no noise is observed.

[0095] As can be seen from the above, by selecting the first diode characteristic element group 22a and the second diode characteristic element group 22b to be composed of diode characteristic elements in point-symmetrical configuration positions in the substrate 26, the variation (noise) of the reference voltage VBG occurring between the selected states is suppressed.

[0096] Next, as an operation example of the dynamic element matching circuit 23 , an example in which randomness is incorporated when selecting diode characteristic elements as the first diode characteristic element group 22 a and the second diode characteristic element group 22 b will be described.

[0097] Figure 8 The present invention is a circuit diagram showing a configuration example of a switch selection circuit 24a that realizes a dynamic element matching circuit of a modified example incorporating randomness. The switch selection circuit 24a sets the state in which one diode characteristic element randomly selected from eight diode characteristic elements Q1 to Q8 is used as the first diode characteristic element group 22a and the other seven diode characteristic elements are used as the second diode characteristic element group 22b as state 1, and the state until the state 8 is changed as one cycle (loop), and controls the switch group 25 so that the state 1 is randomly changed while repeating the selected state for eight cycles.

[0098] The switch selection circuit 24a is composed of the following parts: a shift register 50, which is composed of 8 groups of two-input selectors and groups of flip-flops (FFs) connected to their outputs connected in series; a counter 51, which outputs a selection control signal to each selector; a pseudo-random number sequence generator 52, which provides a pseudo-random number (P / N code) to one side of the selector; and an inverter 53, which inverts the 8-bit output (control signals S1 to S8) from the shift register 50 and outputs it as control signals T1 to T8.

[0099] Fig.9A Yes means Figure 8 The timing diagram of the operation of the switch selection circuit 24a shown in FIG. Figure 8"CNT" is the output signal of counter 51, "SEL[1:8]" is the selection control signal (8 bits) output by pseudo-random number sequence generator 52, and "S1" to "S8" are control signals S1 to S8 output from 8 flip-flops constituting shift register 50. In this figure, the timing of 8 cycles (cycles 1 to 8) is shown, which is one cycle for the transition from state 1 to state 8.

[0100] In this figure, as shown in the signal waveform of "CNT", the counter 51 outputs an H level in state 1, and outputs an L level in other states. In addition, as shown in "SEL[1:8]", the pseudo-random number sequence generator 52 outputs a selection control signal in which one bit is randomly set to an H level among 8 bits in each cycle.

[0101] As a result, in each cycle, the shift register 50 selects the signals SEL1 to 8 from the two input signals in state 1 as indicated by the control signals "S1" to "S8", and as a result, determines and outputs the starting position of one cycle determined by the pseudo-random number sequence generator 52, and after state 2, selects and outputs the output of the previous stage trigger from the two input signals, thereby sequentially transitioning through the remaining 7 states.

[0102] Fig. 9B It means being Figure 8 The switch selection circuit 24a shown in the figure selects the diode characteristic element of the first diode characteristic element group 22a. Regarding the cycle 1 to 8 of the transition from state 1 to state 8, the diode characteristic element selected as the first diode characteristic element group 22a is shown. In addition, in each state, the diode characteristic element selected as the second diode characteristic element group 22b becomes 7 diode characteristic elements other than the diode characteristic element selected as the first diode characteristic element group 22a.

[0103] As shown in this figure, in each cycle, the diode characteristic element selected as the first diode characteristic element group 22a is the diode characteristic element Q1 in cycle 1, and becomes the diode characteristic elements Q7, Q3, Q2, Q8, Q5, Q6, Q4 randomly selected from the diode characteristic elements other than the already selected diode characteristic element in cycles 2 to 8.

[0104] Fig.10 Yes Description Figure 8 The diagram shown is a diagram of the effect of the operation of the dynamic element matching circuit of the modified example incorporating randomness. Fig.10(a) shows the configuration positions (layout) of eight diode characteristic elements Q1 to Q8 constituting the diode characteristic element group 22 on the substrate 26 and the base-emitter voltage VBE (vertical axis) of the diode characteristic elements depending on the configuration positions in the X-axis direction (horizontal axis). Fig.10 (b) means Figure 5 The state transition caused by the dynamic element matching circuit of the embodiment shown without combining randomness is similar to Fig. 9B The figure shows the simulation results obtained by comparing the variation (noise) of the reference voltage VBG between the state transitions caused by the dynamic element matching circuit of the modified example combined with randomness. Figure 7 The simulation results shown in FIG. 1 similarly show the spectrum of the variation (noise) of the reference voltage VBG when one cycle (period) of the selection state is set to 160 μs. Fig.10 In (b), the dotted line indicates Figure 5 The spectrum of the state transition caused by the dynamic element matching circuit of the embodiment without combining randomness is shown, and the solid line represents Fig. 9B The spectrum of state transition caused by the dynamic element matching circuit of the modified example incorporating randomness is shown.

[0105] according to Fig.10 As can be seen from (b), in the state transition without randomness, a relatively strong noise peak can be seen at 6.25kHz. In contrast, in the state transition with randomness, the intensity of the noise peak is suppressed to a smaller level.

[0106] Based on the above, it can be seen that through the dynamic element matching circuit of the modified example, the diode characteristic elements constituting the first diode characteristic element group 22a and the second diode characteristic element group 22b are set to a combination based on selection combined with randomness, so that the changes (noise) of the reference voltage VBG occurring between the selection states are suppressed.

[0107] Next, as another operation example of the dynamic element matching circuit 23 , an example in which ΔΣ modulation is combined when diode characteristic elements are selected as the first diode characteristic element group 22 a and the second diode characteristic element group 22 b will be described.

[0108] Fig.11 This is a diagram for explaining a configuration example of a switch selection circuit 24b that realizes a dynamic element matching circuit according to a modification example incorporating ΔΣ modulation. Fig.11 (a) is for Fig.10 A graph of “VBE variation (with the center represented as 0)” has been added to (a). Fig.11 (b) is a circuit diagram showing a configuration example of the switch selection circuit 24b.

[0109] like Fig.11 As shown in (a) of FIG. 1 , in this example, the target value of the base-emitter voltage VBE corresponds to the center position of the arrangement positions of the diode characteristic elements Q1 to Q8 in the X-axis direction.

[0110] like Fig.11 As shown in (b) of FIG. 2 , the switch selection circuit 24 b includes a target value setting circuit 54 , a ΔΣ modulator 55 , a Y-axis selection circuit 56 , a selector 57 , and an inverter 58 .

[0111] The target value setting circuit 54 holds the target value (here, the configuration position "0" in the X-axis direction), and outputs it to the ΔΣ modulator 55 for setting. The ΔΣ modulator 55 uses the target value (0) given by the target value setting circuit 54 as the target, performs ΔΣ modulation according to the DEM control clock, and repeatedly performs the operation of selecting one of the four positions (-2, -1, 1, 2) in the X-axis direction and outputting it to the selector 57. The Y-axis selection circuit 56 sequentially selects two configuration positions (upper row and lower row) of the diode characteristic elements Q1 to Q8 in the Y-axis direction and outputs them to the selector 57. The selector 57 selects one diode characteristic element determined by the output from the ΔΣ modulator 55 and the Y-axis selection circuit 56, and outputs the control signals S1 to S8 to the switch group 25. The inverter 58 outputs the control signals T1 to T8 obtained by inverting the control signals S1 to S8 from the selector 57 to the switch group 25.

[0112] The switch selection circuit 24b operates according to ΔΣ modulation, so that the selection frequency of the diode characteristic element increases with the two positions (-1, 1) in the X-axis direction, and the frequency of the two positions (-2, 2) decreases, so the change caused by the state switching becomes smaller. Therefore, compared with the cyclic type selection operation, noise can be suppressed.

[0113] The dynamic element matching circuit having such a switch selection circuit 24b selects the first diode characteristic element group 22a and the second diode characteristic element group 22b in a repeated process of selecting a combination of the first diode characteristic element group 22a and the second diode characteristic element group 22b in such a manner that the M diode characteristic elements constituting the first diode characteristic element group 22a are switched according to ΔΣ modulation, and the N diode characteristic elements constituting the second diode characteristic element group 22b are switched according to ΔΣ modulation.

[0114] Thus, with the dynamic element matching circuit of the modification example incorporating ΔΣ modulation, the variation (noise) of the reference voltage VBG occurring between selected states is suppressed, similarly to the dynamic element matching circuit of the modification example incorporating randomness.

[0115] Next, another example of the layout of the diode characteristic element group 28 on the substrate 26 will be described.

[0116] Fig.12 1 is a diagram showing a layout of a diode characteristic element group 28 of a modification example on a substrate 26. In this figure, 16 white rectangles located in the center represent diode characteristic elements selected as the first diode characteristic element group 22a and the second diode characteristic element group 22b, and 20 shaded rectangles located in the periphery represent diode characteristic elements as dummy elements that are not selected as the first diode characteristic element group 22a and the second diode characteristic element group 22b.

[0117] That is, in this variation, in a plan view of the substrate 26 , the dynamic element matching circuit 23 targets the diode characteristic elements of the diode characteristic element group 28 excluding the diode characteristic elements located at the periphery, and selects the first diode characteristic element group 22 a and the second diode characteristic element group 22 b .

[0118] Generally speaking, the diode characteristic elements located at the periphery of the diode characteristic element group 28 have larger characteristic deviations due to the density of impurity diffusion in the semiconductor manufacturing process, etc., compared with the diode characteristic elements located in the center. Therefore, according to this modification, the first diode characteristic element group 22a and the second diode characteristic element group 22b are configured on the basis of excluding the diode characteristic elements with large characteristic deviations, so compared with the normal case where non-selected diode characteristic elements are not provided at the periphery, the characteristic deviations of the selected first diode characteristic element group 22a and the second diode characteristic element group 22b are suppressed.

[0119] Next, an example will be described in which the bipolar transistors 37 b and 37 c included in the secondary temperature coefficient adjustment circuit 37 are included in the diode characteristic element group 22 and are made the objects of dynamic element matching.

[0120] Fig.13 The present invention is a circuit block diagram showing the structure of a semiconductor device 10a according to a modified example in which a bipolar transistor (i.e., a diode characteristic element) included in a secondary temperature coefficient adjustment circuit is included in a diode characteristic element group and is used as an object of dynamic element matching. The semiconductor device 10a is Figure 1 The semiconductor device 10 shown in the figure includes a dynamic element matching circuit group 23 a instead of the switch group 25 and the diode characteristic element group 22 .

[0121] The dynamic element matching circuit group 23a has connection points V1, V2, V3, VDD, and V4 as connection points with the reference voltage generating circuit 30. The connection points V1, V2, V3, VDD, and V4 are connected to the reference voltage generating circuit 30. Figure 1 The connection point V4 corresponds to the input terminal IN of the current mirror circuit 37a.

[0122] Fig.14 Yes means Fig.13 The circuit diagram of the detailed structure of the dynamic element matching circuit group 23a in FIG. The dynamic element matching circuit group 23a is composed of 10 bipolar transistors Q1 to Q10 and 9 switches S20 to S23 and S25 to S29 provided for the bipolar transistors Q1 to Q10, respectively.

[0123] In this variation, according to the DEM control signal from the switch selection circuit 24, the 10 bipolar transistors Q1~Q10 can be selected as the first diode characteristic element group 22a, or selected as the second diode characteristic element group 22b, or selected as the bipolar transistors (i.e., diode characteristic elements) included in the secondary temperature coefficient adjustment circuit 37.

[0124] For example, when the bipolar transistor Q1 is selected as the first diode characteristic element group 22 a , among the switches S20 to S23 and S25 to S29 , only the switches S20 , S27 , and S29 are turned on, and the other switches are turned off.

[0125] Furthermore, when the bipolar transistor Q1 is selected as the second diode characteristic element group 22 b , among the switches S20 to S23 and S252 to S29 , only the switches S21 , S27 , and S29 are turned on, and the other switches are turned off.

[0126] When the bipolar transistor Q1 is selected as the bipolar transistor 37 b included in the secondary temperature coefficient adjustment circuit 37 , only the switches S22 , S25 , and S28 among the switches S20 to S23 and S25 to S29 are turned on, and the other switches are turned off.

[0127] When the bipolar transistor Q1 is selected as the bipolar transistor 37 c included in the secondary temperature coefficient adjustment circuit 37 , only the switches S23 , S26 , and S29 among the switches S20 to S23 and S25 to S29 are turned on, and the other switches are turned off.

[0128] Thus, in this variation, the dynamic element matching circuit group 23a performs within a certain period: while changing the combination of the selected M diode characteristic elements, N diode characteristic elements and at least one diode characteristic element that functions as the secondary temperature coefficient adjustment circuit 37, it repeatedly selects at least one diode characteristic element that functions as the secondary temperature coefficient adjustment circuit 37 from the diode characteristic element group (bipolar transistors Q1 to Q10) in addition to the first diode characteristic element group 22a and the second diode characteristic element group 22b.

[0129] Therefore, not only the diode characteristic element group 22 but also the bipolar transistors 37b and 37c included in the secondary temperature coefficient adjustment circuit 37 become the objects of dynamic element matching, so the adjustment current Ic(t) output from the secondary temperature coefficient adjustment circuit 37 is averaged, and the current mirror circuit 37a of the secondary temperature coefficient adjustment circuit 37 has a narrower adjustment range of the current ratio 1:k, and the circuit scale of the secondary temperature coefficient adjustment circuit 37 is reduced.

[0130] Next, a specific configuration example of the first switch circuit 32 and the second switch circuit 34 included in the semiconductor device 10 according to the embodiment will be described.

[0131] Fig.15 Yes means Figure 1 A circuit diagram of a specific configuration example of the first switch circuit 32 and the second switch circuit 34 in FIG. The first switch circuit 32 (the second switch circuit 34) is composed of: four switches 32a to 32d having two input terminals IN1 and IN2 and two output terminals OUT1 and OUT2, each of which is formed by connecting an N-channel MOS transistor and a P-channel MOS transistor in parallel; and a logic circuit 32e that generates control signals SEL1 and XSEL1 (inversion signals of SEL1) to the gates of the N-channel MOS transistor and the P-channel MOS transistor based on the chopping clock 1 (2) input from the timing generation circuit 21.

[0132] When the control signals SEL1 and XSEL1 are at valid levels (for example, H level and L level, respectively), the input terminals IN1 and IN2 are directly connected to the output terminals OUT1 and OUT2, respectively. On the other hand, when the control signals SEL1 and XSEL1 are at invalid levels (for example, L level and H level, respectively), the input terminals IN1 and IN2 are cross-connected to the output terminals OUT2 and OUT1, respectively.

[0133] Thus, the first switch circuit 32 continuously switches the connection between the first current source 31a and the second current source 31b and the first resistor element 33a and the second resistor element 33b between direct connection and cross connection alternately based on the chopping clock 1 input from the timing generation circuit 21. As a result, the current source supplying current to the first diode characteristic element group 22a and the current source supplying current to the second diode characteristic element group 22b are periodically switched between the first current source 31a and the second current source 31b.

[0134] As a result, the deviation of the output current caused by the manufacturing deviation of the circuit components constituting the first current source 31a and the second current source 31b is averaged, which can reduce the adjustment range of the primary temperature coefficient adjustment circuit 36 ​​and the secondary temperature coefficient adjustment circuit 37, so that the circuit scale of the primary temperature coefficient adjustment circuit 36 ​​and the secondary temperature coefficient adjustment circuit 37 can be reduced.

[0135] Similarly, the second switch circuit 34 continues to alternately switch the connection between the connection points V1 and V2 and the non-inverting input terminal and the inverting input terminal of the differential amplifier 35 between direct and cross connections based on the chopping clock 2 input from the timing generation circuit 21. In addition, the internal circuit 35a of the differential amplifier 35 also switches the connection mode in synchronization with the switching operation of the second switch circuit 34 based on the chopping clock 2 from the timing generation circuit 21 so that the same amplification operation is performed whether the non-inverting input terminal and the inverting input terminal are functionally switched or not.

[0136] As a result, the voltage input to the non-inverting input terminal and the voltage input to the inverting input terminal of the differential amplifier 35 are periodically switched between a first voltage depending on the current density of the current flowing in the first diode characteristic element group 22a and a second voltage depending on the current density of the current flowing in the second diode characteristic element group 22b.

[0137] As a result, characteristic deviations such as offset voltage caused by manufacturing deviations of circuit components constituting the differential amplifier 35 are averaged, and the adjustment ranges of the primary temperature coefficient adjustment circuit 36 ​​and the secondary temperature coefficient adjustment circuit 37 can be reduced, so that the circuit scales of the primary temperature coefficient adjustment circuit 36 ​​and the secondary temperature coefficient adjustment circuit 37 can be reduced.

[0138] Next, a specific configuration example of the time-discrete filter 40 included in the semiconductor device 10 according to the embodiment will be described.

[0139] Fig.16A Yes means Figure 1 4 is a circuit diagram of a specific configuration example of the time discrete filter 40. The time discrete filter 40 is a filter that smoothes the reference voltage VBG generated by the reference voltage generation circuit 30 and outputs the smoothed reference voltage VBG2, and is composed of a logic circuit 40a, a switch 40b, and a capacitor 40c.

[0140] The logic circuit 40a outputs a drive signal SW to the switch 40b in synchronization with the filter clock from the timing generation circuit 21, and drives the switch 40b on and off. As a result, only the voltage during the time when the voltage is stable among the reference voltage VBG input to the switch 40b passes through, is smoothed in the capacitor 40c, and is output as the reference voltage VBG2.

[0141] Fig. 16B Yes means Fig.16A The timing diagram of the operation of the time discrete filter 40 is shown in FIG. Fig.16A , “S1” to “S8” represent control signals S1 to S8 for driving switches S1 to S8, “chopping clock 1” and “chopping clock 2” represent chopping clocks 1 and 2 output by the timing generation circuit 21, respectively, “VBG” represents the reference voltage VBG generated by the reference voltage generation circuit 30, “SW” represents the drive signal SW output by the logic circuit 40a of the time-discrete filter 40, and “VBG2” represents the reference voltage VBG2 output by the time-discrete filter 40.

[0142] according to Fig. 16B It can be seen that noise is generated in the reference voltage "VBG" due to the on-off of the switches S1 to S8 based on the control signals S1 to S8, but the noise is suppressed as shown by the reference voltage "VBG2" by the time discretization (on-off of "SW") of the switch 40b and the capacitor 40c by the time discrete filter 40. As a result, the stabilization waiting time in the acquisition of the signal to the AD converter 41 at the subsequent stage can be shortened.

[0143] Next, a semiconductor device 10 b according to a modification example including an averaging filter as an analog signal processing circuit instead of the time discrete filter 40 , the AD converter 41 , and the averaging filter 42 in the embodiment will be described.

[0144] Fig.17A 1 is a circuit block diagram showing the structure of a semiconductor device 10b according to a modification example including an averaging filter 43 as an analog signal processing circuit instead of the time discrete filter 40, the AD converter 41, and the averaging filter 42 in the embodiment. Figure 1 The semiconductor device 10 shown in the figure includes an averaging filter 43 as an analog signal processing circuit instead of the time discrete filter 40 , the AD converter 41 , and the averaging filter 42 .

[0145] Fig. 17B Yes means Fig.17A The circuit diagram of the detailed structure of the averaging filter 43 is shown. The averaging filter 43 is a filter that smoothes the reference voltage VBG generated by the reference voltage generating circuit 30 and outputs it as the reference voltage VBG3, and is composed of a logic circuit 43a, capacitors 43b and 43c, an operational amplifier 43d, and switches 44a to 44e.

[0146] The logic circuit 43a controls the on-off of the switches 44a to 44e in synchronization with the filter clock from the timing generation circuit 21. Specifically, the on-off of the switches 44a to 44d is controlled so that the state in which the switches 44a and 44c are turned on and the other switches are turned off, and the state in which the switches 44b and 44d are turned on and the other switches are turned off is alternately switched. The switch 44e performs an operation of applying a reset (i.e., short-circuiting and turning off) once in one cycle of dynamic element matching (a cycle in which the diode characteristic elements Q1 to Q8 are selected).

[0147] As a result, the reference voltage VBG input to the switch 44a is sampled and integrated alternately and repeatedly, and is subjected to signal processing equivalent to the processing performed by the time discrete filter 40, the AD converter 41 and the averaging filter 42 in the embodiment, and is output as a temporally averaged reference voltage VBG3.

[0148] Fig. 17C Yes means Fig.17A Here, there are shown examples of combinations of the logic levels of the chopping clocks 1 and 2 output from the timing generation circuit 21 and the diode characteristic elements selected as the first diode characteristic element group 22a in one cycle of the averaging process performed by the averaging filter 43 (three examples from (a) to (c)).

[0149] In combination example (a), in one cycle of averaging processing by the averaging filter 43, chopper clock 1 repeats one cycle, chopper clock 2 repeats two cycles, and the cycle of selecting diode characteristic elements Q1 to Q8 as the first diode characteristic element group 22a repeats four cycles.

[0150] In combination example (b), in one cycle of averaging processing by the averaging filter 43, chopper clock 1 repeats one cycle, chopper clock 2 repeats 16 cycles, and the cycle of selecting diode characteristic elements Q1 to Q8 as the first diode characteristic element group 22a repeats two cycles.

[0151] In combination example (c), in one cycle of averaging processing by the averaging filter 43, chopper clock 1 repeats 8 cycles, chopper clock 2 repeats 16 cycles, and a cycle of selecting diode characteristic elements Q1 to Q8 as the first diode characteristic element group 22a repeats 1 cycle.

[0152] In any combination example, the cycles of chopper clock 1, chopper clock 2, and the diode characteristic elements Q1 to Q8 selected as the first diode characteristic element group 22a are synchronized, and one cycle of averaging processing performed by the averaging filter 43 becomes the least common multiple of the cycle of the chopper clock 1, the cycle of the chopper clock 2, and the cycle of the dynamic element matching circuit 23 selecting the first diode characteristic element group 22a and the second diode characteristic element group 22b.

[0153] Thus, the reference voltage VBG3 output from the averaging filter 43 is averaged in all combinations of the operations of the chopping clock 1, the chopping clock 2, and the dynamic element matching circuit 23, so that variations in elements and circuits (diode characteristic elements, resistor elements, differential amplifiers) are effectively suppressed.

[0154] in addition, Fig. 17C yes Fig.17A The example shown in FIG. 1 shows an example of performing averaging processing by the averaging filter 43 for one cycle, but it may be replaced by Figure 1 The averaging filter 42 shown is an example of one cycle in which the averaging process is performed.

[0155] As described above, the bandgap reference circuit 20 of the above-mentioned embodiment comprises: a diode characteristic element group 22, which is composed of a plurality of diode characteristic elements; a dynamic element matching circuit 23, which performs the following actions within a certain period, namely: while changing the combination of M diode characteristic elements and N diode characteristic elements to be selected, repeatedly performs the actions of selecting a first diode characteristic element group 22a composed of M diode characteristic elements connected in parallel and a second diode characteristic element group 22b composed of N diode characteristic elements connected in parallel from the diode characteristic element group 22, where M is an integer greater than 1 and N is an integer greater than 2 and greater than M; a reference voltage generating circuit 30, which generates a reference voltage VBG based on the difference between the current density of the current flowing through the first diode characteristic element group 22a and the current density of the current flowing through the second diode characteristic element group 22b; and a secondary temperature coefficient adjusting circuit 37, which adjusts the secondary temperature coefficient of the reference voltage VBG generated by the reference voltage generating circuit 30.

[0156] Thus, the reference voltage VBG is generated while switching the M diode characteristic elements constituting the first diode characteristic element group 22a and the N diode characteristic elements constituting the second diode characteristic element group 22b through the dynamic element matching circuit 23, so that the characteristics of the first diode characteristic element group 22a and the second diode characteristic element group 22b are averaged, and a bandgap reference circuit with suppressed characteristic variation is realized. In addition, as a result, the adjustment range of the secondary temperature coefficient adjustment circuit 37 is narrow, so the circuit scale of the secondary temperature coefficient adjustment circuit 37 can be reduced.

[0157] Furthermore, the bandgap reference circuit 20 further includes a primary temperature coefficient adjustment circuit 36 ​​for adjusting the primary temperature coefficient of the reference voltage VBG generated by the reference voltage generation circuit 30. Thus, the primary temperature coefficient of the generated reference voltage VBG is suppressed.

[0158] Furthermore, the sum of M and N is a power of 2. Thus, the digital circuit for generating the combination of M diode characteristic elements and N diode characteristic elements selected by the dynamic element matching circuit 23 is simplified.

[0159] In addition, the dynamic element matching circuit 23 selects the first diode characteristic element group 22a and the second diode characteristic element group 22b so that the ratio of M to N becomes the same value in each repetition. As a result, the characteristic change of the first diode characteristic element group 22a and the second diode characteristic element group 22b is suppressed compared to the case where the ratio of M to N changes, and the noise generated when the diode characteristic elements constituting the first diode characteristic element group 22a and the second diode characteristic element group 22b are switched is suppressed.

[0160] In addition, the dynamic element matching circuit 23 selects the first diode characteristic element group 22a and the second diode characteristic element group 22b so that no matter which diode characteristic element is selected, the number of times it is selected as the first diode characteristic element group 22a and the second diode characteristic element group 22b in a certain period becomes the same value. As a result, the number of times the diode characteristic elements constituting the diode characteristic element group 22 are selected as the first diode characteristic element group 22a and the second diode characteristic element group 22b becomes the same value, the characteristic change of the first diode characteristic element group 22a and the second diode characteristic element group 22b is suppressed, and the noise generated when the diode characteristic elements constituting the first diode characteristic element group 22a and the second diode characteristic element group 22b are switched is suppressed.

[0161] In addition, the diode characteristic element group 22 is arranged on the substrate, and the dynamic element matching circuit 23 selects the first diode characteristic element group 22a and the second diode characteristic element group 22b so that, in a planar view of the substrate, the arrangement positions of the M diode characteristic elements on the substrate are point symmetrical, and the arrangement positions of the N diode characteristic elements on the substrate are point symmetrical. Thus, even if the diode characteristic elements constituting the diode characteristic element group 22 have characteristic deviations that depend on the arrangement positions, the dependence of the first diode characteristic element group 22a and the second diode characteristic element group 22b on the arrangement positions is suppressed.

[0162] Furthermore, in the above-described modification, the dynamic element matching circuit 23 selects the first diode characteristic element group 22a and the second diode characteristic element group 22b in a repeated process of selecting a combination of the first diode characteristic element group 22a and the second diode characteristic element group 22b in such a manner that the M diode characteristic elements constituting the first diode characteristic element group 22a are randomly switched and the N diode characteristic elements constituting the second diode characteristic element group 22b are randomly switched. Thus, the diode characteristic elements selected as the first diode characteristic element group 22a and the second diode characteristic element group 22b are randomly switched, and noise generated when the diode characteristic elements constituting the first diode characteristic element group 22a and the second diode characteristic element group 22b are switched is suppressed.

[0163] Furthermore, in the above-described modification, the dynamic element matching circuit 23 selects the first diode characteristic element group 22a and the second diode characteristic element group 22b in a repeated process of selecting a combination of the first diode characteristic element group 22a and the second diode characteristic element group 22b, so that the M diode characteristic elements constituting the first diode characteristic element group 22a are switched according to ΔΣ modulation, and the N diode characteristic elements constituting the second diode characteristic element group 22b are switched according to ΔΣ modulation. Thus, the diode characteristic elements selected as the first diode characteristic element group 22a and the second diode characteristic element group 22b are switched according to ΔΣ modulation, and noise generated when the diode characteristic elements constituting the first diode characteristic element group 22a and the second diode characteristic element group 22b are switched is suppressed.

[0164] Furthermore, in the above-mentioned modification, the diode characteristic element group 22 is arranged on the substrate, and the dynamic element matching circuit 23 selects the first diode characteristic element group 22a and the second diode characteristic element group 22b by targeting the diode characteristic elements other than the diode characteristic elements located at the periphery of the diode characteristic element group 22 in the plan view of the substrate. Thus, the first diode characteristic element group 22a and the second diode characteristic element group 22b are formed after excluding the diode characteristic elements with large characteristic deviation, so that the characteristic deviation of the selected first diode characteristic element group 22a and the second diode characteristic element group 22b is suppressed compared with the normal case where the non-selected diode characteristic elements are not provided at the periphery.

[0165] In the above-mentioned modification, the dynamic element matching circuit group 23a performs the following operation in a certain cycle: while changing the combination of the M diode characteristic elements, the N diode characteristic elements, and the at least one diode characteristic element functioning as the secondary temperature coefficient adjustment circuit 37 to be selected, the operation of repeatedly selecting at least one diode characteristic element functioning as the secondary temperature coefficient adjustment circuit 37 from the diode characteristic element group (bipolar transistors Q1 to Q10) in addition to the first diode characteristic element group 22a and the second diode characteristic element group 22b. Thus, the at least one diode characteristic element functioning as the secondary temperature coefficient adjustment circuit 37 is also included as an object of dynamic element matching, so that the characteristic variation of the diode characteristic elements constituting the secondary temperature coefficient adjustment circuit 37 is suppressed, and the adjustment range of the secondary temperature coefficient adjustment circuit 37 can be narrowed, so that the circuit scale of the secondary temperature coefficient adjustment circuit 37 can be reduced.

[0166] In addition, the bandgap reference circuit 20 of the embodiment comprises: a first current source 31a and a second current source 31b; a first diode characteristic element, which receives current supply from one of the first current source 31a and the second current source 31b; a second diode characteristic element, which receives current supply from the other of the first current source 31a and the second current source 31b and flows a current having a different current density from that of the first diode characteristic element; a reference voltage generating circuit 30, which generates a reference voltage VBG based on the difference in current density; a primary temperature coefficient adjusting circuit 36, which adjusts the primary temperature coefficient of the reference voltage VBG generated by the reference voltage generating circuit 30; a secondary temperature coefficient adjusting circuit 37, which adjusts the secondary temperature coefficient of the reference voltage VBG generated by the reference voltage generating circuit 30; and a first switch circuit 32, which periodically switches between the first current source 31a and the second current source 31b to supply current to the first diode characteristic element and the current source to supply current to the second diode characteristic element.

[0167] Thus, the characteristic variation of the bandgap reference circuit due to the characteristic difference between the first current source 31 a and the second current source 31 b is suppressed.

[0168] In addition, the bandgap reference circuit 20 of the embodiment comprises: a first current source 31a and a second current source 31b; a first diode characteristic element, which receives a current supply from one of the first current source 31a and the second current source 31b; a second diode characteristic element, which receives a current supply from the other of the first current source 31a and the second current source 31b, and flows a current having a different current density from that of the first diode characteristic element; a reference voltage generating circuit 30, which generates a reference voltage VBG based on the difference in current density; and a primary temperature coefficient adjusting circuit 36, which adjusts the primary temperature coefficient of the reference voltage VBG generated by the reference voltage generating circuit 30. ; and a secondary temperature coefficient adjustment circuit 37, which adjusts the secondary temperature coefficient of the reference voltage VBG generated by the reference voltage generating circuit 30; the reference voltage generating circuit 30 includes: a differential amplifier 35, having a first input terminal and a second input terminal, to which the first input terminal and the second input terminal are input with a first voltage depending on the current density of the current flowing in the first diode characteristic element and a second voltage depending on the current density of the current flowing in the second diode characteristic element; and a second switching circuit 34, which periodically switches the voltage input to the first input terminal and the voltage input to the second input terminal between the first voltage and the second voltage.

[0169] Thus, characteristic variations of the bandgap reference circuit due to characteristic variations of circuit components constituting the differential amplifier 35 are suppressed.

[0170] In addition, the bandgap reference circuit 20 further includes a dynamic element matching circuit 23, which performs the following actions within a certain period, namely: while changing the combination of M diode characteristic elements and N diode characteristic elements to be selected, the dynamic element matching circuit 23 repeatedly performs the actions of selecting a first diode characteristic element group 22a consisting of M diode characteristic elements connected in parallel as the first diode characteristic element from a diode characteristic element group 22 consisting of a plurality of diode characteristic elements, and selecting a second diode characteristic element group 22b consisting of N diode characteristic elements connected in parallel as the second diode characteristic element from the diode characteristic element group 22a, where M is an integer greater than 1 and N is an integer greater than 1.

[0171] Thus, the characteristics of the first diode characteristic element group 22a and the second diode characteristic element group 22b are averaged, and noise generated when the diode characteristic elements constituting the first diode characteristic element group 22a and the second diode characteristic element group 22b are switched is suppressed.

[0172] In addition, the semiconductor device 10 according to the above embodiment includes: the bandgap reference circuit 20; and a discrete-time filter 40 receiving the reference voltage VBG outputted from the bandgap reference circuit 20; the dynamic element matching circuit 23 repeatedly operates in synchronization with the clock signal; and the discrete-time filter 40 performs discrete-time filtering in synchronization with the clock signal. Thus, the generation of noise caused by the switching operation of the dynamic element matching circuit 23, the first switch circuit 32, and the second switch circuit 34 is suppressed.

[0173] In addition, the semiconductor device 10b of the above-mentioned modification example comprises: the bandgap reference circuit 20; and an averaging filter 43 receiving the reference voltage VBG outputted from the bandgap reference circuit 20; the dynamic element matching circuit 23 repeatedly operates in synchronization with the clock signal; and the averaging filter 43 performs averaging filtering in synchronization with the clock signal. Thus, the noise generated when the diode characteristic elements constituting the first diode characteristic element group 22a and the second diode characteristic element group 22b are switched is suppressed.

[0174] In addition, the semiconductor device 10 according to the above embodiment includes: the bandgap reference circuit 20; and an AD converter 41 that receives the reference voltage VBG output from the bandgap reference circuit 20; the dynamic element matching circuit 23 repeatedly operates in synchronization with the clock signal; and the AD converter 41 converts the reference voltage VBG into a digital signal in synchronization with the clock signal. Thus, by staggering the timing of the switch in the dynamic element matching circuit 23 and the timing of the sampling in the AD converter 41, the output error from the AD converter 41 is suppressed.

[0175] In addition, the semiconductor device 10b of the above-mentioned modified example comprises: a first current source 31a and a second current source 31b; a diode characteristic element group 22, which is composed of a plurality of diode characteristic elements; and a dynamic element matching circuit 23, which performs the following actions in a certain period, namely: while changing the combination of M diode characteristic elements and N diode characteristic elements to be selected, repeatedly performs the action of selecting the first diode characteristic element group 22a and the second diode characteristic element group 22b from the diode characteristic element group 22, wherein the first diode characteristic element group 22a is composed of M diode characteristic elements connected in parallel, The first switching circuit 32 periodically switches between the current source for supplying current to the first diode characteristic element group 22a and the current source for supplying current to the second diode characteristic element group 22b; the reference voltage generating circuit 32 generates a reference voltage generating circuit 31a, wherein the first switching circuit 32 receives a current supply from one of the first current source 31a and the second current source 31b; the second diode characteristic element group 22b is composed of N diode characteristic elements connected in parallel and receives a current supply from the other of the first current source 31a and the second current source 31b, wherein M is an integer greater than 1 and N is an integer greater than 2 and greater than M; the first switching circuit 32 periodically switches between the current source for supplying current to the first diode characteristic element group 22a and the current source for supplying current to the second diode characteristic element group 22b; The circuit 30 generates a reference voltage VBG based on the difference between the current density of the current flowing through the first diode characteristic element group 22a and the current density of the current flowing through the second diode characteristic element group 22b, and includes a differential amplifier 35 and a second switch circuit 34. The differential amplifier 35 has a first input terminal and a second input terminal, and the first input terminal and the second input terminal are input with a first voltage depending on the current density of the current flowing through the first diode characteristic element group 22a and a second voltage depending on the current density of the current flowing through the second diode characteristic element group 22b. The second switch circuit 34 generates a reference voltage VBG based on the difference between the current density of the current flowing through the first diode characteristic element group 22a and the current density of the current flowing through the second diode characteristic element group 22b. The voltage input to the first input terminal and the voltage input to the second input terminal are periodically switched between the voltage and the second voltage; a secondary temperature coefficient adjustment circuit 37 adjusts the secondary temperature coefficient of the reference voltage VBG generated by the reference voltage generating circuit 30; and an averaging filter 43 receives the reference voltage VBG output from the reference voltage generating circuit 30; the averaging filter 43 averages the reference voltage VBG with a period of the least common multiple of a certain period in the selection action of the dynamic element matching circuit 23, a period in the action of the first switch circuit 32, and a period in the action of the second switch circuit 34.

[0176] Therefore, since the reference voltage VBG is averaged by the averaging filter 43 according to a certain cycle in the selection operation of the dynamic element matching circuit 23, the cycle in the operation of the first switch circuit 32, and the cycle in the operation of the second switch circuit 34, noise in the reference voltage VBG is effectively suppressed.

[0177] The bandgap reference circuit and semiconductor device of the present disclosure are described above based on the embodiments and modified examples, but the present disclosure is not limited to these embodiments and modified examples. As long as it does not depart from the main purpose of the present disclosure, the embodiments and modified examples are subjected to various modifications that can be thought of by those skilled in the art, or other forms constructed by combining some of the constituent elements of the embodiments and modified examples are also included in the scope of the present disclosure.

[0178] For example, the bandgap reference circuit 20 of the above-mentioned embodiment includes the primary temperature coefficient adjustment circuit 36, the first switch circuit 32, and the second switch circuit 34, but these are not essential for the bandgap reference circuit. By including the dynamic element matching circuit 23, a bandgap reference circuit having a unique effect that characteristic variation is suppressed and which has not been achieved in the past can be realized.

[0179] Furthermore, the bandgap reference circuit 20 of the above-described embodiment includes the timing generation circuit 21, the first current source 31a, and the second current source 31b, but these components are not necessarily required, and a circuit configuration in which these components are provided outside the bandgap reference circuit 20 and used may also be adopted.

[0180] Furthermore, the first switch circuit 32 and the second switch circuit 34 of the bandgap reference circuit 20 of the above-mentioned embodiment do not necessarily need the dynamic element matching circuit 23 and the diode characteristic element group 22, and may be provided with a first diode characteristic element and a second diode characteristic element through which a current having a different current density from that of the first diode characteristic element flows, instead of the dynamic element matching circuit 23 and the diode characteristic element group 22. In this case, the first diode characteristic element and the second diode characteristic element may be a single diode characteristic element or may be formed by connecting two or more diode characteristic elements in parallel.

[0181] Industrial Applicability

[0182] The bandgap reference circuit and semiconductor device disclosed herein can be used as a reference voltage generation circuit used in an AD converter or a voltage measuring device that requires high accuracy and high stability as a bandgap reference circuit and semiconductor device with suppressed characteristic variation.

[0183] Description of Reference Numerals

[0184] 10, 10a, 10b semiconductor device

[0185] 20 Bandgap Reference Circuit

[0186] 21 Timing Generation Circuit

[0187] 22, 27, 28 diode characteristic element group

[0188] 22a The first diode characteristic element group

[0189] 22b Second diode characteristic element group

[0190] 23 Dynamic Component Matching Circuit

[0191] 23a Dynamic Element Matching Circuit Group

[0192] 24, 24a, 24b switch selection circuit

[0193] 25, 25a switch group

[0194] 26 substrate

[0195] 30 Reference voltage generation circuit

[0196] 31a 1st current source

[0197] 31b Second current source

[0198] 32 1st switch circuit

[0199] 32a~32d switch

[0200] 32e logic circuit

[0201] 33a 1st resistor element

[0202] 33b Second resistance element

[0203] 34 2nd switch circuit

[0204] 35 Differential Amplifier

[0205] 35a Internal circuit

[0206] 36 Primary temperature coefficient adjustment circuit

[0207] 37 Secondary temperature coefficient adjustment circuit

[0208] 37a Current mirror circuit

[0209] 37b, 37c Bipolar transistors

[0210] 40 Time Discrete Filter

[0211] 40a, 43a logic circuit

[0212] 40b, 44a to 44e switches

[0213] 40c, 43b, 43c capacitors

[0214] 41 AD converter

[0215] 42, 43 Average filter

[0216] 43d Operational Amplifier

[0217] 50 Shift register

[0218] 51 Counter

[0219] 52 Pseudo-random number sequence generator

[0220] 53, 58 Inverter

[0221] 54 Target value setting circuit

[0222] 55ΔΣ Modulator

[0223] 56Y-axis selection circuit

[0224] 57 Selector

[0225] Q1~Q16 diode characteristic element (bipolar transistor)

[0226] S1~S16、S20~S23、S25~S29、T1~T16 switches

Claims

1. A bandgap reference circuit, characterized in that: have: A diode characteristic element group, consisting of a plurality of diode characteristic elements; The dynamic element matching circuit performs the following operation in a certain period, namely, repeatedly selecting a first diode characteristic element group consisting of a parallel connection of the M diode characteristic elements and a second diode characteristic element group consisting of a parallel connection of the N diode characteristic elements from the diode characteristic element group while changing a combination of the M diode characteristic elements to be selected, wherein the M is an integer greater than 1, and the N is an integer greater than 2 and greater than the M. a reference voltage generating circuit for generating a reference voltage based on a difference between a current density of a current flowing through the first diode characteristic element group and a current density of a current flowing through the second diode characteristic element group; as well as The secondary temperature coefficient adjustment circuit adjusts the secondary temperature coefficient of the reference voltage generated by the reference voltage generation circuit.

2. The bandgap reference circuit according to claim 1, wherein: The invention further includes a primary temperature coefficient adjustment circuit for adjusting the primary temperature coefficient of the reference voltage generated by the reference voltage generation circuit.

3. The bandgap reference circuit according to claim 1 or 2, characterized in that: The sum of the above M and the above N is a power of 2.

4. The bandgap reference circuit according to any one of claims 1 to 3, characterized in that: The dynamic element matching circuit selects the first diode characteristic element group and the second diode characteristic element group so that the ratio of the M to the N becomes the same value in each of the repeated operations.

5. The bandgap reference circuit according to any one of claims 1 to 4, characterized in that: The dynamic element matching circuit selects the first diode characteristic element group and the second diode characteristic element group so that whichever of the diode characteristic elements is selected, the number of times selected as the first diode characteristic element group and the second diode characteristic element group in the certain period becomes the same value.

6. The bandgap reference circuit according to any one of claims 1 to 5, characterized in that: The diode characteristic element group is arranged on a substrate; The above-mentioned dynamic element matching circuit selects the above-mentioned first diode characteristic element group and the above-mentioned second diode characteristic element group so that in the planar observation of the above-mentioned substrate, the configuration positions of the above-mentioned M diode characteristic elements on the above-mentioned substrate are point-symmetrical, and the configuration positions of the above-mentioned N diode characteristic elements on the above-mentioned substrate are point-symmetrical.

7. The bandgap reference circuit according to any one of claims 1 to 5, characterized in that: During the repetition, the dynamic element matching circuit selects the first diode characteristic element group and the second diode characteristic element group so that the M diode characteristic elements are switched randomly and the N diode characteristic elements are switched randomly.

8. The bandgap reference circuit according to any one of claims 1 to 5, characterized in that: During the repetition, the dynamic element matching circuit selects the first diode characteristic element group and the second diode characteristic element group so that the M diode characteristic elements are switched according to ΔΣ modulation and the N diode characteristic elements are switched according to ΔΣ modulation.

9. The bandgap reference circuit according to any one of claims 1 to 8, characterized in that: The diode characteristic element group is arranged on a substrate; The dynamic element matching circuit selects the first diode characteristic element group and the second diode characteristic element group based on diode characteristic elements other than diode characteristic elements located at the periphery of the diode characteristic element group in plan view of the substrate.

10. The bandgap reference circuit according to any one of claims 1 to 9, characterized in that: The above-mentioned dynamic element matching circuit performs the following action within a certain period, namely: while changing the combination of the above-mentioned M diode characteristic elements, the above-mentioned N diode characteristic elements and the at least one diode characteristic element that functions as the above-mentioned secondary temperature coefficient adjustment circuit to be selected, the action of repeatedly selecting at least one diode characteristic element that functions as the above-mentioned secondary temperature coefficient adjustment circuit from the above-mentioned diode characteristic element group in addition to the above-mentioned first diode characteristic element group and the above-mentioned second diode characteristic element group.

11. A bandgap reference circuit, characterized in that: have: a first current source and a second current source; a first diode characteristic element receiving a current supply from one of the first current source and the second current source; a second diode characteristic element which receives a current supply from the other of the first current source and the second current source and flows a current having a different current density from that of the first diode characteristic element; A reference voltage generating circuit generates a reference voltage based on the difference in current density; A primary temperature coefficient adjustment circuit, which adjusts the primary temperature coefficient of the reference voltage generated by the reference voltage generation circuit; A secondary temperature coefficient adjustment circuit, which adjusts the secondary temperature coefficient of the reference voltage generated by the reference voltage generation circuit; as well as The first switch circuit periodically switches between the first current source and the second current source to supply current to the first diode characteristic element and to supply current to the second diode characteristic element.

12. A bandgap reference circuit, characterized in that: have: a first current source and a second current source; a first diode characteristic element receiving a current supply from one of the first current source and the second current source; a second diode characteristic element which receives a current supply from the other of the first current source and the second current source and flows a current having a different current density from that of the first diode characteristic element; A reference voltage generating circuit generates a reference voltage based on the difference in current density; A primary temperature coefficient adjustment circuit, which adjusts the primary temperature coefficient of the reference voltage generated by the reference voltage generation circuit; as well as A secondary temperature coefficient adjustment circuit, which adjusts the secondary temperature coefficient of the reference voltage generated by the reference voltage generation circuit; The reference voltage generating circuit comprises: a differential amplifier having a first input terminal and a second input terminal to which a first voltage depending on a current density of a current flowing through the first diode characteristic element and a second voltage depending on a current density of a current flowing through the second diode characteristic element are input; and The second switch circuit periodically switches a voltage input to the first input terminal and a voltage input to the second input terminal between the first voltage and the second voltage.

13. The bandgap reference circuit according to claim 11 or 12, characterized in that: The invention also comprises a dynamic element matching circuit, which performs the following actions within a certain period, namely: while changing the combination of M diode characteristic elements and N diode characteristic elements to be selected, the invention repeatedly performs the actions of selecting a first diode characteristic element group consisting of the M diode characteristic elements connected in parallel as the first diode characteristic element from a diode characteristic element group consisting of a plurality of the diode characteristic elements, and selecting a second diode characteristic element group consisting of the N diode characteristic elements connected in parallel as the second diode characteristic element from the diode characteristic element group, wherein the M is an integer greater than 1 and the N is an integer greater than 1.

14. A semiconductor device, characterized in that: have: The bandgap reference circuit of claim 13; and A time-discrete filter receiving the reference voltage output from the bandgap reference circuit; The dynamic element matching circuit is synchronized with the clock signal and repeatedly performs the above actions; The time-discrete filter performs a time-discrete filtering process in synchronization with the clock signal.

15. A semiconductor device, characterized in that: have: The bandgap reference circuit of claim 13; and an averaging filter receiving the reference voltage output from the bandgap reference circuit; The dynamic element matching circuit is synchronized with the clock signal and repeatedly performs the above actions; The averaging filter performs averaging filtering in synchronization with the clock signal.

16. A semiconductor device, characterized in that: have: The bandgap reference circuit of claim 13; and An AD converter receives the reference voltage output from the bandgap reference circuit; The dynamic element matching circuit is synchronized with the clock signal and repeatedly performs the above actions; The AD converter converts the reference voltage into a digital signal in synchronization with the clock signal.

17. A semiconductor device, characterized in that: have: a first current source and a second current source; A diode characteristic element group, consisting of a plurality of diode characteristic elements; A dynamic element matching circuit that performs the following actions within a certain period, namely: while changing the combination of the M diode characteristic elements to be selected and the N diode characteristic elements to be selected, repeatedly performs the actions of selecting a first diode characteristic element group and a second diode characteristic element group from the diode characteristic element group, wherein the first diode characteristic element group is formed by connecting the M diode characteristic elements in parallel and receiving a current supply from one of the first current source and the second current source, and the second diode characteristic element group is formed by connecting the N diode characteristic elements in parallel and receiving a current supply from the other of the first current source and the second current source, wherein the M is an integer greater than 1, and the N is an integer greater than 2 that is greater than the M. a first switch circuit that periodically switches a current source that supplies current to the first diode characteristic element group and a current source that supplies current to the second diode characteristic element group between the first current source and the second current source; a reference voltage generating circuit that generates a reference voltage based on a difference between a current density of a current flowing through the first diode characteristic element group and a current density of a current flowing through the second diode characteristic element group, and includes a differential amplifier and a second switching circuit, wherein the differential amplifier has a first input terminal and a second input terminal, to which a first voltage dependent on a current density of a current flowing through the first diode characteristic element group and a second voltage dependent on a current density of a current flowing through the second diode characteristic element group are input, and the second switching circuit periodically switches the voltage input to the first input terminal and the voltage input to the second input terminal between the first voltage and the second voltage; A secondary temperature coefficient adjustment circuit, which adjusts the secondary temperature coefficient of the reference voltage generated by the reference voltage generation circuit; as well as an averaging filter receiving the reference voltage outputted from the reference voltage generating circuit; The averaging filter averages the reference voltage at a period that is a least common multiple of the certain period in the selection operation of the dynamic element matching circuit, the period in the operation of the first switch circuit, and the period in the operation of the second switch circuit.

Images