Supporting additive cryptography

Abstract

Systems and techniques for offloading encryption services are described herein. For example, a method may include receiving a request to provide an encrypted service type, and initiating an encryption algorithm in an encryption hardware component, where the encryption algorithm is associated with the encrypted service type. The method may also include applying the encryption operation to the data to obtain an encrypted result. The encryption operation is associated with an encryption algorithm. The method may also include storing at least a portion of the encryption result in a hardware register of the encryption hardware component. The encryption result is configured for performing an encryption action.

Description

Technical Field

[0001] In general, the present disclosure relates to encryption and decryption of data. In some examples, aspects of the present disclosure relate to systems and techniques for offloading certain aspects of integrity verification, authenticated encryption, and / or data decryption to cryptographic hardware components. Background Art

[0002] There are various scenarios where the integrity of data can be verified, or it is desirable to perform authenticated encryption and / or authenticated decryption on the data. Such operations are typically related to helping ensure that the data has not been altered, for example, before the computing device consumes or otherwise uses the data.

[0003] For example, integrity verification may be performed as part of a secure boot process to ensure the integrity of an image to be loaded, or to verify the integrity of data blocks storing all or any portion of a file system. As another example, authenticated encryption and decryption may be performed to provide data confidentiality and data integrity verification for runtime data. Such operations are typically performed using computing resources of a particular computing device (e.g., software executed on a processor) that are also used to perform other functions of the device. Therefore, such operations may adversely affect the performance characteristics of the device because integrity verification and / or authenticated encryption / decryption are performed using these computing resources of the device, which could otherwise be performing other operations. Summary of the invention

[0004] In some examples, systems and techniques for providing offload services are described. According to at least one illustrative example, a method of offloading cryptographic services is provided. The method includes: receiving a request to provide a cryptographic service type; launching a cryptographic algorithm in a cryptographic hardware component, wherein the cryptographic algorithm is associated with the cryptographic service type; applying a cryptographic operation to data to obtain a cryptographic result, wherein the cryptographic operation is associated with the cryptographic algorithm; and storing at least a portion of the cryptographic result in a hardware register of the cryptographic hardware component, wherein the cryptographic result is configured to perform a cryptographic action.

[0005] In another example, a device for offloading cryptographic services is provided, the device comprising at least one memory, at least one processor, and a cryptographic hardware component coupled to the at least one memory and the at least one processor. The cryptographic hardware component is configured to: receive a request to provide a type of cryptographic service; start a cryptographic algorithm in the cryptographic hardware component, wherein the cryptographic algorithm is associated with the type of cryptographic service; apply a cryptographic operation to data to obtain a cryptographic result, wherein the cryptographic operation is associated with the cryptographic algorithm; and store at least a portion of the cryptographic result in a hardware register of the cryptographic hardware component, wherein the cryptographic result is configured to perform a cryptographic action.

[0006] In another example, a non-transitory computer-readable medium having instructions stored thereon is provided, which, when executed by one or more processors, causes the one or more processors to perform the following operations: receive a request to provide a cryptographic service type; initiate a cryptographic algorithm in a cryptographic hardware component, wherein the cryptographic algorithm is associated with the cryptographic service type; apply a cryptographic operation to data to obtain a cryptographic result, wherein the cryptographic operation is associated with the cryptographic algorithm; and store at least a portion of the cryptographic result in a hardware register of the cryptographic hardware component, wherein the cryptographic result is configured to perform a cryptographic action.

[0007] In another example, a device for offloading cryptographic services is provided, the device comprising: a unit for receiving a request to provide a cryptographic service type; a unit for starting a cryptographic algorithm in a cryptographic hardware component, wherein the cryptographic algorithm is associated with the cryptographic service type; a unit for applying a cryptographic operation to data to obtain a cryptographic result, wherein the cryptographic operation is associated with the cryptographic algorithm; and a unit for storing at least a portion of the cryptographic result in a hardware register of the cryptographic hardware component, wherein the cryptographic result is configured to perform a cryptographic action.

[0008] In some aspects, one or more of the devices described herein are, are part of, and / or include a mobile device or wireless communication device (e.g., a mobile phone or other mobile device), an extended reality (XR) device or system (e.g., a virtual reality (VR) device, an augmented reality (AR) device, or a mixed reality (MR) device), a wearable device (e.g., a connected watch or other wearable device), a vehicle or computing device or a component of a vehicle, a camera, a personal computer, a laptop, a server computer or server device (e.g., an edge or cloud-based server, a personal computer acting as a server device, a mobile device acting as a server device (e.g., a mobile phone), an XR device acting as a server device, a vehicle used as a server device, a network router, or other device acting as a server device), any combination thereof, and / or other types of devices. In some aspects, these devices include a camera or multiple cameras for capturing one or more images. In some aspects, these devices include a display for displaying one or more images, notifications, and / or other displayable data. In some aspects, these devices include one or more sensors (e.g., one or more inertial measurement units (IMUs) such as one or more gyroscopes, one or more gyroscopes, one or more accelerometers, any combination thereof, and / or other sensors).

[0009] This summary is neither intended to identify key or essential features of the claimed subject matter nor is it intended to be used alone to determine the scope of the claimed subject matter. The subject matter should be understood by reference to appropriate portions of the entire specification of this patent, any or all drawings, and each claim.

[0010] The foregoing, together with other features and examples, will become more apparent with reference to the following description, claims and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The following is a detailed description of an illustrative example of the present application with reference to the accompanying drawings:

[0012] Figure 1 is a block diagram illustrating a computing device according to some examples.

[0013] Figure 2 is a block diagram illustrating cryptographic hardware components according to some examples.

[0014] Figure 3 is a flow chart illustrating an example process for offloading integrity verification for data, according to some examples;

[0015] Figure 4 is a flow chart illustrating an example process for offloading authenticated encryption, according to some examples;

[0016] Figure 5 is a flow chart illustrating another example process for offloading authenticated encryption, according to some examples;

[0017] Figure 6 is a flow chart illustrating an example process for offloading authentication decryption, according to some examples;

[0018] Figure 7 is a flow chart illustrating an example process for uninstalling decryption of a software image encrypted on another device, according to some examples;

[0019] Figure 8 is a flow chart illustrating an example process for uninstalling decryption of a software image encrypted on another device, according to some examples; and

[0020] Fig. 9 is a diagram of an example computing system for implementing certain aspects described herein. DETAILED DESCRIPTION

[0021] Certain aspects and examples of the present disclosure are provided below. It is obvious to those of ordinary skill in the art that some of these aspects and examples can be applied independently, and some of them can be applied in combination. In the following description, for ease of explanation, specific details are set forth in order to provide a thorough understanding of the examples of the present application. However, it is obvious that each example can be practiced without these specific details. The drawings and description are not intended to be restrictive. In addition, certain details known to those of ordinary skill in the art can be omitted to avoid confusion in the description.

[0022] In the following description of the drawings, in the various examples described herein, any component described for one drawing may be equivalent to one or more similarly named components described for any other drawing. For the sake of brevity, the description of these components may not be completely repeated for each drawing. Therefore, each and every example of the components of each drawing is combined together by reference, and it is assumed that it is optionally present in each other drawing with one or more similarly named components. In addition, according to the various examples described herein, any description of the components of the drawings will be interpreted as optional examples, and these components can be implemented in addition to, in combination with, or in place of the examples described for the corresponding similarly named components in any other drawings.

[0023] The following description provides only exemplary examples and is not intended to limit the scope, applicability or configuration of the present disclosure. On the contrary, the following description of the exemplary examples will provide an enabling description for implementing the exemplary examples to those of ordinary skill in the art. It should be understood that various changes may be made to the functions and arrangements of the constituent elements without departing from the spirit and scope of the present application as set forth in the appended claims.

[0024] Computing devices such as mobile devices may include various types of storage devices (e.g., flash memory). Such storage devices are typically used to store data. To help ensure device security, all or any portion of the data may be subject to various encryption techniques, such as encrypting sensitive data and decrypting the data when needed. To support encryption and decryption of data, the computing device may include an interface (e.g., a host controller interface) for providing an interface between the storage device and other components of the computing device. The interface may be configured to comply with certain standards (e.g., the Joint Electron Device Engineering Council (JEDEC) Universal Flash Host Controller Interface (UFSHCI) standard and / or other standards) that are designed to provide general techniques for implementing various functions associated with storage devices, such as encrypting and decrypting data stored on the storage device. Therefore, components in the data path between the storage device and other components of the computing device (e.g., memory) are typically designed to comply with such standards.

[0025] An example of a component in a data path between a storage device and other components of a computing device may be a cryptographic hardware component. In some examples, the cryptographic hardware component is a hardware component that is separate from one or more processors of the computing device and that provides inline cryptographic services for data passed to or from a storage device of the computing device, thereby offloading at least a portion of the cryptographic services from one or more processors of the computing device, which allows the processors to perform other operations. This offloading may improve the performance of the computing device because it allows one or more processors of the computing device to perform other operations.

[0026] In order to further improve the performance of computing devices, systems and techniques are needed to offload additional cryptographic operations from one or more processors of the computing device to cryptographic hardware components of the computing device. However, if an interface standard (e.g., JEDEC, etc.) lacks support for certain cryptographic algorithms, such cryptographic hardware components that comply with the standard may not allow such additional offloading of cryptographic techniques.

[0027] Systems, apparatus, processes (also referred to as methods), and computer-readable media (collectively referred to herein as "systems and techniques") for offloading one or more cryptographic techniques to cryptographic hardware components are described herein. In one illustrative example, one or more additional cryptographic techniques or services may include integrity verification. Integrity verification is a technique for determining whether stored data has been altered in an unauthorized or unexpected manner. As an example, integrity verification may be performed during a secure boot process to verify the integrity of an image (e.g., an operating system image, a software image, etc.) being loaded (e.g., into a memory). If the integrity is verified, the image or a portion of the image may be loaded. If the integrity cannot be verified, the image may not be loaded. As another example, techniques such as using a Merkle tree (which may be referred to as a hash tree) may be performed to verify the integrity of a stored block of data before the data is moved from a storage device to a memory, where the computing device uses the data at the memory (e.g., using a processor of the computing device for operation).

[0028] In some examples, integrity verification includes using a hash algorithm (e.g., a secure hash algorithm (SHA)). Such an algorithm operates on input data to produce an output, which can be referred to as a digest. In some examples, the generated digest can be referred to as an encryption result. The digest can be a fixed size (e.g., a fixed number of bits), regardless of the size of the data on which the hash algorithm operates. The probability that the digest generated by the hash algorithm for a given data item is the same as the digest generated using any other data as input to the hash algorithm is very low. Therefore, under the realistic constraints of time, computing resources, and various potential input data, the digest corresponding to the data can be considered to be unique to the data. In some examples, using a hash algorithm to generate a digest for the data allows the digest to be compared with a previously generated digest for the data, where a match indicates passing the integrity check (e.g., verifying the integrity of the data). Performing such a comparison can be an example of performing an encryption action using an encryption result.

[0029] One or more encryption techniques or services may additionally or alternatively include authenticated encryption and authenticated decryption (collectively referred to as authenticated encryption). In some examples, authenticated encryption is a technique that ensures data confidentiality and authenticity. Authenticated encryption can be performed using an authenticated encryption algorithm (e.g., Advanced Encryption Standard Galois / Counter Mode (AES-GCM)). In some examples, when authenticated encryption of data is performed using an authenticated encryption algorithm, encrypted data and a message authentication code (MAC) corresponding to the encrypted data (or plaintext data) are generated as output. In some examples, MAC may be referred to as an encryption result. In some examples, MAC may be stored in one or more registers of an encryption hardware component and may be stored in other storage devices of a computing device in addition or alternatively. In some examples, storing MAC in an encryption hardware component and / or other storage device of a computing device may be an example of performing an encryption action using an encryption result. In some examples, when authenticated decryption is performed using an authenticated encryption algorithm, encrypted data (or plaintext data) is used to generate a MAC (e.g., an encryption result), which is then compared with a MAC previously generated for the data. In some examples, comparing MAC with a previously generated MAC may be an example of performing an encryption action using an encryption result. If the MACs match, the data can be considered authenticated (e.g., the authentication check passed). If the MACs do not match, the data is unauthenticated (e.g., the authentication check failed). Authenticated encryption can be used for any data that requires both encryption and authentication. For example, when a computing device is to be put into hibernation (e.g., suspended), system state information from a memory of the computing device can be used as input to an authenticated encryption algorithm so that the system state information is encrypted before being written to the storage device, and a MAC corresponding to the encrypted system state information is generated. Later, when the computing device is to be taken out of hibernation (e.g., resumed), the authenticated encryption algorithm is used again to generate a MAC and the data is decrypted. The MAC generated during the decryption process can be compared to the MAC generated during the encryption process to ensure the authenticity of the system state information.

[0030] In some examples, providing integrity verification or authenticated encryption using a processor of a computing device requires processor cycles (which could otherwise be used to perform other operations), thereby reducing performance of the device. Accordingly, examples described herein provide a cryptographic hardware component that is configured to perform integrity verification or authenticated encryption, thereby at least partially offloading services from a processor of a computing device. Using such a cryptographic hardware component to perform integrity verification or authenticated encryption can improve performance of a computing device (e.g., by improving the time it takes to perform a secure boot, improving the time it takes to resume a device from a hibernation state, allowing a processor of the computing device to perform other operations while generating a data block digest, etc.).

[0031] In some examples, the cryptographic hardware component is configured to perform an integrity verification algorithm (e.g., a SHA algorithm family) and an authenticated encryption algorithm (e.g., AES-GCM), and can be expanded to include hardware registers for storing at least a portion of the output of such an algorithm. In some examples, for the integrity verification algorithm, the cryptographic hardware component includes: a hardware register for storing a digest corresponding to the data whose integrity is being verified, and one or more error registers for storing an indication of a failure of the integrity check. In some examples, for the authenticated encryption algorithm, the cryptographic hardware component includes: a hardware register for storing a MAC corresponding to the data being encrypted or decrypted, and one or more error registers for storing an indication of a failure of the authentication check. In some examples, support for related cryptographic algorithms (e.g., SHA, AES-GCM, etc.) is added to a storage interface standard (e.g., JEDEC, etc.) to facilitate offloading integrity verification and authenticated encryption to the cryptographic hardware component while maintaining compliance with the standard. For example, when implementing one or more examples described herein (e.g., data from a storage device is processed by a cryptographic hardware component), support for one or more cryptographic algorithms (e.g., AES-GCM, SHA, etc.) can be added to the JDEC specification.

[0032] In some aspects, one or more encryption services may additionally or alternatively include: providing inline decryption of data (e.g., software images) that has been encrypted (e.g., encrypted on another computing device) before the data is stored on a storage device of the computing device. For example, the software image may be encrypted using an encryption algorithm (e.g., AES-CBC, etc.) executed at a remote computing device. The encrypted software image may then be sent to the computing device and stored on a storage device (e.g., UFS device, etc.) of the computing device. In order to use the software image, the software image must be decrypted. However, decrypting the software image may require an encryption key and, in some cases, an initialization vector (IV). Therefore, decrypting the software image may require moving the encrypted software image from the storage device to the memory device, where one or more processors execute the encryption algorithm to decrypt the data. Execution of the encryption algorithm may include generating an IV (e.g., using a sequence number (SN) of a particular data block). Decrypting the encrypted software image in this manner consumes computing resources (e.g., processor cycles) of the computing device, which otherwise could be used, for example, for other operations.

[0033] The examples described herein address the use of such computing resources by offloading decryption to a hardware encryption component that provides inline decryption of encrypted software image data before loading the decrypted data into the memory of a computing device. Specifically, the encryption hardware component may include: one or more hardware storage components for storing data items to perform inline decryption. For example, an encryption key and IV for encrypting data may be obtained from a device that encrypts the data, and the encryption hardware component may store this information, thereby allowing the encryption hardware component to perform inline decryption of the data before transferring the decrypted data to the memory of the computing device. This can eliminate the need to use other computing resources (e.g., one or more processors) to decrypt the data after moving the data to the memory in encrypted form. Obtaining the decrypted data may be referred to as obtaining an encryption result. Transferring the decrypted data to the memory may be referred to as performing an encryption action using the encryption result.

[0034] Various aspects of the technology described herein will be discussed below with reference to the accompanying figures. Figure 1 1 is a block diagram illustrating an example of a computing device 100. As shown in the figure, computing device 100 includes a processor 102, a universal flash storage (UFS) device 104, an encryption hardware component 106, a memory device 108, and an additional storage device 110. Each of these components will be described below.

[0035] Computing device 100 is any device, part of a device, or any collection of devices capable of processing instructions electronically, and computing device 100 may include, but is not limited to, any of the following: one or more processors (e.g., components including integrated circuits, such as processor 102), memory (e.g., memory device 108), input and output devices (not shown), non-volatile storage hardware (e.g., UFS device 104, additional storage device 110), one or more physical interfaces, any number of other hardware components (not shown), and / or any combination thereof. Examples of computing devices include, but are not limited to, mobile devices (e.g., laptops, smartphones, personal digital assistants, tablet computers, automotive computing systems, and / or any other mobile computing devices), Internet of Things (IoT) devices, servers (e.g., blade servers in blade server chassis, rack-mounted servers in racks, etc.), desktop computers, storage devices (e.g., disk drive arrays, Fibre Channel storage devices, Internet Small Computer System Interface (iSCSI) storage devices, tape storage devices, flash arrays, network-attached storage devices, etc.), network devices (e.g., switches, routers, multi-layer switches, etc.), wearable devices (e.g., VR headsets, AR headsets, AR glasses, network-connected watches or smart watches, or other wearable devices), robotic devices, televisions, and / or any other type of computing device having the above requirements. In one or more examples, any or all of the above examples may be combined to create a system of such devices, which may be collectively referred to as computing devices. Other types of computing devices may be used without departing from the scope of the examples described herein.

[0036] In some examples, the processor 102 is any component that includes a circuit for executing instructions (e.g., a computer program). For example, such a circuit can be an integrated circuit implemented at least in part using transistors, where the transistors implement components such as arithmetic logic units, control units, logic gates, registers, and the like. In some examples, the processor may include additional components, such as cache memory. In some examples, the processor retrieves and decodes instructions and then executes them. The execution of instructions may include: operating on data, which may include reading and / or writing data. In some examples, the instructions and data used by the processor are stored in a memory (e.g., a memory device 108) of the computing device 100. The processor may perform various operations for executing software such as an operating system, an application, and the like. The processor 102 may cause data to be written from a memory to a storage device of the computing device 100, and / or cause data to be read from a storage device via a memory. Examples of processors include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit, a tensor processing unit, a data processing unit (DPU), a digital signal processor (DSP), and the like. The processor 102 can be operatively connected to the memory device 108, as well as any storage devices of the computing device 100 (e.g., the UFS device 104, the additional storage device 110). As used herein, the phrase operatively connected or operably connected means that there is a direct or indirect connection between elements / components / devices that allows these elements to interact in some manner. For example, the phrase 'operatively connected' can refer to any direct connection (e.g., a direct wired connection between two devices or components) or indirect connection (e.g., a wired and / or wireless connection between any number of devices or components that connect operatively connected devices). Thus, any path through which information can travel can be considered an operative connection. Although Figure 1 Computing device 100 is shown with one processor 102 , but a computing device may have any number of processors without departing from the scope of the examples described herein.

[0037] In some examples, computing device 100 includes UFS device 104. In some examples, UFS device 104 is a flash memory device that complies with the UFS specification. UFS device 104 can be used to store any type of data. Data can be written to UFS device 104, and / or data can be read from UFS device 104. For example, a UFS device can store operating system images, software images, application data, and so on. UFS device 104 can store any other type of data without departing from the scope of protection of the examples described herein. In some examples, UFS device 104 includes NAND flash memory. UFS device 104 can use any other type of storage technology without departing from the scope of protection of the examples described herein. In some examples, UFS device 104 is capable of having a relatively faster data rate than an attached storage device (e.g., other storage device 110) of computing device 100. UFS device 104 can be operably connected to processor 102, encryption hardware component 106, memory device 108, and / or attached storage device 110. Although Figure 1 The computing device 100 is shown with a single UFS device 104, but the computing device may include any number of UFS devices without departing from the scope of the examples described herein. Figure 1 A UFS device 104 is shown, but the computing device 100 may include any other type of flash memory device without departing from the scope of the examples described herein.

[0038] In some examples, computing device 100 includes additional storage device 110. In some examples, additional storage device is a non-volatile storage device. Additional storage device 110 may be, for example, a persistent memory device. In some examples, additional storage device 110 may be any type of computer storage device. Examples of types of computer storage devices include, but are not limited to, hard drives, solid-state drives, flash memory, tape drives, removable disk drives, universal serial bus (USB) storage devices, secure digital (SD) cards, optical storage devices, read-only memory devices, and the like. Although Figure 1 Additional storage device 110 is shown as part of computing device 100, but the additional storage device can be separate from computing device 100 and operatively connected to computing device 100 (e.g., an external drive array, cloud storage, etc.). In some examples, additional storage device 110 operates at a relatively slower data rate than UFS device 104. In some examples, additional storage device 110 is also a UFS storage device. In some examples, additional storage device 110 is operatively connected to processor 102, UFS device 104, cryptographic hardware component 106, and / or memory device 108. Although Figure 1Computing device 100 is shown with a single attached storage device 110 , but computing device 100 may have any number of attached storage devices without departing from the scope of the examples described herein.

[0039] In some examples, computing device 100 includes a memory device 108. The memory device can be any type of computer memory. In some examples, memory device 108 is a volatile memory device. As an example, memory device 108 can be a random access memory (RAM). In one or more examples, data stored in memory device 108 is located at a memory address, and thus processor 102 can use the memory address to access the data. Similarly, processor 102 can use the memory address to write data to memory device 108. Memory device 108 can be used to store any type of data, such as computer programs, calculation results, and so on. In some examples, memory device 108 can be operatively connected to processor 102, UFS device 104, additional storage device 110, and / or encryption hardware component 106. Although Figure 1 The computing device 100 is shown with a single memory device 108 , but the computing device 100 may have any number of memory devices without departing from the scope of the examples described herein.

[0040] In some examples, computing device 100 includes cryptographic hardware component 106. The cryptographic hardware component can be any hardware component capable of performing various cryptographic services. In some examples, cryptographic hardware component 106 is a sub-chip hardware component of a system on a chip (SoC), which may include Figure 1100 ) and the other components shown in . Any other components of the computing device 100 may also be included as part of the SoC without departing from the scope of protection of the examples described herein. In some examples, the encryption hardware component 106 is present in the data path between the storage device (e.g., UFS storage device 104, attached storage device 110) and the memory device 108. In this way, the encryption hardware component 106 can be considered to be an "inline" encryption hardware component. In some examples, the encryption hardware component 106 is configured to perform various types of encryption services on data read or written from the storage device (e.g., UFS device 104, attached storage device 110) of the computing device 100. In some examples, all data from the memory of the computing device 100 to the storage device or from the storage device to the memory passes through the encryption hardware component 106. In other examples, only a portion of the data transferred from the memory of the computing device 100 to the storage device or from the storage device to the memory passes through the encryption hardware component 106. In some examples, the encryption hardware component is designed and configured to comply with one or more relevant industry standards (e.g., JEDEC). When implementing one or more of the examples described herein, support for one or more encryption algorithms (eg, AES-GCM, SHA, etc.) may be added to the JDEC specification.

[0041] Examples of the types of cryptographic services that can be performed include, but are not limited to: encrypting data, decrypting data, performing data integrity verification, and performing authenticated encryption and decryption. In some examples, the cryptographic hardware component 106 is configured to perform various types of cryptographic services by being configured to execute one or more cryptographic algorithms. As an example, in order to perform encryption and decryption, the cryptographic hardware component 106 can be configured to execute one or more of the following algorithms: Advanced Encryption Standard XOR Encryption XOR Adjustable Block Ciphertext Stealing (AES-XTS) algorithm, AES Encryption Block Chaining (AES-CBC) algorithm, AES Electronic Codebook (AES-EBC) algorithm, Encryption Salt Sector Initialization Vector AES-CBC (ESSIV-AES-CBC) algorithm, etc., and include any variants of such algorithms (e.g., 128, 192, 256, etc.). As another example, in order to perform integrity verification, the cryptographic hardware component 106 can be configured to execute a hash algorithm (e.g., one or more members of the SHA hash algorithm family). As another example, in order to perform authenticated encryption, the cryptographic hardware component 106 can be configured to execute the AES-GCM algorithm. The cryptographic hardware component 106 may be configured to perform any other cryptographic algorithm without departing from the scope of the examples described herein. In some examples, the cryptographic hardware component 106 is operatively connected to one or more storage devices (e.g., UFS device 104, additional storage device 110) and memory device 108 of the computing device 100. Figure 1 The computing device 100 is shown as having a single cryptographic hardware component 106, but the computing device 100 may have any number of cryptographic hardware components without departing from the scope of the examples described herein. Figure 2 The cryptographic hardware components are further discussed in the description of .

[0042] Although Figure 1 A specific number of components of a specific configuration is shown, but one of ordinary skill in the art will appreciate that the computing device 100 may include more components or fewer components, and / or components arranged in any number of alternative configurations without departing from the scope of the examples described herein. Figure 1 Although not shown in the figure, it should be understood by those skilled in the art that when powered on, the computing device 100 can execute any number or type of software or firmware (e.g., boot program, operating system, hypervisor, virtual machine, computer application, mobile device application, etc.). Therefore, the examples disclosed herein should not be limited to Figure 1 Configuration of the components shown in .

[0043] Figure 2 A block diagram of an encryption hardware component is shown. In some examples, the encryption hardware component 200 and Figure 1 The same as the cryptographic hardware component 106 shown in and described above. Figure 2 As shown in FIG. 1 , cryptographic hardware component 200 includes a data receiver 202, an algorithm execution device 204, a data transmitter 206, an algorithm result register 208, an error register 210, an encryption key storage device 212, and a sequence number (SN) / initialization vector (IV) storage device 214. Each of these components will be described below.

[0044] As above Figure 1 As discussed in the description of , the cryptographic hardware component 200 is a hardware component present in the data path between one or more storage devices of the computing device and one or more memory devices of the computing device. In some examples, the cryptographic hardware component is a sub-chip of the SoC. In some examples, the cryptographic hardware component 200 is configured to provide various types of cryptographic services to data passed between the memory and storage devices of the computing device through the cryptographic hardware component 200.

[0045] In some examples, the cryptographic hardware component 200 includes a data receiver 202. The data receiver 202 can be any component capable of receiving data from other components of the computing device (e.g., a storage device and / or a memory device). As one example, the data receiver 202 can be a first-in-first-out (FIFO) buffer. In some examples, the data receiver 202 is configured to perform direct memory access (DMA). In some examples, the data receiver 202 is configured to receive data (e.g., from a memory or storage device) and provide the received data to an operatively connected algorithm execution device (discussed below). Although Figure 2 A cryptographic hardware component is shown having a single data receiver 202 , but the cryptographic hardware component may include any number of data receivers without departing from the scope of the examples described herein.

[0046] In some examples, the cryptographic hardware component 200 includes an algorithm execution device 204. The algorithm execution device 204 may be any component or component set configured to execute one or more cryptographic algorithms. For example, the algorithm execution device 204 may include a separate circuit configured to execute one or more cryptographic algorithms, respectively. For another example, the algorithm execution device 204 may include a reconfigurable circuit (e.g., a field programmable gate array (FPGA)) that can be configured to execute one or more cryptographic algorithms. In some examples, the algorithm execution device 204 is configured to provide encryption and decryption of data by executing any number of algorithms (e.g., AES-XTS, AES-ECB, AES-CBC, ESSIV-AES-CBC, etc.). In some examples, the algorithm execution device 204 is configured to provide integrity verification via the execution of a hash algorithm (e.g., one or more members of the SHA family of hash algorithms). In some examples, the algorithm execution device 204 is configured to provide authenticated encryption and / or decryption services via the execution of one or more authenticated encryption algorithms (e.g., AES-GCM). In some examples, the algorithm execution device 204 is operatively connected to the data receiver 202 , the data transmitter 206 , the algorithm result register 208 , the error register 210 , and the encryption key storage device 212 .

[0047] In some examples, the algorithm execution device 204 is configured to perform a hash function (e.g., a hash function of the SHA family) cryptographic service type as part of an integrity verification of data (e.g., during a secure boot process). In some examples, performing the hash algorithm includes receiving data (e.g., from the data receiver 202) as input and applying a mathematical hash function to the data to obtain an output of a fixed-length digest, which can then be stored in one or more algorithm result registers 208 (discussed below) of the cryptographic hardware component 200. As an example, the data receiver 202 can retrieve the digest from a storage device (e.g., a storage device) during a secure boot process. Figure 1 The image data is obtained by using the UFS device 104 shown in FIG. 1 , which data or any portion thereof may be used as an input to a hash function, and an output digest of the hash function may be stored in one or more of the algorithm result registers 208 of the cryptographic hardware component 200 .

[0048] In some examples, the digest generated during the integrity verification can be referred to as a cryptographic result. In some examples, in order to verify the integrity of the data, the digest generated by the hash algorithm and stored in the algorithm result register 208 of the cryptographic hardware component 200 is compared with the previously generated data digest to determine whether the digest and the previously generated digest match. The previously generated digest can be obtained from any suitable location (e.g., it is stored in a hash table associated with the data, stored in another storage device of the computing device, etc.). In one or more examples, the comparison of the digest with the previously generated digest is performed by a component of the cryptographic hardware component 200. Alternatively, the comparison can be performed by another component of the computing device (e.g., a processor). In some examples, performing such a comparison can be referred to as performing a cryptographic action. In some examples, if the digest and the previously generated digest match, the integrity check of the data corresponding to the digest is passed, which at least indicates that a partial integrity check has passed. In some examples, if the digest and the previously generated digest do not match, the integrity check fails. In some examples, in the event of a failure of the integrity check, at least one of the error registers 210 (discussed below) is updated with an indication of the failure.

[0049] In some examples, the algorithm execution device 204 is configured to perform an authenticated encryption algorithm (e.g., AES-GCM) encryption service type when performing authenticated encryption (e.g., during a hibernation / suspend process) or authenticated decryption (e.g., during resumption from a hibernation / suspend process).

[0050] In some examples, executing an authenticated encryption algorithm when performing authenticated encryption may include: receiving data (e.g., from data receiver 202) as input to the authenticated encryption algorithm, and executing the authenticated encryption algorithm to obtain encrypted data and a MAC corresponding to the data. The encryption and generation of the MAC may be performed in any number of ways. For example, the input plaintext data may be encrypted, and then a hash function may be applied to the encrypted data to obtain a MAC corresponding to the encrypted data. For another example, a MAC may be generated by applying a hash function to plaintext data, and then the plaintext data may be encrypted. For another example, a MAC may be generated by applying a hash function to plaintext data, and then encrypting a combination of the plaintext data and the MAC. In some examples, the MAC is stored in one or more algorithm result registers 208 of the encryption hardware component 200. In some examples, the plaintext data to be encrypted is obtained from a memory device (e.g., RAM) of a computing device, and the encrypted data output from the authenticated encryption algorithm is stored in a storage device (e.g., a UFS device).

[0051] In some examples, executing an authenticated encryption algorithm while performing authenticated decryption may include receiving encrypted data (e.g., from data receiver 202) as input to the authenticated encryption algorithm, and executing the authenticated encryption algorithm to obtain decrypted plaintext data and a MAC corresponding to the data. In some examples, decryption and generation of the MAC are performed in a manner consistent with the manner in which the data was encrypted and the MAC was previously generated. For example, if the MAC was created using encrypted data, then during decryption, the MAC is generated again based on the received encrypted data before the data is decrypted to obtain the plaintext data. In some examples, the MAC generated during authenticated decryption is stored in an algorithm result register 208 of the cryptographic hardware component. In some examples, the MAC generated during authenticated decryption is stored in an algorithm result register 208 of the cryptographic hardware component. In some examples, the MAC is stored in an algorithm result register 208 of the cryptographic hardware component from a storage device (e.g., Figure 1 The encrypted data is obtained by the UFS storage device 104 shown in FIG. 1 and the decrypted plaintext data output from the authentication encryption algorithm is transmitted to the memory device of the computing device (eg, Figure 1 Memory device 108 shown).

[0052] In some examples, the MAC generated during the authenticated encryption and the encrypted data can be referred to as the encryption result and stored in the algorithm result register 208. The MAC can then be transferred to other storage devices (e.g., persistent memory) for later comparison during the authenticated decryption. In some examples, storing the MAC in a register and / or other storage device can be referred to as performing an encryption action. In some examples, the MAC generated by the authenticated decryption and the decrypted data can be referred to as the encryption result. In some examples, in order to verify the authenticity of the data, the MAC generated by the authenticated encryption algorithm during the authenticated decryption process and stored in the algorithm result register 208 of the encryption hardware component 200 is compared with the MAC previously generated for the data during the authenticated encryption process. The previously generated MAC can be obtained from any appropriate location (e.g., it is stored in another storage device of the computing device, etc.). In one or more examples, the comparison of the MAC and the previously generated MAC is performed by a component of the encryption hardware component 200. Alternatively, the comparison can be performed by another component of the computing device (e.g., a processor). In some examples, obtaining the previously generated MAC and performing the comparison can be referred to as performing an encryption action. In some examples, if the MAC matches a previously generated MAC, then the authenticity check of the data corresponding to the MAC passes, which indicates that at least part of the authentication check passes. In some examples, if the MAC does not match a previously generated MAC, then the authentication check fails. In some examples, in the event that the authentication check fails, at least one of the error registers 210 (discussed below) is updated with an indication of the failure.

[0053] In some examples, the cryptographic hardware component 200 is requested to perform a cryptographic service type (e.g., integrity verification, authenticated encryption, authenticated decryption, etc.). The request can be received from any appropriate entity. As one example, the request can be received from a boot loader during a secure boot process. As another example, the request can be received from an operating system or other component or application when the computing device is to be suspended into a sleep state or resumed from a sleep state. The request can be received in other ways (e.g., from an application, based on receiving data of a particular type or in a particular state, etc.). In some examples, the request determines (e.g., specifies) which cryptographic service algorithm the algorithm execution device 204 executes. Although Figure 1 The cryptographic hardware component 200 is shown to include a single algorithm execution device 204, but the cryptographic hardware component may include any number of algorithm execution devices without departing from the scope of the examples described herein.

[0054] In some examples, the cryptographic hardware component 200 includes a cryptographic key storage device 212. The cryptographic key storage device 212 can be any type of storage device (see above). Figure 1 ). The encryption key storage device 212 may be a single storage device, or may be any number of independent storage components. In some examples, the encryption key storage device 212 is configured to store one or more encryption keys to be used when executing an authenticated encryption algorithm during authenticated encryption, authenticated decryption, and / or any other encryption service type. The encryption key storage device 212 may store any number of encryption keys, and each key may have any length (e.g., 128 bits, 256 bits, 512 bits, etc.). In some examples, the encryption key storage device 212 is operatively connected to the algorithm execution device 204.

[0055] In some examples, the cryptographic hardware component 200 includes an SN / IV storage device 214. The SN / IV storage device 214 may be any type of storage device (see above). Figure 1 ). The SN / IV storage device 214 may be a single storage device, or may be any number of independent storage components. In some examples, the SN / IV storage device 214 is configured to store one or more SNs (e.g., for performing inline encryption services) and / or one or more IVs (e.g., when performing inline decryption services). The SN / IV storage device 214 may store any number of SNs and / or IVs. Any technique may be used to obtain such SNs and IVs. For example, an IV corresponding to an encrypted software image stored in a storage device of a computing device may be received from a separate device that encrypts the software image. In some examples, the SN / IV storage device 214 is operatively connected to the algorithm execution device 204.

[0056] In some examples, the cryptographic hardware component 200 includes a data transmitter 206. The data transmitter 206 can be any component capable of receiving data from the algorithm execution device 204 and / or from the algorithm result register 208. As an example, the data transmitter 206 can be a first-in-first-out (FIFO) buffer. In some examples, the data transmitter 206 is configured to perform direct memory access (DMA). In some examples, the data transmitter 206 is configured to receive encrypted data to a storage device (e.g., a UFS storage device), to transfer decrypted data to a memory device (e.g., RAM), and / or to transfer encryption results (e.g., MAC, digest, etc.) to another component of the computing device (e.g., an attached storage device). In some examples, the data transmitter 206 is operatively connected to the algorithm execution device 204 and / or the algorithm result register 208. Although Figure 2 A cryptographic hardware component is shown having a single data transmitter 206, but the cryptographic hardware component may include any number of data transmitters without departing from the scope of the examples described herein.

[0057] In some examples, the cryptographic hardware component 200 includes any number of algorithm result registers 208. The algorithm result register 208 can be a hardware register for storing at least a portion of the cryptographic result (e.g., a digest, a MAC, etc.). The algorithm result register 208 can be configured to store data of any size (e.g., 128 bits, 256 bits, 512 bits, 1024 bits, 16 bytes, etc.). In some examples, the algorithm result register 208 is operatively connected to the algorithm execution device 204 and / or the data transmitter 206.

[0058] In some examples, the cryptographic hardware component 200 includes any number of error registers 210. The error register 210 can be a hardware register for storing an indication of an integrity check failure or an authentication check failure. The error register 210 can have any size (e.g., 8 bits, 16 bits, etc.). In some examples, the error register 210 is operatively connected to the algorithm execution device 204.

[0059] Although Figure 2 A specific number of components of a specific configuration are shown, but one of ordinary skill in the art will appreciate that the cryptographic hardware component 200 may include more components or fewer components, and / or components arranged in any number of alternative configurations without departing from the scope of the examples described herein. Therefore, the examples disclosed herein should not be limited to Figure 1 Configuration of the components shown in .

[0060] As discussed above, using the cryptographic hardware component 200 to perform cryptographic service types (e.g., integrity verification and authenticated encryption) and storing the cryptographic results obtained therefrom in hardware registers of the cryptographic hardware component 200 effectively offloads the operations from one or more processors of the computing device. Thus, whenever a storage operation (e.g., reading data from a storage device, writing data to a storage device) requires the security enhancements provided by integrity verification and authenticated encryption, the offloading of the cryptographic algorithm execution improves the performance of the computing device. Examples of performance improvements include, but are not limited to: improved key performance indicators seen when performing integrity checks during a secure boot process (e.g., improved boot time); allowing the cryptographic hardware component 200 to perform processes such as Linux device mapper (dm) authenticity (dm-verity) integrity verification of block storage devices, thereby allowing other computing resources of the computing device (e.g., a processor) to perform other operations; and allowing computing resources of the computing device to perform other operations during authenticated encryption and authenticated decryption operations (e.g., during a suspend or resume process). As an example, if 1.5 gigabytes (GB) of data in the memory of the computing device needs to be captured and written to the storage device during the suspend process, and the block size of the data is 4 kilobytes (KB), there are 384,000 blocks of data, and without the examples described herein, each of these blocks of data must be operated on by one or more processors of the computing device to provide authenticated encryption of the data (e.g., data encryption and MAC generation). However, the examples described herein allow all operations to be performed in the cryptographic hardware component instead, thereby allowing one or more processors to perform other operations, which can increase the amount of time required to put the computing device into a hibernation state.

[0061] Figure 3 is a flow chart showing an example process 300 for performing an integrity verification process using a hash algorithm according to examples described herein. For example, the integrity verification process may be performed at least in part by a process such as Figure 1 The cryptographic hardware components 106 and Figure 2 Process 300 may be performed by a cryptographic hardware component such as cryptographic hardware component 200 shown in FIG.

[0062] At block 302, process 300 includes receiving a request to provide an integrity encryption service type. In some examples, a cryptographic hardware component (e.g., Figure 2The request is received by the cryptographic hardware component 200 as shown in and described above. In some examples, the request is received from any entity (e.g., hardware, software, firmware, or any combination thereof) that seeks to perform integrity verification on previously stored data. As one example, when performing a secure boot of an operating system on a computing device, a boot loader can request integrity verification of the operating system image. As another example, the operating system can request, via the processor, integrity verification of previously stored data to help ensure that loading the data into memory does not pose a security risk of compromising the computing device in some way. In some examples, the request specifies an algorithm to be executed, and the cryptographic hardware component is configured to execute the algorithm (e.g., using Figure 2 , and as described above). In some examples, the encryption algorithm specified in the request is the same as the algorithm previously used for the data. For example, the data may have previously had a hash generated using a SHA family algorithm, and the request may specify the same SHA family algorithm to be executed by the encryption hardware component so that the resulting digest (e.g., the encryption result) can be compared to a digest previously generated for the same data, where the previously generated digest can be included in, for example, a hash table that contains hash values ​​for various segments of the data. In some examples, comparing a digest to a previously generated digest can be referred to as performing a cryptographic action.

[0063] At block 304, process 300 includes initiating a hash algorithm in response to the request. In some examples, a cryptographic hardware component (e.g., Figure 2 ) of an algorithm execution device (e.g., a cryptographic hardware component 200 shown in Figure 2 In some examples, initiating execution of the hash algorithm includes configuring hardware (eg, circuitry), software, or a combination thereof of the algorithm execution device to execute the hash algorithm specified in the request received in block 302.

[0064] At block 306, process 300 includes obtaining data on which a hash algorithm is to be performed. As an example, the hash algorithm may be performed on a cryptographic hardware component (e.g., Figure 2 200) of the encryption hardware component 200 shown in FIG. Figure 2 The data is received at a data receiver 202 shown in FIG. 1 and provided from there to an algorithm execution device (e.g., Figure 2 ). The algorithm execution device 204 shown in FIG. 1 can be accessed from any storage device of the computing device (e.g., Figure 1 The UFS device 104 shown in Figure 1The data is obtained from the attached storage device 110 shown in FIG. 1 , etc. In some examples, the data on which the hash algorithm is to be performed is a portion of the data for which integrity verification is requested. In this way, the data can be received in a series of discrete units (e.g., blocks, segments, etc.), and each such discrete data unit can be used individually as an input to the hash algorithm to generate a digest set for the entire data.

[0065] At block 308, process 300 includes executing a hash algorithm using the data obtained in block 306 as input to generate a digest corresponding to the data. As an example, an algorithm execution device (e.g., Figure 2 The algorithm execution device 204 shown in ) can use data to perform a hash algorithm. In some examples, performing the hash algorithm includes performing a hash function. In some examples, performing the hash function includes: inputting data into the hash function to obtain a summary as an output. In some examples, the summary has a fixed size, regardless of the size of the input data. In some examples, the fixed size of the summary is determined by the specific hash algorithm being executed. Without departing from the scope of protection of the examples described herein, any hash function can be executed, and the specific hash function executed is determined by the hash algorithm being executed. For example, when the hash algorithm SHA-256 is being executed, the summary size will be 256 bits, and the hash function that generates the summary can append binary digits to a binary string representing the input data, pad the data with additional zeros, append a binary representation of an integer representing the length of the input data, create an initial hash value set, create a constant set, use the data to create a message schedule, perform a series of rotations and logical operations, compress the result to the correct size, and perform some additional final modifications to obtain a summary corresponding to the input data.

[0066] At block 310, process 300 includes storing the digest obtained as output from the hash algorithm executed in block 308 in a hardware register. As an example, the digest may be stored in a cryptographic hardware component (e.g., Figure 2 ) of the cryptographic hardware component 200 shown in FIG. Figure 2 ) in one of the algorithm result registers 208 shown in .

[0067] At block 312, process 300 includes obtaining an expected digest for the data. As one example, the expected digest for the data may be stored in a hash table associated with the data. As another example, the expected digest may be obtained from a storage device (e.g., Figure 1 The UFS device 104 shown in Figure 1In some examples, the expected digest is obtained by an encryption hardware component, or by any other component of the computing device that will compare the output digest with the expected digest.

[0068] At block 314, processing 300 includes performing a comparison between the digest stored in the hardware register of the cryptographic hardware component and the expected digest obtained in block 312. In some examples, performing the comparison includes determining whether there are any differences between the digest in the hardware register and the expected digest. The digest corresponding to a particular data item is likely to be unique, meaning that the likelihood that two different data items correspond to the same digest (e.g., a hash collision) is very small. Furthermore, even minor changes to the data can cause the digest to change significantly. Therefore, if the digest matches the expected digest, the data for which integrity verification is required is likely to have not changed since it was previously stored (e.g., the integrity of the data has been verified). Therefore, integrity verification can improve the security of a computing device by ensuring that no malicious or other changes have been made to the stored data.

[0069] At block 316, process 300 includes determining whether the digest and the expected digest match. For example, a cryptographic hardware component (e.g., Figure 2 The cryptographic hardware component 200 shown in ) or different components of the computing device can use the digest and the expected digest from the hardware register of the cryptographic hardware component to make this determination. In some examples, if the digest is the same as the expected digest, the digest matches the expected digest. In some examples, when the digest matches the expected digest, at least a partial integrity check passes. In the presence of additional data units, the integrity check pass is partial, for which data integrity must be verified to obtain a comprehensive integrity check pass, where each other data unit undergoes process 300. In some examples, if the digest and the expected digest are not the same, the integrity check fails and the integrity of the data is not verified. In some examples, when it is determined that the integrity check fails, process 300 proceeds to box 320. In some examples, when it is determined that the integrity check passes, process 300 proceeds to box 318.

[0070] At block 318, process 300 includes providing an indication that the integrity check passed. As an example, a component that performs a comparison of the digest with the expected digest (e.g., Figure 2 The cryptographic hardware component 200 shown in FIG. 300 may provide an indication of a pass of the integrity check to the entity that requested the cryptographic hardware component to perform the hash algorithm in block 302. In some examples, the integrity check passes the indication that the data for which integrity is to be verified is allowed to be removed from the storage device (e.g., Figure 1 The UFS device 104 shown in Figure 1) to a memory of a computing device (e.g., Figure 1 ), where data may be otherwise manipulated at the memory to continue executing a process (eg, a secure boot process).

[0071] At block 320, process 300 includes updating an error register of a cryptographic hardware component with an indication of a failed integrity check. As an example, Figure 2 The cryptographic hardware component 200 shown in FIG. 1 may utilize an indication of an integrity check failure to update Figure 1 The indication may be in any form without departing from the scope of the examples described herein. For example, the state of one or more bits of the error register may change, thereby indicating that the integrity check failed.

[0072] Figure 4 4 is a flow chart showing an example process 400 for performing an authenticated encryption process using an authenticated encryption algorithm according to examples described herein. For example, it may be performed at least in part by a process such as Figure 1 The cryptographic hardware components 106 and Figure 2 Process 400 may be performed by a cryptographic hardware component such as cryptographic hardware component 200 shown in FIG.

[0073] At block 402, process 400 includes receiving a request to provide a cryptographic service type. In some examples, a cryptographic hardware component (e.g., Figure 2 The request is received by an encryption hardware component 200 as shown in and described above. In some examples, the request is received from any entity (e.g., hardware, software, firmware, or any combination thereof) seeking to perform integrity verification on previously stored data. The requested encryption service type can be any other encryption service system (e.g., authenticated encryption, authenticated decryption, etc.) without departing from the scope of the examples described herein.

[0074] At block 404, process 400 includes initiating an encryption algorithm in an encryption hardware component, wherein the encryption algorithm is associated with an encryption service type. In some examples, the encryption hardware component (e.g., Figure 2 ) of an algorithm execution device (e.g., a cryptographic hardware component 200 shown in Figure 2 The algorithm execution device 204 shown in ) is used to execute the encryption algorithm. Examples of encryption algorithms include, but are not limited to: SHA, AES-GCM, AES-XTS, AES-ECB, AES-CBC, and ESSIV-AES-CBC. Other encryption algorithms can be started without departing from the scope of protection of the examples described herein.

[0075] At block 406, process 400 includes applying a cryptographic operation to the data to obtain an encrypted result, wherein the cryptographic operation is associated with an encryption algorithm. Figure 2 The cryptographic hardware component 200 shown in FIG. 1 and described above) is used to apply the cryptographic operation. Examples of cryptographic results include, but are not limited to: digest, MAC, encrypted data, decrypted data, and the like.

[0076] At block 408, process 400 includes storing at least a portion of the encryption result in an encryption hardware component (e.g., Figure 2 The hardware registers of the encryption hardware component 200 (for example, Figure 2 The encryption result is configured to be used to perform an encryption action. Examples of encryption actions include, but are not limited to, storing a digest, performing a comparison between a digest and an expected digest, providing an indication of a passed integrity check, updating an error register (e.g., Figure 2 error register 210), storing the MAC in a hardware register, storing the MAC in a storage device, storing the encrypted data in the storage device, performing a comparison between the MAC and the expected MAC, providing an indication of authentication decryption success, updating the error register with an indication of authentication decryption failure, storing the decrypted data in the memory device, and the like.

[0077] Figure 5 is a flow chart showing another example process 500 for performing an authenticated encryption process using an authenticated encryption algorithm according to examples described herein. For example, it may be performed at least in part by a process such as Figure 1 The cryptographic hardware components 106 and Figure 2 Process 500 may be performed by a cryptographic hardware component such as cryptographic hardware component 200 shown in FIG.

[0078] At block 502, process 500 includes receiving a request to provide a cryptographic service type of authenticated encryption. In some examples, a cryptographic hardware component (e.g., Figure 2 In some examples, the request is received from any entity (e.g., hardware, software, firmware, or any combination thereof) seeking to perform authenticated encryption on data for any purpose. As an example, when a computing device is to be suspended to a hibernation state, a memory (e.g., Figure 2 ) and / or other data storage devices (e.g., storage devices, registers, etc.) to write certain system state information to a storage device (e.g., Figure 1 The UFS storage device 104 shown in Figure 1In some examples, to help ensure the security of the computing device when the device is later resumed from a hibernation state, the system state information can be encrypted and a MAC can be generated for later use in verifying the data. The encrypted data and MAC can be considered part of the encryption result. In some examples, the request specifies an algorithm that the cryptographic hardware component is configured to execute (e.g., using Figure 2 For example, the request may specify that authenticated encryption be performed using AES-GCM.

[0079] At block 504, process 500 includes initiating an authenticated encryption algorithm in response to the request. In some examples, an encryption hardware component (e.g., Figure 2 ) of an algorithm execution device (e.g., a cryptographic hardware component 200 shown in Figure 2 In some examples, initiating execution of the authenticated encryption algorithm includes configuring hardware (e.g., circuitry), software, or a combination thereof of the algorithm execution device to execute the authenticated encryption algorithm specified in the request received in block 302.

[0080] At block 506, process 500 includes obtaining data on which an authenticated encryption algorithm is to be executed. As an example, the authenticated encryption algorithm may be executed on a cryptographic hardware component (e.g., Figure 2 200) of the encryption hardware component 200 shown in FIG. Figure 2 The data is received at a data receiver 202 shown in FIG. 1 and provided from there to an algorithm execution device (e.g., Figure 2 ). The algorithm execution device 204 shown in can be executed from any data location on the computing device (e.g., Figure 1 The memory device 108 shown in Figure 1 The UFS device 104 shown in Figure 1 The data is obtained from the additional storage device 110 shown in , registers, etc.). In some examples, the data on which the authenticated encryption algorithm is to be performed is part of the data for which authenticated encryption is requested. In this way, the data can be received in a series of discrete units (e.g., blocks, segments, etc.), and each such discrete data unit can be used individually as an input to the authenticated encryption algorithm to generate a MAC set for the data and the encrypted data.

[0081] At box 508, process 500 includes executing an authenticated encryption algorithm using the data obtained in box 506 as input to generate encrypted data and a MAC corresponding to the encrypted data or plaintext data (depending on the specific authenticated encryption algorithm being executed). For example, a user may seek to put a computing device to sleep, or the computing device may be configured to sleep after a period of inactivity or in response to low battery power. In this case, the operating system of the computing device may request authenticated encryption of data currently in the device's memory, where the data is used as input to the authenticated encryption algorithm specified in the request received in box 502. In some examples, executing the authenticated encryption algorithm generates encrypted data and a MAC corresponding to the data or the encrypted data (e.g., an encryption result) as output. In some examples, an encryption key (e.g., from Figure 2 The data is encrypted using an encrypted key storage device 212 shown in FIG. 2 ). When generating a MAC (which may also be referred to as an authentication tag), the same key or a different key may be used. In some examples, performing an authenticated encryption algorithm includes using and / or generating other information items, such as an initialization vector, additional authenticated data, values ​​of one or more counters, and the like.

[0082] At block 510, process 500 includes storing a MAC obtained from the authenticated encryption algorithm executed in block 508 as an output in a hardware register. As an example, the MAC may be stored in a cryptographic hardware component (e.g., Figure 2 ) of the cryptographic hardware component 200 shown in FIG. Figure 2 In some examples, storing the MAC in a hardware register can be at least part of performing the encryption action.

[0083] At block 512, process 500 includes storing the MAC obtained from the authenticated encryption algorithm executed at block 508 as an output in a storage device. As an example, the MAC may be stored in a storage device such as a persistent memory or any other storage device (e.g., Figure 1 The UFS device 104 shown in Figure 1 In some examples, the MAC is stored in a storage device such as the additional storage device 110 shown in FIG. Figure 2 In some examples, storing the MAC in the storage device can be referred to as performing at least a portion of the cryptographic action. In some examples, the MAC is later used as the expected MAC when performing authenticated decryption of the data.

[0084] At block 514, process 500 includes storing the encrypted data obtained from the authenticated encryption algorithm executed in block 508 as output on a storage device (e.g., Figure 1 The UFS device 104 shown in Figure 1 In some examples, the encrypted data is stored in an attached storage device 110 shown in FIG. 1 . In some examples, the encrypted data is later used when an authenticated decryption of the data is requested (e.g., during a recovery process). In some examples, storing the encrypted data in a storage device can be referred to as performing at least a portion of an encryption action.

[0085] Figure 6 6 is a flow chart showing an example process 600 for performing an authenticated decryption process using an authenticated encryption algorithm according to examples described herein. For example, the process may be performed at least in part by a process such as Figure 1 The cryptographic hardware components 106 and Figure 2 Process 600 may be performed by a cryptographic hardware component such as cryptographic hardware component 200 shown in FIG.

[0086] At block 602, process 600 includes receiving a request for providing a cryptographic service type of authenticated decryption. In some examples, a cryptographic hardware component (e.g., Figure 2 In some examples, the request is received from any entity (e.g., hardware, software, firmware, or any combination thereof) seeking to perform authenticated decryption of data for any purpose. As an example, when a computing device is to be suspended to a hibernation state, a memory (e.g., Figure 2 108) and / or other data storage devices (e.g., storage devices, registers, etc.) as encrypted data. Figure 1 The UFS storage device 104 shown in Figure 1 ), and generates a MAC corresponding to the data. In such a scenario, when the computing device is to resume operation, a request to provide authenticated decryption may be received, the request including: decrypting the encrypted data, generating a MAC corresponding to the data, and verifying that the MAC generated during authenticated encryption and the MAC generated during decryption match (thereby verifying the data). The decrypted data and MAC may be considered part of the encryption result. In some examples, the request specifies an algorithm to be executed, and the cryptographic hardware component is configured to execute the algorithm (e.g., using Figure 2As an example, the request may specify the use of AES-GCM to perform authenticated decryption. In some examples, the authenticated encryption algorithm used to perform authenticated decryption corresponds to the authenticated encryption algorithm used when previously performing authenticated encryption on the data.

[0087] At block 604, process 600 includes initiating an authenticated encryption algorithm in response to the request. In some examples, an encryption hardware component (e.g., Figure 2 ) of an algorithm execution device (e.g., a cryptographic hardware component 200 shown in Figure 2 In some examples, initiating execution of the authenticated encryption algorithm includes configuring hardware (e.g., circuitry), software, or a combination thereof of the algorithm execution device to execute the authenticated encryption algorithm specified in the request received in block 602.

[0088] At block 606, process 600 includes obtaining data on which an authenticated encryption algorithm is to be executed. As an example, the authenticated encryption algorithm may be executed on a cryptographic hardware component (e.g., Figure 2 200) of the encryption hardware component 200 shown in FIG. Figure 2 The data is received at a data receiver 202 shown in FIG. 1 and provided from there to an algorithm execution device (e.g., Figure 2 204). The algorithm execution device 204 shown in FIG. 204 may be executed from any storage device (e.g., Figure 1 The UFS device 104 shown in Figure 1 The data is obtained from the attached storage device 110 shown in FIG. 1 , etc. In some examples, the data on which the authenticated encryption algorithm is to be executed is part of the data for which authenticated decryption is requested. In this way, the data can be received in a series of discrete units (e.g., blocks, segments, etc.), and each such discrete data unit can be used individually as an input to the authenticated decryption algorithm to generate a MAC set for the entire data.

[0089] At block 608, process 600 includes executing an authenticated encryption algorithm using the data obtained in block 506 as input to generate decrypted data and a MAC corresponding to the decrypted data or plaintext data (depending on the particular authenticated encryption algorithm being executed). Generating the decrypted data and / or the MAC may be referred to as obtaining an encryption result. For example, a user may seek to resume a computing device from a hibernation state. In such a scenario, an operating system or any other component of the computing device may request access to data currently stored on a storage device (e.g., Figure 1 The UFS device 104 shown in Figure 1, wherein the data is used as input to an authenticated encryption algorithm specified in the request received in block 602. In some examples, the authenticated encryption algorithm is executed to generate decrypted data and a MAC corresponding to the data or the encrypted data as output. In some examples, the authenticated encryption algorithm is used (e.g., from Figure 2 The data is decrypted using an encryption key obtained from the encryption key storage device 212 shown in . The same key or a different key may be used when generating a MAC (which may also be referred to as an authentication tag). In some examples, performing an authenticated encryption algorithm includes using and / or generating other information items, such as an initialization vector, additional authenticated data, values ​​of one or more counters, and the like.

[0090] At block 610, process 600 includes storing a MAC obtained from the authenticated encryption algorithm executed in block 608 as an output in a hardware register. As an example, the MAC may be stored in a cryptographic hardware component (e.g., Figure 2 ) of the cryptographic hardware component 200 shown in FIG. Figure 2 In some examples, storing the MAC may be referred to as at least a portion of performing an encryption action.

[0091] At block 612, process 600 includes obtaining an expected MAC for the data. As one example, the expected MAC for the data may be stored in some form of persistent memory of the computing device. As another example, the expected MAC for the data may be stored in a storage device (e.g., Figure 1 The UFS device 104 shown in Figure 1 In some examples, the expected MAC is obtained by an encryption hardware component, or by any other component of the computing device that will compare the output MAC and the expected MAC. In some examples, obtaining the expected MAC can be referred to as performing at least a portion of the encryption action.

[0092] At block 614, processing 600 includes performing a comparison between a MAC stored in a hardware register of the cryptographic hardware component and the expected MAC obtained in block 612. In some examples, performing the comparison may be referred to as performing at least a portion of an encryption action. In some examples, performing the comparison includes determining whether there are any differences between the MAC in the hardware register and the expected MAC. A MAC corresponding to a particular data item is likely to be unique, meaning that the likelihood that two different data items correspond to the same MAC is very small. Furthermore, even a small change in the data can cause the MAC to change significantly. Therefore, if the MAC matches the expected MAC, the data for which authentication decryption is required is likely to have not changed since it was previously stored (e.g., the authenticity of the data has been verified). Therefore, authenticated decryption can improve the security of a computing device by ensuring that no malicious or other changes have been made to the stored data.

[0093] At block 616, process 600 includes determining whether the MAC and the expected MAC match, which may be referred to as performing at least a portion of an encryption action. For example, an encryption hardware component (e.g., Figure 2 The cryptographic hardware component 200 shown in ) or different components of the computing device can use the MAC and the expected MAC from the hardware register of the cryptographic hardware component to make this determination. In some examples, if the MAC is the same as the expected MAC, the MAC matches the expected MAC. In some examples, when the MAC matches the expected MAC, at least part of the authentication check passes. In the presence of additional data units, the authentication check pass is partial, for which the data authenticity must be verified to obtain a comprehensive authenticity check pass, where each other data unit undergoes processing 600. In some examples, if the MAC and the expected MAC are not the same, the authentication check fails and the authenticity of the data is not verified. In some examples, when it is determined that the authentication failed, processing 600 proceeds to box 620. In some examples, when it is determined that the authentication check passes, processing 600 proceeds to box 618.

[0094] At block 618, process 600 includes providing an indication that the authentication check passed, which may be referred to as performing at least a portion of a cryptographic action. As an example, a component that performs a comparison of a MAC with an expected MAC (e.g., Figure 2 The cryptographic hardware component 200 shown in FIG. 600 may provide an indication of a pass in the authentication check to the entity that requested the cryptographic hardware component to perform the authenticated encryption algorithm in block 602. In some examples, a pass in the authentication check indicates that data for which authenticity is verified is allowed to be transferred from a storage device (e.g., Figure 1 The UFS device 104 shown in Figure 1 ) to a memory of a computing device (e.g., Figure 1 ), where data may be manipulated in other ways.

[0095] At block 620, process 600 includes updating an error register of a cryptographic hardware component with an indication of a failed authentication check, which may be referred to as at least a portion of performing a cryptographic action. As an example, Figure 2 The cryptographic hardware component 200 shown in FIG. 1 may utilize an indication of a failed authentication check to update Figure 1 The indication may be in any form without departing from the scope of the examples described herein. For example, the state of one or more bits of the error register may change, thereby indicating that the authentication check failed.

[0096] Figure 7 is a flow chart showing an example process 700 for performing a decryption process using an encryption algorithm according to examples described herein. For example, the decryption process may be performed at least in part by a process such as Figure 1 The cryptographic hardware components 106 and Figure 2 Process 700 may be performed by a cryptographic hardware component such as cryptographic hardware component 200 shown in FIG.

[0097] At block 702, process 700 includes: on a local computing device (e.g., Figure 1 At a computing device 100 of a remote computing device, a request is received to provide a type of cryptographic service, the type of cryptographic service comprising decrypting encrypted data, wherein the encrypted data is encrypted by the remote computing device using plaintext data, an encryption key, and an initialization vector (IV). In some examples, the encrypted data is encrypted by a cryptographic hardware component (e.g., Figure 2 The request is received by an encryption hardware component 200 as shown in and described above. In some examples, the request is received from any entity (e.g., hardware, software, firmware, or any combination thereof) seeking to perform decryption on the data for any purpose. As an example, a software image (or any other type of data) may have been encrypted by a remote computing device (e.g., a server) before it was stored on a storage device of a local computing device (e.g., a mobile computing device). In such a scenario, encryption can be performed according to any of an AES-type encryption algorithm (e.g., CBC, GCM, etc.), wherein the AES-type encryption algorithm at least in part uses an encryption key and IV to encrypt the data. Therefore, decrypting the data uses at least in part the same key and IV used in the encryption process.

[0098] At block 704, process 700 includes, in response to receiving the request, initiating an encryption algorithm in an encryption hardware component of the local computing device. In some examples, the encryption hardware component (e.g., Figure 2 ) of an algorithm execution device (e.g., a cryptographic hardware component 200 shown in Figure 2 In some examples, initiating execution of the encryption algorithm includes: configuring hardware (e.g., circuitry), software, or a combination thereof of the algorithm execution device to execute the encryption algorithm specified in the request received in block 802.

[0099] At block 706, process 700 includes: executing, by a local computing device (e.g., Figure 1 The encryption key and IV may be obtained using any suitable technique. As an example, a remote device that encrypts data may be used to communicate with a computer that has an encryption hardware component (e.g., Figure 2 The key may be obtained by any suitable key derivation and / or exchange process between the encryption hardware component 200 shown in FIG. 1 and the local device storing the encrypted data. As another example, the IV may be sent from the remote device to the local device storing the encrypted data.

[0100] At block 708, process 700 includes storing the IV in a cryptographic hardware component (e.g., Figure 2 In a hardware storage device of the encryption hardware component 200).

[0101] At block 710, process 700 includes obtaining encrypted data (e.g., a software image encrypted by a remote computing device) from a storage device of a local computing device. As an example, the encrypted data may be stored in a cryptographic hardware component (e.g., Figure 2 200) of the encryption hardware component 200 shown in FIG. Figure 2 The encrypted data is received at a data receiver 202 shown in FIG. 1 and provided from there to an algorithm execution device (e.g., Figure 2 204). The algorithm execution device 204 shown in FIG. 204 may be executed from any storage device (e.g., Figure 1 The UFS device 104 shown in Figure 1 The data is obtained by the decryption algorithm from the attached storage device 110 shown in FIG. 1 , etc. In some examples, the data on which the encryption algorithm is to be executed is a portion of the data for which decryption is requested. In this way, the data can be received in a series of discrete units (e.g., blocks, segments, etc.), and each such discrete data unit can be used individually as an input to the decryption algorithm to decrypt the entire encrypted data.

[0102] At block 712, process 700 includes executing an encryption algorithm using the encrypted data, the encryption key, and the IV to obtain decrypted data. As an example, Figure 2The cryptographic hardware component 200 shown in FIG. 8 can perform an encryption algorithm using the encrypted data in block 810 and the key and IV stored by the cryptographic hardware component to obtain decrypted data.

[0103] At block 714, process 700 includes storing the decrypted data on a local computing device (eg, Figure 1 of the computing device 100) (e.g., Figure 1 In some examples, the decryption may be considered inline decryption. Thus, for example, when the encrypted data is transferred from the storage device to one or more memory devices, the decryption may be performed sequentially on discrete portions of the encrypted data.

[0104] Figure 8 8 is a flow chart showing an example process 800 for performing a decryption process using an encryption algorithm according to examples described herein. For example, the decryption process may be performed at least in part by a process such as Figure 1 The cryptographic hardware components 106 and Figure 2 Process 800 may be performed by a cryptographic hardware component such as cryptographic hardware component 200 shown in FIG.

[0105] At block 802, process 800 includes receiving a request for a cryptographic service type to provide decryption. In some examples, a cryptographic hardware component (e.g., Figure 2 The request is received by an encryption hardware component 200 as shown in and described above. In some examples, the request is received from any entity (e.g., hardware, software, firmware, or any combination thereof) seeking to perform decryption of the data for any purpose. As an example, a software image (or any other type of data) may have been encrypted by a remote computing device (e.g., a server) before it was stored on a storage device of a local computing device (e.g., a mobile computing device). In such a scenario, encryption can be performed according to any of an AES-type encryption algorithm (e.g., CBC, GCM, etc.), wherein the AES-type encryption algorithm uses, at least in part, an encryption key and IV to encrypt the data. Thus, decrypting the data uses, at least in part, the same key and IV used in the encryption process.

[0106] At block 804, process 800 includes initiating an encryption algorithm in response to the request. In some examples, an encryption hardware component (e.g., Figure 2 ) of an algorithm execution device (e.g., a cryptographic hardware component 200 shown in Figure 2 In some examples, initiating execution of the encryption algorithm includes: configuring hardware (e.g., circuitry), software, or a combination thereof of the algorithm execution device to execute the encryption algorithm specified in the request received in block 802.

[0107] At block 806, process 800 includes obtaining encrypted data (e.g., a software image encrypted by a remote computing device) on which an encryption algorithm is to be executed. As an example, the encryption algorithm may be executed on a hardware component (e.g., Figure 2 200) of the encryption hardware component 200 shown in FIG. Figure 2 The encrypted data is received at a data receiver 202 shown in FIG. 1 and provided from there to an algorithm execution device (e.g., Figure 2 204). The algorithm execution device 204 shown in FIG. 204 may be executed from any storage device (e.g., Figure 1 The UFS device 104 shown in Figure 1 The data is obtained by the decryption algorithm from the attached storage device 110 shown in FIG. 1 , etc. In some examples, the data on which the encryption algorithm is to be executed is a portion of the data for which decryption is requested. In this way, the data can be received in a series of discrete units (e.g., blocks, segments, etc.), and each such discrete data unit can be used individually as an input to the decryption algorithm to decrypt the entire encrypted data.

[0108] At block 808, process 800 includes obtaining an encryption key and IV for encrypting data. The key and IV may be obtained using any suitable technique. As an example, a remote device that encrypts data may be used with a computer that has an encryption hardware component (e.g., Figure 2 The key may be obtained by any suitable key derivation and / or exchange process between the encryption hardware component 200 shown in FIG. 1 and the local device storing the encrypted data. As another example, the IV may be sent from the remote device to the local device storing the encrypted data.

[0109] At block 810, process 800 includes storing the key and IV obtained in block 808 in a cryptographic hardware component (e.g., Figure 2 In some examples, the IV is stored by the cryptographic hardware component, rather than using, for example, a serial number for deriving the IV, thereby offloading the derivation of the IV from the computational resources of the local computing device.

[0110] At block 812, process 800 includes executing an encryption algorithm for encrypting data at a remote device to obtain decrypted data (e.g., an encryption result). Figure 2 The cryptographic hardware component 200 shown in FIG. 8 can perform an encryption algorithm using the encrypted data in block 810 and the key and IV stored by the cryptographic hardware component.

[0111] At block 814, process 800 includes storing the decrypted data obtained in block 812 on a computer having an encryption hardware component (e.g., Figure 2 This can be referred to as performing at least a portion of the cryptographic action in one or more memory devices of a local computing device of the cryptographic hardware component 200 shown in FIG. 1 . In some examples, the decryption can be considered to be inline decryption. Thus, for example, when the encrypted data is transferred from the storage device to the one or more memory devices, the decryption can be performed sequentially on discrete portions of the encrypted data.

[0112] In some examples, processes 300, 400, 500, 600, 700, 800, or any other process described herein can be performed by a computing device or apparatus and / or one or more components thereof. For example, these processes can be performed in whole or in part by Figure 1 As another example, processes 300, 400, 500, 600, 700, and 800 may be performed in whole or in part by a cryptographic hardware component 106 of the computing device 100 shown in FIG. Figure 2 As another example, these processes may be performed in whole or in part by the cryptographic hardware component 200 shown in FIG. Fig. 9 The computing system 900 shown in FIG. 1 is used to perform Fig. 9 Not shown, but computing system 900 may include at least one cryptographic hardware component.

[0113] The computing device may include any suitable device, such as a vehicle or a computing device of the vehicle (e.g., a driver monitoring system of the vehicle), a mobile device (e.g., a mobile phone), a desktop computing device, a tablet computing device, a wearable device (e.g., a VR handheld device, an AR handheld device, an AR glasses, a network-connected watch or smart watch, or other wearable device), a server computer, a robotic device, a television, and / or any other computing device with resource capabilities to perform the processing described herein (including processing 300, 400, 500, 600 and / or other processing described herein). In some cases, the computing device or device may include various components, such as one or more input devices, one or more output devices, one or more processors, one or more microprocessors, one or more microprocessors, one or more microcomputers, one or more cameras, one or more sensors, one or more encryption hardware components, and / or other components configured to perform the operations of the processing described herein. In some examples, the computing device may include a display, a network interface configured to communicate and / or receive data, any combination thereof, and / or other components. The network interface may be configured to communicate and / or receive data based on an Internet Protocol (IP) or other types of data.

[0114] The components of the computing device may be implemented using circuits. For example, these components may include and / or may be implemented using electronic circuits or other electronic hardware, which may include one or more programmable electronic circuits (e.g., microprocessors, graphics processing units (GPUs), digital signal processors (DSPs), central processing units (CPUs), and / or other suitable electronic circuits), and / or may at least partially include and / or be implemented using computer software, firmware, or any combination thereof to perform the various operations described herein.

[0115] Will Figure 3 The process 300 shown in Figure 4 The process 400 shown in Figure 5 The process 500 shown in Figure 6 The process 600 shown in Figure 7 The process 700 and Figure 8 The process 800 shown in is shown as a logical flow diagram, and its operations represent a sequence of operations that can be implemented in hardware, computer instructions, or a combination thereof. In the context of computer instructions, these operations represent computer executable instructions stored on one or more computer-readable storage media, and when these computer executable instructions are executed by one or more processors, the described operations are performed. Typically, computer executable instructions include routines, programs, objects, components, data structures, etc. that perform specific functions or implement specific data types. The order in which these operations are described is not intended to be interpreted as limiting, and any number of the described operations can be combined in any order and / or in parallel to implement these processes.

[0116] In addition, the processes 300, 400, 500, 600, 700, 800 and / or other processes described herein may be performed under the control of one or more computer systems configured with executable instructions, and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that is executed together on one or more processors by hardware or a combination thereof. As described above, the code may be stored on a computer-readable storage medium or a machine-readable storage medium, for example, in the form of a computer program including multiple instructions that may be executed by one or more processors. The computer-readable storage medium or the machine-readable storage medium may be non-temporary.

[0117] Fig. 9 is a diagram illustrating an example system for implementing certain aspects of the proposed technology. Specifically, Fig. 9An example of a computing system 900 is shown, which may be, for example, any computing device that makes up an internal computing system, a remote computing system, a camera, or any components thereof, wherein the components of the system communicate with each other using connection 905. Connection 905 may be a physical connection using a bus, or a direct connection into processor 910 (e.g., in a chipset architecture). Connection 905 may also be a virtual connection, a networked connection, or a logical connection.

[0118] In some examples, computing system 900 is a distributed system in which the functionality described in the present disclosure can be distributed in one data center, multiple data centers, a peer-to-peer network, etc. In some examples, one or more of the distributed system components represent multiple such components, each of which performs some or all of the functionality described for that component. In some examples, these components can be physical devices or virtual devices.

[0119] The example system 900 includes at least one processing unit (CPU or processor) 910, and connections 905 that couple various system components including system memory 915 (e.g., read only memory (ROM) 920 and random access memory (RAM) 925) to the processor 910. The computing system 900 may include a cache 912 of high-speed memory that is directly connected to, in close proximity to, or integrated as part of the processor 910.

[0120] Processor 910 may include any general purpose processor and hardware services or software services (e.g., services 932, 934, and 936 stored in storage device 930) configured to control processor 910 and a special purpose processor that incorporates software instructions into the actual processor design. Processor 910 may be a completely self-contained computing system in nature, including multiple cores or processors, buses, memory controllers, caches, etc. Multi-core processors may be symmetric or asymmetric.

[0121] To enable user interaction, the computing system 900 includes an input device 945, which can represent any number of input means, such as a microphone for voice, a touch-sensitive screen for gesture or graphical input, a keyboard, a mouse, motion input, voice, and the like. The computing system 900 can also include an output device 935, which can be one or more of a number of output means. In some instances, a multimodal system can enable a user to provide multiple types of input / output to communicate with the computing system 900. The computing system 900 may include a communication interface 940, which can generally manage and control user input and system output. The communication interface can use wired and / or wireless transceivers to perform or facilitate the reception and / or transmission of wired or wireless communications, including those using the following devices: audio jacks / plugs, microphone jacks / plugs, universal serial bus (USB) ports / plugs, Ports / plugs, Ethernet ports / plugs, Fiber optic ports / plugs, Proprietary wired ports / plugs, Wireless signal transmission, Low energy (BLE) wireless signal transmission, Wireless signal transmission, radio frequency identification (RFID) wireless signal transmission, dedicated short-range communication (DSRC) wireless signal transmission, 802.11 Wi-Fi wireless signal transmission, wireless local area network (WLAN) signal transmission, visible light communication (VLC), Worldwide Interoperability for Microwave Access (WiMAX), infrared communication (IR) wireless signal transmission, public switched telephone network (PSTN) signal transmission, integrated services digital network (ISDN) signal transmission, 3G / 4G / 5G / LTE cellular data network wireless signal transmission, ad hoc network signal transmission, radio wave signal transmission, microwave signal transmission, infrared signal transmission, visible light signal transmission, ultraviolet light signal transmission, wireless signal transmission along the electromagnetic spectrum, or some combination thereof. The communication interface 940 may also include one or more global navigation satellite system (GNSS) receivers or transceivers for determining the location of the computing system 900 based on one or more signals received from one or more satellites associated with one or more GNSS systems. GNSS systems include, but are not limited to, the United States' Global Positioning System (GPS), Russia's Global Navigation Satellite System (GLONASS), China's BeiDou Navigation Satellite System (BDS), and Europe's Galileo GNSS. There are no restrictions on operation with any particular hardware arrangement, so the basic features herein may be easily replaced with improved hardware or firmware arrangements developed.

[0122] The storage device 930 may be a non-volatile and / or non-temporary and / or computer-readable memory device and may be a hard disk or other type of computer-readable medium that stores computer-accessible data, such as a magnetic cassette, a flash memory card, a solid-state memory device, a digital versatile disk, a magnetic tape, a floppy disk, a flexible disk, a hard disk, a magnetic tape, a magnetic stripe / strip, any other magnetic storage medium, a flash memory, a memristor memory, any other solid-state memory, a compact disc read-only memory (CD-ROM) disc, a rewritable compact disc (CD) disc, a digital video disc (DVD) disc, a Blu-ray disc (BDD) disc, a holographic disc, another optical medium, a secure digital (SD) card, a micro secure digital (microSD) card, card, a smart card chip, an EMV chip, a subscriber identification module (SIM) card, a mini / micro / nano / pico SIM card, another integrated circuit (IC) chip / card, a random access memory (RAM), a static RAM (SRAM), a dynamic RAM (DRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash EPROM (FLASHEPROM), a cache memory (L1 / L2 / L3 / L4 / L5 / L#), a resistive random access memory (RRAM / ReRAM), a phase change memory (PCM), a spin transfer torque RAM (STT-RAM), another memory chip or cartridge, and / or a combination thereof.

[0123] Storage device 930 may include software services, servers, services, etc., which cause the system to perform functions when the code defining such software is executed by processor 910. In some examples, hardware services that perform a particular function may include software components stored in a computer-readable medium in combination with hardware components (e.g., processor 910, connection 905, output device 935, etc.) required to perform the function.

[0124] As used herein, the term "computer-readable medium" includes, but is not limited to, portable or non-portable storage devices, optical storage devices, and various other media capable of storing, containing or carrying instructions and / or data. Computer-readable media may include non-temporary media that can store data, but does not include carrier waves and / or temporary electronic signals that are transmitted wirelessly or through a wired connection. Examples of non-temporary media may include, but are not limited to: disks or tapes, optical storage media (such as compact discs (CDs) or digital versatile discs (DVDs)), flash memory, memory, or memory devices. Computer-readable media may store code and / or machine-executable instructions that may represent any combination of processes, functions, subroutines, programs, routines, subroutines, modules, software packages, classes, or instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by transmitting and / or receiving information, data, independent variables, parameters, or memory contents. Information, independent variables, parameters, data, etc. may be transmitted, forwarded, or transmitted using any suitable means, including memory sharing, message passing, token passing, network transmission, etc.

[0125] In some examples, computer-readable storage devices, media, and memories may include cables or wireless signals containing bit streams, etc. However, when referred to, non-transitory computer-readable storage media explicitly excludes media such as energy, carrier signals, electromagnetic waves, and signals themselves.

[0126] Specific details are provided in the above description to provide a thorough understanding of the examples and examples provided herein. However, it will be appreciated by those of ordinary skill in the art that these examples can be implemented without these specific details. For ease of clarity, in some cases, the technology proposed herein may be presented as including separate functional blocks, which include functional blocks containing devices, device components, operations in methods embodied in software, steps or routines, or a combination of hardware and software. In addition to the components shown in the accompanying drawings and / or described herein, other components may also be used. For example, circuits, systems, networks, processes and other components may be displayed as components in block diagram form to avoid confusing these examples with unnecessary details. In other instances, in order to avoid confusing these examples, well-known circuits, processes, algorithms, structures and techniques may be displayed without unnecessary details.

[0127] Each example may be described above as a process or method described using a flowchart, flow chart, data flow diagram, structure diagram, or block diagram. Although a flow chart is used to describe the operations as a sequential process, many operations may be performed in parallel or simultaneously. Furthermore, the order of the operations may be adjusted. When the operations are completed, the process terminates, but it may have other operations not included in the accompanying drawings. The process may correspond to a method, function, procedure, subroutine, subprogram, etc. When the process corresponds to a function, the termination of the process corresponds to a return from the function to its calling function or main function.

[0128] The processing and method according to the above-mentioned examples can be implemented using computer executable instructions stored in or available from computer readable media. For example, such instructions may include instructions and data that cause or configure a general-purpose computer, a special-purpose computer, or a processing device to perform a specific function or functional group. The computer resource portion used can be accessed through a network. Computer executable instructions can be, for example, binary, intermediate format instructions (e.g., assembly language), firmware, source code, etc. Examples of computer readable media that can be used to store instructions, information used, and / or information created during the method according to the described examples include disks or optical disks, flash memory, USB devices provided with non-volatile memory, networked storage devices, etc.

[0129] The equipment implementing the processing and methods according to these disclosures may include hardware, software, firmware, middleware, microcode, hardware description language or a combination thereof, and may take any of a variety of forms. When implemented in software, firmware, middleware or microcode, the program code or code segments (e.g., computer program products) for performing the necessary tasks may be stored in a computer-readable medium or a machine-readable medium. The processor may perform the necessary tasks. Typical examples of form factors include laptop computers, smart phones, mobile phones, tablet devices or other small-sized personal computers, personal digital assistants, rack-mounted devices, stand-alone devices, etc. The functions described herein may also be embodied in peripheral devices or add-on cards. As a further example, this function may also be implemented on a circuit board between different chips or different processes executed in a single device.

[0130] Instructions, media for transmitting such instructions, computing resources for executing them, and other structures for supporting such computing resources are exemplary means for providing the functions described in this disclosure.

[0131] In the foregoing description, various aspects of the present application are described with reference to the specific examples of the present application, but those of ordinary skill in the art will recognize that the present application is not limited thereto. Therefore, although the illustrative examples of the present application have been described in detail herein, it should be understood that the concept of the present invention can be embodied and adopted differently in other ways, and the appended claims are intended to be interpreted as including such variations, unless limited by the prior art. The various features and aspects of the above-mentioned application can be used individually or in combination. In addition, without departing from the broader spirit and scope of protection of this specification, the examples described herein can be used in any number of environments and applications outside of those described herein. Therefore, the description and the accompanying drawings should be considered illustrative rather than restrictive. For illustration purposes, the method is described in a specific order. It should be understood that in alternative examples, the method can be performed in an order different from the described order.

[0132] It should be understood by those of ordinary skill in the art that the less than ("<") and greater than (">") symbols or terms used in this document may be replaced with less than or equal to ("≤") and greater than or equal to ("≥") symbols, respectively, without departing from the scope of this specification.

[0133] When a component is described as being “configured to” perform certain operations, such configuration may be achieved, for example, by designing electronic circuits or other hardware to perform the operation, by programming a programmable electronic circuit (e.g., a microprocessor or other appropriate electronic circuit) to perform the operation, or any combination thereof.

[0134] The phrase "coupled to" refers to any component that is physically connected directly or indirectly to another component, and / or any component that communicates directly or indirectly with another component (eg, via a wired or wireless connection to another component and / or other appropriate communication interface).

[0135] Declaration language or other language that refers to "at least one of" a set and / or "one or more of" a set indicates that one member of the set or multiple members of the set (in any combination) satisfies the claim. For example, declaration language that refers to "at least one of A and B" or "at least one of A or B" means A, B, or A and B. In another example, declaration language that refers to "at least one of A, B, and C" or "at least one of A, B, or C" means A, B, C, or A and B, or A and C, or B and C, or A and B and C. Language such as "at least one of" a set and / or "one or more of" a set does not limit the set to the items listed in the set. For example, declaration language that refers to "at least one of A and B" or "at least one of A or B" means A, B, or A and B, and may additionally include items not listed in the set of A and B.

[0136] Various exemplary logic boxes, modules, engines, circuits and algorithmic operations described in conjunction with the examples disclosed herein can all be implemented as electronic hardware, computer software, firmware or a combination thereof. In order to clearly represent this interchangeability between hardware and software, various exemplary components, boxes, modules, circuits and operations are generally described above around their functions. Whether such functions are implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. A skilled person can implement the described functions in an alternative manner for each specific application, but such implementation decisions should not be interpreted as departing from the scope of protection of the present disclosure.

[0137] The techniques described herein may also be implemented using electronic hardware, computer software, firmware, or any combination thereof. This technique may be implemented using any of a variety of devices such as general-purpose computers, wireless communication device handsets, or integrated circuit devices with multiple uses (including applications in wireless communication device handsets and other devices), etc. Any features described as modules or components may be implemented together in an integrated logic device, or may be implemented separately as discrete but interoperable logic devices. If implemented in software, these techniques may be implemented at least in part by a computer-readable data storage medium, the computer-readable data storage medium including program code, the program code including instructions for executing one or more of the methods described above when executed. The computer-readable data storage medium may form part of a computer program product, which may include packaging materials. The computer-readable medium may include a memory or data storage medium, for example, a random access memory (RAM), a read-only memory (ROM), a non-volatile random access memory (NVRAM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic or optical data storage medium, and the like, such as a synchronous dynamic random access memory (SDRAM). Additionally or alternatively, these techniques may be implemented at least in part through a computer-readable communication medium that carries or transmits program code in the form of instructions or data structures (e.g., a propagated signal or wave) and that can be accessed, read, and / or executed by a computer.

[0138] The program code can be executed by a processor, which may include one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated logic circuits or discrete logic circuits. Such a processor can be configured to perform any of the techniques described in this disclosure. A general-purpose processor can be a microprocessor, but the processor can also be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, several microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Therefore, the term "processor" used herein can refer to any of the aforementioned structures, any combination of the aforementioned structures, or any other structure or device suitable for implementing the technology described herein.

[0139] Illustrative aspects of the disclosure include:

[0140] Aspect 1: A method for offloading an encryption service, the method comprising: receiving a request to provide an encryption service type; starting an encryption algorithm in an encryption hardware component, wherein the encryption algorithm is associated with the encryption service type; applying an encryption operation to data to obtain an encryption result, wherein the encryption operation is associated with the encryption algorithm; and storing at least a portion of the encryption result in a hardware register of the encryption hardware component, wherein the encryption result is configured to perform an encryption action.

[0141] Aspect 2: The method according to aspect 1, wherein the encryption service type includes integrity service, the encryption algorithm is a hash algorithm, and the encryption result includes a digest corresponding to the data.

[0142] Aspect 3: The method according to any one of Aspects 1 or 2 further includes: using the encryption result to perform the encryption action.

[0143] Aspect 4: A method according to any one of Aspects 1 to 3, wherein performing the encryption action includes: obtaining the encryption result from the hardware register of the encryption hardware component; and performing a comparison between the encryption result and an expected encryption result to determine whether the encryption result matches the expected encryption result.

[0144] Aspect 5: The method according to Aspect 4 further includes: determining a match between the encryption result and the expected encryption result; and determining that the data at least partially passes the integrity check based on the match between the encryption result and the expected encryption result.

[0145] Aspect 6: The method according to Aspect 4 further includes: determining that the encryption result does not match the expected encryption result; and determining that the integrity check on the data fails based on the fact that the encryption result does not match the expected encryption result.

[0146] Aspect 7: The method according to any one of Aspects 6, further comprising: updating an error register of the cryptographic hardware component with an indication of the failure of the integrity check.

[0147] Aspect 8: The method according to any one of aspects 1 to 7, wherein the cryptographic operation is performed during a secure boot process, and wherein the data is at least a portion of an operating system image file.

[0148] Aspect 9: The method according to any one of aspects 1 to 8, wherein the cryptographic operation is performed during a data block integrity check, and wherein the data is at least part of a read-only file system.

[0149] Aspect 10: A method according to aspect 1, wherein the encryption service type includes an authenticated encryption service, wherein the encryption algorithm is an authenticated encryption algorithm, and applying the encryption operation to obtain the encryption result includes: generating a message authentication code (MAC).

[0150] Aspect 11: The method according to any one of Aspects 1 or 10, wherein applying the encryption operation to the data to obtain the encryption result further comprises: encrypting the data using the authenticated encryption algorithm to obtain encrypted data.

[0151] Aspect 12: The method according to any one of Aspects 1 and 10 to 11 further includes: using the encryption result to perform the encryption action, wherein performing the encryption action includes: obtaining the MAC from the hardware register of the encryption hardware component; and storing the MAC in a persistent memory.

[0152] Aspect 13: The method according to any one of Aspects 1 and 10 to 12, wherein the encrypted data includes encrypted system state information obtained from a memory, and the method further comprises: storing the encrypted data on a non-volatile storage device.

[0153] Aspect 14: A method according to any one of Aspects 1 or 10, wherein the data is encrypted system status information obtained from a non-volatile storage device, and wherein performing the encryption action includes: obtaining the MAC from the hardware register of the encryption hardware component; and performing a comparison between the MAC and an expected MAC to determine whether the MAC matches the expected MAC.

[0154] Aspect 15: The method according to any one of Aspects 1 and 14 further includes: determining that the MAC matches the expected MAC; determining that the authentication check for the data passes based on the MAC matching the expected MAC; and decrypting the data using the encryption algorithm based on the authentication check passing.

[0155] Aspect 16: The method according to any one of Aspects 1 and 14 further includes: determining that the MAC does not match the expected MAC; determining that an authentication check on the data has failed based on the MAC not matching the expected MAC; and based on the authentication check failure, updating an error register of the encryption hardware component using an indication of the authentication check failure.

[0156] Aspect 17: A device for offloading cryptographic services, comprising: a memory; a processor; and a cryptographic hardware component coupled to the memory and the processor, and configured to: receive a request to provide a cryptographic service type; start a cryptographic algorithm in the cryptographic hardware component, wherein the cryptographic algorithm is associated with the cryptographic service type; apply a cryptographic operation to data to obtain an encryption result, wherein the cryptographic operation is associated with the cryptographic algorithm; and store at least a portion of the encryption result in a hardware register of the cryptographic hardware component, wherein the encryption result is configured to perform an encryption action.

[0157] Aspect 18: An apparatus according to Aspect 17, wherein the encryption service type includes an integrity service, the encryption algorithm is a hash algorithm, and the encryption result includes a summary corresponding to the data, and wherein the encryption hardware component is further configured to use the encryption result to perform the encryption action, wherein, in order to perform the encryption action, the encryption hardware component is further configured to: obtain the encryption result from the hardware register of the encryption hardware component; and perform a comparison between the encryption result and an expected encryption result to determine whether the encryption result matches the expected encryption result.

[0158] Aspect 19: An apparatus according to any one of Aspects 17 or 18, wherein the encryption hardware component is further configured to: determine a match between the encryption result and the expected encryption result; and based on the match between the encryption result and the expected encryption result, determine that the data at least partially passes the integrity check.

[0159] Aspect 20: An apparatus according to any one of Aspects 17 or 18, wherein the cryptographic hardware component is further configured to: determine that the encryption result does not match the expected encryption result; and based on the mismatch between the encryption result and the expected encryption result, determine that an integrity check on the data has failed; and use an indication of the integrity check failure to update an error register of the cryptographic hardware component.

[0160] Aspect 21: The apparatus of any one of Aspects 17 to 20, wherein the cryptographic operation is performed during a secure boot process, and wherein the data is at least a portion of an operating system image file.

[0161] Aspect 22: The apparatus of any one of Aspects 17 to 20, wherein the cryptographic operation is performed during a data block integrity check, and wherein the data is at least part of a read-only file system.

[0162] Aspect 23: An apparatus according to any one of Aspects 17 to 20, wherein the encryption service type includes an authenticated encryption service, wherein the encryption algorithm is an authenticated encryption algorithm, and applying the encryption operation to obtain the encryption result includes: generating a message authentication code (MAC).

[0163] Aspect 24: An apparatus according to any one of Aspects 17 or 23, wherein applying the encryption operation to the data to obtain the encryption result also includes: encrypting the data using the authenticated encryption algorithm to obtain encrypted data, and wherein the encryption hardware component is further configured to: use the encryption result to perform the encryption action.

[0164] Aspect 25: An apparatus according to any one of Aspects 17 and 23 or 24, wherein, in order to perform the encryption action, the encryption hardware component is further configured to: obtain the MAC from the hardware register of the encryption hardware component; and store the MAC in a persistent memory.

[0165] Aspect 26: An apparatus according to any one of Aspects 17 or 23 to 25, wherein the encrypted data includes encrypted system status information obtained from a memory, and the encryption hardware component is further configured to: store the encrypted data on a non-volatile storage device.

[0166] Aspect 27: An apparatus according to any one of Aspects 17 or 23, wherein the data is encrypted system status information obtained from a non-volatile storage device, and wherein, in order to perform the encryption action, the encryption hardware component is further configured to: obtain the MAC from the hardware register of the encryption hardware component; and perform a comparison between the MAC and an expected MAC to determine whether the MAC matches the expected MAC.

[0167] Aspect 28: An apparatus according to any one of Aspects 17 or 27, wherein the encryption hardware component is further configured to: determine that the MAC matches the expected MAC; determine that the authentication check for the data passes based on the MAC matching the expected MAC; and decrypt the data using the encryption algorithm based on the authentication check passing.

[0168] Aspect 29: An apparatus according to any one of Aspects 17 or 27, wherein the cryptographic hardware component is further configured to: determine that the MAC does not match the expected MAC; determine that an authentication check on the data has failed based on the MAC not matching the expected MAC; and based on the authentication check failure, update an error register of the cryptographic hardware component using an indication of the authentication check failure.

[0169] Aspect 30: A non-transitory computer-readable medium having instructions stored thereon, which, when executed by one or more processors, causes the one or more processors to perform the operations according to any one of Aspects 1 to 29.

[0170] Aspect 31: An apparatus for offloading cryptographic services, the apparatus comprising one or more units for performing the operations according to any one of aspects 1 to 29.

[0171] Aspect 32: A method for offloading an encryption service, the method comprising: receiving a request to provide an encryption service type at a local computing device, the encryption service type comprising decryption of encrypted data, wherein the encrypted data is encrypted by a remote computing device using plaintext data, an encryption key, and an initialization vector (IV); in response to receiving the request, starting an encryption algorithm in an encryption hardware component of the local computing device; obtaining the encryption key and the IV by the local computing device; storing the IV in a hardware storage device of the encryption hardware component; obtaining the encrypted data from a storage device of the local computing device; executing the encryption algorithm using the encrypted data, the encryption key, and the IV to obtain decrypted data; and storing the decrypted data in a memory device of the local computing device.

[0172] Aspect 33: A device for offloading encryption services, the device comprising: at least one memory; and at least one processor coupled to the at least one memory, and configured to: receive a request to provide an encryption service type, the encryption service type comprising decryption of encrypted data, wherein the encrypted data is encrypted by a remote computing device using plaintext data, an encryption key, and an initialization vector (IV); in response to receiving the request, start an encryption algorithm in an encryption hardware component of the device; obtain the encryption key and the IV; store the IV in a hardware storage device of the encryption hardware component; obtain the encrypted data from the storage device of the device; execute the encryption algorithm using the encrypted data, the encryption key, and the IV to obtain decrypted data; and store the decrypted data in the memory device of the device.

[0173] Aspect 34: A non-temporary computer-readable medium of a local computing device having instructions stored thereon, which, when executed by one or more processors, causes the one or more processors to perform the following operations: receiving a request to provide an encryption service type, the encryption service type including decryption of encrypted data, wherein the encrypted data is encrypted by a remote computing device using plaintext data, an encryption key, and an initialization vector (IV); in response to receiving the request, starting an encryption algorithm in an encryption hardware component of the local computing device; obtaining the encryption key and the IV; storing the IV in a hardware storage device of the encryption hardware component; obtaining the encrypted data from a storage device of the local computing device; executing the encryption algorithm using the encrypted data, the encryption key, and the IV to obtain decrypted data; and storing the decrypted data in a memory device of the local computing device.

[0174] Aspect 35: A device for offloading encryption services, the device comprising: a unit for receiving a request to provide an encryption service type, the encryption service type comprising decryption of encrypted data, wherein the encrypted data is encrypted by a remote computing device using plaintext data, an encryption key, and an initialization vector (IV); a unit for starting an encryption algorithm in an encryption hardware component of the device in response to receiving the request; a unit for obtaining the encryption key and the IV; a unit for storing the IV in a hardware storage device of the encryption hardware component; a unit for obtaining the encrypted data from a storage device of the device; a unit for executing the encryption algorithm using the encrypted data, the encryption key, and the IV to obtain decrypted data; and a unit for storing the decrypted data in a memory device of the device.

Claims

1. A method for uninstalling an encryption service, the method comprising: receiving a request to provide an encryption service type; Initiating an encryption algorithm in an encryption hardware component, wherein the encryption algorithm is associated with the encryption service type; applying a cryptographic operation to the data to obtain an encrypted result, wherein the cryptographic operation is associated with the cryptographic algorithm; and At least a portion of the cryptographic result is stored in a hardware register of the cryptographic hardware component, wherein the cryptographic result is configured to be used to perform a cryptographic action.

2. The method according to claim 1, wherein: The encryption service type includes an integrity service, the encryption algorithm is a hash algorithm, and the encryption result includes a digest corresponding to the data.

3. The method according to claim 1, further comprising: The encryption action is performed using the encryption result.

4. The method according to claim 3, wherein: Executing the encryption action includes: Obtaining the encryption result from the hardware register of the encryption hardware component; and A comparison between the encryption result and an expected encryption result is performed to determine whether the encryption result matches the expected encryption result.

5. The method according to claim 4, further comprising: determining a match between the encryption result and the expected encryption result; as well as Based on the match between the encryption result and the expected encryption result, it is determined that the data at least partially passes the integrity check.

6. The method according to claim 4, further comprising: determining that the encryption result does not match the expected encryption result; as well as A determination is made that an integrity check on the data fails based on the encryption result not matching the expected encryption result.

7. The method according to claim 6, further comprising: An error register of the cryptographic hardware component is updated with an indication of the failure of the integrity check.

8. The method according to claim 1, wherein: The cryptographic operation is performed during a secure boot process, and wherein the data is at least a portion of an operating system image file.

9. The method according to claim 1, wherein: The cryptographic operation is performed during an integrity check of a block of data, and wherein the data is at least part of a read-only file system.

10. The method according to claim 1, wherein: The cryptographic service type comprises an authenticated cryptographic service, wherein the cryptographic algorithm is an authenticated cryptographic algorithm, and applying the cryptographic operation to obtain the cryptographic result comprises generating a message authentication code (MAC).

11. The method according to claim 10, wherein: Applying the cryptographic operation to the data to obtain the encrypted result further includes encrypting the data using the authenticated encryption algorithm to obtain encrypted data.

12. The method according to claim 11, further comprising: Using the encryption result to perform the encryption action, wherein performing the encryption action comprises: obtaining the MAC from the hardware register of the cryptographic hardware component; and The MAC is stored in persistent memory.

13. The method according to claim 12, wherein: The encrypted data includes encrypted system state information obtained from a memory, and the method further includes: The encrypted data is stored on a non-volatile storage device.

14. The method according to claim 10, wherein: The data is encrypted system state information obtained from a non-volatile storage device, and wherein performing the encryption action comprises: obtaining the MAC from the hardware register of the cryptographic hardware component; and A comparison between the MAC and an expected MAC is performed to determine whether the MAC matches the expected MAC.

15. The method according to claim 14, further comprising: Determining that the MAC matches the expected MAC; determining that an authentication check for the data passes based on the MAC matching the expected MAC; as well as Based on the authentication check passing, the data is decrypted using the encryption algorithm.

16. The method according to claim 14, further comprising: determining that the MAC does not match the expected MAC; determining, based on the MAC not matching the expected MAC, that an authentication check for the data has failed; as well as Based on the authentication check failing, an error register of the cryptographic hardware component is updated with an indication of the authentication check failing.

17. A device for uninstalling an encryption service, comprising: at least one memory; at least one processor; as well as a cryptographic hardware component coupled to the at least one memory and the at least one processor and configured to: receiving a request to provide an encryption service type; Initiating an encryption algorithm in the encryption hardware component, wherein the encryption algorithm is associated with the encryption service type; applying a cryptographic operation to the data to obtain an encrypted result, wherein the cryptographic operation is associated with the cryptographic algorithm; and At least a portion of the cryptographic result is stored in a hardware register of the cryptographic hardware component, wherein the cryptographic result is configured to be used to perform a cryptographic action.

18. The device according to claim 17, wherein: The cryptographic service type includes an integrity service, the cryptographic algorithm is a hash algorithm, and the cryptographic result includes a digest corresponding to the data, and wherein the cryptographic hardware component is further configured to perform the cryptographic action using the cryptographic result, wherein, to perform the cryptographic action, the cryptographic hardware component is further configured to: Obtaining the encryption result from the hardware register of the encryption hardware component; and A comparison between the encryption result and an expected encryption result is performed to determine whether the encryption result matches the expected encryption result.

19. The device according to claim 18, wherein: The cryptographic hardware component is further configured to: determining a match between the encryption result and the expected encryption result; and Based on the match between the encryption result and the expected encryption result, it is determined that the data at least partially passes the integrity check.

20. The device according to claim 18, wherein The cryptographic hardware component is further configured to: determining that the encryption result does not match the expected encryption result; and determining that an integrity check on the data fails based on that the encryption result does not match the expected encryption result; as well as An error register of the cryptographic hardware component is updated with an indication of the failure of the integrity check.

21. The device according to claim 17, wherein: The cryptographic hardware component is configured to perform the cryptographic operation during a secure boot process, and wherein the data is at least a portion of an operating system image file.

22. The device according to claim 17, wherein: The cryptographic hardware component is configured to perform the cryptographic operation during a data block integrity check, and wherein the data is at least part of a read-only file system.

23. The device according to claim 17, wherein: The cryptographic service type comprises an authenticated cryptographic service, wherein the cryptographic algorithm is an authenticated cryptographic algorithm, and wherein, in order to apply the cryptographic operation to obtain the cryptographic result, the cryptographic hardware component is configured to generate a message authentication code (MAC).

24. The device according to claim 23, wherein: In order to apply the cryptographic operation to the data to obtain the cryptographic result, the cryptographic hardware component is configured to: encrypt the data using the authenticated encryption algorithm to obtain encrypted data, and wherein the cryptographic hardware component is further configured to: use the encryption result to perform the cryptographic action.

25. The device according to claim 24, wherein: In order to perform the encryption action, the encryption hardware component is further configured to: obtaining the MAC from the hardware register of the cryptographic hardware component; and The MAC is stored in persistent memory.

26. The device according to claim 25, wherein The encrypted data includes encrypted system state information obtained from a memory, and the cryptographic hardware component is further configured to: The encrypted data is stored on a non-volatile storage device.

27. The device according to claim 23, wherein: The data is encrypted system state information obtained from a non-volatile storage device, and wherein, to perform the cryptographic action, the cryptographic hardware component is further configured to: obtaining the MAC from the hardware register of the cryptographic hardware component; and A comparison between the MAC and an expected MAC is performed to determine whether the MAC matches the expected MAC.

28. The device according to claim 27, wherein The cryptographic hardware component is further configured to: Determining that the MAC matches the expected MAC; determining that an authentication check for the data passes based on the MAC matching the expected MAC; and Based on the authentication check passing, the data is decrypted using the encryption algorithm.

29. The device according to claim 27, wherein: The cryptographic hardware component is further configured to: determining that the MAC does not match the expected MAC; determining, based on the MAC not matching the expected MAC, that an authentication check for the data has failed; as well as Based on the authentication check failing, an error register of the cryptographic hardware component is updated with an indication of the authentication check failing.

30. A method for uninstalling an encryption service, the method comprising: receiving, at a local computing device, a request to provide a type of cryptographic service, the type of cryptographic service comprising decryption of encrypted data, wherein the encrypted data was encrypted by a remote computing device using plaintext data, an encryption key, and an initialization vector (IV); In response to receiving the request, initiating an encryption algorithm in an encryption hardware component of the local computing device; obtaining, by the local computing device, the encryption key and the IV; storing the IV in a hardware storage device of the cryptographic hardware component; obtaining the encrypted data from a storage device of the local computing device; performing the encryption algorithm using the encrypted data, the encryption key, and the IV to obtain decrypted data; and The decrypted data is stored in a memory device of the local computing device.

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