Output circuit of artificial neural network array

Abstract

Numerous examples of an output circuit in an artificial neural network and associated methods are disclosed. In one example, a system includes an array of non-volatile memory cells, the array of non-volatile memory cells being arranged in rows and columns; an output block to convert a current from a column of the array to a first digital output during a first time period and to a second digital output during a second time period; a first output register for storing the first digital output during a first time period and outputting the stored first digital output during a second time period; and a second output register for storing the second digital output during the second time period and outputting the stored second digital output during the third time period.

Description

[0001] Priority declaration

[0002] This application claims priority to U.S. patent application No. 18 / 077,993, filed on December 8, 2022, entitled "Output Circuit for Artificial Neural Network Array," and U.S. Provisional Application No. 63 / 409,140, ​​filed on September 22, 2022, entitled "Input Circuit and Output Circuit for Concurrent and Pipelined Operations in Artificial Neural Network Array." Technical Field

[0003] Many examples of output circuits and associated methods for implementing parallelism and pipelining in artificial neural networks are disclosed. Background Art

[0004] Artificial neural networks simulate biological neural networks (the central nervous system of animals, especially the brain), and are used to estimate or approximate functions that may depend on a large number of inputs and are usually unknown. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages with each other.

[0005] FIG1 illustrates an artificial neural network, where circles represent inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the input and be able to learn. Typically, a neural network includes multiple layers of inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. Neurons at each level make decisions based on data received from the synapses, either individually or collectively.

[0006] One of the main challenges in developing artificial neural networks for high-performance information processing is the lack of adequate hardware technology. In fact, practical neural networks rely on a large number of synapses to achieve high connectivity between neurons, i.e. very high computational parallelism. In principle, this complexity can be achieved by digital supercomputers or clusters of dedicated graphics processing units. However, these approaches, in addition to their high cost, are also mediocre in energy efficiency compared to biological networks, which consume much less energy mainly due to the low-precision analog calculations they perform. CMOS analog circuits have been used for artificial neural networks, but given the large number of neurons and synapses, the synapses of most CMOS implementations are too large.

[0007] Applicant previously disclosed an artificial (simulated) neural network using one or more non-volatile memory arrays as synapses in U.S. Patent Application Publication 2017 / 0337466A1, which is incorporated herein by reference. The non-volatile memory array operates as an analog neural memory and includes non-volatile memory cells arranged in rows and columns. The neural network includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive a first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes: a source region and a drain region spaced apart formed in a semiconductor substrate, wherein a channel region extends between the source region and the drain region; a floating gate disposed above a first portion of the channel region and insulated from the first portion; and a non-floating gate disposed above a second portion of the channel region and insulated from the second portion. Each of the plurality of memory cells stores a weight value corresponding to a plurality of electrons on the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weight values ​​to generate a first plurality of outputs.

[0008] Non-volatile memory cell

[0009] Nonvolatile memory is well known. For example, U.S. Pat. No. 5,029,130 ​​(“the '130 patent”), which is incorporated herein by reference, discloses an array of split-gate nonvolatile memory cells, which is a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2 . Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12 with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A word line terminal 22 (which is typically coupled to a word line) has a first portion disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion extending upward and located over the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line 24 is coupled to the drain region 16.

[0010] Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on word line terminal 22, which causes the electrons on floating gate 20 to tunnel through the intervening insulator via Fowler-Nordheim (FN) tunneling from floating gate 20 to word line terminal 22.

[0011] The memory cell 210 is programmed by source side injection (SSI) with hot electrons (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal 22 and a positive voltage on the source region 14. The electron flow will flow from the drain region 16 to the source region 14. When the electrons reach the gap between the word line terminal 22 and the floating gate 20, the electrons will accelerate and become hot. Due to the electrostatic attraction from the floating gate 20, some of the heated electrons will be injected through the gate oxide onto the floating gate 20.

[0012] The memory cell 210 is read by placing a positive read voltage on the drain region 16 and the word line terminal 22 (which turns on the portion of the channel region 18 below the word line terminal). If the floating gate 20 is positively charged (i.e., the electrons are erased), the portion of the channel region 18 below the floating gate 20 is also turned on, and current will flow through the channel region 18, which is sensed as an erased state or a "1" state. If the floating gate 20 is negatively charged (i.e., programmed by electrons), the portion of the channel region below the floating gate 20 is mostly or completely turned off, and current will not (or very little) flow through the channel region 18, which is sensed as a programmed state or a "0" state.

[0013] Table 1 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 210 for performing read operations, erase operations, and program operations:

[0014] Table 1: Operation of the flash memory unit 210 of FIG. 2

[0015] WL BL SL Read 2V-3V 0.6V-2V 0V Erase About 11V-13V 0V 0V programming 1V-2V 10.5μA-3μA 9V-10V

[0016] Other split gate memory cell configurations are known as other types of flash memory cells. For example, FIG. 3 depicts a four-gate memory cell 310, which includes a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, except for the floating gate 20, all gates are non-floating gates, meaning that they are electrically connected or capable of being electrically connected to a voltage source. Programming is performed by heated electrons from the channel region 18 that inject themselves into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0017] Table 2 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 310 for performing read operations, erase operations, and program operations:

[0018] Table 2: Operation of the flash memory unit 310 of FIG. 3

[0019] WL / SG BL CG EG SL Read 1.0V-2V 0.6V-2V 0V-2.6V 0V-2.6V 0V Erase -0.5V / 0V 0V 0V / -8V 8V-12V 0V programming 1V 0.1μA-1μA 8V-11V 4.5V-9V 4.5V-5V

[0020] FIG4 depicts a tri-gate memory cell 410, which is another type of flash memory cell. Memory cell 410 is the same as memory cell 310 of FIG3, except that memory cell 410 does not have a separate control gate. Erase operations (thus erasing by using an erase gate) and read operations are similar to the operations of FIG3, except that no control gate bias is applied. Program operations are also completed without a control gate bias, and therefore, a higher voltage is applied on the source line during a programming operation to compensate for the lack of a control gate bias.

[0021] Table 3 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 410 for performing read operations, erase operations, and program operations:

[0022] Table 3: Operation of the flash memory unit 410 of FIG. 4

[0023] WL / SG BL EG SL Read 0.7V-2.2V 0.6V-2V 0V-2.6V 0V Erase -0.5V / 0V 0V 11.5V 0V programming 1V 0.2μA-3μA 4.5V 7V-9V

[0024] FIG5 depicts a stacked gate memory cell 510, which is another type of flash memory cell. Memory cell 510 is similar to memory cell 210 of FIG2, except that floating gate 20 extends over the entire channel region 18, and control gate 22 (which here will be coupled to the word line) extends over floating gate 20, separated by an insulating layer (not shown). Erasing is performed by FN tunneling of electrons from the FG to the substrate, programming is performed by channel hot electron (CHE) injection at the region between channel 18 and drain region 16, by electron flow from source region 14 toward drain region 16, and a read operation similar to memory cell 210 with a higher control gate voltage.

[0025] Table 4 depicts typical voltage ranges that may be applied to the terminals of the memory cell 510 and the substrate 12 for performing read operations, erase operations, and program operations:

[0026] Table 4: Operation of the flash memory unit 510 of FIG. 5

[0027] CG BL SL Substrate Read 2V-5V 0.6-2V 0V 0V Erase -8V to -10V / 0V FLT FLT 8-10V / 15-20V programming 8V-12V 3-5V 0V 0V

[0028] The methods and devices described herein can be applied to other non-volatile memory technologies, such as but not limited to FINFET split-gate flash memory or stacked-gate flash memory, NAND flash memory, SONOS (silicon-oxide-nitride-oxide-silicon, charge trapped in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trapped in nitride), ReRAM (resistive RAM), PCM (phase change memory), MRAM (magnetic RAM), FeRAM (ferroelectric RAM), CT (charge trapping) memory, CN (carbon tube) memory, OTP (two-level or multi-level one-time programmable) and CeRAM (correlated electron RAM), etc.

[0029] In order to utilize a memory array comprising one of the above-described types of non-volatile memory cells in an artificial neural network, two modifications are made. First, the circuitry is configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory states of other memory cells in the array, as further explained below. Second, continuous (analog) programming of the memory cells is provided.

[0030] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed from a fully erased state to a fully programmed state, and vice versa, independently and continuously with minimal disturbance to other memory cells. This means that the cell storage device is actually analog, or at least can store one of many discrete values ​​(such as 16 or 64 different values), which allows very precise and individual tuning of all the memory cells in the memory array, and makes the memory array ideal for storing and fine tuning the synaptic weights of a neural network.

[0031] Neural Network Using Non-Volatile Memory Cell Array

[0032] Figure 6 The present example conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array. This example uses a non-volatile memory array neural network for a facial recognition application, but any other suitable application may also be implemented using a neural network based on a non-volatile memory array.

[0033] For this example, S0 is the input layer, which is a 32x32 pixel RGB image with 5 bits of precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with 5 bits of precision per pixel). Synapse CB1 from input layer S0 to layer C1 applies different sets of weights in some cases and shared weights in other cases, and scans the input image with a 3x3 pixel overlapping filter (kernel), shifting the filter by 1 pixel (or more than 1 pixel as the model dictates). Specifically, the values ​​of 9 pixels in the 3x3 portion of the image (i.e., called the filter or kernel) are provided to synapse CB1, where these 9 input values ​​are multiplied by the appropriate weights, and after summing the outputs of the multiplications, a single output value is determined and provided by the first synapse of CB1 for generating a pixel of one of the feature maps of layer C1. The 3x3 filter is then shifted right by one pixel within the input layer S0 (i.e., a column of three pixels on the right is added, and a column of three pixels on the left is released), whereby the 9 pixel values ​​in this newly positioned filter are provided to the synapse CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process continues until the 3x3 filter has scanned all three colors and all bits (precision values) over the entire 32x32 pixel image of the input layer S0. The process is then repeated using different sets of weights to generate different feature maps for layer C1 until all feature maps for layer C1 are calculated.

[0034] At layer C1, in this example, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the product of the input and the kernel, so each feature map is a two-dimensional array, so in this example, layer C1 consists of a two-dimensional array of 16 layers (remember that the layers and arrays referred to in this article are logical relationships, not necessarily physical relationships, that is, arrays do not have to be oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of sixteen different sets of synaptic weights applied to the filter scan. The C1 feature maps can all relate to different aspects of the same image features, such as boundary identification. For example, a first map (generated using a first set of weights, shared for all scans used to generate the first map) can identify circular edges, a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges, or the aspect ratio of certain features, and so on.

[0035] Before passing from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. The purpose of pooling function P1 is to average neighboring positions (or a max function can also be used) to, for example, reduce the dependency of edge positions and reduce the data size before entering the next stage. At layer S1, there are 16 15x15 feature maps (i.e., sixteen different arrays, each with 15x15 pixels). The synapse CB2 from layer S1 to layer C2 scans the map in layer S1 using a 4x4 filter, where the filter is shifted by 1 pixel. At layer C2, there are 22 12x12 feature maps. Before passing from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. At layer S2, there are 22 6x6 feature maps. An activation function (pooling) is applied to synapse CB3 from layer S2 to layer C3, where each neuron in layer C3 is connected to each map in layer S2 via a corresponding synapse of CB3. At layer C3, there are 64 neurons. Synapse CB4 from layer C3 to output layer S3 completely connects C3 to S3, i.e., each neuron in layer C3 is connected to each neuron in layer S3. The output at S3 includes 10 neurons, where the highest output neuron determines the class. For example, the output may indicate an identification or classification of the content of the original image.

[0036] The synapses at each layer are implemented using an array or a portion of an array of non-volatile memory cells.

[0037] Figure 7 A block diagram of an array that can be used for this purpose is shown in FIG. 3. The vector-matrix multiplication (VMM) array 32 includes non-volatile memory cells and serves as a synapse between one layer and the next (such as Figure 6 CB1, CB2, CB3 and CB4 in FIG. 3 ). Specifically, the VMM array 32 includes a nonvolatile memory cell array 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36 and a source line decoder 37, which decode the corresponding inputs of the nonvolatile memory cell array 33. The input to the VMM array 32 may come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the nonvolatile memory cell array 33. Alternatively, the bit line decoder 36 may decode the output of the nonvolatile memory cell array 33.

[0038] The non-volatile memory cell array 33 serves two purposes. First, it stores weights to be used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the input with the weights stored in the non-volatile memory cell array 33 and each output line (source line or bit line) adds them to produce an output, which will serve as the input of the next layer or the input of the final layer. By performing multiplication and addition functions, the non-volatile memory cell array 33 eliminates the need for separate multiplication and addition logic circuits, and is also power efficient due to its in-situ memory calculations.

[0039] The output of the non-volatile memory cell array 33 is provided to a differential summer (such as a summing operational amplifier or a summing current mirror) 38, which sums the output of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform the summing of positive and negative weights.

[0040] The summed output value of the difference summer 38 is then provided to the activation function block 39, which modifies the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The modified output value of the activation function block 39 becomes the next layer (e.g., Figure 6 The elements of the feature map of layer C1 in the image are then applied to the next synapse to produce the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes a plurality of synapses (which receive their inputs from an existing neuron layer or from an input layer such as an image database), and the summing operational amplifier 38 and the activation function block 39 constitute a plurality of neurons.

[0041] Figure 7 The inputs to the VMM array 32 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs may be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0042] Figure 8 1 is a block diagram depicting the use of multiple layers of VMM arrays 32, labeled here as VMM arrays 32a, 32b, 32c, 32d, and 32e. Figure 8As shown, the input (denoted as Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to an input VMM array 32a. The converted analog input may be a voltage or a current. The first level of input D / A conversion may be accomplished by using a function or LUT (lookup table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM array 32a. The input conversion may also be accomplished by an analog-to-analog (A / A) converter to convert an external analog input into a mapped analog input to the input VMM array 32a.

[0043] The output generated by the input VMM array 32a is provided as input to the next VMM array (hidden level 1) 32b, which in turn generates outputs provided as input to the next VMM array (hidden level 2) 32c, and so on. The layers of the VMM array 32 serve as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be an independent physical non-volatile memory array, or multiple VMM arrays can utilize different portions of the same non-volatile memory array, or multiple VMM arrays can utilize overlapping portions of the same physical non-volatile memory array. Figure 8 The example shown includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c) and two fully connected layers (32d, 32e). One of ordinary skill in the art will appreciate that this is merely an example and that, on the contrary, the system may include more than two hidden layers and more than two fully connected layers.

[0044] Vector-Matrix Multiplication (VMM) Array

[0045] Fig. 9 Depicted is a neuron VMM array 900 that is particularly suitable for use with the memory cells 310 shown in FIG. 3 and serves as a synapse and component of neurons between an input layer and the next layer. The VMM array 900 includes a memory array 901 of nonvolatile memory cells and a reference array 902 of nonvolatile reference memory cells (at the top of the array). Alternatively, another reference array may be placed at the bottom.

[0046] In the VMM array 900, control gate lines (such as control gate line 903) extend in the vertical direction (so reference array 902 is orthogonal to control gate line 903 in the row direction), and erase gate lines (such as erase gate line 904) extend in the horizontal direction. Here, the inputs to the VMM array 900 are set on the control gate lines (CG0, CG1, CG2, CG3), and the outputs of the VMM array 900 appear on the source lines (SL0, SL1). In one example, only even rows are used, and in another example, only odd rows are used. The current placed on each source line (SL0, SL1, respectively) performs a summing function of all currents from the memory cells connected to that particular source line.

[0047] As described herein for neural networks, non-volatile memory cells of VMM array 900 (ie, memory cells 310 of VMM array 900 ) may be configured to operate in a sub-threshold region.

[0048] The nonvolatile reference memory cell and the nonvolatile memory cell described herein are biased in weak inversion (subthreshold region):

[0049] Ids=Io*e (Vg-Vth) / nVt =w*Io*e (Vg) / nVt ,

[0050] where w = e (-Vth) / nVt

[0051] Where Ids is the drain to source current; Vg is the gate voltage on the memory cell; Vth is the threshold voltage of the memory cell; Vt is the thermal voltage = k*T / q, where k is the Boltzmann constant, T is the temperature in Kelvin, and q is the electron charge; n is the slope factor = 1+(Cdep / Cox), where Cdep = the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer; Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is related to (Wt / L)*u*Cox*(n-1)*Vt 2 is proportional to , where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0052] For an I to V logarithmic converter that uses a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert the input current into an input voltage:

[0053] Vg=n*Vt*log[Ids / wp*Io]

[0054] Wherein, wp is w of a reference memory cell or a peripheral memory cell.

[0055] For a memory array used as a vector matrix multiplier VMM array with current input, the output current is:

[0056] Iout=wa*Io*e (Vg) / nVt ,Right now

[0057] Iout=(wa / wp)*Iin=W*Iin

[0058] W=e (Vthp-Vtha) / nVt

[0059] Here, wa = w for each memory cell in the memory array.

[0060] Vthp is the effective threshold voltage of the peripheral memory cells, and Vtha is the effective threshold voltage of the main (data) memory cells. Note that the threshold voltage of the transistor is a function of the substrate bulk bias voltage, and the substrate bulk bias voltage, denoted as Vsb, can be modulated to compensate for various conditions at this temperature. The threshold voltage Vth can be expressed as:

[0061]

[0062] where Vth0 is the threshold voltage with zero substrate bias, is the surface potential, and γ is the bulk effect parameter.

[0063] The word line or control gate may be used as the input of the memory cell for the input voltage.

[0064] Alternatively, the flash memory cells of the VMM array described herein may be configured to operate in the linear region:

[0065] Ids=β*(Vgs-Vth)*Vds;β=u*Cox*Wt / L

[0066] W=α(Vgs-Vth)

[0067] This means that the weight W in the linear region is proportional to (Vgs-Vth)

[0068] The word line or control gate or bit line or source line can be used as the input of the memory cell operating in the linear region. The bit line or source line can be used as the output of the memory cell.

[0069] For an IV linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor operating in a linear region may be used to linearly convert an input / output current into an input / output voltage.

[0070] Alternatively, the memory cells of the VMM array described herein may be configured to operate in the saturation region:

[0071] Ids= 1 / 2*β*(Vgs-Vth) 2 ; β=u*Cox*Wt / L

[0072] Wα(Vgs-Vth) 2 , which means weight W and (Vgs-Vth) 2 Proportional

[0073] The word line, control gate, or erase gate can be used as the input of the memory cell operating in the saturation region. The bit line or source line can be used as the output of the output neuron.

[0074] Alternatively, the memory cells of the VMM array described herein may be used for all regions or combinations thereof (subthreshold, linear or saturation regions) of each layer or multiple layers of a neural network.

[0075] U.S. Patent No. 10,748,630 describes Figure 7 Other examples of VMM arrays 32 of , which are incorporated herein by reference. As described herein, source lines or bit lines can be used as neuron outputs (current summing outputs).

[0076] Fig.10 A neuron VMM array 1000 is depicted, which is particularly suitable for the memory cell 210 shown in FIG. 2 and is used as a synapse between the input layer and the next layer. The VMM array 1000 includes a memory array 1003 of nonvolatile memory cells, a reference array 1001 of a first nonvolatile reference memory cell, and a reference array 1002 of a second nonvolatile reference memory cell. The reference arrays 1001 and 1002 arranged in the column direction of the array are used to convert the current input flowing into the terminals BLR0, BLR1, BLR2 and BLR3 into voltage inputs WL0, WL1, WL2 and WL3. In practice, the first nonvolatile reference memory cell and the second nonvolatile reference memory cell are diode-connected through a multiplexer 1014 (only partially depicted), in which the current input flows. The reference cell is tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference microarray matrix (not shown).

[0077] The memory array 1003 serves two purposes. First, it stores the weights that the VMM array 1000 will use on its corresponding memory cells. Second, the memory array 1003 effectively multiplies the inputs (i.e., the current inputs provided in the terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by the reference arrays 1001 and 1002 to be supplied to the word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1003, and then adds all the results (memory cell currents) to produce an output on the corresponding bit lines (BL0-BLN), which will be the input of the next layer or the input of the final layer. By performing multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication logic circuits and addition logic circuits, and is also highly power-efficient. Here, the voltage inputs are provided on the word lines WL0, WL1, WL2, and WL3, and the outputs appear on the corresponding bit lines BL0-BLN during the read (inference) operation. The current placed on each of the bit lines BL0-BLN performs a summing function of the currents from all of the nonvolatile memory cells connected to that particular bit line.

[0078] Table 5 depicts operating voltages and currents for the VMM array 1000. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0079] Table 5: Fig.10 Operation of VMMZ array 1000 :

[0080]

[0081] Fig.11 A neuron VMM array 1100 is depicted, which is particularly suitable for the memory cell 210 shown in FIG. 2 and serves as a synapse and component of a neuron between an input layer and a next layer. The VMM array 1100 includes a memory array 1103 of nonvolatile memory cells, a reference array 1101 of a first nonvolatile reference memory cell, and a reference array 1102 of a second nonvolatile reference memory cell. The reference arrays 1101 and 1102 extend in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that in the VMM array 1100, the word lines extend in the vertical direction. Here, the inputs are set on the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and the outputs appear on the source lines (SL0, SL1) during a read operation. The current placed on each source line performs a summing function of all currents from the memory cells connected to that particular source line.

[0082] Table 6 depicts operating voltages and currents for the VMM array 1100. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0083] Table 6: Fig.11 Operation of the VMM array 1100

[0084]

[0085]

[0086] Fig.12 A neuron VMM array 1200 is depicted, which is particularly suitable for the memory cell 310 shown in FIG. 3 and is used as a synapse and component of a neuron between an input layer and a next layer. The VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of a first nonvolatile reference memory cell, and a reference array 1202 of a second nonvolatile reference memory cell. The reference arrays 1201 and 1202 are used to convert the current input flowing into the terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first nonvolatile reference memory cell and the second nonvolatile reference memory cell are diode-connected through a multiplexer 1212 (only partially shown), wherein the current input flows into them through BLR0, BLR1, BLR2, and BLR3. Multiplexers 1212 each include a respective multiplexer 1205 and cascode transistor 1204 to ensure a constant voltage on a bit line (such as BLR0) of each of the first and second nonvolatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0087] The memory array 1203 serves two purposes. First, it stores weights to be used by the VMM array 1200. Second, the memory array 1203 effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which are converted by reference arrays 1201 and 1202 into input voltages to be provided to the control gates (CG0, CG1, CG2, and CG3)) by the weights stored in the memory array, and then adds all the results (cell currents) to produce an output, which appears at BL0-BLN and will be the input to the next layer or the input to the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly power efficient. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3), and the outputs appear on the bit lines (BL0-BLN) during a read operation. The current placed on each bit line performs a summing function of all currents from the memory cells connected to that particular bit line.

[0088] The VMM array 1200 implements unidirectional tuning of the non-volatile memory cells in the memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is placed on the floating gate (causing an erroneous value to be stored in the cell), the cell is erased and the sequence of partial programming operations restarts. As shown, two rows sharing the same erase gate (such as EG0 or EG1) are erased together (which is called a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

[0089] Table 7 depicts operating voltages and currents for the VMM array 1200. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0090] Table 7: Fig.12 Operation of the VMM array 1200

[0091]

[0092] Fig.13A neuron VMM array 1300 is depicted that is particularly suitable for use with the memory cell 310 shown in FIG. 3 and serves as a synapse and component of a neuron between an input layer and a next layer. The VMM array 1300 includes a memory array 1303 of nonvolatile memory cells, a reference array 1301 of a first nonvolatile reference memory cell, and a reference array 1302 of a second nonvolatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1300 is similar to the VMM array 1400, except that the VMM array 1300 implements bidirectional tuning, where each individual cell can be fully erased, partially programmed, and partially erased as needed to achieve a desired amount of charge on the floating gate due to the use of separate EG lines. As shown, reference arrays 1301 and 1302 convert input currents in terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 to be applied to the memory cells in the row direction (through the action of diode-connected reference cells via multiplexer 1314). The current outputs (neurons) are in bit lines BL0-BLN, where each bit line sums all currents from the non-volatile memory cells connected to that particular bit line.

[0093] Table 8 depicts operating voltages and currents for the VMM array 1300. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0094] Table 8: Fig.13 Operation of the VMM array 1300

[0095]

[0096] Fig. 22 A neuron VMM array 2200 is depicted, which is particularly suitable for the memory unit 210 shown in FIG. 2 and is used as a synapse and component of neurons between an input layer and the next layer. In the VMM array 2200, inputs INPUT0, ..., INPUT N On bit lines BL0, BL NThe signals are received on the source lines SL0, SL1, SL2 and SL3, and outputs OUTPUT1, OUTPUT2, OUTPUT3 and OUTPUT4 are generated on the source lines SL0, SL1, SL2 and SL3, respectively.

[0097] Fig.23 A neuron VMM array 2300 is depicted that is particularly suitable for use with the memory cell 210 shown in FIG. 2 and serves as a synapse and component of neurons between an input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ..., OUTPUT N On the bit lines BL0, BL N Generate on.

[0098] Fig.24 A neuron VMM array 2400 is depicted, which is particularly suitable for the memory unit 210 shown in Figure 2 and is used as a synapse and component of neurons between the input layer and the next layer. In this example, input INPUT0, ..., INPUT M On word lines WL0, ......, WL M is received and output OUTPUT0, ......, OUTPUT N On the bit lines BL0, BL N Generate on.

[0099] Fig.25 Depicted is a neuron VMM array 2500 that is particularly suitable for use with the memory cell 310 shown in FIG. 3 and serves as a synapse and component of neurons between an input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M On word lines WL0, ......, WL M is received and output OUTPUT0, ......, OUTPUT N On the bit lines BL0, BL N Generate on.

[0100] Fig.26 Depicted is a neuron VMM array 2600 that is particularly suitable for use with the memory unit 410 shown in FIG. 4 and serves as a synapse and component of neurons between an input layer and the next layer. In this example, inputs INPUT0, ..., INPUT n On the vertical control gate lines CG0, CG NThe signals are received on the source lines SL0 and SL1, and outputs OUTPUT1 and OUTPUT2 are generated on the source lines SL0 and SL1.

[0101] Fig. 27 Depicted is a neuron VMM array 2700 that is particularly suitable for use with the memory unit 410 shown in FIG. 4 and serves as a synapse and component of neurons between an input layer and the next layer. In this example, inputs INPUT0, ..., INPUT N are received at the gates of bit line control gates 2701-1, 2701-2, ..., 2701-(N-1), and 2701-N, which are respectively coupled to bit lines BL0, ..., BL N Example outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0102] Fig.28 Depicted is a neuron VMM array 2800 that is particularly suitable for use with memory cells 310 shown in FIG. 3 , memory cells 510 shown in FIG. 5 , and Figure 7 The memory unit 710 shown in FIG. 1 is used as a synapse and a component of a neuron between an input layer and a next layer. In this example, inputs INPUT0, . . . , INPUT M On word lines WL0, . . . , WL M is received and output OUTPUT0, ......, OUTPUT N On bit lines BL0, BL N Generate on.

[0103] Fig.29 Depicted is a neuron VMM array 2900 that is particularly suitable for use with memory cells 310 shown in FIG. 3 , memory cells 510 shown in FIG. 5 , and Figure 7 The memory unit 710 shown in FIG. 1 is used as a synapse and a component of a neuron between an input layer and a next layer. In this example, inputs INPUT0, . . . , INPUT M On the control gate lines CG0, CG M OUTPUT0, OUTPUT1, OUTPUT2, OUTPUT3, OUTPUT4 N On the vertical source lines SL0, SL N Each source line SL i The source line coupled to all memory cells in column i.

[0104] Fig.30Depicted is a neuron VMM array 3000, which is particularly suitable for use with memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and Figure 7 The memory unit 710 shown in FIG. 1 is used as a synapse and a component of a neuron between an input layer and a next layer. In this example, inputs INPUT0, . . . , INPUT M On the control gate lines CG0, CG M OUTPUT0, OUTPUT1, OUTPUT2, OUTPUT3, OUTPUT4 N On the vertical bit lines BL0, BL N On the generation, each bit line BL i The bit line coupled to all memory cells in column i.

[0105] Long Short-Term Memory

[0106] Prior art includes a concept called long short-term memory (LSTM). LSTM cells are commonly used in neural networks. LSTM allows a neural network to remember information for a predetermined arbitrary time interval and use the information in subsequent operations. A conventional LSTM cell includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the time interval at which information is remembered in the LSTM. VMMs are particularly useful in LSTM cells.

[0107] FIG. 14 depicts an example LSTM 1400. The LSTM 1400 in this example includes units 1401, 1402, 1403, and 1404. Unit 1401 receives an input vector x0 and generates an output vector h0 and a unit state vector c0. Unit 1402 receives an input vector x1, an output vector (hidden state) h0 from unit 1401, and a unit state c0 from unit 1401, and generates an output vector h1 and a unit state vector c1. Unit 1403 receives an input vector x2, an output vector (hidden state) h1 from unit 1402, and a unit state c1 from unit 1402, and generates an output vector h2 and a unit state vector c2. Unit 1404 receives an input vector x3, an output vector (hidden state) h2 from unit 1403, and a unit state c2 from unit 1403, and generates an output vector h3. Additional units may be used, and an LSTM with four units is merely an example.

[0108] Figure 15 depicts an example implementation of an LSTM cell 1500 that may be used for cells 1401, 1402, 1403, and 1404 in Figure 14. LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and generates a cell state vector c(t) and an output vector h(t).

[0109] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control how much of each component in the input vector is allowed to pass through to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors together, and an addition device 1509 for adding two vectors together. The output vector h(t) can be provided to the next LSTM cell in the system, or it can be accessed for other purposes.

[0110] Fig.16 LSTM cell 1600 is depicted, which is an example of a specific implementation of LSTM cell 1500. For the convenience of the reader, the same numbering as LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function devices 1501, 1502 and 1503 and tanh device 1504 each include multiple VMM arrays 1601 and activation function blocks 1602. Therefore, it can be seen that VMM arrays are particularly useful in LSTM cells used in certain neural network systems. Multiplier devices 1506, 1507 and 1508 and addition device 1509 are implemented digitally or in analog. Activation function block 1602 can be implemented digitally or in analog.

[0111] An alternative form of LSTM cell 1600 (and another example of a specific implementation of LSTM cell 1500) is Fig.17 In Fig.17, the sigmoid function devices 1501, 1502 and 1503 and the tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-division multiplexing manner. The LSTM unit 1700 also includes a multiplier device 1703 for multiplying two vectors together, an addition device 1708 for adding two vectors together, a tanh device 1505 (which includes an activation function block 1702), a register 1707 for storing the value i(t) when the value i(t) is output from the sigmoid function block 1702, a register 1704 for storing the value f(t)*c(t-1) when the value is output from the multiplier device 1703 through the multiplexer 1710, a register 1705 for storing the value i(t)*u(t) when the value is output from the multiplier device 1703 through the multiplexer 1710, and a register 1706 for storing the value o(t)*c~(t) when the value is output from the multiplier device 1703 through the multiplexer 1710, and a multiplexer 1709.

[0112] LSTM cell 1600 includes multiple sets of VMM arrays 1601 and corresponding activation function blocks 1602, while LSTM cell 1700 includes only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in the example of LSTM cell 1700. LSTM cell 1700 will require less space than LSTM 1600 because LSTM cell 1700 only requires 1 / 4 of its space for VMM and activation function blocks compared to LSTM cell 1600.

[0113] It is also understood that the LSTM cell will typically include multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside the VMM array (such as summers and activation function blocks and high voltage generation blocks). Providing a separate circuit block for each VMM array would require a large amount of space within the semiconductor device and would be inefficient to a certain extent. Therefore, the examples described below reduce the circuitry required outside the VMM array itself.

[0114] Gate Controlled Recursive Unit

[0115] The simulated VMM implementation can be used for a Gated Recurrent Unit (GRU) system. GRU is a gate mechanism in a recurrent neural network. GRU is similar to LSTM, except that a GRU cell generally contains fewer components than an LSTM cell.

[0116] FIG. 18 depicts an example GRU 1800. The GRU 1800 in this example includes units 1801, 1802, 1803, and 1804. Unit 1801 receives an input vector x0 and generates an output vector h0. Unit 1802 receives an input vector x1, an output vector h0 from unit 1801, and generates an output vector h1. Unit 1803 receives an input vector x2 and an output vector (hidden state) h1 from unit 1802 and generates an output vector h2. Unit 1804 receives an input vector x3 and an output vector (hidden state) h2 from unit 1803 and generates an output vector h3. Additional units may be used, and a GRU with four units is merely an example.

[0117] FIG. 19 depicts an example implementation of a GRU cell 1900 that may be used for cells 1801, 1802, 1803, and 1804 of FIG. 18. GRU cell 1900 receives an input vector x(t) and an output vector h(t-1) from a previous GRU cell, and generates an output vector h(t). GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to components from the output vector h(t-1) and the input vector x(t). GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, a plurality of multiplier devices 1904, 1905, and 1906 for multiplying two vectors together, an addition device 1907 for adding two vectors together, and a complement device 1908 for subtracting the input from 1 to generate an output.

[0118] Fig. 20 A GRU unit 2000 is depicted, which is an example of a specific implementation of the GRU unit 1900. For the convenience of the reader, the same numbering is used in the GRU unit 2000 as in the GRU unit 1900. Fig. 20 As can be seen in FIG. 1 , sigmoid function devices 1901 and 1902 and tanh device 1903 each include multiple VMM arrays 2001 and activation function blocks 2002. Therefore, it can be seen that the VMM array is particularly useful in the GRU unit used in some neural network systems. Multiplier devices 1904, 1905 and 1906, addition device 1907 and complementary device 1908 are implemented in digital or analog form. Activation function block 2002 can be implemented in digital or analog form.

[0119] An alternative form of GRU unit 2000 (and another example of a specific implementation of GRU unit 1900) is Fig.21 In Fig.21In , the GRU unit 2100 utilizes a VMM array 2101 and an activation function block 2102 which, when configured as a sigmoid function, applies a number between 0 and 1 to control how much of each component in the input vector is allowed to pass through to the output vector. Fig.21 , the sigmoid function devices 1901 and 1902 and the tanh device 1903 share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-division multiplexing manner. The GRU unit 2100 also includes a multiplier device 2103 for multiplying two vectors together, an addition device 2105 for adding two vectors together, a complementary device 2109 for subtracting an input from 1 to generate an output, a multiplexer 2104, a register 2106 for holding the value h(t-1)*r(t) when it is output from the multiplier device 2103 through the multiplexer 2104, a register 2107 for holding the value h(t-1)*z(t) when it is output from the multiplier device 2103 through the multiplexer 2104, and a register 2108 for holding the value h^(t)*(1-z(t)) when it is output from the multiplier device 2103 through the multiplexer 2104.

[0120] The GRU unit 2000 includes multiple sets of VMM arrays 2001 and activation function blocks 2002, while the GRU unit 2100 includes only one set of VMM arrays 2101 and activation function blocks 2102, which are used to represent multiple layers in the example of the GRU unit 2100. The GRU unit 2100 will require less space than the GRU unit 2000 because the GRU unit 2100 only requires 1 / 3 of its space for the VMM and activation function blocks compared to the GRU unit 2000.

[0121] It will also be appreciated that a GRU system will typically include multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside the VMM array (such as summers and activation function blocks and high voltage generation blocks). Providing a separate circuit block for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the examples described below reduce the circuitry required outside the VMM array itself.

[0122] The inputs to the VMM array can be analog levels, binary levels, pulses, time-modulated pulses, or digital bits (in which case a DAC is required to convert the digital bits to the appropriate input analog levels), and the outputs can be analog levels, binary levels, timed pulses, pulses, or digital bits (in which case an output ADC is required to convert the output analog levels to digital bits).

[0123] In general, for each memory cell in the VMM array, each weight W can be implemented by a single memory cell or by a differential cell or by two hybrid memory cells (average of 2 cells). In the case of a differential cell, two memory cells are required to implement the weight W as a differential weight (W=W+-W-). In two hybrid memory cells, two memory cells are required to implement the weight W as the average of the two cells.

[0124] Fig.31 A VMM system 3100 is depicted. In some examples, the weights W stored in the VMM array are stored as a differential pair W+ (positive weight) and W- (negative weight), where W=(W+)-(W-). In the VMM system 3100, half of the bit lines are designated as W+ lines, i.e., bit lines connected to memory cells that will store positive weights W+, and the other half of the bit lines are designated as W- lines, i.e., bit lines connected to memory cells that implement negative weights W-. The W- lines are interspersed between the W+ lines in an alternating manner. The subtraction operation is performed by a summing circuit (such as summing circuits 3101 and 3102), which receives current from the W+ line and the W- line. The output of the W+ line and the output of the W- are combined together to effectively give W=W+-W- for each (W+, W-) cell pair of all (W+, W-) line pairs. Although described above with respect to W- lines interspersed between W+ lines in an alternating manner, in other examples, the W+ lines and W- lines may be arbitrarily located anywhere in the array.

[0125] Fig.32 Another example is depicted. In VMM system 3210 , positive weights W+ are implemented in a first array 3211 , and negative weights W− are implemented in a second array 3212 , which is separate from the first array, and the resulting weights are appropriately combined together by summing circuit 3213 .

[0126] Fig.33A VMM system 3300 is depicted, in which the weights W stored in the VMM array are stored as a differential pair W+ (positive weight) and W- (negative weight), where W=(W+)-(W-). The VMM system 3300 includes an array 3301 and an array 3302. Half of the bit lines in each of the arrays 3301 and 3302 are designated as W+ lines, i.e., bit lines connected to memory cells that will store positive weights W+, and the other half of the bit lines in each of the arrays 3301 and 3302 are designated as W- lines, i.e., bit lines connected to memory cells that implement negative weights W-. The W- lines are interspersed between the W+ lines in an alternating manner. The subtraction operation is performed by a summing circuit (such as summing circuits 3303, 3304, 3305, and 3306), which receives current from the W+ lines and the W- lines. The outputs of the W+ lines and the outputs of the W- lines from each array 3301, 3302 are combined together to effectively give W=W+-W- for each (W+, W-) cell pair for all (W+, W-) line pairs. In addition, the W values ​​from each array 3301 and 3302 can be further combined by summing circuits 3307 and 3308 so that each W value is the result of subtracting the W value from array 3301 from the W value from array 3302, which means that the final result from summing circuits 3307 and 3308 is a difference of two difference values.

[0127] Each nonvolatile memory cell used in an analog neural memory system is erased and programmed to hold a very specific and precise amount of charge (i.e., number of electrons) in the floating gate. For example, each floating gate should hold one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0128] Prior art VMM systems require considerable area and involve considerable delays in both the input and output stages. At the input stage, multiple clock cycles are required to load activation data into the row register prior to the programming operation. For example, for 8-bit I / O, 8 bits of activation data are required per row, and there are typically 1024 rows or more, requiring one clock cycle per row, and if there are 1024 rows, 1024 clock cycles are required, resulting in delays between 10ns and 10μs. In the output stage, there is also delay involved in shifting out the neuron output data. For example, for a 128ADC, 128 clocks are required for 8-bit output.

[0129] It is desirable to reduce the delays at both the input and output stages to increase the overall operating speed of the artificial neural network. Summary of the invention

[0130] Many examples of output circuits and associated methods for implementing parallelism and pipelining in artificial neural networks are disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0131] FIG. 1 is a diagram illustrating an example of an artificial neural network.

[0132] FIG. 2 depicts a prior art split-gate flash memory cell.

[0133] FIG. 3 depicts another prior art split gate flash memory cell.

[0134] FIG. 4 depicts another prior art split gate flash memory cell.

[0135] FIG. 5 depicts another prior art split gate flash memory cell.

[0136] Figure 6 A diagram illustrating different levels of an exemplary artificial neural network utilizing one or more non-volatile memory arrays.

[0137] Figure 7 FIG. 1 is a block diagram illustrating a VMM system.

[0138] Figure 8 is a block diagram illustrating an example artificial neural network utilizing one or more VMM systems.

[0139] Fig. 9 Another example of a VMM system is depicted.

[0140] Fig.10 Another example of a VMM system is depicted.

[0141] Fig.11 Another example of a VMM system is depicted.

[0142] Fig.12 Another example of a VMM system is depicted.

[0143] Fig.13 Another example of a VMM system is depicted.

[0144] FIG. 14 depicts a prior art long short term memory system.

[0145] FIG. 15 depicts an example cell for use in a long short term memory system.

[0146] Fig.16 An example implementation of the unit of FIG. 15 is depicted.

[0147] Fig.17 Another example implementation of the unit of FIG. 15 is depicted.

[0148] FIG. 18 depicts a prior art gate-controlled recursive cell system.

[0149] FIG. 19 depicts an example cell for use in a gate-controlled recursive cell system.

[0150] Fig. 20 An example implementation of the unit of FIG. 19 is depicted.

[0151] Fig.21 Another example implementation of the unit of FIG. 19 is depicted.

[0152] Fig. 22 Another example of a VMM system is depicted.

[0153] Fig.23 Another example of a VMM system is depicted.

[0154] Fig.24 Another example of a VMM system is depicted.

[0155] Fig.25 Another example of a VMM system is depicted.

[0156] Fig.26 Another example of a VMM system is depicted.

[0157] Fig. 27 Another example of a VMM system is depicted.

[0158] Fig.28 Another example of a VMM system is depicted.

[0159] Fig.29 Another example of a VMM system is depicted.

[0160] Fig.30 Another example of a VMM system is depicted.

[0161] Fig.31 Another example of a VMM system is depicted.

[0162] Fig.32 Another example of a VMM system is depicted.

[0163] Fig.33 Another example of a VMM system is depicted.

[0164] Fig.34 Another example of a VMM system is depicted.

[0165] Fig.35A and Fig.35B Depicted are input blocks for a VMM system.

[0166] Fig.36 Depicted are input blocks for a VMM system.

[0167] Fig.37A and Fig.37BSignals associated with input operations for a VMM array are depicted.

[0168] Fig.38A Depicted are input blocks for a VMM system.

[0169] Fig.38B Describes an input method.

[0170] Fig.39A , Fig.39B , Fig.39C and Fig.39D Depicted are input blocks for a VMM system.

[0171] Fig.40A Depicted are output blocks for a VMM system.

[0172] Fig.40B Depicted are output blocks for a VMM system.

[0173] Fig.40C Depicted are output blocks for a VMM system.

[0174] Fig.41 Waveforms for a VMM system are depicted.

[0175] Fig.42 Waveforms for a VMM system are depicted.

[0176] Fig.43 Waveforms for a VMM system are depicted.

[0177] Fig.44 Waveforms for a VMM system are depicted.

[0178] Fig.45 A neural readout operation method is depicted.

[0179] Fig.46 A neural readout operation method is depicted.

[0180] Fig.47 A neural readout operation method is depicted.

[0181] Fig.48 A neural readout operation method is depicted.

[0182] Fig.49 A neural readout operation method is depicted. DETAILED DESCRIPTION

[0183] VMM system architecture

[0184] Fig.34Depicted is a block diagram of a VMM system 3400. The VMM system 3400 includes a VMM array 3401, a row decoder 3402, a high voltage decoder 3403, a column decoder 3404, a bit line driver 3405 (such as a bit line control circuit for programming), an input circuit 3406, an output circuit 3407, a control logic component 3408, and a bias generator 3409. The VMM system 3400 also includes a high voltage generation block 3410, which includes a charge pump 3411, a charge pump regulator 3412, and a high voltage level generator 3413. The VMM system 3400 also includes a (programming / erasing or weight tuning) algorithm controller 3414, an analog circuit 3415, a control engine 3416 (which may include special functions such as arithmetic functions, activation functions, embedded microcontroller logic, but is not limited to such), a test control logic unit 3417, and a static random access memory (SRAM) block 3418 to store intermediate data such as for input circuits (e.g., activation data) or output circuits (neuron output data, partial and output neuron data) or data for programming (such as data for an entire row or multiple rows).

[0185] The input circuit 3406 may include various circuits such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter, digital-to-time modulated pulse converter), an AAC (analog-to-analog converter, such as a current-to-voltage converter, a logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 3406 may implement one or more of normalization, linear or nonlinear up / down scaling functions, or arithmetic functions. The input circuit 3406 may implement a temperature compensation function for the input level. The input circuit 3406 may implement an activation function such as a ReLU or a sigmoid. The input circuit 3406 may store digital activation data to be applied as an input signal or combined with an input signal during a programming or read operation. The digital activation data may be stored in a register. The input circuit 3406 may include circuits for driving array terminals, such as CG, WL, EG, and SL lines, which may include sample-and-hold circuits and buffers. The DAC may be used to convert the digital activation data into an analog input voltage to be applied to the array.

[0186] Output circuit 3407 may include circuits such as ITV (current voltage circuit), ADC (analog-to-digital converter, for converting neuron analog output into digital bits), AAC (analog-to-analog converter, such as current-voltage converter, logarithmic converter), APC (analog-to-pulse converter, analog-to-time modulated pulse converter), or any other type of converter. Output circuit 3407 may convert the array output into activation data. Output circuit 3407 may implement an activation function, such as a rectified linear activation function (ReLU) or sigmoid. Output circuit 3407 may implement one or more of statistical normalization, regularization, up / down scaling / gain function, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm) for the neuron output. Output circuit 3407 may implement a temperature compensation function for the neuron output or array output (such as a bit line output) to keep the power consumption of the array approximately constant, or to improve the accuracy of the array (neuron) output, such as by keeping the IV slope approximately the same over temperature. The output circuit 3407 may include a register for storing output data.

[0187] Fig.35A An input block 3500 for providing input to a VMM array 3401 is depicted. The input block 3500 includes a global digital-to-analog converter (DAC) 3501; row registers 3502-0 to 3502-n, each corresponding to one of the rows numbered 0 to n in the array; digital comparator blocks 3503-0 to 3503-n, each corresponding to one of the rows numbered 0 to n in the array; row sample-and-hold buffers 3504-0 to 3504-n, each corresponding to one of the rows numbered 0 to n in the array; and output signals 3505-0 to 3505-n, each corresponding to one of the rows numbered 0 to n in the array, and represented as CGIN0, CGIN 1, ..., CGINn-1, and CGINn, respectively. The signal GDACsup is a global DAC signal provided by the global DAC 3501. The signals CGIN0 to CGINn are coupled to the respective row inputs of the array 3401. CLKDAC is the input clock of GDAC, which is used to provide analog output values. In one example, these analog output values ​​correspond to counts of CLKDAC clock.

[0188] The digital comparator block 3503 compares the value stored in the associated row register 3502 with the signal CLKCOUNTx. CLKCOUNTx is the result of the counter counting the clock signal during a predetermined interval; if a match occurs, the corresponding row S / H 3504 is enabled by the corresponding digital comparator block 3503 to sample the value from the global DAC 3501 into the corresponding row S / H buffer. This technique will be referred to as global row DAC sampling. As described above, each row in the VMM array 3401 has a corresponding row register 3502, a digital comparator block 3503, and a row S / H 3504.

[0189] During operation, the row registers 3502-0 to 3502-n are loaded with the digital input bits DINx for that particular row (where x is the number of bits, such as 8 or 16 bits) and receive a clock signal CLK. The CLK signal is used to load data from the digital input bits DINx into the corresponding row registers 3502-x. The global DAC 3501 is shared by all rows and performs digital-to-analog conversion on the digital bits DINx stored in the particular row registers 3502 in a time-division multiplexed manner. The conversion is completed by comparing the digital input bits of a particular row with the signal CLKCOUNTx (which is a digital count value) by each of the digital comparator blocks 3503. When the digital count value of the signal CLKCOUNTx matches the content of the corresponding row register 3502, the corresponding row sample-and-hold buffer 3504 for that row samples the analog output from the global DAC 3501 and holds the value, which is then applied as the output signal 3505 for that particular row. The output signal 3504 may be applied to, for example, a control gate line or a word line or an erase gate in the manner described above with respect to other figures during a programming operation in that particular row.

[0190] Alternatively, the row sample and hold buffer 3504 may be shared between two or more rows by time division multiplexing the row sample and hold buffer.

[0191] Fig.35BAn input block 3550 is depicted for providing input to the VMM array 3401. The input block 3550 includes a global digital-to-analog converter (DAC) 3551; row registers 3552-0 to 3552-n, each corresponding to one of the rows numbered 0 to n in the VMM array 3401; digital multiplexer (mux) blocks 3553-0 to 3553-n, each corresponding to one of the rows numbered 0 to n; row sample-and-hold (S / H) buffers 3554-0 to 3554-n, each corresponding to one of the rows numbered 0 to n; and output signals 3555-0 to 3555-n, denoted as CGIN0, CGIN1, ..., CGINn-1, and CGINn, each corresponding to one of the rows numbered 0 to n. The digital multiplexer block 3553 is used to multiplex the data of the corresponding row register 3552 into the bus GDAC_DINx, which is applied as an input to the global DAC 3551. The corresponding row S / H buffer 3554 samples the value from the global DAC into the local S / H buffer 3554. Each row has its own row register 3552, S / H buffer 3554 and output signal 3555.

[0192] During operation, the row registers 3552-0 to 3552-n are loaded with the digital input bits DINx for the particular row (where x is the number of bits, such as 8 or 16 bits) and receive a clock signal CLK. The CLK signal is used to load data from the digital input bits DINx into the corresponding row registers 3552. The global digital-to-analog converter 3551 is shared by all rows and performs digital-to-analog conversion on the digital bits DINx stored in the particular row registers 3552 in a time-division multiplexed manner. The conversion is completed by time-division multiplexing the data of the row registers to the data input terminal (bus GDAC_DINx) of the global DAC 3551. The multiplexing of the row register data to the data input bus GDAC_DINx is enabled by the corresponding enable signal EN-x 3557-x of each row. The corresponding row sample-and-hold buffer 3554 samples the analog output from the global DAC 3551 and holds the value, which is then applied as the output signal 3555 of the particular row. Output signal 3555 may be applied to, for example, a control gate line or a word line during a programming operation in that particular row in the manner described above with respect to other figures.

[0193] Alternatively, the row sample and hold buffer 3554 may be shared among multiple rows by time division multiplexing the row sample and hold buffer.

[0194] Fig.36An input block 3600 for providing input to the VMM array 3401 is depicted. . The input block 3600 includes two global DACs 3601-0 and 3601-1; row registers 3602-0 to 3602-n, each corresponding to one of the rows numbered 0 to n in the VMM array 3401; digital comparator blocks 3603 to 3603-n, each corresponding to one of the rows numbered 0 to n in the VMM array 3401; row sample-and-hold buffers 3604-0 to 3604-n, each corresponding to one of the rows numbered 0 to n in the VMM array 3401; and output signals 3605-0 to 3605-n, denoted as CGIN0, CGIN1, ..., CGINn-1, and CGINn, each corresponding to one of the rows numbered 0 to n. The digital comparator block 3603 compares the value stored in the corresponding row register 3602 with the signal CLKCOUNTx, which is the result of a counter counting the clock signal during a predetermined interval. When the digital count value of the signal CLKCOUNTx matches the content of the corresponding row register 3602, the corresponding row S / H buffer 3604 is enabled to sample the value from the global DAC 3601 into the corresponding S / H buffer 3604. Each row has its own row register 3602, digital comparator block 3603 and row S / H buffer 3604.

[0195] During operation, row registers 3602-0 to 3602-n are loaded with digital input bits DINx for the associated row (where x is the number of bits, such as 8 or 16 bits) and receive a clock signal CLK. The CLK signal is used to load data from the digital input bits DINx into row registers 3602-x. Global DAC 3601 (composed of multiple global DACs, such as 3601-0 and 3601-1) is shared by all rows. In one example, global DAC 3601-0 operates on even rows, and global DAC 3601-1 operates on odd rows. Global DAC 3601 receives a clock signal CLKDAC and outputs an analog value corresponding to the count of the CLKDAC clock. . Global DAC 3601 performs digital-to-analog conversion (via GDAC_DINx bus) on the digital bits DINx stored in the associated row register 3602. The corresponding row sample and hold buffer 3604 for that row samples the analog output from the global digital to analog converter 3601 and holds the value, which is then applied as the output signal 3605 for that particular row. The output signal 3605 may be applied to, for example, a control gate line or a word line during a programming operation in that particular row or rows in the manner described above with respect to other figures.

[0196] Fig.37A Waveform 3700 is depicted, which illustrates the Fig.35A The row sample and hold buffer 3504 in Fig.35B The row sample and hold buffer 3554 or Fig.36 Example voltage levels for outputs CGIN0 and CGIN1 after row sample and hold buffer 3604 in response to corresponding sample and hold actions of GDACsup 3701. Signal GDACsup 3701 is a supply voltage from a global DAC, such as from Fig.35A Global DAC 3501 in Fig.35B The global DAC 3551 in Fig.36 3701 is a linear DAC voltage curve, i.e., the global DAC output represents a linear conversion of the digital input value to the analog value. This linear translation is suitable for memory cells operating in the linear region. As an example, signal 3702 shows the sampled voltage value (level) on row 0 (CGIN0), and signal 3703 shows the sampled voltage value (level) on row 1 (CGIN1). Signal DAC_sampling_en 3704 is a control signal that enables the sample and hold operation. Four examples of sampling are shown at edges 3705, 3706, 3707, and 3708, corresponding to the different voltages being sampled.

[0197] Fig.37B Waveform 3720 is depicted, which illustrates the Fig.35A The row sample and hold buffer 3504 in Fig.35B The row sample and hold buffer 3554 or Fig.36 Example logarithmic voltage levels for outputs CGIN0 and CGIN1 following the row sample and hold buffer 3604 in response to the corresponding sample and hold action of GDACsup 3721. The use of logarithmic conversion of digital input values ​​to analog values ​​is applicable to memory cells operating in the subthreshold region. Alternatively, it can be used for memory cells operating in the saturation region. Signal GDACsup 3721 is a supply voltage from a global DAC, such as from Fig.35A Global DAC 3501 in Fig.35B The global DAC 3551 in Fig.363721 is a logarithmic DAC curve. As an example, signal 3722 shows the sampled voltage value (level) on row 0 (CGIN0), and signal 3723 shows the sampled voltage value (level) on row 1 (CGIN1). Signal DAC_sampling_en 3724 is a control signal that enables the sample and hold operation. Four examples of sampling are shown at edges 3725, 3726, 3727, and 3728, corresponding to the different voltages being sampled.

[0198] The smart DAC sampling method is as follows. Fig.37A and Fig.37B As shown, sampling enable is done only on the row register for a particular input operation, which means that sampling is enabled at the first minimum value of the row register and ends at the maximum value of the row register. This is to reduce the sampling time required based only on the range of input values ​​on the row register (i.e., the value that activates the input).

[0199] Additionally, if a maximum number of rows are enabled for sampling at one time, for example 128 rows at most, then if 180 rows are allowed for the same input value, sampling will occur twice, 1st for 128 rows and 2nd for 62 rows, or alternatively 1st sampling time for 90 rows and 2nd sampling time for 90 rows. This is to reduce the load on the sampling circuitry in case a large load causes an undesirable settling time.

[0200] FIG. 38 depicts an input block 3800 for use with a VMM array 3401. The input block 3800 includes a sub-block 3810, an SRAM 3418, registers 3801-0, 3801-1, ..., 3801-n, and address decoders 3804-0, 3804-1, ..., 3804-n. The sub-block 3810 optionally includes registers from Fig.35A , Fig.35B and Fig.36 One of the input blocks 3500, 3550 and 3600. Fig.35A , Fig.35B and Fig.36, as the case may be, the sub-block 3810 includes registers 3802-0, 3802-1, ..., 3802-n and row sample-and-hold buffers 3803-0, 3803-1, ..., 3803-n and circuits therebetween. In the case where the sub-block 3810 includes the input block 3500, the register 3802 includes the row register 3502, and the row sample-and-hold buffer 3803 includes the row sample-and-hold buffer 3504. In the case where the sub-block 3810 includes the input block 3550, the register 3802 includes the row register 3552, and the row sample-and-hold buffer 3803 includes the row sample-and-hold buffer 3554. In the case where the sub-block 3810 includes the input block 3600, the register 3802 includes the row register 3602, and the row sample-and-hold buffer 3803 includes the row sample-and-hold buffer 3604.

[0201] The address decoder 3804 receives the address of the data input load operation to load data into register 3802 or register 3801. The data is activation data or input data such as from an object or image to be classified or recognized in a neural network application. It outputs a signal enabling register 3801 or register 3802, which indicates which register is asserted for the data input load operation. The data input of (not shown) typically varies between 8 bits and 256 bits.

[0202] Address decoder 3804 also receives an address for a read-verify or program operation and outputs a signal to register 3801 or register 3802 indicating which row or rows are asserted for the read-verify or program operation. Read-verify is a read operation used in weight tuning where a cell is programmed to a target current representing a target weight in a neural network and the cell current is then verified to ensure that it is close to the target current during the weight tuning algorithm.

[0203] Registers 3802 enable the activation data stored in each such register to enable row sample and hold buffers 3803. In an example implementation, registers 3802 may have 1024 rows and 1024 instances, with each register 3802 storing 8 bits of activation data.

[0204] To load data into register 3802, the number of clock cycles R required is R = number of rows x 8 (for 8-bit active data) divided by the data width, e.g. 16-bit data input (e.g. R = 1024*8 / 16 = 512).

[0205] Register 3801 includes a register coupled to and associated with each register 3802. Each register 3801 is loaded with activation data of its associated register 3802, which can be performed sequentially within R clock cycles. Thereafter, during the first clock cycle, data from each register 3801 is loaded in parallel into its associated register 3802. Therefore, registers 3802 are loaded in parallel from corresponding registers 3801 within a single time period, rather than serially loaded within R clock cycles. This greatly speeds up the timing of data in the data input load operation.

[0206] Optionally, SRAM 3418 may be used to sequentially load all registers 3802 as a background operation during R clock cycles.

[0207] Optionally, SRAM 3418 is used to sequentially load registers 3801 with its data.

[0208] Fig.38B Describes the use of Fig.38A An input method 3850 is performed by an input block 3800 of the present invention. A first operation is outputting a plurality of row enable signals (3851) by a plurality of address decoders in response to an address. A next operation is sequentially storing activation data (3852) by a first plurality of registers in response to the plurality of row enable signals. The sequential storing optionally includes receiving activation data from a static random access memory by the first plurality of registers. A next operation is storing activation data received from the first plurality of registers in parallel by a second plurality of registers (3853). A next operation is driving rows of a nonvolatile memory cell array during a read neuron operation by a plurality of row sample-and-hold buffers in response to the activation data received from the second plurality of registers (3854).

[0209] Fig.39A Input block 3900 is depicted. Input block 3900 includes sub-block 3910, VMM array 3401, and address decoders 3904-0, 3904-1, ..., 3904-n. Sub-block 3910 optionally includes Fig.35A , Fig.35B and Fig.36 One of the input blocks 3500, 3550 and 3600. Fig.35A , Fig.35B and Fig.36, as the case may be, the sub-block 3910 includes row registers 3902-0, 3902-1, ..., 3902-n and row sample-and-hold buffers 3903-0, 3903-1, ..., 3903-n and circuits therebetween. In the case where the sub-block 3910 includes the input block 3500, the row register 3902 includes the row register 3502, and the row sample-and-hold buffer 3803 includes the row sample-and-hold buffer 3504. In the case where the sub-block 3910 includes the input block 3550, the row register 3902 includes the row register 3552, and the row sample-and-hold buffer 3903 includes the row sample-and-hold buffer 3554. In the case where the sub-block 3910 includes the input block 3600, the row register 3902 includes the row register 3602, and the row sample-and-hold buffer 3903 includes the row sample-and-hold buffer 3604.

[0210] The address decoder 3904 receives the address of the data input load operation to load data (not shown) into the row register 3902. The data is activation data or input data such as from an object or image to be classified or recognized in a neural network application. It outputs a signal to enable the row register 3902, which indicates which register is asserted for the data input load operation. The data input (not shown) typically varies between 8 bits and 256 bits.

[0211] The address decoder 3904 may also receive an address for a read-verify or program operation and output a signal to the row register 3902 indicating which row or rows are asserted for a read-verify program operation. In this example, each row register stores activation data (e.g., 8-bit activation data) and one tag bit or multiple tag bits, such as one tag bit for row enable and another for row DAC sampling. For example, row register 3902-0 includes tag bit 3905-0, row register 3902-1 includes tag bit 3905-1, row register 3902-n includes tag bit 3905-n, and so on. Tag bit (row enable tag bit) 3905 is used for row enable to disable activation input data stored in the row register, regardless of whether the row is selected by the address decoder 3904. For example, if the tag bit 3905-0 of row 0 has a certain value (e.g., a "1" value), the activation data in row register 3902-0 is output. If the tag bit 3905-0 has a different value (e.g., a "0" value), the activation data in the row register 3902-0 will not be output, and the row S / H buffer 3903-0 will receive the Z state from the row register 3902-0. Another tag bit (row S / H tag bit) is used for row DAC sampling to enable or disable sampling of the global DAC value into the local row S / H buffer 3903.

[0212] Fig.39BAn input block 3920 is depicted. Input block 3920 is similar to input block 3900, except that it contains a second set of row registers (shadow registers) 3906-0, 3906-1, ..., 3906-n, each row register containing a corresponding tag bit 3907-0, 3907-1, ..., 3907-n. Each row can switch between row register 3902 and row register 3906. For example, during one operation, address decoder 3904 provides an output to row register 3902, and during another operation, address decoder 3904 provides an output to row register 3906. For example, during one operation, if tag bit 3905 is enabled, row register 3902-0 outputs data, and during another operation, if tag bit 3907 is enabled, row register 3906 outputs data. This switching can be achieved by a multiplexer (not shown) or other control logic components. In this way, one set of row registers 3902 or 3906 can be loaded with activation data while the other set is used to actively output its activation data based on a signal from the address decoder 3904.

[0213] Fig.39C An input block 3940 is depicted. Input block 3940 is similar to input block 3900, except that it contains a second set of row registers 3908-0, 3908-1, ..., 3908-n, each row register containing a corresponding tag bit 3909-0, 3909-1, ..., 3909-n. Each row can switch between row register 3902 and row register 3908. For example, during one operation, address decoder 3904 provides a signal to row register 3902, and during another operation, address decoder 3904 provides an output to row register 3908. For example, during one operation, if tag bit 3905 is enabled, row register 3902 outputs data, and during another operation, if tag bit 3909 is enabled, row register 3908 outputs data. Such switching can be achieved by a multiplexer (not shown) or other control logic component. In this way, one set of row registers 3902 or 3908 can be loaded with activation data, while another set of row registers is used to actively output its activation data according to the signal from the address decoder 3904.

[0214] Fig.39DAn input block 3960 is depicted. Input block 3960 is similar to input block 3940, except that it contains a second set of row sample-and-hold buffers 3911-0, 3911-1, ..., 3911-n for the same array input (e.g., CGINx). Each row can switch between a row register 3902 and a row register 3908. For example, during one operation, the address decoder 3904 provides a signal to the row register 3902, and during another operation, the address decoder 3904 provides an output to the row register 3908. Similarly, during one operation, the row register 3902 outputs data according to the tag bit 3905, and during another operation, the row register 3908 outputs data according to the tag bit 3909. Each row can switch between a row S / H buffer 3903 and a row S / H buffer 3911 (using a control signal, not shown). Such switching can be achieved by a multiplexer (not shown) or other control logic component. In this way, one set of row registers 3902 or 3908 can be loaded with activation data, while the other set is used to actively output its activation data according to the signal from the address decoder 3904.

[0215] In one example, first activation data and a first tag bit are loaded into row register 3902, and second activation data and a second tag bit are loaded into row register 3908. The first activation data and the second activation data may be the same or different, and the first tag bit and the second tag bit may be the same or different.

[0216] Fig.40AOutput block 4000 is depicted. Output block 4000 receives output current from VMM array 3401 (not shown), typically from a bit line or source line of VMM array 3401. Output block 4000 includes current-to-voltage converter 4001, analog-to-digital converter 4002, output register 4003, and output register 4004. Current-to-voltage converter 4001 converts the current received from VMM array 3401 into corresponding voltages, whose values ​​reflect the current values ​​received from VMM array 3401. Analog-to-digital converter 4002 converts these corresponding voltages into bits representing the voltage values ​​received from the corresponding current-to-voltage converter 4001, thus reflecting the current values ​​received from VMM array 3401. These bits are then stored in output register 4003 or output register 4004. Output operation can switch between output register 4003 and output register 4004. For example, during a first operation of a first time period (e.g., one or more clock cycles), output data is loaded into output register 4003. During a second operation during a second time period (e.g., one or more clock cycles) after the first time period, the data is read from output register 4003 by another device in the system while new output data is loaded into output register 4004. During a third operation during a third time period (e.g., one or more clock cycles) after the second time period, the new output data is read from output register 4004 by another device in the system, and optionally, the output data can be loaded into output register 4003, and the sequence is repeated. This reduces the delay associated with the output operation because the external device can read data from the first output register while loading other data into another output register.

[0217] Optionally, output block 4000 optionally includes column tag bits 4005 to enable current-to-voltage converter 4001 and analog-to-digital converter 4002. Column tag bits 4005 may be included in current-to-voltage converter 4001 or analog-to-digital converter 4002. Column tag bits 4005 may include a column tag bit for each column in VMM array 3401. Column tag bits 4005 are loaded similarly to the above reference FIG. 39A to FIG. 39D The row tag bit is loaded as discussed above. The column tag bit functions similarly to the FIG. 39A to FIG. 39D For example, depending on which one includes the column tag bit 4005, the current-to-voltage converter 4001 and the analog-to-digital converter 4002 can be configured to output data for the column when the column tag bit 4005 of the column has a first value, and not output data when the column tag bit has a second value.

[0218] Fig.40BOutput block 4020 is depicted. Output block 4020 is the same as output block 4000 except for accumulator 4021. Accumulator 4021 can sum the values ​​received from current-to-voltage converter 4001, analog-to-digital converter 4002, output register 4003, and output register 4004 during a specific time period. For example, this may be useful if a neural read operation is performed on VMM array 3401 in a time-division multiplexed manner, for example, by reading half of the rows during a first time period and the other half of the rows during a second time period. The output from the first time period can be received by output register 4003, and the output from the second time period can be received by output register 4004, and the accumulator can sum the values ​​received from output register 4003 and output register 4004.

[0219] Output block 4000 optionally includes column tag bits 4005 to enable current-to-voltage converter 4001 and analog-to-digital converter 4002. Column tag bits 4005 may be included in current-to-voltage converter 4001 or analog-to-digital converter 4002. Column tag bits 4005 may include a column tag bit for each column in VMM array 3401. Column tag bits 4005 are loaded similarly to the above reference FIG. 39A to FIG. 39D The row tag bit is loaded as discussed above. The column tag bit functions similarly to the FIG. 39A to FIG. 39D For example, depending on which one includes the column tag bit 4005, the current-to-voltage converter 4001 and the analog-to-digital converter 4002 can be configured to output data for the column when the column tag bit 4005 of the column has a first value, and not output data when the column tag bit has a second value.

[0220] Fig.40C An example circuit for an output accumulator 4021 is provided. The output accumulator receives data from a current-to-voltage converter 4001, an analog-to-digital converter 4002, an output register 4003, and an output register 4004. The data is received by a shifter 4042, which performs a shift function in response to EN_SHIFT. The output D1 of the shifter 4042 is provided to an adder 4043, which adds D1 to D2, which also receives D2 and is enabled by EN_ADD.

[0221] The output of the adder 4043 is provided to one or more accumulator registers 4044, which store the output of the adder 4043 and provide it back to the adder 4043 as D2 for the next addition operation. In a configuration where there are more than two accumulator registers 4044, one shifter 4042 and one adder 4043, the shifter 4042 and the adder 4043 are shared between different outputs of the ITV 4001+ADC4002 or the output register 4003 or 4004. Each accumulator register is used for the operation of each output of the ITV 4001+ADC 4002 or the output register 4003 or 4004. In this way, the outputs of the current-to-voltage converter 4001, the analog-to-digital converter 4002, the output register 4003, and the output register 4004 can be added within a time period.

[0222] For example, shifter 4042 is used during serial input (DAC) mode, where one bit of the activation input is read at a time, and the amount of shift of the output bit depends on the binary position of the input bit. For example, the LSB (least significant bit) of the input bit results in no shift of the output, input bit (LSB+1) results in a left shift of 1 bit, input bit (LSB+2) results in a left shift of 2 bits, and so on, and where for an 8-bit activation input, this read operation is performed 8 times. The final output of accumulator register 4044 is the result of the entire 8-bit activation input.

[0223] Fig.41 Waveform 4100 depicts a first phase 4101 in which a row register is loaded with activation data and a second phase 4102 in which a neural read operation is performed using the activation data.

[0224] Fig.42 A waveform 4200 of a random access read operation 4201 is depicted.

[0225] Fig.43 A waveform 4300 of a burst read operation 4301 is depicted.

[0226] Fig.44 Waveform 4400 of a neural read operation 4401 is depicted.

[0227] Fig.45 A neural read operation 4500 is depicted. The neural read operation 4500 begins (4501). Activation data is loaded into the row register (4502). Next, a set of N rows are enabled (4503). Next, a column address is input (4504). A read operation is performed (4505), which involves the following steps: Fig.37A and Fig.37B The DAC sampling shown (which uses FIG. 35A to FIG. 35B , Fig.36 , Figure 38 and FIG. 39A to FIG. 39D The circuit shown) and Fig.34 The (bit line) output circuit 3407 in (which will use ITV to convert current to voltage, and use ADC to convert voltage to digital output), where the output data is the digital output from the ADC. The data is loaded into the output register (4506). The system determines whether another column address needs to be read. If yes, return to operation 4504. If not, the system determines whether another group of N rows needs to be read (4508). If yes, return to operation 4503. If not, the neural read operation is completed (4509), at which time the data output is optionally shifted out (4510) or the neural read operation is ended. Each time a neural read operation is performed, for a group of rows that are switched columns, the neural read time is 1 row of DAC delay + N ITVs + DAC delay with N-way column multiplexing. For example, if the DAC delay is 2μs and the ITV+ADC delay is 1μs, the time to read the entire row is 1×(DAC delay)+16×(ITV+ADC delay)=18μs. Basically, the DAC latency does not add any additional time to the next neural read.

[0228] Fig.46 A neural read operation 4600 is depicted. The neural read operation 4600 begins (4601). Activation data is loaded into a first set of row registers (4603). The activation data is then loaded into a second set of row registers (4602). Concurrently with this event, the column address or row group is changed (4604). The read operation is performed (4605). Output data is loaded into the output registers (4606). If the read operation is not completed (4607), the process returns to operation 4604. If the read operation is completed, the system (using a logic controller, not shown) determines whether data needs to be loaded from the second set of row registers into the first set of row registers (4608). If not, the neural read operation is completed (4611). If yes, data is loaded from the second set of row registers into the first set of row registers (4609). The system then determines whether the neural read operation is complete (4610). If yes, the neural read operation is complete (4611). If no, then it returns to operation 4604.

[0229] Fig.47A neural read operation 4700 is depicted. First, activation data is loaded into a first set of row registers (4701). Then, activation data is loaded into a second set of row registers (4702). Concurrently with this event, the column address or row group is changed (4703). A read operation is performed (4704). Data is loaded into an output register (4705). If the read operation is complete (4706), the system proceeds to operation 4707. If not, the system returns to operation 4703. In operation 4707, the system determines whether the second set of row registers and their corresponding row S / H buffers are enabled. If yes, the operation is complete (4708). If no, the second set of row registers and their corresponding row S / H buffers are enabled, and the system returns to operation 4703 to continue the neural read operation.

[0230] Fig.48 A read operation 4800 is depicted. Previously, digital output data has been loaded into output register 1 or output register 2. Then, the output data is shifted out of output register 1 or output register 2 (4801).

[0231] Fig.49 A neural read operation 4900 is depicted. First, activation data is loaded into the row register (4901). Then, data is shifted out of output register 1 or output register 2 (4902). Concurrently with this event, the column address or row group is changed (4903). A neural read operation is performed (4904). Data is loaded into output register 1 or output register 2 (4905). If the neural read operation is complete (4906), the operation is complete (4907). If not, the system returns to operation 4903 to continue the neural read operation.

[0232] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (no intervening materials, elements, or spaces are provided in between) and "indirectly on" (intervening materials, elements, or spaces are provided in between). Similarly, the term "adjacent" includes "directly adjacent" (no intervening materials, elements, or spaces are provided in between) and "indirectly adjacent" (intervening materials, elements, or spaces are provided in between), "mounted to" includes "directly mounted to" (no intervening materials, elements, or spaces are provided in between) and "indirectly mounted to" (intervening materials, elements, or spaces are provided in between), and "electrically coupled to" includes "directly electrically coupled to" (no intervening materials or elements electrically connecting the elements together) and "indirectly electrically coupled to" (intervening materials or elements electrically connecting the elements together). For example, forming an element "above" a substrate may include directly forming the element on the substrate without intervening materials / elements in between, and indirectly forming the element on the substrate with one or more intervening materials / elements in between.

Claims

1. A system, comprising: an array of non-volatile memory cells arranged in rows and columns; an output block for converting a current from a column of the array into a first digital output during a first time period and converting the current into a second digital output during a second time period; a first output register for storing the first digital output during the first time period and outputting the stored first digital output during the second time period; and A second output register is configured to store the second digital output during the second time period and output the stored second digital output during a third time period.

2. The system according to claim 1, further comprising: An accumulator for summing data received from one or more of the output block, the first output register, and the second output register.

3. The system according to claim 2, wherein: The output block includes a current-to-voltage converter that converts the current from the column of the array into a voltage and an analog-to-digital converter that converts the voltage into the first digital output.

4. The system according to claim 3, wherein: The current-to-voltage converter and the analog-to-digital converter include column tag bits.

5. The system according to claim 4, wherein: The current-to-voltage converter outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value.

6. The system according to claim 4, wherein: The analog-to-digital converter outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value.

7. The system according to claim 2, wherein: The accumulator comprises: a shifter to receive data from one or more of the output block, the first output register, and the second output register, and to generate a first output; an adder for receiving the first output and the second output and summing the first output and the second output to generate a third output; and An accumulator register is used to receive and store the third output, and provide the third output as the second output to the adder.

8. The system according to claim 7, wherein: The output block includes a current-to-voltage converter that converts the current from the column of the array into a voltage and an analog-to-digital converter that converts the voltage into the first digital output.

9. The system according to claim 1, wherein: The output block includes a current-to-voltage converter that converts the current from the column of the array into a voltage and an analog-to-digital converter that converts the voltage into the first digital output.

10. A method comprising: During the first period: converting, by an output block, current from a column of a nonvolatile memory cell array into a first digital output; as well as storing the first digital output in a first output register; and During the second time period: converting, by the output block, current from a column of a nonvolatile memory cell array into a second digital output; storing the second digital output in a second output register; as well as The stored first digital output is output from the first output register.

11. The method according to claim 10, comprising: During the third period: converting, by the output block, current from a column of a nonvolatile memory cell array into a third digital output; storing the third digital output in the first output register; And outputting the stored second digital output from the second output register.

12. The method according to claim 11, further comprising: Data received from one or more of the output block, the first output register, and the second output register are summed by an accumulator.

13. The method according to claim 12, wherein: The output block includes a current-to-voltage converter that converts the current from the column of the array into a voltage and an analog-to-digital converter that converts the voltage into the first digital output.

14. The method according to claim 13, wherein: The current-to-voltage converter and the analog-to-digital converter include column tag bits.

15. The method according to claim 14, wherein: The current-to-voltage converter outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value.

16. The method according to claim 14, wherein: The analog-to-digital converter outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value.

17. The method according to claim 12, wherein: The accumulator comprises: a shifter to receive data from one or more of the output block, the first output register, and the second output register, and to generate a first output; an adder for receiving the first output and the second output and summing the first output and the second output to generate a third output; and An accumulator register is used to receive and store the third output, and provide the third output as the second output to the adder.

18. The method according to claim 12, wherein: The output block includes a current-to-voltage converter that converts the current from the column of the array into a voltage and an analog-to-digital converter that converts the voltage into the first digital output.

19. The method according to claim 10, wherein: The output block includes a current-to-voltage converter that converts the current from the column of the array into a voltage and an analog-to-digital converter that converts the voltage into the first digital output.

20. A system, comprising: an array of non-volatile memory cells arranged in rows and columns; an output block for converting a current from a column of the array into a first digital output during a first time period and converting the current into a second digital output during a second time period, the output block comprising a current-to-voltage converter for converting the current from the column of the array into a voltage and an analog-to-digital converter for converting the voltage into the first digital output and the second digital output; and An accumulator for summing data received from the output block during the first time period and the second time period.

21. The system of claim 20, wherein: The current-to-voltage converter and the analog-to-digital converter include column tag bits.

22. The system of claim 21, wherein: The current-to-voltage converter outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value.

23. The system of claim 21, wherein: The analog-to-digital converter outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value.

24. The system of claim 21, comprising: a first output register for storing the first digital output during the first time period and outputting the stored first digital output during the second time period; and A second output register is configured to store the second digital output during the second time period and output the stored second digital output during a third time period.

25. The system of claim 20, wherein: The accumulator comprises: a shifter to receive data from one or more of the output block, the first output register, and the second output register, and to generate a first output; an adder for receiving the first output and the second output and summing the first output and the second output to generate a third output; and An accumulator register is used to receive and store the third output, and provide the third output as the second output to the adder.

26. A system, comprising: an array of non-volatile memory cells arranged in rows and columns; a first output register for storing the first digital output during the first time period and outputting the stored first digital output during the second time period; a second output register for storing the second digital output during the second time period and outputting the stored second digital output during a third time period; and An accumulator for summing data received from the first output register and the second output register.

27. The system of claim 20, wherein: The system includes a column tag bit.

28. The system of claim 21, wherein: The accumulator receives data when the column tag bits have a first value and does not receive data when the column tag bits have a second value.

29. The system of claim 26, wherein: The accumulator comprises: a shifter to receive data from one or more of the output block, the first output register, and the second output register, and to generate a first output; an adder for receiving the first output and the second output and summing the first output and the second output to generate a third output; and An accumulator register is used to receive and store the third output, and provide the third output as the second output to the adder.

30. A system, comprising: an array of non-volatile memory cells arranged in rows and columns; An output block, the output block comprising: a first current-to-voltage converter that converts current from the column of the array to a first voltage during a first time period and a first analog-to-digital converter that converts the first voltage to a first digital output; and a second current-to-voltage converter that converts current from the column of the array to a second voltage during a second time period and a second analog-to-digital converter that converts the second voltage to a second digital output; and An accumulator is used to sum the first digital output and the second digital output.

31. The system of claim 30, wherein: The first current-to-voltage converter and the first analog-to-digital converter include first column tag bits, and the second current-to-voltage converter and the second first analog-to-digital converter include second column tag bits.

32. The system of claim 31, wherein: The first current-to-voltage converter outputs data when the first column tag bit has a first value and does not output data when the first column tag bit has a second value, and the second current-to-voltage converter outputs data when the second column tag bit has the first value and does not output data when the second column tag bit has the second value.

33. The system of claim 21, comprising: a first output register for storing the first digital output during the first time period and outputting the stored first digital output to the accumulator during the second time period; and A second output register is configured to store the second digital output during the second time period and output the stored second digital output to the accumulator during a third time period.

34. A system, comprising: an array of non-volatile memory cells arranged in rows and columns; an output block for converting a current from a column of the array into a first digital output during a first time period and converting the current into a second digital output during a second time period; a first output register for storing the first digital output during the first time period and outputting the stored first digital output during the second time period; and A second output register is configured to store the second digital output during the second time period and output the stored second digital output during a third time period. An accumulator for summing one of: (i) data received from the first output register during the first time period and from the second output register during the second time period, or (2) data received from the first output register during the first time period and from the first output register during the second time period.

35. The system of claim 34, wherein: The output block includes a current-to-voltage converter that converts the current from the column of the array into a voltage during the first time period and an analog-to-digital converter that converts the voltage into the first digital output.

36. The system of claim 35, wherein: The current-to-voltage converter and the analog-to-digital converter include column tag bits.

37. The system of claim 36, wherein: The current-to-voltage converter outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value.

38. The system of claim 36, wherein: The analog-to-digital converter outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value.

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