An incremental encoder signal expansion synchronization circuit

Abstract

The present invention provides an incremental encoder signal expansion synchronization circuit, which is located between an incremental encoder or a normalization circuit and a back-end processing circuit. The incremental encoder signal expansion synchronization circuit includes a de-jitter circuit module, a shaping circuit module, and a signal conversion circuit module, which are arranged in sequence. The de-jitter circuit module includes a resistor unit and a diode unit arranged in parallel with each other, and a capacitor unit connected to the resistor unit and the diode unit respectively. The front ends of the resistor unit and the diode unit are connected to the output signal unit of the incremental encoder or the normalization circuit. The shaping circuit module includes a digital circuit unit connected to the de-jitter circuit module. The digital circuit unit is used to convert an irregular trend signal output from the de-jitter circuit module into a standard TTL level. The signal conversion circuit module includes an RS-422 driver chip connected to the digital circuit unit. The RS-422 driver chip is used to convert the standard TTL level into a differential signal.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit control, and in particular to an incremental encoder signal expansion synchronization circuit. Background Art

[0002] In the existing technology, incremental encoders are mostly used in electronic circuit design, automated control, precision measurement, instrument design, rail transit detection and other fields to transmit and control signals. At present, the signals output by incremental encoders are generally single-ended distribution, and their application in application scenarios such as multi-axis synchronous control, automated production lines, and triggering multi-device actions is very limited. In addition, the signals output by incremental encoders are subject to a lot of interference during transmission to the back-end processing circuit, making the signals reaching the back-end processing circuit not pure enough, affecting the system stability and reliability. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the purpose of the present invention is to provide an incremental encoder signal expansion synchronization circuit, which aims to solve the technical problems in the prior art that the signals output by the incremental encoder are generally single-ended distribution, and are very limited in application scenarios such as multi-axis synchronous control, automated production lines, and triggering multi-device actions. In addition, the signals output by the incremental encoder are subject to a lot of interference during transmission to the back-end processing circuit, making the signals reaching the back-end processing circuit not pure enough, affecting the stability and reliability of the system.

[0004] In order to achieve the above object, the present invention is implemented through the following technical solutions:

[0005] A signal expansion synchronization circuit for an incremental encoder is located between an incremental encoder or a normalization circuit and a back-end processing circuit, and is characterized in that the signal expansion synchronization circuit for the incremental encoder includes a de-jitter circuit module, a shaping circuit module, and a signal conversion circuit module arranged in sequence, the de-jitter circuit module includes a resistor unit and a diode unit arranged in parallel with each other, and a capacitor unit connected to the resistor unit and the diode unit respectively, the front ends of the resistor unit and the diode unit are connected to the output signal unit of the incremental encoder or the normalization circuit, the shaping circuit module includes a digital circuit unit connected to the de-jitter circuit module, the digital circuit unit is used to convert the irregular trend signal output from the de-jitter circuit module into a standard TTL level, the signal conversion circuit module includes an RS-422 driver chip connected to the digital circuit unit, and the RS-422 driver chip is used to convert the standard TTL level into a differential signal.

[0006] According to one aspect of the above technical solution, the output signal unit of the incremental encoder or the normalization circuit includes an A-phase single-ended signal and a B-phase single-ended signal.

[0007] According to one aspect of the above technical solution, the resistance unit includes a resistor R1 connected to the A-phase single-ended signal, and a resistor R2 connected to the B-phase single-ended signal, the diode unit includes a diode D1 connected to the A-phase single-ended signal, and a diode D2 connected to the B-phase single-ended signal, and the capacitor unit includes a capacitor C1 connected to the resistor R1 and the diode D1, respectively, and a capacitor C2 connected to the resistor R2 and the diode D2, respectively.

[0008] According to one aspect of the above technical solution, ends of the capacitor C1 and the capacitor C2 are both grounded.

[0009] According to one aspect of the above technical solution, the digital circuit unit includes an OR gate U1A and an OR gate U1C connected to the resistor R1, and an OR gate U1B and an OR gate U1D connected to the resistor R2.

[0010] According to one aspect of the above technical solution, the RS-422 driver chip includes a first IC chip U2 and a second IC chip U3.

[0011] According to one aspect of the above technical solution, one end of the first IC chip U2 is connected to the OR gate U1A through pin 1, and the other end is connected to the back-end processing circuit through pins 2 and 3; one end of the second IC chip U3 is connected to the OR gate U1A through pin 1, and the other end is connected to the back-end processing circuit through pins 2 and 3; one end of the first IC chip U2 is connected to the OR gate U1C through pin 9, and the other end is connected to the back-end processing circuit through pins 10 and 11; one end of the second IC chip U3 is connected to the OR gate U1C through pin 9, and the other end is connected to the back-end processing circuit through pins 10 and 11.

[0012] According to one aspect of the above technical solution, one end of the first IC chip U2 is connected to the OR gate U1B through pin 7, and the other end is connected to the back-end processing circuit through pins 6 and 5. One end of the second IC chip U3 is connected to the OR gate U1B through pin 7, and the other end is connected to the back-end processing circuit through pins 6 and 5. One end of the first IC chip U2 is connected to the OR gate U1D through pin 15, and the other end is connected to the back-end processing circuit through pins 14 and 13. One end of the second IC chip U3 is connected to the OR gate U1D through pin 15, and the other end is connected to the back-end processing circuit through pins 14 and 13.

[0013] According to one aspect of the above technical solution, the first IC chip U2 is connected to the voltage supply terminal through the 4th pin, and is connected to the ground terminal through the 12th pin and the 8th pin.

[0014] According to one aspect of the above technical solution, the second IC chip U3 is connected to the voltage supply terminal through the 4th pin, and is connected to the ground terminal through the 12th pin and the 8th pin.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] By setting an incremental encoder signal expansion synchronization circuit between the incremental encoder or normalization circuit and the back-end processing circuit, which includes an anti-jitter circuit module, a shaping circuit module, and a signal conversion circuit module arranged in sequence, when the signal from the incremental encoder or normalization circuit is received, the burrs and noise in the signal are first filtered out by the combination of the resistance unit, the diode unit and the capacitor unit in the anti-jitter circuit module to ensure that the signal is smooth and stable; then the signal after the anti-jitter processing is reshaped into a standard square wave pulse signal by the digital circuit unit in the shaping circuit unit. The reason is that the output signal of the encoder is not smooth after being transmitted over a long distance or being interfered with. The edges may become irregular, and the shaping circuit module can restore the input signal to a standard TTL level square wave signal through logic circuits such as Schmitt triggers to improve the signal's anti-interference ability, ensure that the signal can be accurately identified and processed in different terminals of the back-end processing circuit, and further improve the accuracy of signal transmission; finally, the RS-422 driver chip in the signal conversion circuit module converts the single-ended TTL signal output by the encoder into two differential signals with opposite phases, which can provide strong anti-interference ability and signal integrity in long-distance transmission, facilitate stable signal transmission over long distances or between multiple terminals, and thus achieve synchronous control of different terminal devices;

[0017] The incremental encoder signal expansion synchronization circuit of the present invention can realize the following functions: synchronous data acquisition by multiple terminals, triggering the actions of multiple application terminals, signal isolation and amplification, improving system reliability, and facilitating system expansion. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of the incremental encoder signal expansion synchronization circuit in the entire control circuit in the first embodiment of the present invention;

[0019] Figure 2 for Figure 1 Schematic diagram of the structure of the incremental encoder signal expansion synchronization circuit Figure 1 ;

[0020] Figure 3 for Figure 1 Schematic diagram of the structure of the incremental encoder signal expansion synchronization circuit Figure 2 ;

[0021] Description of main component symbols:

[0022]

[0023] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0024] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. The drawings illustrate several embodiments of the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present invention.

[0025] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0027] See also Figures 1 to 3 , shown is an incremental encoder signal expansion synchronization circuit 20 in the first embodiment of the present invention, located between the incremental encoder or normalization circuit 10 and the back-end processing circuit 30, the incremental encoder signal expansion synchronization circuit 20 includes a de-jitter circuit module 21, a shaping circuit module 22, and a signal conversion circuit module 23 arranged in sequence, the de-jitter circuit module 21 includes a resistor unit and a diode unit arranged in parallel with each other, and a capacitor unit connected to the resistor unit and the diode unit respectively, the front end of the resistor unit and the diode unit is connected to the output signal unit of the incremental encoder or normalization circuit 10, the shaping circuit module 22 includes a digital circuit unit connected to the de-jitter circuit module 21, the digital circuit unit is used to convert the irregular trend signal output from the de-jitter circuit module 21 into a standard TTL level, the signal conversion circuit module 23 includes an RS-422 driver chip connected to the digital circuit unit, the RS-422 driver chip is used to convert the standard TTL level into a differential signal.

[0028] It can be understood that the present invention sets an incremental encoder signal expansion synchronization circuit 30 between the incremental encoder or normalization circuit 10 and the back-end processing circuit, which includes a de-jitter circuit module 21, a shaping circuit module 22, and a signal conversion circuit module 23 arranged in sequence. After receiving the signal sent by the incremental encoder or normalization circuit 10, the burrs and noise in the signal are first filtered out by the combination of the resistor unit, the diode unit and the capacitor unit in the de-jitter circuit module 21 to ensure that the signal is smooth and stable; then the signal after de-jitter processing is reshaped into a standard square wave pulse signal by the digital circuit unit in the shaping circuit unit. The reason is that the output signal of the encoder is not smooth after being transmitted over a long distance or After being interfered with, the edge of the signal may become irregular. The shaping circuit module 22 can restore the input signal to a standard TTL level square wave signal through logic circuits such as Schmitt triggers to improve the signal's anti-interference ability, ensure that the signal can be accurately identified and processed in different terminals of the back-end processing circuit, and further improve the accuracy of signal transmission; finally, the RS-422 driver chip in the signal conversion circuit module 23 converts the single-ended TTL signal output by the encoder into two differential signals with opposite phases, which can provide strong anti-interference ability and signal integrity in long-distance transmission, facilitate stable transmission of signals over long distances or between multiple terminals, and thus realize synchronous control of different terminal devices;

[0029] The incremental encoder signal expansion synchronization circuit of the present invention can realize the following functions: synchronous data acquisition by multiple terminals, triggering the actions of multiple application terminals, signal isolation and amplification, improving system reliability, and facilitating system expansion;

[0030] Specifically, multi-terminal synchronous data acquisition: In some complex industrial control systems, multiple devices (such as motion controllers, PLCs, position feedback devices, etc.) may need to share the same encoder signal. Through signal expansion, the encoder pulse signal can be distributed to multiple terminal devices, enabling multiple control systems to synchronously obtain position signals, thereby performing synchronous control and monitoring.

[0031] Triggering actions on multiple application terminals: After expanding the capacity of the incremental encoder signal, the signal can trigger the execution of actions on multiple different application terminals at the same time. For example, in some application scenarios, the encoder pulse signal may need to trigger several control systems at the same time to start, stop, or adjust the operation of different devices. With the expansion, synchronization signals can be sent to multiple devices at the same time to ensure the timing consistency of their actions;

[0032] Signal isolation and amplification: During signal expansion, signal isolation or buffers are often used to protect the encoder output. Multiple terminal devices may experience varying electrical noise or interference. Isolation after signal expansion can reduce interference, protect the encoder, and ensure signal integrity. Furthermore, the expansion circuit can amplify the signal, allowing the encoder signal to maintain stable transmission over longer distances without being affected by cable loss.

[0033] Improve system reliability: If multiple devices need to receive signals from the same encoder, directly connecting the encoder signal in parallel to multiple devices may cause signal attenuation and increased noise, which in turn affects system reliability. Through capacity expansion, the encoder signal can be independently and stably provided to each terminal device, avoiding signal distortion or errors caused by excessive load. In situations where multiple devices work together, signal capacity expansion can ensure stable transmission of encoder signals and reduce the risk of single point failures.

[0034] Facilitates system expansion: Encoder signal expansion facilitates system expansion. When adding new devices or terminals to the existing system, encoder signals can be directly obtained from the signal expansion device without changing the existing hardware architecture. This reduces the additional wiring and debugging work associated with system expansion.

[0035] Specifically, in this embodiment, the output signal unit of the incremental encoder or normalization circuit 10 includes an A-phase single-ended signal 11 and a B-phase single-ended signal 12; the resistance unit includes a resistor R1 connected to the A-phase single-ended signal 11, and a resistor R2 connected to the B-phase single-ended signal 12; the diode unit includes a diode D1 connected to the A-phase single-ended signal 11, and a diode D2 connected to the B-phase single-ended signal 12; the capacitor unit includes a capacitor C1 connected to the resistor R1 and the diode D1, respectively, and a capacitor C2 connected to the resistor R2 and the diode D2, respectively; the ends of the capacitor C1 and the capacitor C2 are both grounded.

[0036] It can be understood that in this embodiment, taking two single-ended signals (A-phase single-ended signal 11 and B-phase single-ended signal 12) as an example, during the transmission of the output signal unit of the incremental encoder or normalization circuit 10, burrs or noise may appear on the signal edge due to mechanical movement, jitter or interference. The debounce circuit filters out these burr signals through a combination of resistor R1 (R1=470Ω), capacitor C1 (C1=10pF) and diode D1 (D1=1N5819G), ensuring that the transmission of the A-phase single-ended signal 11 is smoother and more stable; similarly, the combination of resistor R2 (R2=470Ω), capacitor C2 (C2=10pF) and diode D2 (D2=1N5819G) filters out these burr signals, ensuring that the transmission of the B-phase single-ended signal 12 is smoother and more stable.

[0037] The principle is that the debouncing circuit absorbs sudden high-frequency interference (glitch signals) through the charging and discharging process of the capacitor. At the same time, the diode provides protection, and the resistor and capacitor form a low-pass filter, which can filter out unnecessary high-frequency noise and prevent false triggering of the signal. This effectively eliminates glitches caused by mechanical jitter or electrical noise, ensuring that the encoder pulse signal is cleaner and more stable, which is convenient for subsequent processing by the shaping circuit.

[0038] Furthermore, the digital circuit unit includes an OR gate U1A and an OR gate U1C connected to the resistor R1, and an OR gate U1B and an OR gate U1D connected to the resistor R2.

[0039] As you can understand, the main function of the shaping circuit module 22 is to reshape the debounced signal into a standard square wave pulse signal. After long-distance transmission or interference, the encoder output signal may have irregular edges. The shaping circuit uses logic circuits such as Schmitt triggers to restore the input signal to a standard TTL-level square wave signal.

[0040] The principle is that OR gate U1A and OR gate U1C can identify the high and low levels of the A-phase single-ended signal 11 after debounce, and convert the irregular trend signal into a clear rising level signal or a falling level signal (standard TTL level) through state output; similarly, OR gate U1B and OR gate U1D can identify the high and low levels of the B-phase single-ended signal 12 after debounce, and convert the irregular trend signal into a clear rising level signal or a falling level signal through state output. This shaping method can enhance the signal's anti-interference ability and ensure the stability of the signal, shaping the debounced signal into a stable pulse signal, ensuring that the signal can be accurately identified and processed in different terminals, further improving the accuracy of signal transmission.

[0041] Furthermore, the RS-422 driver chip includes a first IC chip U2 and a second IC chip U3.

[0042] Specifically, one end of the first IC chip U2 is connected to the OR gate U1A through pin 1, and the other end is connected to the back-end processing circuit through pins 2 and 3. One end of the second IC chip U3 is connected to the OR gate U1A through pin 1, and the other end is connected to the back-end processing circuit through pins 2 and 3. One end of the first IC chip U2 is connected to the OR gate U1C through pin 9, and the other end is connected to the back-end processing circuit through pins 10 and 11. One end of the second IC chip U3 is connected to the OR gate U1C through pin 9, and the other end is connected to the back-end processing circuit through pins 10 and 11. One end of the first IC chip U2 is connected to the OR gate U1B through pin 7, and the other end is connected to the back-end processing circuit through pins 6 and 11. Pin 5 is connected to the back-end processing circuit, one end of the second IC chip U3 is connected to the OR gate U1B through pin 7, and the other end is connected to the back-end processing circuit through pins 6 and 5, one end of the first IC chip U2 is connected to the OR gate U1D through pin 15, and the other end is connected to the back-end processing circuit through pins 14 and 13, one end of the second IC chip U3 is connected to the OR gate U1D through pin 15, and the other end is connected to the back-end processing circuit through pins 14 and 13; the first IC chip U2 is connected to the voltage supply end through pin 4, and to the ground end through pins 12 and 8; the second IC chip U3 is connected to the voltage supply end through pin 4, and to the ground end through pins 12 and 8.

[0043] As you can understand, RS-422 is a differential signal transmission standard that provides strong anti-interference capabilities and signal integrity over long distances. The single-ended to RS-422 converter converts the encoder's single-ended TTL signal into a differential signal, facilitating stable signal transmission over long distances or between multiple terminals. This circuit utilizes a differential driver (such as the AM26LS31CDR RS-422 driver chip) to convert the single-ended signal into two differential signals with opposite phases. Differential transmission maintains signal integrity in high-noise environments because the receiver compares the voltage difference between the two signal lines to identify the signal, thereby canceling out external interference. The converted RS-422 differential signal exhibits high anti-interference capabilities, making it suitable for long-distance signal transmission in industrial environments. It ensures that the encoder signal remains stable even over long transmission distances, enabling synchronized control of different terminal devices.

[0044] In the specific embodiment of this invention, the shaped A-phase single-ended signal 11 passes through the 1st pin of the first IC chip U2 and the 1st pin of the second IC chip U3, and is output from the 2nd and 3rd pins of the first IC chip U2 and the second IC chip U3, as well as passes through the 9th pin of the first IC chip U2 and the 9th pin of the second IC chip U3, and is output from the 10th and 11th pins of the first IC chip U2 and the second IC chip U3; the shaped B-phase single-ended signal 12 passes through the 7th pin of the first IC chip U2 and the 7th pin of the second IC chip U3, and is output from the 6th and 5th pins of the first IC chip U2 and the second IC chip U3, as well as passes through the 15th pin of the first IC chip U2 and the 15th pin of the second IC chip U3, and is output from the 14th and 13th pins of the first IC chip U2 and the second IC chip U3.

[0045] In summary, the incremental encoder signal expansion synchronization circuit in the above embodiment of the present invention can realize: synchronous data acquisition by multiple terminals, triggering the actions of multiple application terminals, signal isolation and amplification, improving system reliability, and facilitating system expansion.

[0046] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0047] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. An incremental encoder signal expansion synchronization circuit, located between the incremental encoder or normalization circuit and the back-end processing circuit, characterized in that: The incremental encoder signal expansion synchronization circuit includes a debouncing circuit module, a shaping circuit module, and a signal conversion circuit module, which are arranged in sequence. The debouncing circuit module includes a resistor unit and a diode unit arranged in parallel, and a capacitor unit connected to the resistor unit and the diode unit respectively. The front ends of the resistor unit and the diode unit are connected to the output signal unit of the incremental encoder or the normalization circuit. The shaping circuit module includes a digital circuit unit connected to the debouncing circuit module, and the digital circuit unit is used to convert the irregular trend signal output from the debouncing circuit module into a standard TTL level. The signal conversion circuit module includes an RS-422 driver chip connected to the digital circuit unit, and the RS-422 driver chip is used to convert the standard TTL level into a differential signal. The output signal unit of the incremental encoder or normalization circuit includes an A-phase single-ended signal and a B-phase single-ended signal; The resistance unit includes a resistor R1 connected to the A-phase single-ended signal and a resistor R2 connected to the B-phase single-ended signal; The digital circuit unit includes an OR gate U1A and an OR gate U1C connected to the resistor R1, and an OR gate U1B and an OR gate U1D connected to the resistor R2; The RS-422 driver chip includes a first IC chip U2 and a second IC chip U3; One end of the first IC chip U2 is connected to the OR gate U1A through pin 1, and the other end is connected to the back-end processing circuit through pins 2 and 3. One end of the second IC chip U3 is connected to the OR gate U1A through pin 1, and the other end is connected to the back-end processing circuit through pins 2 and 3. One end of the first IC chip U2 is connected to the OR gate U1C through pin 9, and the other end is connected to the back-end processing circuit through pins 10 and 11. One end of the second IC chip U3 is connected to the OR gate U1C through pin 9, and the other end is connected to the back-end processing circuit through pins 10 and 11.

2. The incremental encoder signal expansion synchronization circuit according to claim 1, characterized in that: The diode unit includes a diode D1 connected to the A-phase single-ended signal and a diode D2 connected to the B-phase single-ended signal. The capacitor unit includes a capacitor C1 connected to the resistor R1 and the diode D1, respectively, and a capacitor C2 connected to the resistor R2 and the diode D2, respectively.

3. The incremental encoder signal expansion synchronization circuit according to claim 2, characterized in that: Ends of the capacitor C1 and the capacitor C2 are both grounded.

4. The incremental encoder signal expansion synchronization circuit according to claim 1, characterized in that: One end of the first IC chip U2 is connected to the OR gate U1B through pin 7, and the other end is connected to the back-end processing circuit through pins 6 and 5. One end of the second IC chip U3 is connected to the OR gate U1B through pin 7, and the other end is connected to the back-end processing circuit through pins 6 and 5. One end of the first IC chip U2 is connected to the OR gate U1D through pin 15, and the other end is connected to the back-end processing circuit through pins 14 and 13. One end of the second IC chip U3 is connected to the OR gate U1D through pin 15, and the other end is connected to the back-end processing circuit through pins 14 and 13.

5. The incremental encoder signal expansion synchronization circuit according to claim 4, characterized in that: The first IC chip U2 is connected to the voltage supply terminal through the 4th pin and is connected to the ground terminal through the 12th pin and the 8th pin.

6. The incremental encoder signal expansion synchronization circuit according to claim 5, characterized in that: The second IC chip U3 is connected to the voltage supply terminal through the 4th pin and is connected to the ground terminal through the 12th pin and the 8th pin.

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