Reconfigurable FMCW radar SoC architecture

Abstract

The invention discloses a reconfigurable FMCW radar SoC architecture, and relates to the technical field of radars. Comprising a radio frequency transceiving subsystem and a baseband signal processing subsystem, and the radio frequency transceiving subsystem is electrically connected with the baseband signal processing subsystem; the baseband signal processing subsystem comprises a chip provided with an ASIC algorithm processing module, an SoC bus, an SoC microprocessor provided with an SoC MCU module, and an SoC peripheral interface module. The radio frequency receiving and transmitting subsystem comprises a receiving channel, a transmitting channel, a frequency synthesizer and a frequency mixer, the radio frequency receiving and transmitting subsystem performs information interaction with each sub-module in a chip through an SoC bus, a reconfigurable FMCW radar radio frequency transceiver and a related data processing module are integrated into the chip through an SoC system architecture design, and the FMCW radar radio frequency transceiver and the related data processing module are integrated into the chip. The system has the advantages of simple structure, high stability, high resolution, low power consumption, strong applicability and the like.

Description

Technical Field

[0001] The present invention relates to the field of radar technology, and in particular to a reconfigurable FMCW radar SoC architecture. Background Art

[0002] Frequency Modulated Continuous Wave (FMCW) is a radar technology solution that has the characteristics of strong anti-interference, high transmission rate, high resolution, strong penetration, simple system structure, low power consumption, and high safety. It can be widely used in rescue, emergency, security, medical care and other fields, with a very rich application scenario and broad market prospects. The existing FMCW radar technology solution mainly uses discrete chips to build radar systems, or integrates the key modules such as the RF transceiver in the radar system according to a specific application scenario, and then uses other off-chip modules to build radar systems.

[0003] Up to now, the implementation scheme of FMCW radar technology at home and abroad is mainly to use discrete devices to build FMCW radar, such as CEM400, a product of Huanuo Star Technology Co., Ltd., which adopts a multiple-transmit multiple-receive (MIMO) architecture ultra-wideband radar, which can penetrate non-metallic, low-water content objects such as brick walls, stone slabs, doors and concrete walls. However, such products basically use discrete devices sold on the market to build FMCW RF front-end transceiver systems, with low integration, and thus low reliability, poor convenience, and performance dependence on commercially available chips, which are easily affected by the supply chain. In academic research, domestic and foreign academic circles have achieved certain results in the research of FMCW radar chips. For example, the document (10.1109 / ISSCC.2019.8662536) uses an on-chip radar transceiver to realize an FMCW radar transceiver chip that meets the UWB standards of many countries. However, the level of integration of related results is not high, and the current related research is only designed for specific industry protocols and industry standards. This leads to the limited reconfigurability and compatibility of related FMCW radar systems, which cannot meet the different requirements for core indicators such as detection distance and detection accuracy of FMCW radars in different application scenarios.

[0004] In general, although FMCW radar has a good market prospect, due to the lack of successful integrated solutions, related products cannot meet market expectations in terms of unit cost, adaptability and, most importantly, reliability. Therefore, the market is eager to have an FMCW radar system that can be integrated on a chip to overcome the above problems encountered by the existing FMCW radar with discrete device implementation solutions. Summary of the invention

[0005] The present invention provides a reconfigurable FMCW radar SoC architecture to solve the problems in the background technology.

[0006] To achieve the above object, the present invention provides the following technical solutions: a reconfigurable FMCW radar SoC architecture, comprising a radio frequency transceiver subsystem and a baseband signal processing subsystem, wherein the radio frequency transceiver subsystem and the baseband signal processing subsystem are electrically connected; the baseband signal processing subsystem comprises a chip with an ASIC algorithm processing module, a SoC bus, a SoC microprocessor with a SoC MCU module, and a SoC peripheral interface module; the SoC MCU module is used to control the radio frequency transceiver subsystem, and adjust according to the external information of the chip and the feedback signal of the radio frequency transceiver subsystem;

[0007] The ASIC algorithm processing module is used to process the time domain signal output by the RF transceiver subsystem, convert the time domain signal into a frequency domain signal through an algorithm, and transmit the frequency domain signal to the SoC MCU module or to an off-chip device via the SoC peripheral interface module for processing and analysis;

[0008] The RF transceiver subsystem includes a receiving channel, a transmitting channel, a frequency synthesizer and a mixer. The RF transceiver subsystem exchanges information with each submodule inside the chip through the SoC bus, can drive the operation of the transceiver subsystem according to the control information of the on-chip main control chip, and transmit the signal to the ASIC algorithm processing module for processing.

[0009] Furthermore, the RF transceiver subsystem and the baseband signal processing subsystem are each configured with at least one N-way channel, where N is an integer greater than or equal to 1.

[0010] Furthermore, the RF transceiver subsystem is directly connected to the ASIC algorithm processing module inside the chip. The ASIC algorithm processing module converts the time domain signal obtained by mixing the RF transceiver subsystem into a frequency domain signal, and transmits the frequency domain signal to the SoC MCU module through the SoC bus for further processing. The original time domain signal obtained by mixing and the processed frequency domain signal can be directly transmitted to the off-chip terminal through the SoC peripheral interface for further processing.

[0011] Furthermore, the control command output by the user terminal or the SoC MCU module controls the operation of the radio frequency transceiver subsystem through the SoC bus.

[0012] Furthermore, the radio frequency transceiver subsystem architecture is reconfigurable; the transmission channel includes a passive matching network, a power amplifier and an off-chip antenna.

[0013] Furthermore, the receiving channel includes an off-chip antenna, a low-noise amplifier, a mixer, a transconductance amplifier, a bandpass filter and an analog-to-digital converter. The mixer can transform the time domain signal obtained by mixing into two signals with a phase difference of 90°, namely an I channel signal and a Q channel signal. The two channel signals are respectively input into independent BPFs and ADCs for filtering, sampling and signal conversion.

[0014] Furthermore, the frequency synthesizer includes an on-chip crystal oscillator circuit, a chirp signal generator, a phase-locked loop, a matching network, and a power divider;

[0015] The phase-locked loop is used to generate an FMCW signal of a specific frequency band, which is used for signal transmission of a transmitting channel and signal mixing of a receiving channel;

[0016] The chirp signal generator generates a control signal sequence for controlling the phase-locked loop to output a specific frequency bandwidth and chirp slope according to the control signal. At the same time, at the start and end time of the chirp, the chirp signal generator will feed back the corresponding trigger signal to the baseband signal processing subsystem to ensure that the SoC MCU or the off-chip terminal is synchronized with the chirp signal.

[0017] The power divider divides one FMCW signal generated by the phase-locked loop into two FMCW signals with equal power, one of which is used for signal transmission of the transmission channel and the other is mixed with the reception signal of the reception channel. The oscillator type used by the frequency synthesizer is reconfigurable.

[0018] Furthermore, it also includes a phase-locked loop architecture of a low quantization noise Chirp signal injection technology in a radio frequency transceiver subsystem, wherein the phase-locked loop includes a frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a true fractional frequency divider, and an output buffer;

[0019] The chirp signal generator controls the true fractional frequency divider to generate a corresponding true fractional + integer frequency division ratio through a parallel digital signal, and the phase-locked loop responds accordingly, changes the frequency following the signal generated by the chirp signal generator, and generates a corresponding FMCW signal.

[0020] Furthermore, the ASIC algorithm processing module includes a retiming unit and a fast Fourier transform unit. The retiming unit receives a Chirp signal start trigger signal and an end trigger signal from the RF transceiver subsystem, or receives a Chirp signal start trigger signal and an end trigger signal of the RF transceiver subsystem actively controlled by the user terminal or the SoC MCU, determines the start time of receiving data from the RF transceiver subsystem, and sends the received data to the FFT unit and the SoC MCU or the user terminal, or sends the unretimed original data to the SoC MCU or the user terminal;

[0021] Furthermore, the FFT unit receives data from the retiming unit, converts the time domain digital signal into a frequency domain digital signal through FFT, and transmits the frequency domain digital signal to the SoC MCU or the user terminal.

[0022] Compared with the prior art, the present invention provides a reconfigurable FMCW radar SoC architecture, which has the following beneficial effects:

[0023] The reconfigurable FMCW radar SoC architecture integrates the reconfigurable FMCW radar RF transceiver and related data processing modules into the chip through SoC system architecture design. It has the advantages of simple structure, high stability, high resolution, low power consumption, and strong applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 It is a schematic diagram of the overall architecture of a reconfigurable FMCW radar SoC architecture of the present invention;

[0026] Figure 2 A schematic diagram of the radio frequency transceiver subsystem architecture of a reconfigurable FMCW radar SoC architecture of the present invention;

[0027] Figure 3 A schematic diagram of a phase-locked loop architecture of a low quantization noise chirp signal injection technology for a reconfigurable FMCW radar SoC architecture according to the present invention;

[0028] Figure 4 The figure is a schematic diagram of an ASIC algorithm processing module of a reconfigurable FMCW radar SoC architecture of the present invention. DETAILED DESCRIPTION

[0029] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0030] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0031] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments.

[0032] See also Figure 1-4 The present invention discloses a reconfigurable FMCW radar SoC architecture, which includes at least one N-channel RF transceiver subsystem and at least one N-channel baseband signal processing subsystem, wherein N is an integer greater than or equal to 1; the baseband signal processing subsystem includes at least one chip with an ASIC algorithm processing module, at least one SoC bus, at least one SoC microprocessor module and at least one SoC peripheral interface module; the SoC microprocessor (MCU) module is internally provided with a SoC MCU module, and the MCU module is used to control the RF transceiver subsystem and make adjustments according to chip external information and RF transceiver subsystem feedback signals.

[0033] The ASIC algorithm processing module is used to process the time domain signal output by the RF transceiver subsystem, convert the time domain signal into a frequency domain signal through an algorithm, and transmit the frequency domain signal to the MCU module or to an off-chip device via the SoC peripheral interface module for processing and analysis.

[0034] The RF transceiver subsystem includes at least one receiving channel, at least one transmitting channel, at least one frequency synthesizer and at least one mixer. The RF transceiver subsystem exchanges information with the sub-modules inside the chip through the SoC bus, can drive the operation of the transceiver subsystem according to the control information of the on-chip main control chip, and transmit the signal to the ASIC algorithm processing module for processing.

[0035] like Figure 1 As shown in the figure: the FMCW radar SoC includes a radio frequency transceiver subsystem and a baseband signal processing subsystem. The present invention adopts a radio frequency transceiver subsystem composed of a multiple-transmit multiple-receive antenna array (MIMO). The radio frequency transceiver subsystem is directly connected to the ASIC algorithm processing module inside the chip. The ASIC algorithm processing module converts the time domain signal obtained by mixing the radio frequency transceiver subsystem into a frequency domain signal, and transmits the frequency domain signal to the SoC MCU module through the SoC bus for further processing. At the same time, the original time domain signal obtained by mixing and the processed frequency domain signal in the present invention can be directly transmitted to the off-chip terminal through the SoC peripheral interface for further processing, thereby improving the application flexibility of the present invention.

[0036] Figure 1The control commands output by the user terminal or SoC MCU can control the operation enable and various working modes of the RF transceiver subsystem through the SoC bus. Figure 1 The specific control method is: the control signal controls the operation of the synthesizer, so that the frequency synthesizer generates the target frequency and the target chirp signal, and at the same time the frequency synthesizer feeds back the chirp signal start trigger signal and end trigger signal to the baseband processing subsystem.

[0037] like Figure 2 As shown: the present invention also includes an architecture implementation scheme of the RF transceiver subsystem, and the RF transceiver subsystem architecture is reconfigurable; the transmitting channel includes a passive matching network, a power amplifier (PA) and an off-chip antenna, and a passive matching network is used to obtain a higher in-band flatness; the receiving channel includes an off-chip antenna, a low noise amplifier (LNA), a mixer (MIXER), a transconductance amplifier (TIA), a bandpass filter (BPF) and an analog-to-digital converter (ADC). In the present invention, the MIXER can transform the time domain signal obtained by mixing into two signals with a phase difference of 90°, namely, an I channel signal and a Q channel signal. The two channel signals are respectively input into independent BPFs and ADCs for filtering, sampling and signal conversion, thereby obtaining higher anti-aliasing performance and anti-noise performance; the frequency synthesizer includes an on-chip crystal oscillator circuit (XO), a chirp signal generator (Chirp Gen), a phase-locked loop, a matching network and a power divider (PD). In the present invention, the phase-locked loop is used to generate an FMCW signal of a specific frequency band, which is used for signal transmission of the transmitting channel and signal mixing of the receiving channel; the Chirp Gen generates a control signal sequence that controls the phase-locked loop to output a specific frequency bandwidth and Chirp slope based on the control signal. At the same time, at the start and end times of the Chirp, the Chirp Gen will feed back the corresponding trigger signal to the baseband signal processing subsystem to ensure that the SoC MCU or the off-chip terminal can be synchronized with the Chirp signal. At the same time, the PD in the present invention divides the FMCW signal generated by the phase-locked loop into two FMCW signals with equal power, one of which is used for signal transmission of the transmitting channel, and the other is mixed with the receiving signal of the receiving channel.

[0038] Furthermore, the type of oscillator used by the frequency synthesizer can be reconfigured. In a specific embodiment, a ring oscillator with multiple outputs of different phases can be used as the oscillator, and the power divider can be omitted when the frequency synthesizer uses a ring oscillator with multiple outputs of different phases.

[0039] The reconfigurability in the RF transceiver subsystem architecture of the present invention means that: the output power, matching bandwidth and other performance indicators of the transmitting channel are reconfigurable; the signal gain, filter bandwidth and other performance indicators of the receiving channel are reconfigurable; the output frequency range of the frequency synthesizer, the slope of the Chirp signal, the Chirp signal waveform and other performance indicators are reconfigurable; the advantage of reconfigurability is that the present invention can be highly adaptable to multi-scenario applications, and can autonomously calibrate and adjust the module performance indicators according to the target distance, target size, environmental space size and ambient temperature of different application scenarios, so as to achieve the best FMCW radar measurement and perception effect; the performance indicators not mentioned in the above description but can be autonomously configured by the SoC MCU and the off-chip user terminal in the present invention are all applicable to the reconfigurable concept mentioned in the present invention.

[0040] like Figure 3 As shown: the present invention also includes a phase-locked loop architecture of a low quantization noise (Quantization Noise, Q-Noise) Chirp signal injection technology in a radio frequency transceiver subsystem. The phase-locked loop of the present invention includes a phase frequency detector (PFD), a charge pump (CP), a loop filter (LPF), a voltage-controlled oscillator (VCO), a true fractional divider (True-Fractional Divider, TF-Divider) and an output buffer (Buffer). The Chirp Gen module in the present invention controls the TF-Divider to generate a corresponding true fractional + integer division ratio through parallel digital signals, and the phase-locked loop responds accordingly, thereby changing the frequency following the signal generated by the Chirp Gen, thereby generating a corresponding FMCW signal. Since the TF-Divider can generate true fractional division, the quantization accuracy of the Chirp signal injection can be higher, so the Q-Noise is smaller and the linearity of the FMCW signal is higher.

[0041] For the TF-Divider in the present invention mentioned above, for example, if the present invention is required to generate a frequency division signal corresponding to N+0.3, if the TF-Divider is not used and only a general frequency divider is used, that is, a frequency divider that only generates N or N+1 frequency division, then in any frequency division, the frequency division ratio, that is, the ratio of the input frequency to the output frequency, is only N or N+1, and its average value of the frequency division ratio over time is N+1. Then, the quantized frequency division ratio error generated in any frequency division, that is, the difference between the required frequency division ratio and the actual frequency division ratio, is 0.3 or -0.7, and the probability of generation is 0.7 and 0.3 respectively. Now further assume that the injection signal of this general frequency divider is an evenly distributed random number sequence, then the mean square error of the frequency division ratio in this frequency division process is:

[0042]

[0043] Further assume that TF-Divider is used, and assume that a 6-bit TF-Divider is used in a certain implementation of the present invention, and the minimum frequency division ratio step size is 0.015625, then for the frequency division ratio corresponding to N+0.3 generated above, the two closest frequency division ratios of this TF-Divider are 0.296875 and 0.3125, respectively, and the frequency division ratio errors corresponding to the occurrence probabilities are 0.003125 or -0.0125, respectively, and the occurrence probabilities are 0.8 and 0.2, respectively. Then, the mean square error of the frequency division ratio when using TF-Divider in this example is:

[0044]

[0045] It can be considered that the mean square error can be used to quantize the magnitude of the quantization error of the frequency division error. Therefore, it can be further considered that the TF-Divider proposed in the present invention can effectively reduce the quantization noise introduced when the FMCW signal is injected.

[0046] like Figure 4 As shown: the present invention also includes an implementation scheme of an ASIC algorithm processing module in a baseband signal processing subsystem, the ASIC algorithm processing module includes a retiming unit and a fast Fourier transform (FFT) unit, the retiming unit receives a Chirp signal start trigger signal and an end trigger signal from the RF transceiver subsystem, or receives a Chirp signal start trigger signal and an end trigger signal of the RF transceiver subsystem actively controlled by a user terminal or SoCMCU, thereby determining the start time of receiving data from the RF transceiver subsystem, and sending the received data to the FFT unit and the SoC MCU or the user terminal, or sending the unretimed original data to the SoC MCU or the user terminal; the FFT unit receives data from the retiming unit, converts the time domain digital signal into a frequency domain digital signal through FFT, and sends the frequency domain digital signal to the SoC MCU or the user terminal. Using this kind of ASIC algorithm processing module of the architecture, the necessary processing of the signal received by the FMCW radar can be realized in the SoC, and the data processing related chips in the existing discrete FMCW radar system can be omitted, which not only saves the power consumption and cost of the system, but also eliminates various problems in the data transmission of discrete devices, thereby effectively improving the signal processing speed.

[0047] Specifically, in Figure 1 The matching network submodule in the transmit channel described in the foregoing may be included in the transmit channel in an alternative embodiment, thereby implementing the matching network inside the chip.

[0048] Specifically, the SoC microprocessor in the embodiment may need to use some existing digital IP cores, which may be interchangeable with the digital circuit used in this embodiment.

[0049] Specifically, the baseband signal processing subsystem may be implemented using existing discrete components, such as FPGA, dedicated digital chips, etc. in alternative embodiments.

[0050] Specifically, the control circuit of the multiple-transmit multiple-receive antenna array may be implemented off-chip in an alternative embodiment.

[0051] Specifically, the on-chip crystal oscillator circuit may use the following solution in an alternative embodiment: using an off-chip active crystal oscillator chip, no longer designing an oscillator circuit on the chip, and only using a drive circuit.

[0052] In summary, the reconfigurable FMCW radar SoC architecture integrates the reconfigurable FMCW radar RF transceiver and related data processing modules into the chip through SoC system architecture design. It has the advantages of simple structure, high stability, high resolution, low power consumption, and strong applicability.

[0053] The implementation scheme of the on-chip phase-locked loop circuit device in the present invention has the advantages of reconfigurability, large frequency modulation bandwidth, high frequency modulation linearity, etc. The implementation scheme of the on-chip adjustable bandpass filter circuit device has the advantages of being able to adjust the intermediate frequency bandwidth and gain according to the target and scenario; the overall SoC architecture scheme in the present invention has the advantages of monolithic integration, high stability, and low mass production cost; the ASIC algorithm architecture scheme in the present invention has the advantages of autonomous processing and calculation, efficient interaction, etc.

[0054] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in conjunction with such instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with such instruction execution systems, devices or apparatuses.

[0055] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering, or processing in another suitable manner as necessary, and then stored in a computer memory.

[0056] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0057] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A reconfigurable FMCW radar SoC architecture, including a radio frequency transceiver subsystem and a baseband signal processing subsystem, characterized in that: The radio frequency transceiver subsystem is electrically connected to the baseband signal processing subsystem; The baseband signal processing subsystem includes a chip with an ASIC algorithm processing module, a SoC bus, a SoC microprocessor with a SoC MCU module, and a SoC peripheral interface module; the SoC MCU module is used to control the RF transceiver subsystem and adjust according to the chip external information and the RF transceiver subsystem feedback signal; The ASIC algorithm processing module is used to process the time domain signal output by the RF transceiver subsystem, convert the time domain signal into a frequency domain signal through an algorithm, and transmit the frequency domain signal to the SoC MCU module or to an off-chip device via the SoC peripheral interface module for processing and analysis; The RF transceiver subsystem includes a receiving channel, a transmitting channel, a frequency synthesizer and a mixer. The RF transceiver subsystem exchanges information with each submodule inside the chip through the SoC bus, can drive the operation of the transceiver subsystem according to the control information of the on-chip main control chip, and transmit the signal to the ASIC algorithm processing module for processing.

2. The reconfigurable FMCW radar SoC architecture according to claim 1, characterized in that: The radio frequency transceiver subsystem and the baseband signal processing subsystem are both configured with at least one N-way, where N is an integer greater than or equal to 1.

3. The reconfigurable FMCW radar SoC architecture according to claim 1, characterized in that: The RF transceiver subsystem is directly connected to the ASIC algorithm processing module inside the chip. The ASIC algorithm processing module converts the time domain signal obtained by mixing the RF transceiver subsystem into a frequency domain signal, and transmits the frequency domain signal to the SoC MCU module through the SoC bus for further processing. The original time domain signal obtained by mixing and the processed frequency domain signal can be directly transmitted to the off-chip terminal through the SoC peripheral interface for processing.

4. The reconfigurable FMCW radar SoC architecture according to claim 2, characterized in that: The control command output by the user terminal or the SoC MCU module controls the operation of the radio frequency transceiver subsystem through the SoC bus.

5. The reconfigurable FMCW radar SoC architecture according to claim 1, characterized in that: The radio frequency transceiver subsystem architecture is reconfigurable; the transmission channel includes a passive matching network, a power amplifier and an off-chip antenna.

6. The reconfigurable FMCW radar SoC architecture according to claim 5, characterized in that: The receiving channel includes an off-chip antenna, a low-noise amplifier, a mixer, a transconductance amplifier, a bandpass filter and an analog-to-digital converter. The mixer can transform the time domain signal obtained by mixing into two signals with a phase difference of 90°, namely an I channel signal and a Q channel signal. The two channel signals are respectively input into independent BPFs and ADCs for filtering, sampling and signal conversion.

7. The reconfigurable FMCW radar SoC architecture according to claim 6, characterized in that: The frequency synthesizer includes an on-chip crystal oscillator circuit, a chirp signal generator, a phase-locked loop, a matching network and a power divider; The phase-locked loop is used to generate an FMCW signal of a specific frequency band, which is used for signal transmission of a transmitting channel and signal mixing of a receiving channel; The chirp signal generator generates a control signal sequence for controlling the phase-locked loop to output a specific frequency bandwidth and chirp slope according to the control signal. At the same time, at the start and end time of the chirp, the chirp signal generator will feed back the corresponding trigger signal to the baseband signal processing subsystem to ensure that the SoC MCU or the off-chip terminal is synchronized with the chirp signal.

8. The reconfigurable FMCW radar SoC architecture according to claim 7, characterized in that: The power divider divides one FMCW signal generated by the phase-locked loop into two FMCW signals with equal power, one of which is used for signal transmission of the transmission channel, and the other is mixed with the reception signal of the reception channel. The oscillator type used by the frequency synthesizer is reconfigurable; Also included is a phase-locked loop architecture of a low quantization noise Chirp signal injection technology in a radio frequency transceiver subsystem, wherein the phase-locked loop includes a frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a true fractional frequency divider, and an output buffer; The chirp signal generator controls the true fractional frequency divider to generate a corresponding true fractional + integer frequency division ratio through a parallel digital signal, and the phase-locked loop responds accordingly, changes the frequency following the signal generated by the chirp signal generator, and generates a corresponding FMCW signal.

9. The reconfigurable FMCW radar SoC architecture according to claim 1, characterized in that: The ASIC algorithm processing module includes a retiming unit and a fast Fourier transform unit, and the retiming unit receives a Chirp signal start trigger signal and an end trigger signal from a radio frequency transceiver subsystem; Or receiving the Chirp signal start trigger signal and end trigger signal of the RF transceiver subsystem actively controlled by the user terminal or SoC MCU, determining the start time of receiving data from the RF transceiver subsystem, and sending the received data to the FFT unit and SoC MCU or user terminal, or sending the unretimed original data to the SoC MCU or user terminal; 10. The reconfigurable FMCW radar SoC architecture according to claim 9, characterized in that: The FFT unit receives data from the retiming unit, converts the time domain digital signal into a frequency domain digital signal through FFT, and transmits the frequency domain digital signal to the SoC MCU or the user terminal.

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