Display panel and manufacturing method thereof

Abstract

The invention relates to a display panel and a manufacturing method thereof. The display panel comprises an array substrate and a color film substrate arranged opposite to the array substrate. The array substrate comprises a substrate, an active layer, a first metal layer, a second metal layer, a common electrode layer and a third metal layer which are sequentially arranged in the thickness direction of the array substrate. The first metal layer comprises a grid electrode; the second metal layer comprises a source electrode and a drain electrode; the common electrode layer comprises at least two common electrodes and at least one first electrode connecting line; the third metal layer comprises at least two common electrode wires and at least one second electrode connecting wire; wherein the first electrode connecting lines are connected with two adjacent common electrodes, the second electrode connecting lines are connected with the common electrode lines, and the second electrode connecting lines are located on the sides, away from the second metal layer, of the first electrode connecting lines and make contact with the first electrode connecting lines. The penetration rate of the display panel can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof. Background Art

[0002] High transmission Fringe Field Switching (HFS) type display products drive the liquid crystal deflection through the horizontal electric field between the common electrode (COM-ITO) and the pixel electrode (Pixel-ITO) on the array substrate side, thereby realizing the normal display of the display panel, wherein the voltage on the COM-ITO is provided by the common electrode line (Acom). In the traditional common electrode connection design, in order to avoid a short circuit between the COM-ITO of two pixels (Pixel) and the gate line (Gate) when the COM-ITO is connected, a via design and a bridging metal between the two vias are usually used to connect the COM-ITO of two adjacent pixels. However, since the vias and the shielding layer (BM) used to shield the vias are not light-transmitting, the aperture ratio will be greatly reduced, thereby reducing the penetration rate of the display panel. Summary of the invention

[0003] The embodiments of the present application provide a display panel and a manufacturing method thereof, which can effectively improve the transmittance of the display panel.

[0004] In order to achieve the above-mentioned object, according to a first aspect of the present application, a display panel is provided, the display panel comprising an array substrate and a color filter substrate arranged opposite to the array substrate; the array substrate comprises:

[0005] substrate;

[0006] A first metal layer, disposed above the substrate, wherein the first metal layer includes a gate;

[0007] An active layer is arranged on a side of the first metal layer away from the substrate;

[0008] A second metal layer is disposed on a side of the active layer away from the substrate, the second metal layer comprising a source electrode and a drain electrode;

[0009] a common electrode layer, disposed on a side of the second metal layer away from the active layer, the common electrode layer comprising at least two common electrodes and at least one first electrode connecting line; and

[0010] A third metal layer is disposed on a side of the common electrode layer away from the second metal layer, the third metal layer comprising at least two common electrode lines and at least one second electrode connecting line;

[0011] The first electrode connection line connects two adjacent common electrodes, the second electrode connection line is connected to the common electrode line, and the second electrode connection line is located on a side of the first electrode connection line away from the second metal layer and contacts the first electrode connection line.

[0012] In some embodiments, the first metal layer further includes a plurality of gate lines extending along a first direction, the second metal layer further includes a plurality of data lines extending along a second direction, the first direction intersects with the second direction, the plurality of data lines and the plurality of gate lines are intersected to define a plurality of pixel areas, and the common electrodes correspond to the pixel areas one by one;

[0013] The first electrode connection line and the second electrode connection line both extend along the second direction, and in the second direction, the length of the second electrode connection line is greater than or equal to the length of the first electrode connection line.

[0014] In some embodiments, the common electrode line is located on a side of the common electrode away from the second metal layer and is in contact with the common electrode;

[0015] The common electrode line extends along the first direction and is located at the edge of the common electrode. One end of the second electrode connecting line is connected to the common electrode line, and the other end extends toward the adjacent common electrode.

[0016] In some embodiments, the third metal layer also includes a second electrode connection line extension portion, the second electrode connection line extension portion is located at an end of the second electrode connection line away from the common electrode line, the orthographic projection of the second electrode connection line extension portion on the substrate is located within the orthographic projection range of the common electrode on the substrate, and the width of the second electrode connection line extension portion in the first direction is greater than the width of the second electrode connection line in the first direction.

[0017] In some embodiments, a material of the first electrode connection line is the same as a material of the common electrode, and a material of the second electrode connection line is the same as a material of the common electrode line.

[0018] In some embodiments, the material of the common electrode is metal oxide, and the material of the common electrode line is metal.

[0019] In some embodiments, the display panel further comprises:

[0020] A plurality of spacer columns are arranged between the array substrate and the color filter substrate, and the spacer columns are located between two adjacent common electrodes;

[0021] The orthographic projection of the first electrode connecting line on the substrate and the orthographic projection of the second electrode connecting line on the substrate are both located between the orthographic projections of adjacent spacer columns on the substrate.

[0022] In some embodiments, the array substrate further includes:

[0023] A gate insulating layer, disposed between the first metal layer and the active layer;

[0024] A passivation layer, disposed between the second metal layer and the common electrode layer;

[0025] a planar layer, disposed on a side of the third metal layer away from the common electrode layer; and

[0026] A pixel electrode layer, arranged on a side of the planar layer away from the third metal layer;

[0027] The pixel electrode layer is connected to the second metal layer through a first via hole penetrating the planar layer and the passivation layer.

[0028] According to a second aspect of the present application, a method for manufacturing a display panel is provided, comprising:

[0029] providing a substrate;

[0030] forming a first metal layer on the substrate, wherein the first metal layer includes a gate;

[0031] forming an active layer on the first metal layer;

[0032] forming a second metal layer on the active layer, wherein the second metal layer includes a source electrode and a drain electrode;

[0033] forming a common electrode layer on the second metal layer, the common electrode layer comprising at least two common electrodes and at least one first electrode connection line, the common electrodes corresponding to the pixel areas one by one, and the first electrode connection line connecting two adjacent common electrodes;

[0034] A third metal layer is formed on the common electrode layer, the third metal layer includes at least two common electrode lines and at least one second electrode connecting line, the second electrode connecting line is connected to the common electrode line, the second electrode connecting line is located on a side of the first electrode connecting line away from the second metal layer, and is in contact with the first electrode connecting line.

[0035] In some embodiments, the common electrode layer and the third metal layer are formed by a half-tone mask process.

[0036] The present application provides a display panel and a manufacturing method thereof. Adjacent common electrodes on the array substrate side of the display panel of the present application are connected by a first electrode connection line, and a second electrode connection line is arranged on the first electrode connection line. The second electrode connection line contacts the first electrode connection line and is connected to the common electrode line. Therefore, the common electrode line can transmit a common signal to two adjacent common electrodes connected by the first electrode connection line through the second electrode connection line. In the present application, the first metal layer, the common electrode layer, and the third metal layer are located in different film layers, and there will be no short circuit at the overlap; and the present application directly arranges the first electrode connection line in the same layer of the common electrode to bridge the two adjacent common electrodes, so that the signal between the adjacent common electrodes is connected to stabilize the common electrode signal; at the same time, the second electrode connection line is stacked and directly contacted with the first electrode connection line to transmit the common signal, and the conductivity of the signal is enhanced. The present application does not need to set a via hole and a bridging metal connecting the via hole, and can realize the signal connection between adjacent common electrodes, and thus does not need to set a BM to block the via hole, so that the aperture ratio of the pixel is improved, which is beneficial to improve the penetration rate of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0038] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0039] Figure 1 It is a top view of a display panel provided by the prior art;

[0040] Figure 2 yes Figure 1 Sectional view at 1-1 in the middle;

[0041] Figure 3 yes Figure 1 Sectional view at 2-2 in the middle;

[0042] Figure 4 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0043] Figure 5 is a top view of a display panel provided by an embodiment of the present application;

[0044] Figure 6 yes Figure 5 Sectional view at 3-3 in the middle;

[0045] Figure 7 yes Figure 5 Sectional view at 4-4;

[0046] Figure 8 yes Figure 5 Sectional view at 5-5;

[0047] Fig. 9 is a top view of a first metal layer of a display panel provided by an embodiment of the present application;

[0048] Fig.10 is a top view of a first metal layer and a second metal layer of a display panel provided by an embodiment of the present application;

[0049] Fig.11 It is a top view of a first metal layer, a second metal layer, a common electrode layer and a third metal layer of a display panel provided by an embodiment of the present application.

[0050] Description of reference numerals:

[0051] 10. Display panel; 100. Array substrate; 110. Substrate; 111. Gate insulating layer; 112. Active layer; 1121. Semiconductor structure; 113. Passivation layer; 114. Flat layer; 115. First contact hole; 116. Second contact hole; 117. Bridge metal; 120. First metal layer; 121. Gate line; 122. Gate; 123. First blocking part; 130. Second metal layer; 131. Data line; 132. Source; 133. Drain; 134. Second blocking part; 140, common electrode layer; 141, common electrode; 1411, first common electrode; 1412, second common electrode; 142, first electrode connecting line; 143, third blocking portion; 150, third metal layer; 151, common electrode line; 152, second electrode connecting line; 153, fourth blocking portion; 154, second electrode connecting line extension portion; 160, pixel electrode layer; 170, limiting retaining wall; 180, spacer column; 190, first via hole; 200, color film substrate; 300, liquid crystal layer. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0053] See also Figure 1-Figure 3 , Figure 1The top view of a display panel provided by the prior art is shown in FIG. 1. The display panel includes an array substrate 100 and a color filter substrate 200 , and a liquid crystal layer 300 located between the array substrate 100 and the color filter substrate 200 .

[0054] See also Figure 2 , the display panel is in HFS display mode, that is, the common electrode 141 (COM-ITO) and the pixel electrode (Pixel-ITO) are both located on the side of the array substrate 100, and the liquid crystal deflection is driven by the horizontal electric field between the common electrode 141 and the pixel electrode on the side of the array substrate 100. Specifically, the array substrate 100 includes a substrate 110, a common electrode layer 140, a first metal layer 120, a gate insulating layer 111, an active layer 112, a second metal layer 130, a passivation layer 113 and a pixel electrode layer 160 arranged in sequence along the thickness direction thereof. Among them, the common electrode layer 140 includes a plurality of common electrodes 141 arranged in an array. The first metal layer 120 includes a plurality of gate lines 121, which extend along a first direction and are arranged along a second direction. The second metal layer 130 includes a plurality of data lines 131, which extend along the second direction and are arranged along the first direction. The plurality of data lines 131 and the plurality of gate lines 121 are cross-arranged to define a plurality of pixel areas, and the common electrodes 141 are arranged one-to-one in correspondence with the pixel areas.

[0055] See also Figure 1 and Figure 3 , the second metal layer 130 also includes a bridging metal 117. Along the second direction, two adjacent pixel areas are respectively provided with a first contact hole 115 and a second contact hole 116, the first contact hole 115 exposes the common electrode 141 of one of the pixel areas, the second contact hole 116 exposes the common electrode 141 of the other pixel area, the first contact hole 115 and the second contact hole 116 are both filled with electrode materials, the bridging metal 117 contacts the electrode materials in the first contact hole 115 and the electrode materials in the second contact hole 116, so as to realize electrical connection between the common electrodes 141 of the two adjacent pixel areas. However, a shielding layer is usually required above the contact hole, and the shielded area above the contact hole cannot transmit light, so the design of the via hole will reduce the aperture ratio, thereby reducing the penetration rate of the display panel.

[0056] To solve the above problems, please refer to Figure 4-Figure 11The present application provides a display panel 10, which includes an array substrate 100 and a color film substrate 200 arranged opposite to the array substrate 100. The array substrate 100 includes a substrate 110, an active layer 112, a first metal layer 120, a second metal layer 130, a common electrode layer 140 and a third metal layer 150. The first metal layer 120 is arranged above the substrate 110, and the first metal layer 120 includes a gate 122; the active layer 112 is arranged on a side of the first metal layer 120 away from the substrate 110; the second metal layer 130 is arranged on a side of the first metal layer 120 away from the active layer 112, and the second metal layer 130 includes a source 132 and a drain 133; the common electrode layer 140 is arranged on a side of the second metal layer 130 away from the active layer 112, and the common electrode layer 140 includes at least two common electrodes 141 and at least one first electrode The third metal layer 150 is arranged on the side of the common electrode layer 140 away from the second metal layer 130, and the third metal layer 150 includes at least two common electrode lines 151 and at least one second electrode connection line 152; wherein, the first electrode connection line 142 connects two adjacent common electrodes 141, the second electrode connection line 152 is connected to the common electrode line 151, and the second electrode connection line 152 is located on the side of the first electrode connection line 142 away from the second metal layer 130, and is in contact with the first electrode connection line 142.

[0057] The array substrate 100 of the present application directly sets the first electrode connection line 142 on the same layer of the common electrode 141, and the adjacent common electrodes 141 are bridged by the first electrode connection line 142 to achieve signal conduction between the adjacent common electrodes 141, thereby stabilizing the signal of the common electrodes 141. Therefore, the present application does not need to set vias to connect the adjacent common electrodes 141, nor does it need to set a shielding layer to block the vias, which can effectively improve the aperture ratio. In addition, the array substrate 100 of the present application sets the second electrode connection line 152 on the first electrode connection line 142, and the second electrode connection line 152 contacts the first electrode connection line 142 and is connected to the common electrode line 151. The common electrode line 151 can transmit the common signal to the two adjacent common electrodes 141 connected by the corresponding first electrode connection line 142 through the second electrode connection line 152, and the second electrode connection line 152 is stacked and directly contacted with the first electrode connection line 142, which can enhance the conductivity of the signal and ensure the signal stability of the common electrode 141. In addition, the first metal layer 120, the common electrode layer 140, and the third metal layer 150 of the present application are located in different film layers, and there will be no short circuit at the overlapping parts.

[0058] For further information, see Figure 5-Figure 7 The array substrate 100 further includes a gate insulating layer 111, a passivation layer 113, a planarization layer 114, and a pixel electrode layer 160. The gate insulating layer 111 is disposed between the first metal layer 120 and the active layer 112; the passivation layer 113 is disposed between the second metal layer 130 and the common electrode layer 140; the planarization layer 114 is disposed on a side of the third metal layer 150 away from the common electrode layer 140; and the pixel electrode layer 160 is disposed on a side of the planarization layer 114 away from the third metal layer 150.

[0059] In one embodiment, see Figure 5-Figure 11 The array substrate 100 includes a substrate 110 , a first metal layer 120 , a gate insulating layer 111 , an active layer 112 , a second metal layer 130 , a passivation layer 113 , a common electrode layer 140 , a third metal layer 150 , a planarization layer 114 and a pixel electrode layer 160 .

[0060] The substrate 110 may be a flexible substrate, such as polyimide (PI), or a rigid substrate, such as glass, but is not limited thereto.

[0061] The first metal layer 120 is disposed on one side of the substrate 110. Figure 5 and Fig. 9 , the first metal layer 120 includes a gate 122 and a plurality of gate lines 121, the gate 122 is connected to the gate line 121 and is a part of the gate line 121. The gate line 121 extends along a first direction, and the plurality of gate lines 121 are arranged along a second direction. The material of the first metal layer 120 is a metal, such as a combination of one or more of Mo, Al, and Cu, but is not limited thereto. In the present application, the first direction refers to the X direction in the figure, and the second direction refers to the Y direction in the figure.

[0062] The gate insulating layer 111 is disposed on a side of the first metal layer 120 away from the substrate 110 to insulate the first metal layer 120 from the active layer 112 and the second metal layer 130. The gate insulating layer 111 is made of an inorganic material, such as silicon nitride (SiNx), silicon oxide (SiOx), etc., but is not limited thereto.

[0063] The active layer 112 is disposed on a side of the gate insulating layer 111 away from the first metal layer 120, and includes a semiconductor structure 1121. The semiconductor structure 1121 is disposed on a side of the gate insulating layer 111 away from the gate 122 as a part of a thin film transistor. The material of the active layer 112 may be amorphous silicon (a-Si) or doped amorphous silicon, but is not limited thereto.

[0064] The second metal layer 130 is disposed on a side of the active layer 112 away from the gate insulating layer 111. Figure 5 and Fig.10 The second metal layer 130 includes a source electrode 132, a drain electrode 133 and a plurality of data lines 131. Figure 6 , the source electrode 132 and the drain electrode 133 are connected to the active layer 112, and the source electrode 132, the drain electrode 133, the semiconductor structure 1121 and the gate electrode 122 constitute a thin film transistor. The data line 131 extends along the second direction, and a plurality of the data lines 131 are arranged along the first direction. The plurality of data lines 131 and the plurality of gate lines 121 are cross-arranged to define a plurality of pixel areas, and each of the pixel areas is correspondingly provided with a pixel unit, and each pixel unit includes a thin film transistor. For example, the first direction may be perpendicular to the second direction, and a plurality of the pixel areas may be arranged in an array, that is, arranged in an array along the first direction and the second direction, and correspondingly, the pixel units and the thin film transistors are also arranged in an array. The material of the second metal layer 130 is a metal, such as a combination of one or more of Mo, Al, and Cu, but is not limited thereto.

[0065] The passivation layer 113 is disposed on a side of the second metal layer 130 away from the active layer 112, and covers the source electrode 132, the drain electrode 133, and the data line 131 to protect the second metal layer 130. The material of the passivation layer 113 is an inorganic material, such as silicon nitride (SiNx), silicon oxide (SiOx), etc., but is not limited thereto.

[0066] The common electrode layer 140 is disposed on a side of the passivation layer 113 away from the second metal layer 130. Figure 5 and Fig.11, the common electrode layer 140 includes a plurality of common electrodes 141 and a plurality of first electrode connection lines 142, the common electrodes 141 correspond to the pixel areas one by one, that is, one common electrode 141 is arranged in each pixel area. The common electrode 141 is a block electrode, and the plurality of common electrodes 141 are arranged in an array along the first direction and the second direction. Along the second direction, the plurality of common electrodes 141 are arranged at intervals, the first electrode connection line 142 is located between adjacent common electrodes 141 and connects two adjacent common electrodes 141, and the first electrode connection line 142 can realize the signal connection between the two adjacent common electrodes 141 to stabilize the common (COM) signal on the common electrode 141. The material of the common electrode 141 can be a metal oxide, such as indium tin oxide (ITO), but is not limited thereto.

[0067] For details, please refer to Figure 5 Taking the first common electrode 1411 and the second common electrode 1412 adjacent to each other in the second direction as an example, the first electrode connection line 142 extends along the second direction, one end of the first electrode connection line 142 is connected to the first common electrode 1411, and the other end of the first electrode connection line 142 is connected to the second common electrode 1412. The material of the first electrode connection line 142 can be the same as that of the common electrode 141, so that the first electrode connection line 142 and the common electrode 141 are arranged in the same layer, that is, patterned by the same process to simplify the process.

[0068] The third metal layer 150 is disposed on a side of the common electrode layer 140 away from the passivation layer 113. Figure 5 and Fig.11 The third metal layer 150 includes a plurality of common electrode lines 151 and a plurality of second electrode connection lines 152. The plurality of common electrode lines 151 are arranged along the second direction and extend along the first direction. The common electrode lines 151 are used to provide common signals to the common electrodes 141. Figure 5 and Figure 7, the second electrode connection line 152 is connected to the common electrode line 151, and the second electrode connection line 152 is located on the side of the first electrode connection line 142 away from the second metal layer 130, and is in contact with the first electrode connection line 142, so the common signal of the common electrode line 151 can be transmitted to the two adjacent common electrodes 141 connected to the corresponding first electrode connection line 142 through the second electrode connection line 152 connected thereto. The second electrode connection line 152 and the first electrode connection line 142 are stacked and contacted, and together constitute a signal connection line between adjacent common electrodes 141, which can increase the overall conductivity of the signal connection line between the two adjacent common electrodes 141, so as to further improve the signal stability of the common electrode 141.

[0069] In the present application, the material of the second electrode connection line 152 is the same as that of the common electrode line 151, so that the second electrode connection line 152 and the common electrode line 151 are arranged in the same layer, that is, patterned by the same process to simplify the process. The material of the third metal layer 150 is metal, that is, the material of the second electrode connection line 152 and the material of the common electrode line 151 are metal, such as a combination of one or more of Mo, Al, and Cu, but not limited thereto.

[0070] For details, please refer to Figure 5 , the first electrode connection line 142 and the second electrode connection line 152 both extend along the second direction. In the second direction, the length of the second electrode connection line 152 is greater than or equal to the length of the first electrode connection line 142, that is, one end of the second electrode connection line 152 extends to the first common electrode 1411, and the other end of the second electrode connection line 152 extends to the second common electrode 1412, which is beneficial for the common electrode 141 that is far away from the common electrode line 151 among the two adjacent common electrodes 141 to maintain signal stability.

[0071] In the present application, one common electrode line 151 may be provided corresponding to one pixel region. The common electrode line 151 may be provided at the edge of the common electrode 141. The common electrode line 151 is located on the side of the common electrode 141 away from the second metal layer 130 and is in contact with the common electrode 141, so as to facilitate signal transmission to the common electrode 141 and connection with the second electrode connection line 152, while reducing the impact on the pixel opening region. One end of the second electrode connection line 152 is connected to the common electrode line 151, and the other end extends toward the adjacent common electrode 141. For details, please refer to Figure 5The common electrode line 151 can be set at the edge of the second common electrode 1412 close to the first common electrode 1411, and one end of the second electrode connecting line 152 is connected to the common electrode line 151, and the other end extends to the range of the second common electrode 1412.

[0072] In some embodiments, see Figure 5 and Fig.11 , the third metal layer 150 further includes a second electrode connection line extension portion 154, the second electrode connection line extension portion 154 is located at an end of the second electrode connection line 152 away from the common electrode line 151, the orthographic projection of the second electrode connection line extension portion 154 on the substrate 110 is located within the orthographic projection range of the common electrode 141 on the substrate 110, wherein the length of the second electrode connection line 152 in the second direction is equal to the length of the first electrode connection line 142 in the second direction ( Fig.11 The second electrode connection line 152 covers the first electrode connection line 142), and the width of the second electrode connection line extension 154 in the first direction is greater than the width of the second electrode connection line 152 in the first direction. This can increase the contact area between the second electrode connection line 152 and the common electrode 141 on the side away from the common electrode line 151, and further enhance the signal conductivity between two adjacent common electrodes 141 to ensure the signal stability of the common electrode 141.

[0073] The planar layer 114 is disposed on a side of the third metal layer 150 away from the common electrode layer 140 to planarize the third metal layer 150 . The planar layer 114 is made of an organic material, such as soluble polytetrafluoroethylene (PFA), but is not limited thereto.

[0074] The pixel electrode layer 160 is disposed on a side of the planar layer 114 away from the third metal layer 150, and the pixel electrode layer 160 is a strip electrode or a comb electrode. The array substrate 100 is further provided with a first via hole 190 penetrating the passivation layer 113 and the planar layer 114, and the first via hole 190 exposes the drain electrode 133 located in the second metal layer 130, and the pixel electrode layer 160 is electrically connected to the drain electrode 133 of the thin film transistor through the first via hole 190, and the drain electrode 133 is connected to the source electrode 132 through the semiconductor structure 1121, and the source electrode 132 is connected to the data line 131, that is, the signal transmission between the data line 131 and the pixel electrode layer 160 is realized. The material of the pixel electrode layer 160 can be a metal oxide, such as indium tin oxide (ITO), but is not limited thereto.

[0075] In the present application, the array substrate 100 provides a data signal to the pixel electrode layer 160 through the data line 131, and the common electrode 141 provides a common signal through the common electrode line 151. The liquid crystal is deflected under the action of the data signal and the common signal, thereby realizing the picture display of the display panel 10, that is, the HFS display mode, and the liquid crystal deflection is driven by the horizontal electric field between the common electrode 141 on the array substrate 100 side and the pixel electrode layer 160.

[0076] In this application, please refer to Figure 4 The display panel 10 further includes a liquid crystal layer 300 and a plurality of spacer columns 180 .

[0077] The liquid crystal layer 300 is disposed between the array substrate 100 and the color filter substrate 200 , and the display panel 10 realizes picture display through the deflection of the liquid crystal molecules.

[0078] The spacer column 180 is disposed between the array substrate 100 and the color filter substrate 200 to play a supporting role. Figure 5 The orthographic projection of the spacer column 180 on the substrate 110 is located in the non-display area between the orthographic projections of two adjacent common electrodes 141 on the substrate 110, so as to reduce the influence on the pixel aperture ratio. The spacer column 180 is located on one side of the thin film transistor in the first direction, so as to reasonably utilize the non-display area between the two adjacent common electrodes 141 and improve the pixel aperture ratio.

[0079] In the present application, the orthographic projection of the first electrode connection line 142 on the substrate 110 and the orthographic projection of the second electrode connection line 152 on the substrate 110 are both located between the orthographic projections of adjacent spacer columns 180 on the substrate 110. While making rational use of space, it can reduce the risk of interference between the first electrode connection line 142, the second electrode connection line 152 and metal wires such as the thin film transistor and the data line 131 due to their close distance.

[0080] In some embodiments, the display panel 10 further includes a limiting retaining wall 170 located on the array substrate 100 , and the limiting retaining wall 170 is located on at least one side of the spacer column 180 . Figure 5 and Figure 8The orthographic projection of the limiting retaining wall 170 on the substrate 110 is located between the orthographic projection of the common electrode 141 on the substrate 110 and the orthographic projection of the spacer column 180 on the substrate 110. The limiting retaining wall 170 includes a first barrier 123, a second barrier 134, a third barrier 143 and a fourth barrier 153 which are sequentially arranged along the thickness direction of the substrate 110. The first barrier 123 is located in the first metal layer 120 and is made of the same material as the first metal layer 120; the second barrier 134 is located in the second metal layer 130 and is made of the same material as the second metal layer 130; the third barrier 143 is located in the common electrode layer 140 and is made of the same material as the common electrode layer 140; the fourth barrier 153 is located in the third metal layer 150 and is made of the same material as the third metal layer 150. The first barrier 123, the second barrier 134, the third barrier 143 and the fourth barrier 153 are formed respectively while preparing the first metal layer 120, the second metal layer 130, the common electrode layer 140 and the third metal layer 150. The first barrier 123, the second barrier 134 and the third barrier 143 are all independent convex structures. The first barrier 123, the second barrier 134, the third barrier 143 and the fourth barrier 153 are stacked in the thickness direction of the substrate 110 to form a convex structure, forming the limiting retaining wall 170, which can prevent the spacer column 180 from sliding when the array substrate 100 and the color film substrate 200 are assembled, so as to limit the spacer column 180. The limiting retaining wall 170 can be arranged on one side or two opposite sides of the spacer column 180 in the second direction, and no specific limitation is made here.

[0081] The present application also provides a method for manufacturing a display panel 10, and the method for manufacturing the display panel 10 includes:

[0082] Providing a substrate 110;

[0083] Forming a first metal layer 120 on the substrate 110, wherein the first metal layer 120 includes a gate 122;

[0084] forming a gate insulating layer 111 on the first metal layer 120;

[0085] forming an active layer 112 on the gate insulating layer 111;

[0086] A second metal layer 130 is formed on the active layer 112 , wherein the second metal layer 130 includes a source electrode 132 and a drain electrode 133 ;

[0087] forming a passivation layer 113 on the second metal layer 130;

[0088] A common electrode layer 140 is formed on the passivation layer 113 , wherein the common electrode layer 140 includes at least two common electrodes 141 and at least one first electrode connection line 142 , wherein the first electrode connection line 142 connects two adjacent common electrodes 141 ;

[0089] A third metal layer 150 is formed on the common electrode layer 140, wherein the third metal layer 150 includes at least two common electrode lines 151 and at least one second electrode connection line 152, wherein the second electrode connection line 152 is connected to the common electrode line 151, and the second electrode connection line 152 is located on a side of the first electrode connection line 142 away from the second metal layer 130, and is in contact with the first electrode connection line 142;

[0090] forming a planarization layer 114 on the third metal layer 150; and

[0091] A pixel electrode layer 160 is formed on the planar layer 114 to form the array substrate 100 .

[0092] Furthermore, the method for manufacturing the display panel 10 further includes:

[0093] Forming a spacer column 180 on the array substrate 100;

[0094] Providing a color filter substrate 200, and aligning the color filter substrate 200 with the array substrate 100, wherein one end of the spacer column 180 is connected to the array substrate 100, and the other end is connected to the color filter substrate 200;

[0095] Liquid crystal is injected between the array substrate 100 and the color filter substrate 200 to form the display panel 10 .

[0096] In some embodiments, during the preparation of the array substrate 100, the common electrode layer 140 and the third metal layer 150 can be formed by a half-tone mask process. The patterns of the common electrode layer 140 and the third metal layer 150 are formed by a single mask process, which can save processes, simplify processes, and reduce costs. Since the common electrode layer 140 and the third metal layer 150 are made of different materials and are located in different layers, the masks of the common electrode layer 140 and the third metal layer 150 can be implemented by a half-tone process.

[0097] Specifically, taking the HFS display panel 10 of the 6-mask process as an example, the preparation method of the array substrate 100 includes:

[0098] S1. Provide a substrate 110. The substrate 110 may be a flexible substrate, such as polyimide (PI), or a rigid substrate, such as glass.

[0099] S2, depositing a first metal material layer on the substrate 110, and patterning the first metal material layer through a first photomask process to form a pattern of the first metal layer 120. Fig. 9 The first metal layer 120 includes a plurality of gate lines 121, a gate 122 and a first barrier 123. The material of the first metal layer 120 is metal, such as a combination of one or more of Mo, Al and Cu.

[0100] S3, depositing a gate insulating material layer on the first metal layer 120 to form the gate insulating layer 111. The gate insulating layer 111 is made of an inorganic material, such as silicon nitride (SiNx), silicon oxide (SiOx), and the like.

[0101] S4, depositing an active material layer on the gate insulating layer 111. The material of the active layer 112 may be amorphous silicon (a-Si) or doped amorphous silicon.

[0102] S5, depositing a second metal material layer on the active film layer, and patterning the active material layer and the second metal material layer through a second photomask process to form patterns of the active layer 112 and the second metal layer 130. The active layer 112 includes a semiconductor structure 1121. Fig.10 The second metal layer 130 includes a plurality of data lines 131, a source electrode 132, a drain electrode 133, and a second blocking portion 134. The active layer 112 and the second metal layer 130 are formed in one photomask process, which can reduce the number of photomasks, simplify the process, and reduce the cost. The material of the second metal layer 130 is metal, such as a combination of one or more of Mo, Al, and Cu.

[0103] S6, depositing a passivation material layer on the second metal layer 130, and patterning the passivation material layer through a third photomask process to form the passivation layer 113, wherein the passivation layer 113 includes a second via hole, and the second via hole exposes the drain electrode 133. The material of the passivation layer 113 is an inorganic material, such as silicon nitride (SiNx), silicon oxide (SiOx), etc.

[0104] S7, depositing a common electrode material layer on the passivation layer 113. The material of the common electrode 141 may be indium tin oxide (ITO).

[0105] S8, depositing a third metal material layer on the common electrode material layer, and patterning the common electrode material layer and the third metal material layer through a fourth photomask process to form patterns of the common electrode layer 140 and the third metal layer 150. Fig.11 The common electrode layer 140 includes a common electrode 141, a first electrode connection line 142 and a third blocking portion 143, wherein the first electrode connection line 142 connects two adjacent common electrodes 141; the third metal layer 150 includes a common electrode line 151, a second electrode connection line 152, a second electrode connection line extension 154 and a fourth blocking portion 153, wherein the second electrode connection line 152 is connected to the common electrode line 151, the second electrode connection line 152 is located at a side of the first electrode connection line 142 away from the second metal layer 130 and in contact with the first electrode connection line 142, and the second electrode connection line extension 154 is located at an end of the second electrode connection line 152 away from the common electrode line 151. The material of the third metal layer 150 is metal, such as a combination of one or more of Mo, Al and Cu.

[0106] S9, depositing a flat material layer on the third metal layer 150, and patterning the flat material layer through a fifth photomask process to form the flat layer 114, wherein the flat layer 114 includes a third via hole, and the third via hole is connected to the second via hole to form the first via hole 190. The material of the flat layer 114 may be PFA.

[0107] S10, depositing a pixel electrode material layer on the planar layer 114, and patterning the pixel electrode material layer through a sixth photomask process to form a pattern of the pixel electrode layer 160, and the pixel electrode layer 160 is connected to the drain 133 through the first via hole 190 to form the array substrate 100.

[0108] In the present application, the display panel 10 may be a Fringe Field Switching (FFS) display type, a High Transmission Fringe Field Switching (HFS) display type, etc., but is not limited thereto.

[0109] The present application provides a display panel and a manufacturing method thereof. Adjacent common electrodes on the array substrate side of the display panel of the present application are connected by a first electrode connection line, and a second electrode connection line is arranged on the first electrode connection line. The second electrode connection line contacts the first electrode connection line and is connected to the common electrode line. Therefore, the common electrode line can transmit a common signal to two adjacent common electrodes connected by the first electrode connection line through the second electrode connection line. In the present application, the first metal layer, the common electrode layer, and the third metal layer are located in different film layers, and there will be no short circuit at the overlap; and the present application directly arranges the first electrode connection line in the same layer of the common electrode to bridge the two adjacent common electrodes, so that the signal between the adjacent common electrodes is connected to stabilize the common electrode signal; at the same time, the second electrode connection line is stacked and directly contacted with the first electrode connection line to transmit the common signal, and the conductivity of the signal is enhanced. The present application does not need to set a via hole and a bridging metal connecting the via hole, and can realize the signal connection between adjacent common electrodes, and thus does not need to set a BM to block the via hole, so that the aperture ratio of the pixel is improved, which is beneficial to improve the penetration rate of the display panel.

[0110] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0111] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0112] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0113] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: It comprises an array substrate and a color filter substrate arranged opposite to the array substrate; the array substrate comprises: substrate; A first metal layer, disposed above the substrate, wherein the first metal layer includes a gate; An active layer is arranged on a side of the first metal layer away from the substrate; A second metal layer is disposed on a side of the active layer away from the substrate, the second metal layer comprising a source electrode and a drain electrode; a common electrode layer, disposed on a side of the second metal layer away from the active layer, the common electrode layer comprising at least two common electrodes and at least one first electrode connecting line; and A third metal layer is disposed on a side of the common electrode layer away from the second metal layer, the third metal layer comprising at least two common electrode lines and at least one second electrode connecting line; The first electrode connection line connects two adjacent common electrodes, the second electrode connection line is connected to the common electrode line, and the second electrode connection line is located on a side of the first electrode connection line away from the second metal layer and contacts the first electrode connection line.

2. The display panel according to claim 1, characterized in that: The first metal layer further includes a plurality of gate lines extending along a first direction, the second metal layer further includes a plurality of data lines extending along a second direction, the first direction intersects with the second direction, the plurality of data lines and the plurality of gate lines are intersected to define a plurality of pixel areas, and the common electrodes correspond to the pixel areas one by one; The first electrode connection line and the second electrode connection line both extend along the second direction, and in the second direction, the length of the second electrode connection line is greater than or equal to the length of the first electrode connection line.

3. The display panel according to claim 2, characterized in that: The common electrode line is located at a side of the common electrode away from the second metal layer and is in contact with the common electrode; The common electrode line extends along the first direction and is located at the edge of the common electrode. One end of the second electrode connecting line is connected to the common electrode line, and the other end extends toward the adjacent common electrode.

4. The display panel according to claim 3, characterized in that: The third metal layer also includes a second electrode connection line extension portion, which is located at an end of the second electrode connection line away from the common electrode line, the orthographic projection of the second electrode connection line extension portion on the substrate is located within the orthographic projection range of the common electrode on the substrate, and the width of the second electrode connection line extension portion in the first direction is greater than the width of the second electrode connection line in the first direction.

5. The display panel according to claim 1, characterized in that: The material of the first electrode connecting line is the same as that of the common electrode, and the material of the second electrode connecting line is the same as that of the common electrode line.

6. The display panel according to claim 5, characterized in that: The material of the common electrode is metal oxide, and the material of the common electrode line is metal.

7. The display panel according to any one of claims 1 to 6, characterized in that: The display panel further includes: A plurality of spacer columns are arranged between the array substrate and the color filter substrate, and the orthographic projections of the spacer columns on the substrate are located between the orthographic projections of two adjacent common electrodes on the substrate; The orthographic projection of the first electrode connecting line on the substrate and the orthographic projection of the second electrode connecting line on the substrate are both located between the orthographic projections of adjacent spacer columns on the substrate.

8. The display panel according to any one of claims 1 to 6, characterized in that: The array substrate further includes: A gate insulating layer, disposed between the first metal layer and the active layer; a passivation layer, disposed between the second metal layer and the common electrode layer; a planar layer, disposed on a side of the third metal layer away from the common electrode layer; and A pixel electrode layer, arranged on a side of the planar layer away from the third metal layer; The pixel electrode layer is connected to the second metal layer through a first via hole penetrating the planar layer and the passivation layer.

9. A method for manufacturing a display panel, characterized in that: include: providing a substrate; forming a first metal layer on the substrate, wherein the first metal layer includes a gate; forming an active layer on the first metal layer; forming a second metal layer on the active layer, wherein the second metal layer includes a source electrode and a drain electrode; forming a common electrode layer on the second metal layer, wherein the common electrode layer includes at least two common electrodes and at least one first electrode connecting line, wherein the first electrode connecting line connects two adjacent common electrodes; A third metal layer is formed on the common electrode layer, the third metal layer includes at least two common electrode lines and at least one second electrode connecting line, the second electrode connecting line is connected to the common electrode line, the second electrode connecting line is located on a side of the first electrode connecting line away from the second metal layer, and is in contact with the first electrode connecting line.

10. The method for manufacturing a display panel according to claim 9, characterized in that: The common electrode layer and the third metal layer are formed by a half-tone mask process.

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