Array substrate, display panel and display device

Abstract

Provided is an array substrate, comprising: a substrate; a plurality of scan lines and a plurality of data lines; and a plurality of sub-pixels, each of the sub-pixels comprising a first active layer, a second active layer and a pixel electrode; wherein each of the sub-pixels further comprises a first connecting portion, a second connecting portion and a pixel electrode connecting portion, the first connecting portion electrically connecting a data line and a first region of the first active layer, the second connecting portion electrically connecting a second region of the second active layer and the pixel electrode connecting portion, and the pixel electrode connecting portion being directly connected to the pixel electrode; and the total length of the first connecting portion is a first length, the average width of the first connecting portion in a direction perpendicular to the extension direction of the first connecting portion is a first width, the total length of the second connecting portion is a second length, and the average width of the second connecting portion in a direction perpendicular to the extension direction of the second connecting portion is a second width; the deviation ratio of the first length to the second length is less than or equal to 10%, and the deviation ratio of the first width to the second width is less than or equal to 10%.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to an array substrate, a display panel and a display device. BACKGROUND

[0002] Electronic Paper Display (EPD) is a display technology that simulates traditional printed paper, with high contrast, low power consumption and clear display even under direct sunlight. EPD technology is based on the electrophoresis phenomenon, that is, charged particles move under the action of electric field. In EPD, tiny white and black particles are suspended in a liquid, and when an electric field is applied, these particles will move according to the direction of the electric field, thereby forming an image on the display screen. EPD display technology has been widely used in e-book readers, smart labels and other fields due to its unique display characteristics and low power consumption advantages. With the continuous progress of technology, EPD is expected to play an important role in more fields. In EPD display products, how to ensure better display effect is one of the issues that display product researchers are concerned about.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure, and therefore, the above information can contain information that does not constitute prior art. SUMMARY

[0004] In one aspect, an array substrate is provided, the array substrate comprising:

[0005] a substrate substrate;

[0006] a plurality of scan lines on the substrate substrate, the plurality of scan lines extending along a first direction and arranged along a second direction;

[0007] a plurality of data lines on the substrate substrate, the plurality of data lines extending along the second direction and arranged along the first direction; and

[0008] a plurality of sub-pixels on the substrate substrate, the plurality of sub-pixels arrayed along the first direction and the second direction, the sub-pixel comprising a first active layer, a second active layer and a pixel electrode, a first region of the first active layer and a data line being electrically connected, a second region of the first active layer and a first region of the second active layer being electrically connected, a second region of the second active layer and the pixel electrode being electrically connected;

[0009] The sub-pixel further comprises a first connecting portion, a second connecting portion and a pixel electrode connecting portion, the first connecting portion electrically connects the data line and the first region of the first active layer, the second connecting portion electrically connects the second region of the second active layer and the pixel electrode connecting portion, and the pixel electrode connecting portion is directly connected with the pixel electrode.

[0010] The total length of the first connecting portion is a first length, the average width of the first connecting portion in a direction perpendicular to the extension direction of the first connecting portion is a first width, the total length of the second connecting portion is a second length, and the average width of the second connecting portion in a direction perpendicular to the extension direction of the second connecting portion is a second width, the deviation ratio of the first length to the second length is less than or equal to 10%, and the deviation ratio of the first width to the second width is less than or equal to 10%.

[0011] According to some exemplary embodiments, the first active layer and the second active layer are symmetrically arranged relative to a first virtual straight line axis, and a first portion of the first connecting portion is symmetrically arranged relative to the first virtual straight line axis with at least a second portion of the first connecting portion.

[0012] According to some exemplary embodiments, the first portion of the first connecting portion and the second connecting portion are symmetrically arranged relative to the first virtual straight line axis, or

[0013] the second portion of the first connecting portion and the second connecting portion are symmetrically arranged relative to the first virtual straight line axis, or

[0014] the first connecting portion and the second connecting portion are symmetrically arranged relative to the first virtual straight line axis.

[0015] According to some exemplary embodiments, the sub-pixel further comprises a third connecting portion, the third connecting portion electrically connects the second region of the first active layer and the first region of the second active layer, and the third connecting portion is symmetrically arranged relative to the first virtual straight line axis.

[0016] According to some exemplary embodiments, the first connecting portion comprises a first sub-portion and a second sub-portion, the first sub-portion is directly connected with the first region of the first active layer, and the second sub-portion is located on one side of the first sub-portion close to the data line and is directly connected with the data line.

[0017] The second connecting portion comprises a third sub-portion and a fourth sub-portion, the third sub-portion is directly connected with the second region of the second active layer, and the fourth sub-portion is located on one side of the third sub-portion close to the pixel electrode connecting portion and is directly connected with the pixel electrode connecting portion.

[0018] The third connecting part comprises a fifth sub-part, a sixth sub-part and a seventh sub-part, the fifth sub-part and the seventh sub-part are connected at two sides of the sixth sub-part respectively, the fifth sub-part is directly connected with the second area of the first active layer, the seventh sub-part is directly connected with the first area of the second active layer, the orthographic projection of the sixth sub-part on the substrate substrate does not overlap with the orthographic projection of the first active layer and the second active layer on the substrate substrate; and

[0019] The minimum size of at least one of the second sub-part, the fourth sub-part and the sixth sub-part along the extension direction of the first virtual straight line axis is smaller than the minimum size of at least one of the first sub-part, the third sub-part, the fifth sub-part and the seventh sub-part along the extension direction of the first virtual straight line axis.

[0020] According to some exemplary embodiments, the first active layer and the second active layer are arranged spaced apart along the first direction, the size of the first active layer along the first direction is greater than the size along the second direction, and the size of the second active layer along the first direction is greater than the size along the second direction; and

[0021] The first area and the second area of the first active layer are arranged spaced apart along the second direction, the first area and the second area of the second active layer are arranged spaced apart along the second direction, the first area of the second active layer is located at one side of the second area of the first active layer along the first direction, the second area of the second active layer is located at one side of the first area of the first active layer along the first direction, and the pixel electrode connecting part is located at one side of the second area of the second active layer away from the first area of the second active layer along the second direction.

[0022] According to some exemplary embodiments, the first connecting part is in the shape of a strip extending along the first direction, and the second part of the second connecting part is symmetrically arranged with the first connecting part relative to the first virtual straight line axis; and

[0023] The second connecting part further comprises a third part, the third part is located at one side of the second part along the second direction, and the third part connects the second part and the pixel electrode connecting part.

[0024] According to some exemplary embodiments, the second connecting part is in the shape of an L rotated 90° counterclockwise, and the first part of the first connecting part is symmetrically arranged with the second connecting part relative to the first virtual straight line axis; and

[0025] The first connecting part further comprises a fourth part, the fourth part is connected at one side of the first part away from the second connecting part along the first direction, and the fourth part electrically connects the first part and the data line.

[0026] According to some exemplary embodiments, the sub-pixel further comprises a gate electrode electrically connected with the scan line, a projection of the gate electrode on the substrate and a projection of the first active layer on the substrate at least partially overlap, a projection of the gate electrode on the substrate and a projection of the second active layer on the substrate at least partially overlap.

[0027] The gate electrode has at least one notch, the notch is partially recessed into the gate electrode along the second direction, a projection of the notch on the substrate is located between a projection of the first active layer on the substrate and a projection of the second active layer on the substrate.

[0028] According to some exemplary embodiments, the sub-pixel further comprises a gate electrode electrically connected with the scan line, a projection of the gate electrode on the substrate and a projection of the first active layer on the substrate at least partially overlap, a projection of the gate electrode on the substrate and a projection of the second active layer on the substrate at least partially overlap; and

[0029] The gate electrode comprises a first edge and a second edge located on two sides of the second direction, the first edge continuously extends along the first direction, and the second edge continuously extends along the first direction.

[0030] According to some exemplary embodiments, the third connection part comprises a fifth sub-part, a sixth sub-part and a seventh sub-part, the fifth sub-part and the seventh sub-part are connected on two sides of the sixth sub-part along the first direction respectively, the fifth sub-part is directly connected with the second region of the first active layer, the seventh sub-part is directly connected with the first region of the second active layer, and a projection of the sixth sub-part on the substrate does not overlap with projections of the first active layer and the second active layer on the substrate;

[0031] The fifth sub-part and the seventh sub-part are both in the shape of a strip extending along the first direction, a minimum dimension of the sixth sub-part along the second direction is smaller than a minimum dimension of the fifth sub-part along the second direction, and a minimum dimension of the sixth sub-part along the second direction is smaller than a minimum dimension of the seventh sub-part along the second direction.

[0032] According to some exemplary embodiments, the first active layer and the second active layer are arranged at intervals along the first direction, a dimension of the first active layer along the first direction is smaller than a dimension along the second direction, and a dimension of the second active layer along the first direction is smaller than a dimension along the second direction; and

[0033] The first region and the second region of the first active layer are spaced apart along the first direction, the first region and the second region of the second active layer are spaced apart along the first direction, the first region of the second active layer is located on a side of the second region of the first active layer away from the first region of the first active layer, and the pixel electrode connecting portion is located on a side of the second region of the second active layer away from the first region of the second active layer along the first direction.

[0034] According to some exemplary embodiments, the first sub-portion is in a long strip shape extending along the second direction, the second sub-portion is connected to the first sub-portion along the first direction and away from a side of the second active layer, and a minimum dimension of the second sub-portion along the second direction is smaller than a minimum dimension of the first sub-portion along the second direction; and / or,

[0035] The third sub-portion is in a long strip shape extending along the second direction, the fourth sub-portion is connected to the second sub-portion along the first direction and away from a side of the first active layer, and a minimum dimension of the fourth sub-portion along the second direction is smaller than a minimum dimension of the third sub-portion along the second direction; and / or,

[0036] The fifth sub-portion and the seventh sub-portion are each in a long strip shape extending along the second direction, a minimum dimension of the sixth sub-portion along the second direction is smaller than a minimum dimension of the fifth sub-portion along the second direction, and a minimum dimension of the sixth sub-portion along the second direction is smaller than a minimum dimension of the seventh sub-portion along the second direction.

[0037] According to some exemplary embodiments, the first active layer and the second active layer are each axisymmetric with respect to a second virtual straight line axis, the second virtual straight line axis passes through at least one of the second sub-portion, the fourth sub-portion, and the sixth sub-portion.

[0038] According to some exemplary embodiments, the first sub-portion and the third sub-portion are symmetrically arranged with respect to the first virtual straight line axis, and at least a portion of the second sub-portion and at least a portion of the fourth sub-portion are symmetrically arranged with respect to the first virtual straight line axis.

[0039] In another aspect, an array substrate is provided, the array substrate comprising:

[0040] a substrate substrate;

[0041] a plurality of scan lines on the substrate substrate, the plurality of scan lines extending along a first direction and arranged along a second direction;

[0042] a plurality of data lines on the substrate substrate, the plurality of data lines extending along the second direction and arranged along the first direction; and

[0043] a plurality of sub-pixels arranged in an array along the first direction and the second direction on the substrate, the sub-pixel comprising a first active layer, a second active layer and a pixel electrode, a first region of the first active layer being electrically connected to the data line, a second region of the first active layer being electrically connected to a first region of the second active layer, a second region of the second active layer being electrically connected to the pixel electrode;

[0044] wherein the sub-pixel further comprises a first connecting portion, a second connecting portion and a pixel electrode connecting portion, the first connecting portion electrically connecting the data line and the first region of the first active layer, the second connecting portion electrically connecting the second region of the second active layer and the pixel electrode connecting portion, the pixel electrode connecting portion being directly connected to the pixel electrode;

[0045] the first connecting portion comprises a first sub-portion and a second sub-portion, the first sub-portion being directly connected to the first region of the first active layer, the second sub-portion being located on a side of the first sub-portion close to the data line and being directly connected to the data line;

[0046] the second connecting portion comprises a third sub-portion and a fourth sub-portion, the third sub-portion being directly connected to the second region of the second active layer, the fourth sub-portion being located on a side of the third sub-portion close to the pixel electrode connecting portion and being directly connected to the pixel electrode connecting portion;

[0047] the third connecting portion comprises a fifth sub-portion, a sixth sub-portion and a seventh sub-portion, the fifth sub-portion and the seventh sub-portion being connected to two sides of the sixth sub-portion respectively, the fifth sub-portion being directly connected to the second region of the first active layer, the seventh sub-portion being directly connected to the first region of the second active layer, a projection of the sixth sub-portion on the substrate not overlapping with projections of the first active layer and the second active layer on the substrate; and

[0048] at least one of the second sub-portion, the fourth sub-portion and the sixth sub-portion has a minimum dimension along an extension direction of the first virtual straight line smaller than a minimum dimension of at least one of the first sub-portion, the third sub-portion, the fifth sub-portion and the seventh sub-portion along the extension direction of the first virtual straight line.

[0049] In another aspect, there is provided a display panel comprising the array substrate as in any one of the above.

[0050] In another aspect, there is provided a display device comprising the display panel as described above. BRIEF DESCRIPTION OF DRAWINGS

[0051] Other objects and advantages of the present disclosure will become apparent and help to understand the present disclosure from the following description of the present disclosure made with reference to the accompanying drawings.

[0052] Figure 1 A plan view of an array substrate of a related art is schematically shown.

[0053] Figure 2 A plan view of another array substrate of a related art is schematically shown.

[0054] Figure 3A A plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0055] Figure 3B A plan view of a source / drain metal layer of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0056] Figure 4 A plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0057] Figure 5 A plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0058] Figure 6 A cross-sectional view of an array substrate according to some embodiments of the present disclosure is schematically shown, wherein, Figure 6 A cross-sectional view taken along line AA' in Figure 3A is schematically shown.

[0059] Figure 7 A cross-sectional view of an array substrate according to some embodiments of the present disclosure is schematically shown, wherein, Figure 7 A cross-sectional view taken along line BB' in Figure 5 is schematically shown.

[0060] Figure 8A A plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0061] Figure 8B A plan view of a source / drain metal layer of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0062] Figure 9 A plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0063] Figure 10 A plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0064] Figure 11A A plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0065] Figure 11B A plan view of a source-drain metal layer of an array substrate according to some embodiments of the present disclosure is schematically illustrated.

[0066] Figure 12A A plan view of an array substrate according to some embodiments of the present disclosure is schematically illustrated.

[0067] Figure 12B A plan view of a source-drain metal layer of an array substrate according to some embodiments of the present disclosure is schematically illustrated.

[0068] Figure 13A A plan view of an array substrate according to some embodiments of the present disclosure is schematically illustrated.

[0069] Figure 13B A plan view of a source-drain metal layer of an array substrate according to some embodiments of the present disclosure is schematically illustrated.

[0070] Figure 14 A plan view of an array substrate according to some embodiments of the present disclosure is schematically illustrated, wherein Figure 14 A cross-sectional view taken along a center line CC’ is schematically illustrated. Figure 11A

[0071] It should be noted that, for the sake of clarity, the size of layers, structures or regions in the drawings can be exaggerated or reduced, i.e. the drawings are not necessarily drawn to scale relative to each other. DETAILED DESCRIPTION

[0072] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments. It is apparent, however, that various exemplary embodiments can be practiced without

[0073] In the drawings, the size and relative sizes of elements and regions can be exaggerated for clarity and / or descriptive purposes. As such, the dimensions and relative sizes of various elements and regions shown in the figures can not be drawn to scale. When an element or layer is referred to as being "on" another element or substrate, it can be directly on the other element or substrate or intervening layers can also be present. For example, an element or layer can be "on" another element or substrate without being in contact with the other element or substrate. In the figures, like reference numerals refer to like elements throughout. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. ​

[0074] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on, directly connected to, or directly coupled to another element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to," or "directly coupled to," another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, the Y-axis, and the Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0075] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element without departing from the scope of the exemplary embodiments.

[0076] Figure 1 The figure schematically shows a plan view of an array substrate in the related art. Figure 2 A schematic plan view of another array substrate in the related art is shown.

[0077] Reference Figure 1 or Figure 2 The array substrate includes two transistors connected in series. Compared with a substrate including only one transistor, the dual-transistor structure has a lower off-state leakage current and is particularly suitable for bistable drive products, such as electronic shelf labels (ESL) products.

[0078] In this array substrate with dual series transistors, the two transistors have an asymmetric structure, for example Figure 1 and Figure 2The asymmetric structure causes resistance difference, which leads to difference in hysteresis characteristics of the two transistors, and further leads to display power consumption increase, white spot defect, crosstalk, and image sticking, etc.

[0079] Figure 3A A plan view of an array substrate according to some embodiments of the present disclosure is schematically shown. Figure 3B A plan view of a source-drain metal layer of an array substrate according to some embodiments of the present disclosure is schematically shown. Figure 4 A plan view of an array substrate according to some embodiments of the present disclosure is schematically shown. Figure 5 A plan view of an array substrate according to some embodiments of the present disclosure is schematically shown. Figure 6 A cross-sectional view of an array substrate according to some embodiments of the present disclosure is schematically shown, wherein, Figure 6 A cross-sectional view of an array substrate according to some embodiments of the present disclosure is schematically shown, wherein, Figure 3A A cross-sectional view taken along line AA' in FIG. Figure 7 A cross-sectional view of an array substrate according to some embodiments of the present disclosure is schematically shown, wherein, Figure 7 A cross-sectional view taken along line BB' in FIG. Figure 5 A cross-sectional view taken along line BB' in FIG.

[0080] With reference to Figure 3A and Figure 3B , the display substrate includes a plurality of scan lines SL, a plurality of data lines DL, and a plurality of sub-pixels SP. The plurality of scan lines SL extends along a first direction X and is arranged along a second direction Y, and the plurality of data lines DL extends along the second direction Y and is arranged along the first direction X. The plurality of sub-pixels SP is arranged in an array along the first direction X and the second direction Y, and each sub-pixel SP includes a first active layer 310, a second active layer 320, and a pixel electrode 510. The first active layer 310 includes a channel region 311 and first and second regions 312 and 313 located on both sides of the channel region 311, and the second active layer 320 includes a channel region 321 and first and second regions 322 and 323 located on both sides of the channel region 321. The first region 312 of the first active layer 310 is electrically connected to one of the data lines DL, the second region 313 of the first active layer 310 is electrically connected to the first region 322 of the second active layer 320, and the second region 323 of the second active layer 320 is electrically connected to the pixel electrode 510.

[0081] The sub-pixel SP further includes a first connecting part 410, a second connecting part 420, a third connecting part 430, a gate 210 and a pixel electrode connecting part 440. The first connecting part 410 electrically connects the data line DL and the first region 312 of the first active layer 310, the second connecting part 420 electrically connects the second region 323 of the second active layer 320 and the pixel electrode connecting part 440, the pixel electrode connecting part 440 is directly connected with the pixel electrode 510, and the third connecting part 430 electrically connects the second region 313 of the first active layer 310 and the first region 322 of the second active layer 320. The gate 210 is electrically connected with one scan line SL, the orthographic projection of the gate 210 on the substrate overlaps the orthographic projection of the channel region 311 of the first active layer 310 on the substrate, and the orthographic projection of the gate 210 on the substrate overlaps the orthographic projection of the channel region 321 of the second active layer 320 on the substrate. A part of the scan line SL can be thickened as the gate 210 of the first active layer 310 and the second active layer 320.

[0082] The first active layer 310, the first connecting part 410, a part of the third connecting part 430 and a part of the gate 210 constitute the first transistor T1, the second active layer 320, another part of the third connecting part 430, the second connecting part 420 and another part of the gate 210 constitute the second transistor T2, and the third connecting part 430 realizes the series connection of the first transistor T1 and the second transistor T2.

[0083] Continuing to refer to Figure 3A and Figure 3B , the total length of the extension of the first connecting part 410 is a first length, the average width of the first connecting part 410 in the direction perpendicular to the extension direction thereof is a first width, the total length of the extension of the second connecting part 420 is a second length, the average width of the second connecting part 420 in the direction perpendicular to the extension direction thereof is a second width, the deviation ratio of the first length to the second length is less than or equal to 10%, and the deviation ratio of the first width to the second width is less than or equal to 10%. By setting the difference between the total length of the extension and the average width of the first connecting part 410 and the second connecting part 420 to be relatively small, the difference between the resistance of the first connecting part 410 and the resistance of the second connecting part 420 can be made relatively small, so that the display defect caused by the difference in the hysteresis characteristics of the first transistor T1 and the second transistor T2 can be effectively avoided.

[0084] It should be noted that the shape of the connecting part is a straight line type or a broken line type, and the total length of the extension of the connecting part should be understood as the distance from one end to the other end along the edge contour thereof. For example, referring to Figure 3B , the total length of the extension of the first connecting part 410 is L1, and the total length of the extension of the second connecting part 420 is the sum of L2 and L3, wherein 90%*(L2+L3)≤L1≤110%*(L2+L3).

[0085] The connecting portion can be of equal-width design or non-equal-width design. When the connecting portion is of equal-width design, the average width of the connecting portion is the width at any position. When the connecting portion is of non-equal-width design, the average width of the connecting portion can be calculated according to the actual shape of the connecting portion (for example, it can be calculated by the ratio of the total area to the total extension length of the connecting portion).

[0086] For example, referring to Figure 3B , the first connecting portion 410 and the second connecting portion 420 are both of equal-width design. The average width of the first connecting portion 410 is W1, and the average width of the second connecting portion 420 is W2, where 90%*W2≤W1≤110%*W2.

[0087] According to some exemplary embodiments, in combination with referring to Figure 3A and Figure 6 , the array substrate can include a substrate 100, a gate metal layer 200 located on the substrate 100, a gate insulating layer GI located on the side of the gate metal layer 200 away from the substrate 100, a semiconductor layer 300 located on the side of the gate insulating layer GI away from the substrate 100, a source-drain metal layer 400 located on the side of the semiconductor layer 300 away from the substrate 100, a passivation layer PVX located on the side of the source-drain metal layer 400 away from the substrate 100, and a pixel electrode layer 500 located on the side of the passivation layer PVX away from the substrate 100.

[0088] The gate electrode 210 and the scan line SL are located on the gate metal layer 200, the first active layer 310 and the second active layer 320 are located on the semiconductor layer 300, the data line DL, the first connecting portion 410, the second connecting portion 420, the third connecting portion 430, and the pixel electrode connecting portion 440 are located on the source-drain metal layer 400, and the pixel electrode 510 is located on the pixel electrode layer 500. The passivation layer PVX includes a first via V01, and the pixel electrode 510 is electrically connected through the first via V01 and the pixel electrode connecting portion 440.

[0089] It should be noted that the first connecting portion 410 and the data line DL are connected into an integrated structure, and the first connecting portion 410 and the data line DL have no obvious boundary line. The linear structure extending along the second direction Y is the data line DL, and the structure protruding towards the first direction X compared to the data line DL is the first connecting portion 410.

[0090] The second connecting portion 420 and the pixel electrode connecting portion 440 are connected into an integrated structure, and there is no obvious boundary between the second connecting portion 420 and the pixel electrode connecting portion 440. The shape of the pixel electrode connecting portion 440 is, for example, a square. The width of the connected end of the second connecting portion 420 to the pixel electrode 510 can be obviously smaller than the size of the pixel electrode connecting portion 440. The position where the edge shape and size change suddenly should be considered as the boundary between the pixel electrode connecting portion 440 and the second connecting portion 420.

[0091] When the width of the connected end of the second connecting portion 420 to the pixel electrode 510 is substantially equal to the size of the pixel electrode connecting portion 440, the edge of the pixel electrode connecting portion 440 can be determined in combination with the position of the first via V01. For reference, Figure 3A , the orthographic projection of the first via V01 on the substrate substrate is located at the center of the pixel electrode connecting portion 440 on the substrate substrate.

[0092] It should be noted that the source-drain metal layer 400 and the semiconductor layer 300 can be formed in the same patterning process using a halftone mask. Therefore, there is a semiconductor layer 300 under the source-drain metal layer 400. The part of the semiconductor layer 300 that is more than the source-drain metal layer 400 is the channel region of the active layer.

[0093] According to some exemplary embodiments, in combination with reference to Figure 3A and Figure 6 , the sub-pixel SP further includes a storage capacitor Cst, the storage capacitor Cst includes a first capacitor plate 220 and a second capacitor plate 450. The first capacitor plate 220 can be located in the gate metal layer 200, and the second capacitor plate 450 can be located in the source-drain metal layer 400. The passivation layer PVX and the gate insulation layer GI include a second via V02. The pixel electrode 510 is electrically connected to the first capacitor plate 220 through the second via V02. The pixel electrode 510 inputs a pixel voltage signal into the first capacitor plate 220. A plurality of second capacitor plates 450 arranged at intervals along the second direction Y are connected into a column through a plurality of capacitor connecting portions 460 and input a voltage signal different from the pixel voltage signal in the peripheral region.

[0094] According to some exemplary embodiments, in combination with reference to Figure 3A and Figure 3BThe first active layer 310 and the second active layer 320 are symmetrically arranged relative to the first virtual straight line axis A1, the first part of the first connecting portion 410 and the second part of the first connecting portion 410 are symmetrically arranged relative to the first virtual straight line axis A1, and by arranging at least a part of the first connecting portion 410 and at least a part of the second connecting portion 420 symmetrically relative to the first virtual straight line axis A1, the difference between the extension length and the average width of the first connecting portion 410 and the second connecting portion 420 can be reduced, and the difference between the resistance of the first connecting portion 410 and the second connecting portion 420 is small.

[0095] According to some exemplary embodiments, in combination with reference to Figure 3A and Figure 3B The third connecting portion 430 is symmetrically arranged relative to the first virtual straight line axis A1, that is, a part of the third connecting portion 430 connected with the second region 313 of the first active layer 310 and another part of the third connecting portion 430 connected with the first region 322 of the second active layer 320 are symmetrically arranged relative to the first virtual straight line axis A1, which is beneficial to further avoid display defects caused by the difference in hysteresis characteristics of the first transistor T1 and the second transistor T2.

[0096] According to some exemplary embodiments, in combination with reference to Figure 3A The first active layer 310 and the second active layer 320 are arranged in a first direction X, and the first virtual straight line axis A1 extends in a second direction Y. The size of the first active layer 310 in the first direction X is greater than the size in the second direction Y, and the first region 312 and the second region 313 of the first active layer 310 are arranged in the second direction Y; the size of the second active layer 320 in the first direction X is greater than the size in the second direction Y, and the first region 322 and the second region 323 of the second active layer 320 are arranged in the second direction Y.

[0097] The first region 322 of the second active layer 320 is located on one side of the second region 313 of the first active layer 310 in the first direction X, the second region 323 of the second active layer 320 is located on one side of the first region 312 of the first active layer 310 in the first direction X, and the pixel electrode connecting portion 440 is located on one side of the second region 323 of the second active layer 320 away from the first region 322 of the second active layer 320 in the second direction Y.

[0098] According to some exemplary embodiments, in combination with reference to Figure 3A and Figure 3BThe first connecting portion 410 is in a strip shape extending along the first direction X, one end of the first connecting portion 410 extends along the first direction X to connect with the data line DL, and the other end of the first connecting portion 410 extends along the first direction X to connect with the first area 312 of the first active layer 310. The second portion 420A of the second connecting portion 420 is symmetrically arranged with the first connecting portion 410 relative to the first virtual straight line axis A1, and the second connecting portion 420 further includes a third portion 420B, the third portion 420B is located on one side of the second portion 420A along the second direction Y, and the third portion 420B connects the second portion 420A and the pixel electrode connecting portion 440.

[0099] According to some exemplary embodiments, with reference to Figure 3B The extending width of the third portion 420B is equal to the extending width of the second portion 420A, the shape of the orthographic projection of the third portion 420B on the substrate plate is a rectangle, the edge of the third portion 420B away from the first connecting portion 410 along the first direction X is flush with the edge of the second portion 420A away from the first connecting portion 410 along the first direction X, and the shape of the orthographic projection of the second connecting portion 420 on the substrate plate is an L shape rotated 90° counterclockwise.

[0100] Figure 8A A plan view of an array substrate according to some embodiments of the present disclosure is schematically shown. Figure 8B A plan view of a source-drain metal layer of an array substrate according to some embodiments of the present disclosure is schematically shown. Figure 9 A plan view of an array substrate according to some embodiments of the present disclosure is schematically shown. Figure 10 A plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0101] According to some exemplary embodiments, with reference to Figure 8A and Figure 8B The second connecting portion 420 is in an L shape rotated 90° counterclockwise, and the first portion 410A of the first connecting portion 410 is symmetrically arranged with the second connecting portion 420 relative to the first virtual straight line axis A1. The first connecting portion 410 further includes a fourth portion 410B, the fourth portion 410B is connected on one side of the first portion 410A away from the second connecting portion 420 along the first direction X, and the fourth portion 410B electrically connects the first portion 410A and the data line DL.

[0102] According to some exemplary embodiments, with reference to Figure 8A The first connecting portion 410 is designed to be equal in width at each place, and the second connecting portion 420 is designed to be equal in width at each place.

[0103] According to some exemplary embodiments, with reference to Figure 8BThe edge of the fourth portion 410B away from the third connecting portion 430 along the second direction Y is flush with the edge of the first portion 410A away from the third connecting portion 430 along the second direction Y, and a projection of the first connecting portion 410 on the substrate is substantially Z-shaped.

[0104] According to some exemplary embodiments, referring to Figure 4 and Figure 9 , the gate 210 has at least one notch 211, the notch 211 is partially recessed into the gate 210 along the second direction Y, and a projection of the notch 211 on the substrate is between a projection of the first active layer 310 on the substrate and a projection of the second active layer 320 on the substrate. By providing the notch 211 in the portion of the gate 210 between the first active layer 310 and the second active layer 320, and by providing the notch 211 at a position where the dimension of the gate 210 along the second direction Y is narrowed, the leakage current of the transistor is reduced.

[0105] It should be noted that in the structure shown in Figure 4 and Figure 9 , the notch 211 is provided only on one side of the gate 210 along the second direction Y, and the notch 211 can also be provided on both sides of the gate 210 along the second direction Y according to actual process requirements.

[0106] According to some exemplary embodiments, referring to Figure 5 and Figure 10 , the gate 210 includes a first edge 212 and a second edge 213 on both sides of the second direction Y, the first edge 212 continuously extends along the first direction X, and the second edge 213 continuously extends along the first direction X. That is, compared with the structure of Figure 4 and Figure 9 , the gate 210 is not provided with the notch 211, so that the resistance of the gate 210 can be reduced.

[0107] In combination with referring to Figure 6 and Figure 7 , Figure 6 the cross-sectional view shown is a cross-sectional view of the gate 210 provided with the notch 211, Figure 7 and the cross-sectional view shown is a cross-sectional view of the gate 210 provided with or without the notch 211.

[0108] According to some exemplary embodiments, referring to Figure 4 and Figure 9The third connecting portion 430 includes a fifth sub-portion 431, a sixth sub-portion 432, and a seventh sub-portion 433. The fifth sub-portion 431 and the seventh sub-portion 433 are respectively connected to two sides of the sixth sub-portion 432 along the first direction X. The fifth sub-portion 431 is directly connected to the second region 313 of the first active layer 310. The seventh sub-portion 433 is directly connected to the first region 322 of the second active layer 320. The sixth sub-portion 432 has a projection on the substrate which does not overlap with the projections of the first active layer 310 and the second active layer 320 on the substrate. The fifth sub-portion 431 and the seventh sub-portion 433 are both in the shape of a strip extending along the first direction X. The minimum dimension of the sixth sub-portion 432 along the second direction Y is smaller than the minimum dimension of the fifth sub-portion 431 along the second direction Y. The minimum dimension of the sixth sub-portion 432 along the second direction Y is smaller than the minimum dimension of the seventh sub-portion 433 along the second direction Y. By narrowing the dimension of the fifth sub-portion 431 along the second direction Y in the third connecting portion 430 between the first active layer 310 and the second active layer 320, the leakage current of the transistor can be effectively reduced.

[0109] For example, the fifth sub-portion 431 and the seventh sub-portion 433 are both in the shape of an equal-width strip. The width of the fifth sub-portion 431 is equal to the width of the seventh sub-portion 433. The sixth sub-portion 432 is in the shape of a rectangle. The width W3 of the sixth sub-portion 432 is smaller than the width W4 of the fifth sub-portion 431. The width W3 of the sixth sub-portion 432 is smaller than the width W5 of the seventh sub-portion 433. The width W4 of the fifth sub-portion 431 is equal to the width W5 of the seventh sub-portion 433.

[0110] Figure 11A A plan view of an array substrate according to some embodiments of the present disclosure is schematically shown. Figure 11B A plan view of a source-drain metal layer of an array substrate according to some embodiments of the present disclosure is schematically shown. Figure 12A A plan view of an array substrate according to some embodiments of the present disclosure is schematically shown. Figure 12B A plan view of a source-drain metal layer of an array substrate according to some embodiments of the present disclosure is schematically shown. Figure 13A A plan view of an array substrate according to some embodiments of the present disclosure is schematically shown. Figure 13B A plan view of a source-drain metal layer of an array substrate according to some embodiments of the present disclosure is schematically shown. Figure 14 A plan view of an array substrate according to some embodiments of the present disclosure is schematically shown, wherein Figure 14 A cross-sectional view taken along a center line CC’ is schematically shown. Figure 11A A cross-sectional view taken along a center line CC’ is schematically shown.

[0111] According to some exemplary embodiments, reference is made to Figure 11AThe first active layer 310 and the second active layer 320 are arranged at intervals along the second direction Y, the first active layer 310 has a size along the first direction X smaller than a size along the second direction Y, and the first region 312 and the second region 313 of the first active layer 310 are arranged at intervals along the first direction X; the second active layer 320 has a size along the first direction X smaller than a size along the second direction Y, and the first region 322 and the second region 323 of the second active layer 320 are arranged at intervals along the first direction X. The first region 322 of the second active layer 320 is located on a side of the second region 313 of the first active layer 310 away from the first region 312 of the first active layer 310, and the pixel electrode connecting part 440 is located on a side of the second region 323 of the second active layer 320 away from the first region 322 of the second active layer 320 along the first direction X, i.e., the first region 312 of the first active layer 310, the second region 313 of the first active layer 310, the first region 322 of the second active layer 320, and the second region 323 of the second active layer 320 are arranged at intervals along the first direction X in sequence.

[0112] According to some exemplary embodiments, in combination with reference to Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A and Figure 13B , the first connecting part 410 includes a first sub-part 411 and a second sub-part 412, the first sub-part 411 is directly connected with the first region 312 of the first active layer 310, and the second sub-part 412 is located on a side of the first sub-part 411 close to the data line DL and is directly connected with the data line DL. The second connecting part 420 includes a third sub-part 421 and a fourth sub-part 422, the third sub-part 421 is directly connected with the second region 323 of the second active layer 320, and the fourth sub-part 422 is located on a side of the third sub-part 421 close to the pixel electrode connecting part 440 and is directly connected with the pixel electrode connecting part 440. The third connecting part 430 includes a fifth sub-part 431, a sixth sub-part 432, and a seventh sub-part 433, the fifth sub-part 431 and the seventh sub-part 433 are respectively connected on two sides of the sixth sub-part 432, the fifth sub-part 431 is directly connected with the second region 313 of the first active layer 310, the seventh sub-part 433 is directly connected with the first region 322 of the second active layer 320, and the sixth sub-part 432 has a non-overlapping projection on the substrate with the first active layer 310 and the second active layer 320.

[0113] At least one of the second sub-portion 412, the fourth sub-portion 422, and the sixth sub-portion 432 has a minimum dimension along the extension direction of the first virtual straight line axis A1 that is smaller than that of at least one of the first sub-portion 411, the third sub-portion 421, the fifth sub-portion 431, and the seventh sub-portion 433. That is, by narrowing the dimension of at least one of the second sub-portion 412 (one end of the first connecting portion 410 connected with the data line DL), the fourth sub-portion 422 (one end of the second connecting portion 420 and the pixel electrode connecting portion 440), and the sixth sub-portion 432 (the portion of the third connecting portion 430 located between the first active layer 310 and the second active layer 320) along the extension direction of the first virtual straight line axis A1, the leakage current of the transistor can be effectively reduced, as will be specifically described below in conjunction with the accompanying drawings. The dimension of at least one of the second sub-portion 412, the fourth sub-portion 422, and the sixth sub-portion 432 along the extension direction of the first virtual straight line axis A1 can be set to be smaller according to the process capability, for example, the dimension is 3-5 μm.

[0114] According to some exemplary embodiments, in conjunction with the description of Figure 12A and Figure 12B , the first sub-portion 411 has an elongated strip shape extending along the second direction Y, the second sub-portion 412 has a shape of a rectangle in orthographic projection on the substrate, the second sub-portion 412 is connected with the first sub-portion 411 along the first direction X and away from one side of the second connecting portion 420, and the second sub-portion 412 is connected with the data line DL, and the dimension W6 of the second sub-portion 412 along the second direction Y is smaller than the dimension W7 of the first sub-portion 411 along the second direction Y.

[0115] According to some exemplary embodiments, in conjunction with the description of Figure 13A and Figure 13B , the third sub-portion 421 has an elongated strip shape extending along the second direction Y, the fourth sub-portion 422 has a shape of a rectangle in orthographic projection on the substrate, the fourth sub-portion 422 is connected with the third sub-portion 421 along the first direction X and away from one side of the first active layer 310, and the dimension W8 of the fourth sub-portion 422 along the second direction Y is smaller than the dimension W9 of the third sub-portion 421 along the second direction Y.

[0116] According to some exemplary embodiments, in conjunction with the description of Figure 11A Figure 11BThe fifth sub-section 431 and the seventh sub-section 433 each have an elongated shape extending in the second direction Y, the shape of the orthographic projection of the sixth sub-section 432 on the substrate includes a rectangle, the dimension W10 of the sixth sub-section 432 in the second direction Y is less than the dimension W11 of the fifth sub-section 431 in the second direction Y, the dimension W10 of the sixth sub-section 432 in the second direction Y is less than the dimension W12 of the seventh sub-section 433 in the second direction Y, the dimension W11 of the fifth sub-section 431 in the second direction Y is equal to the dimension W12 of the seventh sub-section 433 in the second direction Y, and the orthographic projection of the third connecting section 430 on the substrate has an H shape.

[0117] According to some exemplary embodiments, with reference to Figure 13A and Figure 13B the total length of the extension of the first connecting section 410 is a first length, the average width of the first connecting section 410 in a direction perpendicular to the direction of the extension thereof is a first width, the total length of the extension of the second connecting section 420 is a second length, the average width of the second connecting section 420 in a direction perpendicular to the direction of the extension thereof is a second width, the deviation ratio of the first length to the second length is less than or equal to 10%, and the deviation ratio of the first width to the second width is less than or equal to 10%.

[0118] It is to be noted that when the connecting section is not an elongated strip structure continuously extending, the connecting section should include a plurality of sub-sections respectively independently extending connected to each other, and the total length of the extension of the connecting section should be the sum of the lengths of the respective sub-sections respectively extending. For example, the first connecting section 410 is not an elongated strip structure continuously extending, and the total length of the extension of the first connecting section 410 should be understood as the sum of the extension length L4 of the first sub-section 411 (i.e. the dimension W7 of the first sub-section 411 in the second direction Y) and the extension length L5 of the second sub-section 412. Similarly, the total length of the extension of the second connecting section 420 should be understood as the sum of the extension length L6 of the third sub-section 421 (i.e. the dimension W9 of the third sub-section 421 in the second direction Y) and the extension length L7 of the fourth sub-section 422.

[0119] According to some exemplary embodiments, with reference to Figure 13A and Figure 13B at least a portion of the first connecting section 410 and at least a portion of the second connecting section 420 are symmetrically arranged with respect to the first virtual straight line axis A1, for example, the first sub-section 411 and the third sub-section 421 are symmetrically arranged with respect to the first virtual straight line axis A1, and at least a portion of the second sub-section 412 and at least a portion of the fourth sub-section 422 are symmetrically arranged with respect to the first virtual straight line axis A1.

[0120] According to some exemplary embodiments, with reference to Figure 13A and Figure 13B, the first connecting portion 410 and the second connecting portion 420 are symmetrically arranged relative to the first virtual straight line axis A1, the first sub-portion 411 and the third sub-portion 421 are symmetrically arranged relative to the first virtual straight line axis A1, and the second sub-portion 412 and the fourth sub-portion 422 are symmetrically arranged relative to the first virtual straight line axis A1 (the size of the second sub-portion 412 along the first direction X can be equal to the size of the fourth sub-portion 422 along the first direction X by adjusting the pixel electrode connecting portion 440).

[0121] According to some exemplary embodiments, in combination with reference to Figure 13A and Figure 13B , the first active layer 310 and the second active layer 320 are respectively symmetric relative to a second virtual straight line axis A2 passing through at least one of the second sub-portion 412, the fourth sub-portion 422 and the sixth sub-portion 432, i.e. the second sub-portion 412, the fourth sub-portion 422 or the sixth sub-portion 432 with a relatively narrow width are arranged at a relatively central position of the first active layer 310 and the second active layer 320 along the second direction Y, which can make the electric field and the carrier distribution in the first active layer 310 and the second active layer 320 more symmetrical and uniform, so as to be more easily controlled by the gate 210, the leakage current is smaller, and at the same time, the current congestion can be reduced, thereby reducing the power consumption and heat generation.

[0122] For example, the first connecting portion 410 is symmetric relative to the second virtual straight line axis A2, and / or the second connecting portion 420 is symmetric relative to the second virtual straight line axis A2, and / or the third connecting portion 430 is symmetric relative to the second virtual straight line axis A2.

[0123] According to some exemplary embodiments, in combination with reference to Figure 11A and Figure 14 The array substrate can further include an organic insulating layer ORG between the passivation layer PVX and the pixel electrode layer 500, the organic insulating layer ORG includes a third via hole V03, the orthographic projection of the first via hole V01 on the substrate substrate is located within the orthographic projection of the third via hole V03 on the substrate substrate, and the orthographic projection of the second via hole V02 on the substrate substrate is located within the orthographic projection of the third via hole V03 on the substrate substrate. The pixel electrode 510 is electrically connected to the pixel electrode connecting portion 440 through the first via hole V01 and the third via hole V03, and the pixel electrode 510 is electrically connected to the first capacitor plate 220 through the second via hole V02 and the third via hole V03.

[0124] At least some embodiments of the present disclosure also provide a display panel including the array substrate as described above.

[0125] For example, the display panel can further include an electronic ink layer on the array substrate, a counter electrode on a side of the electronic ink layer away from the substrate substrate, and a counter substrate on a side of the counter electrode away from the substrate substrate.

[0126] At least some embodiments of the present disclosure also provide a display device including the display substrate as described above. The display device can include any device or product having a display function. For example, the display device can be an e-book reader, a smart tag, a smart watch, a digital signage, etc.

[0127] It should be understood that the display device according to some example embodiments of the present disclosure has all the features and advantages of the display substrate described above, which can be referred to the description above for the display substrate and will not be repeated here.

[0128] As used herein, the terms "substantially," "about," "approximately," and other similar terms are used as terms of approximation and not as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. In view of the process fluctuations, measurement problems and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), etc., "about" or "approximately," as used herein, includes the stated value and means a range of values determined to be acceptable by one of ordinary skill in the art to the particular value. For example, "about" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0129] While some embodiments in accordance with the general inventive concept of the present disclosure have been illustrated and described, it is understood that various changes in form and details can be made therein without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined with the following claims and their equivalents.

Claims

1. An array substrate, wherein: The array substrate includes: substrate; A plurality of scan lines are located on the base substrate, and the plurality of scan lines extend along a first direction and are arranged along a second direction; a plurality of data lines located on the base substrate, wherein the plurality of data lines extend along the second direction and are arranged along the first direction; and a plurality of sub-pixels located on the base substrate, the plurality of sub-pixels being arranged in an array along the first direction and the second direction, the sub-pixels comprising a first active layer, a second active layer, and a pixel electrode, a first region of the first active layer being electrically connected to one of the data lines, a second region of the first active layer being electrically connected to a first region of the second active layer, and a second region of the second active layer being electrically connected to the pixel electrode; The sub-pixel further includes a first connecting portion, a second connecting portion, and a pixel electrode connecting portion, wherein the first connecting portion electrically connects the data line and the first area of ​​the first active layer, the second connecting portion electrically connects the second area of ​​the second active layer and the pixel electrode connecting portion, and the pixel electrode connecting portion is directly connected to the pixel electrode; and The total extended length of the first connecting portion is a first length, the average width of the first connecting portion along a direction perpendicular to its extension direction is a first width, the total extended length of the second connecting portion is a second length, the average width of the second connecting portion along a direction perpendicular to its extension direction is a second width, the deviation ratio of the first length compared to the second length is less than or equal to 10%, and the deviation ratio of the first width compared to the second width is less than or equal to 10%.

2. The array substrate according to claim 1, wherein: The first active layer and the second active layer are arranged axially symmetrically with respect to a first virtual straight line, and the first portion of the first connecting portion and at least the second portion of the second connecting portion are arranged axially symmetrically with respect to the first virtual straight line.

3. The array substrate according to claim 2, wherein: The first portion of the first connecting portion and the second connecting portion are arranged symmetrically with respect to the first virtual straight line, or, The second portion of the first connecting portion and the second connecting portion are arranged symmetrically with respect to the first virtual straight line, or, The first connecting portion and the second connecting portion are arranged axially symmetrically with respect to the first virtual straight line.

4. The array substrate according to claim 2 or 3, wherein: The sub-pixel further includes a third connection portion, which electrically connects the second region of the first active layer and the first region of the second active layer. The third connection portion is arranged axially symmetrically with respect to the first virtual straight line.

5. The array substrate according to claim 4, wherein: The first connecting portion includes a first sub-portion and a second sub-portion, the first sub-portion is directly connected to the first region of the first active layer, and the second sub-portion is located on a side of the first sub-portion close to the data line and is directly connected to the data line; The second connecting portion includes a third sub-portion and a fourth sub-portion, the third sub-portion is directly connected to the second region of the second active layer, and the fourth sub-portion is located on a side of the third sub-portion close to the pixel electrode connecting portion and is directly connected to the pixel electrode connecting portion; The third connecting portion includes a fifth sub-portion, a sixth sub-portion, and a seventh sub-portion, wherein the fifth sub-portion and the seventh sub-portion are respectively connected to both sides of the sixth sub-portion, the fifth sub-portion is directly connected to the second region of the first active layer, the seventh sub-portion is directly connected to the first region of the second active layer, and an orthographic projection of the sixth sub-portion on the base substrate does not overlap with an orthographic projection of the first active layer and the second active layer on the base substrate; as well as A minimum dimension of at least one of the second sub-section, the fourth sub-section, and the sixth sub-section along the extension direction of the first virtual linear axis is smaller than a minimum dimension of at least one of the first sub-section, the third sub-section, the fifth sub-section, and the seventh sub-section along the extension direction of the first virtual linear axis.

6. The array substrate according to claim 4, wherein: The first active layer and the second active layer are spaced apart along the first direction, the first active layer has a larger size along the first direction than along the second direction, and the second active layer has a larger size along the first direction than along the second direction; and The first area and the second area of ​​the first active layer are arranged at intervals along the second direction, the first area and the second area of ​​the second active layer are arranged at intervals along the second direction, the first area of ​​the second active layer is located on one side of the second area of ​​the first active layer along the first direction, the second area of ​​the second active layer is located on one side of the first area of ​​the first active layer along the first direction, and the pixel electrode connection portion is located on a side of the second area of ​​the second active layer away from the first area of ​​the second active layer along the second direction.

7. The array substrate according to claim 6, wherein: The first connecting portion is in a strip shape extending along the first direction, and the second portion of the second connecting portion and the first connecting portion are arranged axially symmetrically with respect to the first virtual straight line; and The second connecting portion further includes a third portion located on one side of the second portion along the second direction, and the third portion connects the second portion and the pixel electrode connecting portion.

8. The array substrate according to claim 6, wherein: The second connecting portion is in an L-shape rotated 90° counterclockwise, and the first portion of the first connecting portion and the second connecting portion are arranged symmetrically with respect to the first virtual straight line; and The first connecting portion further includes a fourth portion connected to a side of the first portion away from the second connecting portion along the first direction, and the fourth portion electrically connects the first portion and the data line.

9. The array substrate according to any one of claims 6 to 8, wherein: The sub-pixel further includes a gate electrically connected to the scan line, wherein an orthographic projection of the gate on the base substrate at least partially overlaps with an orthographic projection of the first active layer on the base substrate, and an orthographic projection of the gate on the base substrate at least partially overlaps with an orthographic projection of the second active layer on the base substrate; The gate has at least one notch, which is partially recessed into the gate along the second direction, and the orthographic projection of the notch on the base substrate is located between the orthographic projection of the first active layer on the base substrate and the orthographic projection of the second active layer on the base substrate.

10. The array substrate according to any one of claims 6 to 8, wherein: The sub-pixel further includes a gate electrically connected to the scan line, wherein an orthographic projection of the gate on the base substrate at least partially overlaps with an orthographic projection of the first active layer on the base substrate, and an orthographic projection of the gate on the base substrate at least partially overlaps with an orthographic projection of the second active layer on the base substrate; as well as The gate includes a first edge and a second edge located on both sides of the second direction, the first edge continuously extends along the first direction, and the second edge continuously extends along the first direction.

11. The array substrate according to any one of claims 6 to 8, wherein: The third connecting portion includes a fifth sub-portion, a sixth sub-portion, and a seventh sub-portion, wherein the fifth sub-portion and the seventh sub-portion are respectively connected to two sides of the sixth sub-portion along the first direction, the fifth sub-portion is directly connected to the second region of the first active layer, the seventh sub-portion is directly connected to the first region of the second active layer, and an orthographic projection of the sixth sub-portion on the base substrate does not overlap with an orthographic projection of the first active layer and the second active layer on the base substrate; as well as The fifth sub-section and the seventh sub-section are both in the shape of strips extending along the first direction, the minimum dimension of the sixth sub-section along the second direction is smaller than the minimum dimension of the fifth sub-section along the second direction, and the minimum dimension of the sixth sub-section along the second direction is smaller than the minimum dimension of the seventh sub-section along the second direction.

12. The array substrate according to claim 5, wherein: The first active layer and the second active layer are spaced apart along the first direction, a size of the first active layer along the first direction is smaller than a size along the second direction, and a size of the second active layer along the first direction is smaller than a size along the second direction; and The first area and the second area of ​​the first active layer are arranged at intervals along the first direction, the first area and the second area of ​​the second active layer are arranged at intervals along the first direction, the first area of ​​the second active layer is located on a side of the second area of ​​the first active layer away from the first area of ​​the first active layer, and the pixel electrode connection portion is located on a side of the second area of ​​the second active layer away from the first area of ​​the second active layer along the first direction.

13. The array substrate according to claim 12, wherein: The first sub-portion is in the shape of an elongated strip extending along the second direction, the second sub-portion is connected to a side of the first sub-portion along the first direction and away from the second active layer, and the minimum dimension of the second sub-portion along the second direction is smaller than the minimum dimension of the first sub-portion along the second direction; and / or, The third sub-section is in the shape of a long strip extending along the second direction, the fourth sub-section is connected to a side of the second sub-section along the first direction and away from the first active layer, and the minimum dimension of the fourth sub-section along the second direction is smaller than the minimum dimension of the third sub-section along the second direction; and / or, The fifth sub-section and the seventh sub-section are both in the shape of long strips extending along the second direction, the minimum dimension of the sixth sub-section along the second direction is smaller than the minimum dimension of the fifth sub-section along the second direction, and the minimum dimension of the sixth sub-section along the second direction is smaller than the minimum dimension of the seventh sub-section along the second direction.

14. The array substrate according to claim 13, wherein: The first active layer and the second active layer are respectively symmetrical with respect to a second virtual straight line axis, and the second virtual straight line axis passes through at least one of the second sub-portion, the fourth sub-portion, and the sixth sub-portion.

15. The array substrate according to any one of claims 13 or 14, wherein: The first subsection and the third subsection are arranged symmetrically with respect to the first virtual straight line, and at least a portion of the second subsection and at least a portion of the fourth subsection are arranged symmetrically with respect to the first virtual straight line.

16. An array substrate, wherein: The array substrate includes: substrate; A plurality of scan lines are located on the base substrate, and the plurality of scan lines extend along a first direction and are arranged along a second direction; a plurality of data lines located on the base substrate, wherein the plurality of data lines extend along the second direction and are arranged along the first direction; and a plurality of sub-pixels located on the base substrate, the plurality of sub-pixels being arranged in an array along the first direction and the second direction, the sub-pixels comprising a first active layer, a second active layer, and a pixel electrode, a first region of the first active layer being electrically connected to one of the data lines, a second region of the first active layer being electrically connected to a first region of the second active layer, a second region of the second active layer being electrically connected to the pixel electrode, and the first active layer and the second active layer being axially symmetrically arranged with respect to a first virtual straight line; The sub-pixel further includes a first connecting portion, a second connecting portion, a third connecting portion, and a pixel electrode connecting portion, wherein the first connecting portion electrically connects the data line and the first area of ​​the first active layer, the second connecting portion electrically connects the second area of ​​the second active layer and the pixel electrode connecting portion, the third connecting portion electrically connects the second area of ​​the first active layer and the first area of ​​the second active layer, and the pixel electrode connecting portion is directly connected to the pixel electrode; The first connecting portion includes a first sub-portion and a second sub-portion, the first sub-portion is directly connected to the first region of the first active layer, and the second sub-portion is located on a side of the first sub-portion close to the data line and is directly connected to the data line; The second connecting portion includes a third sub-portion and a fourth sub-portion, the third sub-portion is directly connected to the second region of the second active layer, and the fourth sub-portion is located on a side of the third sub-portion close to the pixel electrode connecting portion and is directly connected to the pixel electrode connecting portion; The third connecting portion includes a fifth sub-portion, a sixth sub-portion, and a seventh sub-portion, wherein the fifth sub-portion and the seventh sub-portion are respectively connected to both sides of the sixth sub-portion, the fifth sub-portion is directly connected to the second region of the first active layer, the seventh sub-portion is directly connected to the first region of the second active layer, and an orthographic projection of the sixth sub-portion on the base substrate does not overlap with an orthographic projection of the first active layer and the second active layer on the base substrate; and A minimum dimension of at least one of the second sub-section, the fourth sub-section, and the sixth sub-section along the extension direction of the first virtual linear axis is smaller than a minimum dimension of at least one of the first sub-section, the third sub-section, the fifth sub-section, and the seventh sub-section along the extension direction of the first virtual linear axis.

17. A display panel, wherein: The display panel includes the array substrate according to any one of claims 1 to 16.

18. A display device, wherein: The display device includes the display panel according to claim 17.

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