Switching circuit for switching USB and audio signal of Type-C interface

Abstract

The invention discloses a switching circuit for switching a USB and an audio signal through a Type-C interface, and the circuit comprises a first switch which is connected with an audio end and an output end, and is called as an audio channel; and the second switch is connected with the USB end and the output end and is called as a USB path. The first switch comprises a first NMOS (N-channel Metal Oxide Semiconductor) tube and a second NMOS tube which are connected in series; the 3.3 V voltage supplies power to the first current source, and the output end of the first current source is connected with the grid electrode of the first NMOS tube; the grid electrode of the first NMOS tube is also connected with an audio end through a first resistor and is also connected with the grid electrode of the second NMOS tube through a third switch; the substrate and the source electrode of the first NMOS tube are connected and are connected with an audio end at the same time; the drain electrode of the first NMOS tube is connected with the substrate and the source electrode of the second NMOS tube; the grid electrode of the second NMOS tube is further connected with 1.8 V voltage through a fourth switch, and the drain electrode of the second NMOS tube is connected with the output end. The Type-C switch is integrated in the baseband chip under the advanced integrated circuit manufacturing process, the voltage resistance requirement of input and output equipment is met at the same time, and switching of a USB signal and an audio signal by the Type-C interface can be achieved.

Description

Technical Field

[0001] The present application relates to a semiconductor integrated circuit, and more particularly to an analog switch circuit for switching USB and audio signals through a Type-C interface under an advanced integrated circuit manufacturing process. Background Art

[0002] USB Type-C, also known as USB-C, is a hardware interface form of Universal Serial Bus (USB), hereinafter referred to as Type-C interface.

[0003] Traditionally, smart devices (such as mobile phones) use a 3.5mm headphone jack to transmit audio signals. In recent years, some mobile phones have begun to use the Type-C interface to transmit audio signals, while removing the 3.5mm headphone jack. The Type-C interface is used to transmit both USB signals and audio signals, so an analog switch circuit is required to switch between audio signals and USB signals in different modes, hereinafter referred to as the Type-C switch.

[0004] The USB2.0 protocol has two main working modes - high-speed mode and full-speed mode. In high-speed mode, the high and low levels of the transmitted USB signal are 0.8V and 0V respectively. In full-speed mode, the high and low levels of the transmitted USB signal are 3.3V and 0V respectively. In order to save a large-capacity DC-blocking capacitor and achieve better pop noise performance, class G power amplifiers are often used on smart devices to drive audio signals, and the high and low levels of the transmitted audio signals are 1.5V and -1.5V respectively. The Type-C switch needs to switch the signal between different high and low levels, which is achievable under large-scale integrated circuit manufacturing processes (such as 350nm, 180nm, etc.).

[0005] As the requirements for integration and cost of smart devices gradually increase, the Type-C switch integrated on the SOC (System on aChip) side can significantly reduce the complexity of board-level routing and reduce chip procurement costs. However, the maximum withstand voltage of input and output devices (I / O devices) under advanced integrated circuit manufacturing processes (such as 22nm, 12nm, etc.) is 1.8V, while the maximum voltage requirement of USB signals is 3.3V. This requires solving the withstand voltage problem of the Type-C switch and correctly transmitting USB signals and audio signals. Summary of the invention

[0006] The technical problem to be solved by the present application is: how to make the Type-C switch for switching USB signals and audio signals have a higher voltage resistance, so as to correctly transmit both USB signals and audio signals.

[0007] In order to solve the above technical problems, the present application proposes a switch circuit for switching USB and audio signals in a Type-C interface, including: a first switch connects an audio terminal and an output terminal, which is called an audio path; a second switch connects a USB terminal and an output terminal, which is called a USB path; the audio terminal is connected to an audio module inside a smart device, the USB terminal is connected to a USB module inside a smart device, and the output terminal is connected to a Type-C interface on the surface of the smart device; when the first switch is closed, the second switch is disconnected; when the second switch is closed, the first switch is disconnected. The first switch includes a first NMOS tube and a second NMOS tube connected in series; a 3.3V voltage supplies power to a first current source, and the output terminal of the first current source is connected to the gate of the first NMOS tube; the gate of the first NMOS tube is also connected to the audio terminal through a first resistor, and the gate of the first NMOS tube is also connected to the gate of the second NMOS tube through a third switch; the substrate and source of the first NMOS tube are connected, and are connected to the audio terminal at the same time; the drain of the first NMOS tube is connected to the substrate and source of the second NMOS tube; the gate of the second NMOS tube is also connected to a 1.8V voltage through a fourth switch, and the drain of the second NMOS tube is connected to the output terminal.

[0008] Further, when the first current source is working, the third switch is closed, and the fourth switch is open, the first NMOS tube and the second NMOS tube are both turned on, and the first switch is closed. When the first current source is turned off, the third switch is open, and the fourth switch is closed, the first NMOS tube is turned off, and the first switch is open.

[0009] Furthermore, the third switch includes a fifth NMOS tube and a sixth PMOS tube connected in parallel; the gate voltage of the fifth NMOS tube is 1.8V when the first switch is closed and is zero when the second switch is closed; the gate of the sixth PMOS tube is connected to a 1.8V voltage; the source of the fifth NMOS tube is connected to the drain of the sixth PMOS tube, and is also connected to the gate of the first NMOS tube; the drain of the fifth NMOS tube is connected to the source of the sixth PMOS tube, and is also connected to the gate of the second NMOS tube; the source of the fifth NMOS tube is connected to the substrate; a parasitic first diode is provided between the substrate and the drain of the fifth NMOS tube; and a parasitic second diode is provided between the drain and the substrate of the sixth PMOS tube.

[0010] Furthermore, when the audio path is working, the fifth NMOS tube is turned on when the gate voltage VG1 of the first NMOS tube is less than 1.8V; the sixth PMOS tube M6 is turned on when VG1 is greater than 1.8V; the combination of the fifth NMOS tube and the sixth PMOS tube realizes the closing of the third switch. When the USB path is working, the fifth NMOS tube and the sixth PMOS tube are both in the off state, and the third switch is opened.

[0011] Further, the fourth switch includes a seventh PMOS tube and an eighth PMOS tube connected in series; the gate voltage of the seventh PMOS tube is 1.8V when the first switch is closed, and is zero when the second switch is closed; the gate voltage of the eighth PMOS tube is 3.3V when the first switch is closed, and is zero when the second switch is closed; the drain of the seventh PMOS tube is connected to the gate of the second NMOS tube; the source of the seventh PMOS tube is connected to the source of the eighth PMOS tube; the drain of the eighth PMOS tube is connected to a 1.8V voltage; a parasitic third diode is provided between the drain of the seventh PMOS tube and the substrate; and a parasitic fourth diode is provided between the drain of the eighth PMOS tube and the substrate.

[0012] Furthermore, when the audio path is working, when the gate voltage VG2 of the second NMOS tube is less than 1.8V, the seventh PMOS tube is turned off and the fourth switch is disconnected; when VG2≥1.8V, the eighth PMOS tube is turned off and the fourth switch is disconnected. When the USB path is working, the seventh PMOS tube and the eighth PMOS tube are both turned on and the fourth switch is closed.

[0013] Further, the second switch includes a third NMOS tube and a fourth PMOS tube connected in parallel; the 3.3V voltage supplies power to the second current source, and the output end of the second current source is connected to the gate of the third NMOS tube; the gate of the third NMOS tube is also connected to the drain through the second resistor, and the gate of the third NMOS tube is also connected to the audio end through the fifth switch; the drain of the third NMOS tube is also connected to the USB end and the source of the fourth PMOS tube; the source of the third NMOS tube is connected to the output end and the drain of the fourth PMOS tube; the third resistor connects the substrate and the source of the third NMOS tube; the fourth resistor connects the source and the substrate of the fourth PMOS tube; the gate of the fourth PMOS tube supplies power to the third current source, and the output end of the third current source is grounded; the gate of the fourth PMOS tube is also connected to the audio end through the sixth switch; the gate of the fourth PMOS tube is also connected to the source through the fifth resistor.

[0014] Furthermore, when the second current source and the third current source are working, as the USB terminal voltage increases, the third NMOS tube is turned off from on, and the fourth PMOS tube is turned on from off, and the combination of the third NMOS tube and the fourth PMOS tube realizes the closing of the second switch. When the second current source and the third current source are turned off, the third NMOS tube and the fourth PMOS tube are both turned off, and the second switch is opened.

[0015] Further, the fifth switch includes a ninth NMOS tube and a tenth NMOS tube connected in series; the gate voltage of the ninth NMOS tube is a threshold voltage when the first switch is closed, and is zero when the second switch is closed; the gate voltage of the tenth NMOS tube is a threshold voltage when the first switch is closed, and is 1.8V when the second switch is closed; the source of the ninth NMOS tube is connected to the audio terminal; the source of the ninth NMOS tube M9 is also connected to the substrate of the ninth NMOS tube through a sixth resistor; a parasitic fifth diode is provided between the substrate and the drain of the ninth NMOS tube; the drain of the ninth NMOS tube is also connected to the drain and substrate of the tenth NMOS tube; a parasitic sixth diode is provided between the substrate and the drain of the tenth NMOS tube; and the drain of the tenth NMOS tube is also connected to the gate of the third NMOS tube.

[0016] Furthermore, when the USB channel is working, the ninth NMOS tube is turned off and the fifth switch is opened. When the audio channel is working, when the audio signal voltage is between -1.5V and 0V, the ninth NMOS tube and the tenth NMOS tube are both turned on and the fifth switch is closed; when the audio signal voltage is between 0 and +1.5V, the ninth NMOS tube and the tenth NMOS tube are both turned off and the fifth switch is opened.

[0017] Further, the sixth switch includes an eleventh NMOS tube, a twelfth PMOS tube and a thirteenth NMOS tube connected in series; the gate of the eleventh NMOS tube is connected to the gate of the first NMOS tube; the gate voltage of the twelfth PMOS tube is the opposite of the threshold voltage when the first switch is closed, and is zero when the second switch is closed; the gate of the thirteenth NMOS tube is connected to the gate of the second NMOS tube; the source of the eleventh NMOS tube is connected to the audio terminal, and the source of the eleventh NMOS tube is also connected to the substrate; a parasitic seventh diode is provided between the substrate and the drain of the eleventh NMOS tube; the drain of the eleventh NMOS tube is also connected to the drain of the twelfth PMOS tube; the source of the twelfth PMOS tube is connected to the substrate, and a parasitic eighth diode is provided between the substrate and the drain of the twelfth PMOS tube; the source of the twelfth PMOS tube is also connected to the source of the thirteenth NMOS tube; the source of the thirteenth NMOS tube is also connected to the substrate, and a parasitic ninth diode is provided between the substrate and the drain of the thirteenth NMOS tube; the drain of the thirteenth NMOS tube is also connected to the gate of the fourth PMOS tube.

[0018] Further, when the USB channel is working, the thirteenth NMOS tube is turned off and the sixth switch is opened. When the audio channel is working, when the audio signal voltage is between -1.5V and 0V, the twelfth PMOS tube is turned off and the sixth switch is opened; when the audio signal voltage is between 0 and 1.5V, the eleventh NMOS tube, the twelfth PMOS tube and the thirteenth NMOS tube are all turned on and the sixth switch is closed.

[0019] The technical effect achieved by this application is: the Type-C switch is integrated into the baseband chip under the advanced integrated circuit manufacturing process, and the voltage resistance requirements of the input and output devices under the advanced integrated circuit manufacturing process are met, and the switching requirements of the Type-C interface for USB signals and audio signals can be realized. Compared with the existing solutions, this application can achieve higher integration and lower cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is an overall schematic diagram of a switch circuit for switching USB and audio signals on a Type-C interface proposed in this application.

[0021] Figure 2 yes Figure 1 A schematic diagram of a specific implementation circuit of the first switch S1 in FIG.

[0022] Figure 3 yes Figure 2 A schematic diagram of a specific implementation circuit of the third switch S3.

[0023] Figure 4 yes Figure 2 A schematic diagram of a specific implementation circuit of the fourth switch S4.

[0024] Figure 5 yes Figure 1 A schematic diagram of a specific implementation circuit of the second switch S2 in FIG.

[0025] Figure 6 yes Figure 5 Schematic diagram of a specific implementation circuit of the fifth switch S5.

[0026] Figure 7 yes Figure 5 Schematic diagram of a specific implementation circuit of the sixth switch S6.

[0027] Figure 8 This is the eye diagram of the Type-C switch output signal working in high-speed mode when USB signal is input.

[0028] Fig. 9 This is the eye diagram of the Type-C switch output signal when operating in full-speed mode with USB signal input.

[0029] Fig.10 This is the FFT diagram of the signal at the output of the Type-C switch when the audio signal is input.

[0030] Explanation of the reference numerals in the figure: S1 to S6 are switches; M1 to M13 are MOS tubes; I1 to I3 are current sources; R1 to R6 are resistors; D1 to D9 are parasitic diodes; V33 is a 3.3V voltage; V18 is a 1.8V voltage. DETAILED DESCRIPTION

[0031] See also Figure 1 , the switch circuit for switching USB and audio signals on the Type-C interface proposed in this application includes: an audio end, a USB end, and an output end. The audio end is connected to the audio module inside the smart device. The maximum voltage swing of the audio module when working is -1.5V to 1.5V, and the voltage is zero when the audio module is turned off. The USB end is connected to the USB module inside the smart device. The maximum voltage swing of the USB module when working is 0 to 3.3V, and the voltage is zero when the USB module is turned off. The output end is connected to the Type-C interface on the surface of the smart device. The audio end is connected to the output end through the first switch S1, which is called the audio path. The USB end is connected to the output end through the second switch S2, which is called the USB path. When the audio path is closed, the USB path is disconnected. When the USB path is closed, the audio path is disconnected. At any time, the first switch S1 and the second switch S2 are either both disconnected, or only one of the switches is closed. The first switch S1 and the second switch S2 cannot be closed at the same time. This application focuses on solving the implementation method of the first switch S1 and the second switch S2.

[0032] See also Figure 2 ,This is Figure 1 A specific implementation circuit of the first switch S1 in the embodiment. The circuit includes two NMOS tubes M1 and M2 connected in series, two switches S3 and S4, a current source I1, and a resistor R1. The 3.3V voltage V33 supplies power to the first current source I1, and the output of the first current source I1 is connected to the gate of the first NMOS tube M1. The gate of the first NMOS tube M1 is also connected to the audio terminal through the first resistor R1, and the gate of the first NMOS tube M1 is also connected to the gate of the second NMOS tube M2 through the third switch S3. The substrate and source of the first NMOS tube M1 are connected and connected to the audio terminal at the same time. The drain of the first NMOS tube M1 is connected to the substrate and source of the second NMOS tube M2. The gate of the second NMOS tube M2 is also connected to the 1.8V voltage V18 through the fourth switch S4, and the drain of the second NMOS tube M2 is connected to the output terminal. The gate voltage of the first NMOS tube M1 is VG1, and the gate voltage of the second NMOS tube M2 is VG2.

[0033] Figure 2In the implementation circuit of the first switch S1 shown, when the audio path is working, the first switch S1 needs to be closed and the second switch S2 needs to be opened. The first current source I1 is working, the third switch S3 is closed, and the fourth switch S4 is opened. The gate control signal (i.e., gate voltage) VG1 of the two NMOS tubes M1 and M2 is VG2 and is composed of the first current source I1 and the resistor R1 self-biasing. The gate-source voltage VGS of the two NMOS tubes M1 and M2 is equal to the voltage VR1 across the first resistor R1, VGS=VR1=I1×R1, and the appropriate first resistor value is selected so that VR1≤1.8V, so the corresponding resistance of the two NMOS tubes M1 and M2 is a constant value, which can achieve relatively good signal harmonics. The two NMOS tubes M1 and M2 are both in the on state, realizing the closure of the first switch S1. As four-port devices, the NMOS tubes M1 and M2 have a gate-drain voltage, a gate-source voltage, and a gate-body (where body represents substrate) voltage of VR1, and a source-drain voltage, a source-body voltage, and a drain-body voltage of 0V, that is, the highest voltage at any two ends is VR1, which does not exceed 1.8V, thus avoiding the overvoltage problem of input and output devices under advanced integrated circuit manufacturing processes.

[0034] Figure 2 In the implementation circuit of the first switch S1 shown, when the USB path is working, the first switch S1 needs to be disconnected and the second switch S2 needs to be closed. The first current source I1 is turned off, the third switch S3 is turned off, and the fourth switch S4 is closed, so the gate voltage VG1 of the first NMOS tube M1 is 0, the gate voltage VG2 of the second NMOS tube M2 is 1.8V, and the first NMOS tube M1 is turned off to achieve the disconnection of the first switch S1. When the output end is connected to the USB end, the maximum voltage swing range of the output end is 0 to 3.3V. Since the gate voltage VG2 of the second NMOS tube M2 is 1.8V, when the output end voltage exceeds 1.8V, the second NMOS tube M2 is turned off, and the maximum source voltage of the second NMOS tube M2 is 1.8V. The gate-drain voltage of the second NMOS tube M2 is between -1.8 and +1.5V, the gate-source voltage and the gate-body voltage are between 0V and 1.8V, the drain-source voltage and the drain-body voltage are between 0V and 1.5V, and the voltage at any two ends is between -1.8V and 1.8V, and there is no overvoltage problem. The drain of the first NMOS tube M1, that is, the source of the second NMOS tube M2, has a maximum voltage of 1.8V, the gate voltage of the first NMOS tube M1 is 0V, the gate-source voltage and the gate-body voltage are 0V, the gate-drain voltage is between -1.8V and 0V, the drain-source voltage and the drain-body voltage are between 0 and 1.8V, and the voltage at any two ends of the first NMOS tube M1 is between -1.8V and 1.8V, and there is no overvoltage problem.

[0035] See also Figure 3 ,This is Figure 2A specific implementation circuit of the third switch S3 in FIG. The third switch S3 is connected between the gate of the first NMOS tube M1 and the gate of the second NMOS tube M2. The third switch S3 only conducts the gate voltage VG1 of the first NMOS tube M1 and the gate voltage VG2 of the second NMOS tube M2. There is no requirement for impedance. It only needs to consider the overvoltage problem of closing and opening. The third switch S3 designed in this application is mainly composed of an NMOS tube M5 and a PMOS tube M6 connected in parallel. The gate voltage of the fifth NMOS tube M5 is 1.8V when the first switch S1 is closed, which is used to transfer the VG1 voltage to the gate of the second NMOS tube M2. The gate voltage of the fifth NMOS tube M5 is zero when the second switch S2 is closed, because at this time the gate voltage VG2 of the second NMOS tube M2 is 1.8V, and the gate voltage of the first NMOS tube M1 is 0V. The third switch S3 needs to be disconnected to isolate VG1 and VG2. The gate of the sixth PMOS tube M6 is connected to a 1.8V voltage V18. The source of the fifth NMOS tube M5 is connected to the drain of the sixth PMOS tube M6, and is also connected to the gate of the first NMOS tube M1. The drain of the fifth NMOS tube M5 is connected to the source of the sixth PMOS tube M6, and is also connected to the gate of the second NMOS tube M2. The source of the fifth NMOS tube M5 is connected to the substrate. The first diode D1 is a parasitic diode of the fifth NMOS tube M5, and the second diode D2 is a parasitic diode of the sixth PMOS tube M6.

[0036] When the audio path is working, the first switch S1 is closed and the second switch S2 is open. The gate voltage VG1 of the first NMOS tube M1 is equal to the audio terminal voltage plus VR1. The audio terminal voltage is between -1.5V and 1.5V. Assuming VR1 = 1.5V, the voltage range of VG1 is 0V to 3V. When VG1 < 1.8V, the gate-source voltage of the fifth NMOS tube M5 is > 0, and the fifth NMOS tube M5 is turned on (or weakly turned on). When VG1 > 1.8V, the gate-source voltage of the sixth PMOS tube M6 is < 0V, and the sixth PMOS tube M6 is turned on (or weakly turned on). The combination of the fifth NMOS tube M5 and the sixth PMOS tube M6 is realized in the range of 0V to 3V, and the third switch S3 is closed. In this state, the gate voltage of the fifth NMOS tube M5 is 1.8V, the gate-source voltage, the gate-drain voltage, and the gate-body voltage are between -1.8V and 1.8V, the drain-source voltage and the drain-body voltage are 0, the voltages at either end of the fifth NMOS tube M5 are between -1.8V and 1.8V, and the fifth NMOS tube M5 has no overvoltage problem. The gate voltage of the sixth PMOS tube M6 is 1.8V, the gate-source voltage, the gate-drain voltage, and the gate-body voltage are between -1.8V and 1.8V, the drain-source voltage and the drain-body voltage are 0V, the voltages at either end of the sixth PMOS tube M6 are between -1.8V and 1.8V, and the sixth PMOS tube M6 has no overvoltage problem.

[0037] When the USB path is working, the first switch S1 is disconnected and the second switch S2 is closed. VG1 is 0, and VG2 is 1.8V. At this time, the gate voltage of the fifth NMOS tube M5 is 0V, the source voltage and the drain voltage are 0V and 1.8V respectively, and the fifth NMOS tube M5 is in the off state. The gate voltage of the sixth PMOS tube M6 is 1.8V, the source voltage and the drain voltage are 1.8V and 0V respectively, and the sixth PMOS tube M6 is in the off state. Therefore, the third switch S3 is disconnected. The voltages at either end of the fifth NMOS tube M5 and the sixth PMOS tube M6 are between -1.8V and 1.8V, and there is no overvoltage problem.

[0038] See also Figure 4 ,This is Figure 2 A specific implementation circuit of the fourth switch S4 in the embodiment. The fourth switch S4 is connected between the gate of the second NMOS tube M2 and the 1.8V voltage V18. The fourth switch S4 designed in the present application mainly adopts the method of connecting two PMOS tubes M7 and M8 in series. The gate voltage of the seventh PMOS tube M7 is 1.8V when the first switch S1 is closed, and is zero when the second switch S2 is closed. The gate voltage of the eighth PMOS tube M8 is 3.3V when the first switch S1 is closed, and is zero when the second switch S2 is closed. The drain of the seventh PMOS tube M7 is connected to the gate of the second NMOS tube M2. The source of the seventh PMOS tube M7 is connected to the source of the eighth PMOS tube M8. The drain of the eighth PMOS tube M8 is connected to the 1.8V voltage V18. There is a parasitic diode D3 between the drain of the seventh PMOS tube M7 and the substrate. There is a parasitic diode D4 between the drain of the eighth PMOS tube M8 and the substrate.

[0039] When the audio path is working, the first switch S1 is closed and the second switch S2 is open. VG2=VG1 is equal to the audio terminal voltage plus VR1. The audio terminal voltage is between -1.5V and 1.5V. Assuming VR1=1.5V, the voltage range of VG2 is between 0V and 3.3V. Since the gate voltage of the seventh PMOS tube M7 is 1.8V, when VG2<1.8V, the seventh PMOS tube M7 is turned off, so the fourth switch S4 is turned off. When VG2≥1.8V, the seventh PMOS tube M7 is turned on, and at the same time, the VG2 voltage is transmitted to the common point A of the seventh PMOS tube M7 and the eighth PMOS tube M8 (that is, the source and substrate connected to the two). At this time, since the gate voltage of the eighth PMOS tube M8 is 3.3V, the eighth PMOS tube M8 is turned off, so the fourth switch S4 is turned off. In summary, when VG2 is between 0 and 3V, the fourth switch S4 is disconnected (the fourth switch S4 can be disconnected when any one of the devices M7 and M8 is turned off). Next, consider the overvoltage problem of the seventh PMOS tube M7 and the eighth PMOS tube M8 when the audio path is working. When VG2 is between 0 and 1.8V, the seventh PMOS tube M7 is turned off, and the drain parasitic diode D4 of the eighth PMOS tube M8 is forward-conducted, which will raise the common point A of M7 and M8 to nearly 1.8V, then the gate-drain voltage of the seventh PMOS tube M7 is between -1.8V and 0V, the gate-source voltage, the gate-body voltage, and the drain-body voltage are between 0V and 1.8V, and the source-drain voltage is between 0 and 1.8V. The voltage at either end of the seventh PMOS tube M7 is between -1.8V and 1.8V, and there is no overvoltage problem. The gate voltage of the eighth PMOS tube M8 is 3.3V, and the source voltage and the drain voltage are both close to 1.8V, so the gate-source voltage, the gate-drain voltage, and the gate-body voltage of the eighth PMOS tube M8 are all -1.5V, the source-drain voltage and the drain-body voltage are 0V, and the voltages at either end of the eighth PMOS tube M8 are between -1.8V and 1.8V, and the eighth PMOS tube M8 has no overvoltage problem. When VG2 is between 1.8V and 3V, the drain-body parasitic diode D3 of the seventh PMOS tube M7 is forward-conducted, and the voltage of the common point A of M7 and M8 changes with VG2. In this state, the gate-source voltage, the gate-drain voltage, and the gate-body voltage of the seventh PMOS tube M7 are all between 0 and -1.5V, the drain-source voltage and the drain-body voltage are 0V, and the voltages at either end of the seventh PMOS tube M7 are between -1.8V and 1.8V, and the seventh PMOS tube M7 has no overvoltage problem. For the eighth PMOS tube M8, the gate voltage is 3.3V, the source voltage and the body voltage vary in the range of 1.8V to 3V, and the drain voltage is 1.8V. Then the gate-source voltage and the gate-body voltage are between 0.3V and 1.5V, the gate-drain voltage is 1.5V, the drain-source voltage and the drain-body voltage are between 0 and -1.2V, and the voltages at either end of the eighth PMOS tube M8 are between -1.8V and 1.8V, and the eighth PMOS tube M8 has no overvoltage problem.In summary, when VG2 fluctuates between 0 and 3 V, the seventh PMOS tube M7 and the eighth PMOS tube M8 have no overvoltage problem.

[0040] When the USB channel is working, the first switch S1 is disconnected and the second switch S2 is closed. The gate voltages of the seventh PMOS tube M7 and the eighth PMOS tube M8 are both 0, and the substrates of the seventh PMOS tube M7 and the eighth PMOS tube M8 are raised to close to V18 through the fourth diode D4, and then the seventh PMOS tube M7 and the eighth PMOS tube M8 are both turned on, so the fourth switch S4 is in a closed state. After being turned on, the VG2 voltage is 1.8V, the gate-source voltage, gate-drain voltage, and gate-body voltage of the seventh PMOS tube M7 and the eighth PMOS tube M8 are all -1.8V, the source-drain voltage and the drain-body voltage are 0, and the voltages at any two ends of the seventh PMOS tube M7 and the eighth PMOS tube M8 are between -1.8V and 1.8V, and there is no overvoltage problem.

[0041] See also Figure 5 ,This is Figure 1 A specific implementation circuit of the second switch S2 in the embodiment. The circuit is mainly composed of an NMOS tube M3 and a PMOS tube M4 connected in parallel, and also includes two current sources I2 and I3, and four resistors R2 to R5. The 3.3V voltage V33 supplies power to the second current source I2, and the output end of the second current source I2 is connected to the gate of the third NMOS tube M3. The gate of the third NMOS tube M3 is also connected to the drain through the second resistor R2, and the gate of the third NMOS tube M3 is also connected to the audio end through the fifth switch S5. The drain of the third NMOS tube M3 is also connected to the USB end and the source of the fourth PMOS tube M4. The source of the third NMOS tube M3 is connected to the output end and the drain of the fourth PMOS tube M4. The third resistor R3 connects the substrate and source of the third NMOS tube M3. The fourth resistor R4 connects the source and substrate of the fourth PMOS tube M4. The gate of the fourth PMOS tube M4 supplies power to the third current source I3, and the output end of the third current source I3 is grounded. The gate of the fourth PMOS tube M4 is also connected to the audio end through the sixth switch S6. The gate of the fourth PMOS transistor M4 is also connected to the source through the fifth resistor R5. The gate voltage of the third NMOS transistor M3 is VG3, and the gate voltage of the fourth PMOS transistor M4 is VG4.

[0042] Since the output voltage swings within the range of -1.5V to +1.5V along with the audio signal when the audio path is working, in order to solve the shutdown and overvoltage problems of the third NMOS tube M3 and the fourth PMOS tube M4 in this state, the gate control voltages of the third NMOS tube M3 and the fourth PMOS tube M4 are controlled by the fifth switch S5 and the sixth switch S6, which will be explained in detail later.

[0043] Figure 5In the implementation circuit of the second switch S2 shown, when the USB path is working, the first switch S1 needs to be disconnected and the second switch S2 needs to be closed. The second current source I2 and the third current source I3 are working. The second current source I2 is generated by a PMOS current mirror. When the gate voltage VG3 of the third NMOS tube M3 is close to 3.3V, the second current source I2 enters the linear region, and the output current is reduced from I2 to near 0. The third current source I3 is generated by an NMOS current mirror. When the gate voltage VG4 of the fourth PMOS tube M4 is close to 0V, the third current source I3 enters the linear region, and the output current is reduced from I3 to near 0. The fifth switch S5 and the sixth switch S6 are disconnected, and the gate control signal (i.e., gate voltage) VG3 of the third NMOS tube M3 is composed of the second current source I2 and the second resistor R2 self-bias. When the USB signal at the USB end increases from 0, the gate voltage VG3 of the third NMOS tube M3 increases with it. VG3=Vusb+VR2, Vusb is the USB signal voltage at the USB end, VR2 is the voltage across the second resistor R2. VR2=I2×R2, select the appropriate second resistor value so that VR2≤1.8V, and ensure that the gate-source voltage of the fourth PMOS tube M4 has no overvoltage problem. The on-resistance of the third NMOS tube M3 is constant. When the USB signal voltage Vusb increases and causes VG3 to approach 3.3V, VG3 will not increase with the increase of the USB signal voltage Vusb, and the on-resistance of the third NMOS tube M3 will increase with the increase of the USB signal voltage Vusb, and the conduction performance will gradually deteriorate. When the USB signal voltage Vusb exceeds 3.3V-Vth3, Vth3 is the threshold voltage of the third NMOS tube M3, and the third NMOS tube M3 is completely turned off. The conduction characteristics of the fourth PMOS tube M4 are exactly opposite to those of the third NMOS tube M3. When the USB signal voltage Vusb is 0, the fourth PMOS tube M4 is turned off. When the USB signal voltage Vusb rises to Vth4, Vth4 is the threshold voltage of the fourth PMOS tube M4, and the fourth PMOS tube M4 begins to conduct. Then, as the USB signal voltage Vusb increases, the conduction impedance of the fourth PMOS tube M4 decreases. Until the USB signal voltage Vusb reaches I3×R5 (i.e. Figure 5After the fourth PMOS tube M4 is turned on and the USB signal voltage Vusb is turned on, the gate voltage VG4 of the fourth PMOS tube M4 increases as the USB signal voltage Vusb increases, and the on-resistance of the fourth PMOS tube M4 is constant. The third NMOS tube M3 and the fourth PMOS tube M4 are connected in parallel to form the second switch S2, which can achieve a relatively constant on-resistance, that is, the second switch S2 is closed. When the USB channel is working, the voltage at the USB end is 0 to 3.3V. Assuming that the maximum VR2 and VR5 are both 1.8V, the gate-source voltage, gate-drain voltage, and gate-body voltage of the third NMOS tube M3 are VR2≤1.8V, the source-drain voltage and the drain-body voltage are 0V, and the voltage at any two ends of the third NMOS tube M3 does not exceed 1.8V, so the third NMOS tube M3 has no overvoltage problem. The source-gate voltage, drain-gate voltage, and body-gate voltage of the fourth PMOS tube M4 are VR5≤1.8V, the source-drain voltage and the drain-body voltage are 0V, and the voltage at any two ends of the fourth PMOS tube M4 does not exceed 1.8V, so the fourth PMOS tube M4 has no overvoltage problem.

[0044] Figure 5 In the implementation circuit of the second switch S2 shown, when the audio path is working, the first switch S1 needs to be closed and the second switch S2 needs to be opened. The second current source I2 and the third current source I3 are turned off. When the output end and the audio end are connected, the voltage fluctuation range of the output end is -1.5V to 1.5V, and the voltage corresponding to the USB end is 0V. It is necessary to solve the shutdown and overvoltage problems of the third NMOS tube M3 and the fourth PMOS tube M4 in this state. When the output end voltage is -1.5 to 0V, in order to ensure that the third NMOS tube M3 can be turned off, the gate voltage of the third NMOS tube M3 needs to change with the source voltage, that is, when the gate-source voltage is 0, the third NMOS tube M3 can be turned off. Since the drain voltage of the third NMOS tube M3, that is, the USB end voltage is 0, when the audio path is working, Figure 1The output voltage signal changes with the audio signal, and its range is -1.5V to +1.5V. When the output voltage changes in the range of -1.5V to 0V, in order to ensure that the third NMOS tube M3 is in the off state, it is necessary to control the gate voltage of the third NMOS tube M3 to follow the output voltage change, that is, it is necessary to ensure that the gate-source voltage of the third NMOS tube M3 is 0. The gate-source voltage and gate-body voltage of the third NMOS tube M3 are 0, the gate-drain voltage is -1.5V to 0, the drain-source voltage and the drain-body voltage are 0 to 1.5V, and the voltage at any two ends does not exceed 1.8V, and the third NMOS tube M3 has no overvoltage problem. When the output voltage is in the range of 0 to 1.5V, the gate voltage of the third NMOS tube M3 needs to be kept at 0, and the third NMOS tube M3 can be in the off state. The gate-source voltage, gate-body voltage, drain-source voltage, and drain-body voltage of the third NMOS tube M3 are -1.5V to 0V, the gate-drain voltage is 0V, and the voltage at any two ends does not exceed 1.8V. The third NMOS tube M3 also has no overvoltage problem. In summary, when the output terminal voltage fluctuates between -1.5V and +1.5V, the third NMOS tube M3 is in a turned-off state and has no overvoltage problem. The fifth switch S5 needs to realize that the gate voltage of the third NMOS tube M3 follows the audio terminal voltage when the output terminal voltage is -1.5V to 0, and the gate voltage of the third NMOS tube M3 is 0 when the output terminal voltage is 0 to +1.5V. On the contrary, for the fourth PMOS tube M4, when the output terminal voltage changes from -1.5V to 0, the gate voltage of the fourth PMOS tube M4 needs to be maintained at 0, and when the output terminal voltage changes from 0 to 1.5V, the gate voltage of the fourth PMOS tube M4 needs to follow the audio terminal voltage to achieve the purpose of shutting down the fourth PMOS tube M4. Similarly, when the output voltage changes from -1.5V to +1.5V, the voltage at either end of the fourth PMOS tube M4 is between -1.8V and 1.8V, and there is no overvoltage problem. Here, the sixth switch S6 is required to realize the gate voltage control of the fourth PMOS tube M4. When the third NMOS tube M3 and the fourth PMOS tube M4 are turned off at the same time, the second switch S2 is in an off state.

[0045] See also Figure 6 ,This is Figure 5A specific implementation circuit of the fifth switch S5 in the embodiment. The circuit is mainly composed of two NMOS tubes M9 and M10 connected in series. The gate voltage of the ninth NMOS tube M9 is the threshold voltage of the ninth NMOS tube M9 when the first switch S1 is closed, and is zero when the second switch S2 is closed. The gate voltage of the tenth NMOS tube M10 is the threshold voltage of the tenth NMOS tube M10 when the first switch S1 is closed, and is 1.8V when the second switch S2 is closed. The source of the ninth NMOS tube M9 is connected to the audio terminal. The source of the ninth NMOS tube M9 is also connected to the substrate of the ninth NMOS tube M9 through the sixth resistor R6. There is a parasitic diode D5 between the substrate and the drain of the ninth NMOS tube M9. The drain of the ninth NMOS tube M9 is also connected to the drain and substrate of the tenth NMOS tube M10. There is a parasitic diode D6 between the substrate and the drain of the tenth NMOS tube M10. The drain of the tenth NMOS tube M10 is also connected to the gate of the third NMOS tube M3.

[0046] When the USB channel is working, the first switch S1 is disconnected and the second switch S2 is closed. The gate voltages of the two NMOS tubes M9 and M10 are 0V and 1.8V respectively, and the fifth switch S5 can be turned off normally. The gate voltage VG3 of the third NMOS tube M3 varies between VR2 and 3.3V. For the convenience of explanation, VR2=1.8V is taken, that is, VG3 varies between 1.8V and 3.3V. Since the gate voltage of the tenth NMOS tube M10 is 1.8V, the source voltage of the tenth NMOS tube M10 is charged to nearly 1.8V through M10, then the gate-source voltage and gate-body voltage of the tenth NMOS tube M10 are 0, the drain-gate voltage, the drain-source voltage, and the drain-body voltage vary between 0 and 1.5V, and the voltage at any two ends of the tenth NMOS tube M10 does not exceed 1.8V, and there is no overvoltage problem. For the ninth NMOS tube M9, its drain is the source end of the tenth NMOS tube M10, the drain voltage of the ninth NMOS tube M9 is 1.8V, the gate voltage of the ninth NMOS tube M9 is 0V, the ninth NMOS tube M9 is in the off state, the gate-source voltage of the ninth NMOS tube M9 is 0, the gate-drain voltage, the gate-body voltage, the source-drain voltage, and the body-drain voltage are -1.8V, and the ninth NMOS tube M9 has no overvoltage problem. The fifth switch S5 is composed of the ninth NMOS tube M9 and the tenth NMOS tube M10 connected in series, the ninth NMOS tube M9 is in the off state, and therefore the fifth switch S5 is in the open state.

[0047] When the audio path is working, the first switch S1 is closed and the second switch S2 is open. The voltage of the audio signal varies between -1.5V and 1.5V. The gate voltage of the two NMOS tubes M9 and M10 is the threshold voltage Vth of the NMOS tube, which can transmit a voltage lower than 0V. The fifth switch S5 is in a closed state when the audio signal amplitude is between -1.5V and 0V. The gate-source voltage, gate-drain voltage, and gate-body voltage of the ninth NMOS tube M9 and the tenth NMOS tube M10 are 1.5V+Vth at most, and the source-drain voltage and drain-body voltage are 0V, which can basically ensure that there is no overvoltage. Due to the existence of the second resistor R2, VG3 of the positive voltage part will be pulled to 0V, so that M9 and M10 cannot be turned on in the voltage range of -1.5V to 1.5V when the audio signal changes. The fifth switch S5 is in a disconnected state when the audio signal amplitude is between 0 and +1.5V. The gate-source voltage, gate-drain voltage, and gate-body voltage of the ninth NMOS tube M9 and the tenth NMOS tube M10 are 1.5V-Vth at most, and the drain-source voltage and drain-body voltage are 1.5V at most. The voltage at either end of M9 and M10 does not exceed the range of -1.8V to 1.8V, so there is no overvoltage problem.

[0048] See also Figure 7 ,This is Figure 5 A specific implementation circuit of the sixth switch S6 in the embodiment. The circuit is mainly composed of an NMOS tube M11, a PMOS tube M12 and another NMOS tube M13 connected in series. The gate of the eleventh NMOS tube M11 is connected to the gate of the first NMOS tube M1. The gate voltage of the twelfth PMOS tube M12 is the opposite of the threshold voltage of the twelfth PMOS tube M12 when the first switch S1 is closed (the PMOS threshold voltage is a negative number, and "-Vth" is used here to represent the opposite of the threshold voltage of the PMOS tube), and is zero when the second switch S2 is closed. The gate of the thirteenth NMOS tube M13 is connected to the gate of the second NMOS tube M2. The source of the eleventh NMOS tube M11 is connected to the audio terminal, and the source of the eleventh NMOS tube M11 is also connected to the substrate. There is a parasitic diode D7 between the substrate and the drain of the eleventh NMOS tube M11. The drain of the eleventh NMOS tube M11 is also connected to the drain of the twelfth PMOS tube M12. The source of the twelfth PMOS tube M12 is connected to the substrate, and a parasitic diode D8 is provided between the substrate and the drain of the twelfth PMOS tube M12. The source of the twelfth PMOS tube M12 is also connected to the source of the thirteenth NMOS tube M13. The source of the thirteenth NMOS tube M13 is also connected to the substrate, and a parasitic diode D9 is provided between the substrate and the drain of the thirteenth NMOS tube M13. The drain of the thirteenth NMOS tube M13 is also connected to the gate of the fourth PMOS tube M4.

[0049] When the USB channel is working, the gate voltages VG1 and VG2 of the two NMOS tubes M11 and M13 are 0V and 1.8V respectively. VG4 is the gate voltage of the fourth PMOS tube M4, and the voltage range is 0 to (3.3-VR5). If VR5=1.8V, then the voltage range of VG4 is 0 to 1.5V. VG2 is 1.8V, which is higher than 0 to 1.5V, so the thirteenth NMOS tube M13 is in the off state. Therefore, the sixth switch S6 is in the off state. The voltage at either end of the thirteenth NMOS tube M13 is 1.8V at most, and the voltage at either end of the eleventh NMOS tube M11 and the twelfth PMOS tube M12 is close to 0V, so the eleventh NMOS tube M11, the twelfth PMOS tube M12, and the thirteenth NMOS tube M13 have no overvoltage problem.

[0050] When the audio path is working, the gate voltages VG1 and VG2 of the two NMOS tubes M11 and M13 are higher than the audio signal by a VR1 voltage. When the audio signal is in the range of -1.5V to 0V, the eleventh NMOS tube M11 is turned on, and the voltage of the common terminal B (i.e., the drain connected to the two) of the eleventh NMOS tube M11 and the twelfth PMOS tube M12 fluctuates with the voltage fluctuation of the audio terminal, i.e., between -1.5V and 0V, and the voltage difference between any two ends of the eleventh NMOS tube M11 is VR1, which does not exceed 1.8V, and there is no overvoltage problem. Since the gate terminal voltage of the twelfth PMOS tube M12 is -Vth, when the source voltage changes from -1.5V to 0, the twelfth PMOS tube M12 is in the off state, and the maximum voltage difference between any two ends is 1.5+Vth, and there is no overvoltage problem. The gate voltage of the thirteenth NMOS tube M13 is VG2, which varies between 0.3V and 1.8V. Since the twelfth PMOS tube M12 is in the off state, the sixth switch S6 is in the off state, and VG4 is pulled to 0V by the fifth resistor R5. VG4 is the drain of the thirteenth NMOS tube M13, so the maximum voltage difference between any two ends of the thirteenth NMOS tube M13 is 1.8V, and there is no overvoltage problem. In summary, when the audio signal is between -1.5V and 0V, the sixth switch S6 is in the off state, the eleventh NMOS tube M11, the twelfth PMOS tube M12, and the thirteenth NMOS tube M13 have no overvoltage problem, and VG4 is pulled to 0, which is higher than the source voltage of the fourth PMOS tube M4, so the fourth PMOS tube M4 is in the off state. When the audio signal is between 0 and 1.5V, the gate-drain voltage difference of the eleventh NMOS tube M11 is VR1, and it is in the on state. The voltage of the common point B of the eleventh NMOS tube M11 and the twelfth PMOS tube M12 changes with the audio voltage range. Within this range, the maximum voltage difference of the eleventh NMOS tube M11 is VR1, which does not exceed 1.8V, and there is no overvoltage problem. The gate voltage of the twelfth PMOS tube M12 is -Vth, and its source voltage is between 0 and 1.5V, so it is in the on state. Then the voltage of the common point C of the twelfth PMOS tube M12 and the thirteenth NMOS tube M13 changes with the audio signal, and the maximum voltage difference between any two ends of the twelfth PMOS tube M12 is 1.5V+Vth, and there is no overvoltage problem. The gate-source voltage difference of the thirteenth NMOS tube M13 is VR1, so the thirteenth NMOS tube M13 is also in the on state, and the maximum voltage difference between any two ends is VR1, which is less than 1.8V, so the thirteenth NMOS tube M13 also has no overvoltage problem.In summary, when the audio signal is between 0 and 1.5 V, since the eleventh NMOS tube M11, the twelfth PMOS tube M12, and the thirteenth NMOS tube M13 are all turned on, the sixth switch S6 is in a closed state, and the audio signal can be transmitted to the gate of the fourth PMOS tube M4. The gate-drain voltage of the fourth PMOS tube M4 is 0, so the fourth PMOS tube M4 is in a turned-off state, and the eleventh NMOS tube M11, the twelfth PMOS tube M12, and the thirteenth NMOS tube M13 have no overvoltage problem.

[0051] When the USB channel is working and the USB is working in high-speed mode, the corresponding output eye pattern is as follows Figure 8 As shown, the horizontal axis is time (unit: ns) and the vertical axis is voltage (unit: mV). When the USB channel is working and the USB is working in full-speed mode, the corresponding output eye diagram is as follows Fig. 9 As shown, the horizontal axis is time (unit: ns) and the vertical axis is voltage (unit: V). It can be seen that the eye diagrams of the two figures can clearly show the signal change process, so the USB signal can be transmitted normally without signal error problems, indicating that the function and performance of the USB channel are normal.

[0052] When the audio path is working, a 1KHz sinusoidal signal is used as the simulated input. Fig.10 This is the FFT (Fast Fourier Transform) diagram of the output 1KHz signal, with the horizontal axis being the frequency (unit: Hz) and the vertical axis being the relative energy value (unit: dB). It can be seen that its SFDR (Spurious Free Dynamic Range) is 100dB, which basically does not cause harmonic impact on the signal, indicating that the audio signal can be transmitted normally, and the performance and function of the audio channel are normal.

[0053] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should all be included in the protection scope of the present application.

Claims

1. A switch circuit for switching USB and audio signals on a Type-C interface, comprising: The first switch connects the audio terminal and the output terminal, which is called the audio path; The second switch connects the USB end and the output end, which is called the USB path; The audio end is connected to the audio module inside the smart device, the USB end is connected to the USB module inside the smart device, and the output end is connected to the Type-C interface on the surface of the smart device; when the first switch is closed, the second switch is disconnected; when the second switch is closed, the first switch is disconnected; it is characterized in that the first switch includes a first NMOS tube and a second NMOS tube connected in series; the 3.3V voltage supplies power to the first current source, and the output end of the first current source is connected to the gate of the first NMOS tube; the gate of the first NMOS tube is also connected to the audio end through the first resistor, and the gate of the first NMOS tube is also connected to the gate of the second NMOS tube through the third switch; the substrate and source of the first NMOS tube are connected and connected to the audio end at the same time; the drain of the first NMOS tube is connected to the substrate and source of the second NMOS tube; the gate of the second NMOS tube is also connected to the 1.8V voltage through the fourth switch, and the drain of the second NMOS tube is connected to the output end.

2. The switch circuit for switching USB and audio signals of the Type-C interface according to claim 1, characterized in that: When the first current source is working, the third switch is closed, and the fourth switch is open, the first NMOS transistor and the second NMOS transistor are both turned on, and the first switch is closed; When the first current source is turned off, the third switch is opened, and the fourth switch is closed, the first NMOS transistor is turned off, and the first switch is opened.

3. The switch circuit for switching USB and audio signals of the Type-C interface according to claim 1, characterized in that: The third switch includes a fifth NMOS tube and a sixth PMOS tube connected in parallel; the gate voltage of the fifth NMOS tube is 1.8V when the first switch is closed and is zero when the second switch is closed; the gate of the sixth PMOS tube is connected to a 1.8V voltage; the source of the fifth NMOS tube is connected to the drain of the sixth PMOS tube, and is also connected to the gate of the first NMOS tube; the drain of the fifth NMOS tube is connected to the source of the sixth PMOS tube, and is also connected to the gate of the second NMOS tube; the source of the fifth NMOS tube is connected to the substrate; a parasitic first diode is provided between the substrate and the drain of the fifth NMOS tube; and a parasitic second diode is provided between the drain and the substrate of the sixth PMOS tube.

4. The switch circuit for switching USB and audio signals of the Type-C interface according to claim 3, characterized in that: When the audio path is working, the fifth NMOS tube is turned on when the gate voltage VG1 of the first NMOS tube is less than 1.8V; the sixth PMOS tube M6 is turned on when VG1 is greater than 1.8V; the combination of the fifth NMOS tube and the sixth PMOS tube realizes the closing of the third switch; When the USB path is working, the fifth NMOS tube and the sixth PMOS tube are both in the off state, and the third switch is disconnected.

5. The switch circuit for switching USB and audio signals of a Type-C interface according to claim 1, characterized in that: The fourth switch includes a seventh PMOS tube and an eighth PMOS tube connected in series; the gate voltage of the seventh PMOS tube is 1.8V when the first switch is closed, and is zero when the second switch is closed; the gate voltage of the eighth PMOS tube is 3.3V when the first switch is closed, and is zero when the second switch is closed; the drain of the seventh PMOS tube is connected to the gate of the second NMOS tube; the source of the seventh PMOS tube is connected to the source of the eighth PMOS tube; the drain of the eighth PMOS tube is connected to a 1.8V voltage; a parasitic third diode is provided between the drain of the seventh PMOS tube and the substrate; and a parasitic fourth diode is provided between the drain of the eighth PMOS tube and the substrate.

6. The switch circuit for switching USB and audio signals of the Type-C interface according to claim 5, characterized in that: When the audio path is working, when the gate voltage VG2 of the second NMOS tube is less than 1.8V, the seventh PMOS tube is turned off and the fourth switch is disconnected; when VG2 is greater than or equal to 1.8V, the eighth PMOS tube is turned off and the fourth switch is disconnected; When the USB channel is working, the seventh PMOS tube and the eighth PMOS tube are both turned on, and the fourth switch is closed.

7. The switch circuit for switching USB and audio signals of a Type-C interface according to claim 1, characterized in that: The second switch includes a third NMOS tube and a fourth PMOS tube connected in parallel; the 3.3V voltage supplies power to the second current source, and the output end of the second current source is connected to the gate of the third NMOS tube; the gate of the third NMOS tube is also connected to the drain through the second resistor, and the gate of the third NMOS tube is also connected to the audio end through the fifth switch; the drain of the third NMOS tube is also connected to the USB end and the source of the fourth PMOS tube; the source of the third NMOS tube is connected to the output end and the drain of the fourth PMOS tube; the third resistor connects the substrate and the source of the third NMOS tube; The fourth resistor connects the source and substrate of the fourth PMOS tube; the gate of the fourth PMOS tube supplies power to the third current source, and the output end of the third current source is grounded; the gate of the fourth PMOS tube is also connected to the audio end through the sixth switch; the gate of the fourth PMOS tube is also connected to the source through the fifth resistor.

8. The switch circuit for switching USB and audio signals of the Type-C interface according to claim 7, characterized in that: When the second current source and the third current source are working, as the voltage at the USB terminal increases, the third NMOS tube switches from on to off, and the fourth PMOS tube switches from off to on, and the combination of the third NMOS tube and the fourth PMOS tube closes the second switch; When the second current source and the third current source are turned off, the third NMOS tube and the fourth PMOS tube are both turned off, and the second switch is disconnected.

9. The switch circuit for switching USB and audio signals of a Type-C interface according to claim 7, characterized in that: The fifth switch includes a ninth NMOS tube and a tenth NMOS tube connected in series; the gate voltage of the ninth NMOS tube is a threshold voltage when the first switch is closed, and is zero when the second switch is closed; the gate voltage of the tenth NMOS tube is a threshold voltage when the first switch is closed, and is 1.8V when the second switch is closed; the source of the ninth NMOS tube is connected to the audio terminal; the source of the ninth NMOS tube M9 is also connected to the substrate of the ninth NMOS tube through a sixth resistor; a parasitic fifth diode is provided between the substrate and the drain of the ninth NMOS tube; the drain of the ninth NMOS tube is also connected to the drain and the substrate of the tenth NMOS tube; a parasitic sixth diode is provided between the substrate and the drain of the tenth NMOS tube; the drain of the tenth NMOS tube is also connected to the gate of the third NMOS tube.

10. The switch circuit for switching USB and audio signals of the Type-C interface according to claim 9, characterized in that: When the USB path is working, the ninth NMOS tube is turned off and the fifth switch is disconnected; When the audio path is working, when the audio signal voltage is between -1.5V and 0V, the ninth NMOS tube and the tenth NMOS tube are both turned on, and the fifth switch is closed; when the audio signal voltage is between 0 and +1.5V, the ninth NMOS tube and the tenth NMOS tube are both turned off, and the fifth switch is opened.

11. The switch circuit for switching USB and audio signals of a Type-C interface according to claim 7, characterized in that: The sixth switch includes an eleventh NMOS tube, a twelfth PMOS tube and a thirteenth NMOS tube connected in series; the gate of the eleventh NMOS tube is connected to the gate of the first NMOS tube; the gate voltage of the twelfth PMOS tube is the opposite of the threshold voltage when the first switch is closed, and is zero when the second switch is closed; the gate of the thirteenth NMOS tube is connected to the gate of the second NMOS tube; the source of the eleventh NMOS tube is connected to the audio terminal, and the source of the eleventh NMOS tube is also connected to the substrate; a parasitic seventh diode is provided between the substrate and the drain of the eleventh NMOS tube; the drain of the eleventh NMOS tube is also connected to the drain of the twelfth PMOS tube; the source of the twelfth PMOS tube is connected to the substrate, and a parasitic eighth diode is provided between the substrate and the drain of the twelfth PMOS tube; the source of the twelfth PMOS tube is also connected to the source of the thirteenth NMOS tube; the source of the thirteenth NMOS tube is also connected to the substrate, and a parasitic ninth diode is provided between the substrate and the drain of the thirteenth NMOS tube; the drain of the thirteenth NMOS tube is also connected to the gate of the fourth PMOS tube.

12. The switch circuit for switching USB and audio signals of a Type-C interface according to claim 11, characterized in that: When the USB path is working, the thirteenth NMOS tube is turned off and the sixth switch is disconnected; When the audio path is working, when the audio signal voltage is between -1.5V and 0V, the twelfth PMOS tube is turned off and the sixth switch is opened; when the audio signal voltage is between 0 and 1.5V, the eleventh NMOS tube, the twelfth PMOS tube and the thirteenth NMOS tube are all turned on and the sixth switch is closed.

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