Row and column scanning control system based on dormancy and wake-up functional chip

Abstract

The invention provides a row and column scanning control system based on a sleep and wake-up functional chip. The row and column scanning control system is composed of a linear Hall chip matrix and a main control unit. The chip matrix is arranged according to an N * M structure, and each chip is provided with a dormancy pin, an awakening pin and a signal output pin. The main control unit is provided with N groups of sleep ports, wake-up ports and M groups of acquisition input ports. Sleep and wake-up pins of the chips in each row are short-circuited to corresponding ports, and signal output pins of the chips in each column are short-circuited to an acquisition input port. And the main control unit realizes matrix management by logically controlling the sleep and wake-up pins. The system supports a high-speed line-by-line mode, a high-speed interval line mode and a medium-speed scanning mode so as to meet the requirements for real-time performance and power consumption optimization in different application scenes. When the magnetic field change is detected in the dormant state, the chip can send an interrupt signal to the main control unit through the wake-up pin, so that the quick response of the system is realized. The method supports three scanning modes, has the characteristic of low power consumption, and is particularly suitable for application scenes such as a three-mode keyboard and the like.

Description

Technical Field

[0001] The invention relates to the field of electronic equipment, in particular to a row and column scanning control system based on a dormancy and wake-up function chip. Background Art

[0002] Linear Hall chip is a sensor chip widely used in industrial control and automotive electronics to detect magnetic field changes and output corresponding electrical signals. Traditional linear Hall chip control systems usually adopt a simple row and column scanning architecture, but in large-scale chip matrices, there are the following technical problems: (1) High resource usage: When MCU pins are limited, directly controlling the row and column signals of a large-scale chip matrix will lead to pin resource exhaustion and limit system scalability; (2) Lack of real-time performance: In high-speed signal acquisition scenarios, traditional systems have delays in row and column switching, making it difficult to meet the requirements of high-precision and high-speed data acquisition; (3) Weak anti-interference ability: In complex environments, high-frequency noise is easily superimposed on the signal, affecting the sampling accuracy of the ADC signal. Summary of the invention

[0003] The present application provides a row and column scanning control system that responds to a chip based on sleep and wake-up functions, which minimizes the overall system power consumption while meeting high-speed response requirements.

[0004] The present application provides a row and column scanning control system based on a sleep and wake-up function chip, wherein the control system includes: A linear Hall chip matrix, wherein a plurality of the linear Hall chips are arranged in an n×m matrix structure, wherein each linear Hall chip comprises: A sleep pin is used to receive a sleep signal to control the working state of the chip and switch the chip to a sleep state; Wake-up pin, used to receive logic control signals to manage the output status of the chip, or output interrupt signals to trigger system wake-up; A main control unit is connected to the linear Hall chip matrix, and controls the working state switching, row and column signal switching, target row activation and signal acquisition of the chip matrix by configuring the logical combination of the sleep pin and / or the wake-up pin; The system supports a signal output mode and an interrupt wake-up mode, wherein the signal output mode includes a high-speed progressive scan mode, a high-speed interlaced scan mode and a medium-speed scan mode.

[0005] Optionally, the high-speed progressive scanning mode includes: The main control unit configures the sleep pins of all the linear Hall chips to put them in normal working state, configures the wake-up pins according to the preset scanning logic to activate the output signal of the target row, and controls the output state of other rows at the same time, thereby realizing high-speed scanning and signal acquisition of the linear Hall chip matrix row by row.

[0006] Optionally, the high-speed interlaced line scanning mode includes: The main control unit configures sleep pins so that the linear Hall chips in n adjacent rows in the linear Hall chip matrix are in normal working state, and the linear Hall chips in the remaining rows remain in sleep state; the main control unit activates the output signal of the current target row according to a preset scanning sequence, and the chips in the next row are in a ready state; by dynamically adjusting the working and output states of the chip matrix, the system power consumption is reduced while achieving high-speed scanning and data acquisition.

[0007] Optionally, the medium-speed scanning mode is applicable to power consumption-sensitive scenarios, including: The main control unit only configures the sleep pin of the target row chip to put it in working state, and the other row chips remain in sleep state; the main control unit configures the wake-up pin of the target row through direct control or serial communication to realize the output collection of the target row signal.

[0008] Optionally, in the interrupt wake-up mode, the following process is included: The main control unit configures all the sleep pins in the linear Hall chip matrix to a low power consumption mode, so that all the linear Hall chips enter a low-frequency signal acquisition state, and at the same time the main control unit switches to a sleep state, retaining only an interrupt wake-up function; All of the linear Hall chips detect changes in the external magnetic field at preset time intervals; When the change of the external magnetic field detected by any of the linear Hall chips exceeds the set threshold, the linear Hall chip outputs the interrupt signal to the main control unit. After receiving the interrupt signal, the main control unit switches from the sleep state to the working state, reconfigures the working logic of the linear Hall chip matrix, activates the target row chip, and completes signal acquisition.

[0009] Optionally, the main control unit includes multiple groups of ports, each group of ports includes: A sleep port, connected to the sleep pins of the linear Hall chips in each row; The wake-up port is respectively connected to the wake-up pins of the linear Hall chip in each row.

[0010] Optionally, the control system further comprises a shift register for realizing row-by-row dynamic control through serial communication, characterized in that: The shift register receives the control signal from the main control unit and switches the working state of the chip row by row, activating the target row chip and controlling the other row chips to remain in sleep state; The main control unit activates the target row signal output or receives the interrupt signal through the wake-up port.

[0011] Optionally, the output signal supports analog voltage output or digital signal output to meet the requirements of different data acquisition devices.

[0012] Optionally, the logic control signal includes but is not limited to a level signal, a level inversion signal, a pulse signal, a timing control signal, a data carrier signal, etc.

[0013] Optionally, the linear Hall chip matrix may adopt a dynamic n×m arrangement, where n and m are any positive integers, to adapt to different signal acquisition requirements.

[0014] Optionally, the linear Hall chips in n adjacent rows in the linear Hall chip matrix are in normal working state, where n is any positive integer greater than or equal to 2.

[0015] Optionally, the main control unit realizes synchronous signal acquisition of multiple linear Hall chip matrices through a clock signal to meet cross-matrix application requirements.

[0016] The present invention provides a row and column scanning control system based on a sleep and wake-up function chip, including a linear Hall chip matrix and a main control unit. The linear Hall chip matrix adopts an n×m arrangement structure, and each chip is provided with a sleep pin and a wake-up pin, which are respectively used to control the working state and signal output state of the chip, or trigger the system wake-up through an interrupt signal. The main control unit realizes the working state switching, row and column signal switching, target row activation and signal acquisition of the chip matrix by dynamically configuring the logical combination of the sleep pin and the wake-up pin. The system supports high-speed line-by-line scanning mode, high-speed interval line scanning mode and medium-speed scanning mode to meet the requirements of real-time and power consumption optimization in different application scenarios. In addition, the system supports interrupt wake-up mode, which can trigger the main control unit to wake up when the chip detects a change in the magnetic field in the standby state, thereby realizing the combination of low power consumption operation and high response speed. The present invention is suitable for application scenarios such as three-mode keyboards.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Shown is a structural schematic diagram of a row-column scanning control system based on a sleep and wake-up function chip provided in the present application.

[0019] Figure 2The figure is a schematic structural diagram of a row-column scanning control system based on a sleep and wake-up function chip according to an embodiment of the present application.

[0020] Figure 3 The figure shows a waveform diagram of a row and column scanning control system based on a sleep and wake-up function chip in a high-speed progressive scanning mode according to an embodiment of the present application.

[0021] Figure 4 Shown is a waveform diagram of a row and column scanning control system based on a sleep and wake-up function chip in a high-speed interlaced row scanning mode according to an embodiment of the present application.

[0022] Figure 5 Shown is a waveform diagram of a row and column scanning control system based on a sleep and wake-up function chip in a medium-speed scanning mode according to an embodiment provided by the present application.

[0023] Figure 6 The figure shows a waveform diagram of a row and column scanning control system based on a sleep and wake-up function chip in an interrupt wake-up mode according to an embodiment of the present application.

[0024] Figure 7 Shown is a structural schematic diagram of a row-column scanning control system based on a sleep and wake-up function chip according to another embodiment provided by the present application. DETAILED DESCRIPTION

[0025] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices consistent with some aspects of the present application as detailed in the appended claims.

[0026] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one" or "one" do not indicate a quantitative limit, but indicate that there is at least one. If it only refers to "one", it will be explained separately. "Multiple" or "several" means two or more. Unless otherwise specified, similar words such as "front", "rear", "lower" and / or "upper" are only for the convenience of explanation and are not limited to one position or one spatial orientation. Similar words such as "include" or "comprise" mean that the elements or objects appearing in front of "include" or "comprise" cover the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, and may include electrical connections, whether direct or indirect. The singular forms "a", "said" and "the" used in this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0027] like Figure 1 As shown, the present application provides a row and column scanning control system based on a sleep and wake-up function chip, and the control system includes: The linear Hall chip matrix 1 is composed of a plurality of the linear Hall chips 2 arranged in an n×m matrix structure, wherein each linear Hall chip 2 comprises: The sleep pin SLEEP is used to receive a sleep signal to control the working state of the chip and switch the chip to the sleep state; The wake-up pin AWAKE is used to receive a logic control signal to manage the output state of the chip, or output an interrupt signal to trigger system wake-up; A main control unit MCU is connected to the linear Hall chip matrix, and controls the working state switching, row and column signal switching, target row activation and signal acquisition of the linear Hall chip matrix by configuring the logical combination of the sleep pin and / or the wake-up pin; The control system supports a signal output mode and an interrupt wake-up mode, wherein the signal output mode includes a high-speed progressive scan mode, a high-speed interlaced scan mode and a medium-speed scan mode.

[0028] In this embodiment, the control system includes a linear Hall chip matrix and a main control unit. The linear Hall chip matrix is ​​composed of a plurality of linear Hall chips arranged in an n×m structure. Each chip is provided with a sleep pin and a wake-up pin, wherein the sleep pin is used to receive a sleep signal output by the main control chip, so that the main control chip controls the working state of the chip through the sleep pin. The wake-up pin is used to receive a logic control signal, so that the main control chip controls the signal output state of the chip through the wake-up pin, or the wake-up pin can also output an interrupt signal to trigger system wake-up. The main control unit realizes the working state switching, row and column signal switching, target row activation and signal acquisition of the chip matrix by dynamically configuring the logical combination of the sleep pin and the wake-up pin. The logical combination includes but is not limited to high and low levels, and the specific situation is described in detail below. The system of the present invention supports high-speed line-by-line scanning mode, high-speed interlaced line scanning mode and medium-speed scanning mode to meet the requirements of real-time performance and power consumption optimization in different application scenarios. In addition, the system supports an interrupt wake-up mode, which can trigger the main control unit to wake up when the chip detects a change in the magnetic field in the standby state, thereby realizing a combination of low power consumption operation and high response speed. The present invention is suitable for application scenarios such as a three-mode keyboard. In some embodiments, the main control unit MCU includes multiple groups of ports, each group of ports includes: A sleep port SLEEP', connected to the sleep pin SLEEP of each row of the linear Hall chip respectively; The wake-up port AWAKE' is respectively connected to the wake-up pin AWAKE of each row of the linear Hall chip.

[0029] The main control unit is connected to each row of the linear Hall chips through their respective sleep ports SLEEP` and sleep pins SLEEP, so that the main control unit transmits a sleep signal to each row of the linear Hall chips to control the chip to switch between a normal working state and a sleep state, and, through their respective wake-up ports AWAKE` and wake-up pins AWAKE, the main control unit transmits a logic control signal to each row of the linear Hall chips to manage the chip to switch between a normal output state and a high-impedance state.

[0030] In addition, it should be noted that the number of the multiple groups of ports of the main control unit matches the chip matrix structure.

[0031] In some embodiments, the linear Hall chip matrix may adopt a dynamic n×m arrangement, where n and m are any positive integers, to adapt to different signal acquisition requirements.

[0032] In some implementations, the high-speed progressive scan mode includes: The main control unit configures the sleep pins of all the linear Hall chips to put them in normal working state, configures the wake-up pins according to the preset scanning logic to activate the output signal of the linear Hall chip in the target row, and simultaneously controls the output state of the linear Hall chips in other rows, thereby realizing high-speed scanning and signal acquisition of the linear Hall chip matrix row by row.

[0033] Specifically, in the high-speed progressive scanning mode, the main control unit configures the sleep pins of all chips to a low level, so that all chips are in a normal working state, collects chip data of the target row as needed, and configures the wake-up pin to a high level according to the preset scanning logic, so that the chips of the target row can output signals normally. Figure 2 , Figure 3 As shown, taking the 8×8 linear Hall chip matrix as an example, the ports of the main control unit MCU can be set to 8 groups. When the data of the chips in the first row need to be collected, the wake-up port AWAKE`0 of the main control unit MCU is high, and the other wake-up ports AWAKE`1~AWAKE`7 are low. Correspondingly, the wake-up pin of the chips in the first row is high, and the wake-up pins of the chips in the other rows are low. When the data of the chips in the second row need to be collected, the wake-up port AWAKE`1 of the main control unit is high, and the other wake-up ports AWAKE`0, AWAKE`2~AWAKE`7 are low. Correspondingly, the wake-up pin of the chips in the second row is high, and the wake-up pins of the chips in the other rows are low. In this way, the main control unit can selectively control the output signal of the chips in the target row, while the chips in the other non-target rows enter the sleep mode, retaining only the necessary working modules, greatly reducing unnecessary energy consumption. At the same time, the main control unit reduces unnecessary data reading and processing, thereby reducing the overall system power consumption.

[0034] In some embodiments, the high-speed interlaced line scanning mode includes: The main control unit configures sleep pins so that the linear Hall chips in n adjacent rows in the linear Hall chip matrix are in normal working state, and the linear Hall chips in the remaining rows remain in sleep state; the main control unit activates the output signal of the linear Hall chip in the current target row according to a preset scanning order, and the linear Hall chip in the next row is in a ready state; by dynamically adjusting the working state and output state of the linear Hall chip matrix, the system power consumption is reduced while achieving high-speed scanning and data acquisition.

[0035] In the high-speed progressive scanning mode of the previous embodiment, when the data of the target row chip needs to be collected, the main control unit only controls the chip of the current target row to be in a normal working state, and does not control the chips of the n adjacent rows of the current target row to be in a normal working state. However, in this embodiment, in the high-speed interlaced row scanning mode, the main control unit can simultaneously control multiple rows of chips to be in a normal working state. When the chip data of the target row needs to be collected, the normal output signal of the chip of the current target row is activated accordingly, and the chip of the next target row is controlled to be in a ready state.

[0036] Specific, combined Figure 2 , Figure 4 As shown, we continue to use the 8× 8 linear Hall chip matrix and take two-row interval scanning as an example for explanation. In the high-speed interval row scanning mode, the main control unit MCU controls the sleep ports SLEEP`0-SLEEP`7 to implement two-row interval scanning, in which the two rows of chips are controlled to be in normal working state, while the other rows of chips are in sleep state, and the output of each row of chips is controlled through the wake-up port AWAEK`0-AWAKE`7. For example, when the main control unit needs to collect the first row of data, the sleep ports SLEEP`0 and SLEEP`1 are configured to be at a low level, the wake-up port AWAKE`0 outputs a high level, and the outputs of the remaining AWAKE`1-AWAKE`7 remain at a low level. At this time, since the sleep port SLEEP`1 is at a low level, the chips of the corresponding row are in a ready state. When the main control unit needs to collect the second row of data, the sleep ports SLEEP`1 and SLEEP`2 are configured to be at a low level, the wake-up port AWAKE`1 outputs a high level, and the outputs of the remaining rows of chips remain at a low level. Similarly, at this time, since the sleep port SLEEP`2 is at a low level, the chips in the corresponding row are in a ready state.

[0037] Since the next row of chips is in normal working state when the main control unit collects the chip data of the current row, at this time, the output of the next row of chips can be directly switched on and off by controlling the wake-up pin AWAKE of the next row of chips. Therefore, sampling can be performed without waiting after the row scan is switched, thereby greatly improving the scanning speed of the system. In this way, compared with the high-speed progressive scanning mode, the system scanning speed in the high-speed interlaced row scanning mode of this embodiment is faster and the power consumption is lower. In this way, compared with the high-speed progressive scanning mode, the system scanning speed in the high-speed interlaced row scanning mode of this embodiment is faster.

[0038] In some embodiments, the main control unit configures the sleep pin to put the linear Hall chips in n adjacent rows in the linear Hall chip matrix into normal working state, where n is any positive integer greater than or equal to 2.

[0039] In some embodiments, the main control unit realizes synchronous signal acquisition of multiple linear Hall chip matrices through clock signals to meet cross-matrix application requirements.

[0040] In some embodiments, the medium-speed scanning mode is suitable for power-sensitive scenarios, including: The main control unit only configures the sleep pin of the linear Hall chip in the target row to put it in working state, while the linear Hall chips in other rows remain in sleep state; the main control unit configures the wake-up pin of the linear Hall chip in the target row through direct control or serial communication to realize the output collection of the signal of the linear Hall chip d in the target row.

[0041] In this embodiment, in the medium-speed scanning mode, the main control unit controls the output state of each row of chips by controlling all sleep ports. Figure 2 , Figure 5 As shown, when the target row chip of the data collected by the main control unit is the first row chip, the sleep port SLEEP`0 is configured to be low level, and SLEEP`1~ SLEEP`7 is configured to be high level; or, when the target row chip of the data collected by the main control unit is the second row chip, the sleep port SLEEP`1 is configured to be low level, and the sleep port SLEEP`0 and the sleep port SLEEP`2~ SLEEP`7 are configured to be high level. In this way, the chip data of all rows can be collected by switching in sequence. The medium-speed scanning mode has lower power consumption than the above-mentioned high-speed progressive scanning mode and high-speed interlaced scanning mode.

[0042] In some embodiments, in the interrupt wake-up mode, the following process is included: The main control unit configures all the sleep pins in the linear Hall chip matrix to a low power consumption mode, so that all the linear Hall chips enter a low-frequency signal acquisition state, and at the same time the main control unit switches to a sleep state, retaining only an interrupt wake-up function; All of the linear Hall chips detect changes in the external magnetic field at preset time intervals; When the change of the external magnetic field detected by any of the linear Hall chips exceeds a set threshold, the linear Hall chip outputs the interrupt signal to the main control unit; After receiving the interrupt signal, the main control unit switches from the sleep state to the working state, reconfigures the working logic of the linear Hall chip matrix, activates the linear Hall chip of the target row, and completes signal acquisition.

[0043] Specifically, Figure 6As shown, in the interrupt wake-up mode, before all the linear Hall chips enter the low-frequency signal acquisition state, the main control unit first configures all sleep ports to high-level output, and configures all wake-up ports to interrupt wake-up input state, and enters the sleep state itself. At this time, all chips enter the low-frequency signal acquisition state, and detect changes in the external magnetic field at preset time intervals, for example, detecting changes in the external magnetic field once at intervals of 12.5ms. Further, if any chip detects that the external magnetic field changes by more than the set threshold, the chip switches its wake-up pin from a high level to a low level output to the main control unit, and the low level output is the interrupt signal output. When the main control unit receives the interrupt signal, the main control unit is awakened, that is, it switches from the sleep state to the working state, and wakes up the entire system to resume work. In this way, the overall power consumption of the system is reduced, the response speed of the system is improved, and the user experience is improved.

[0044] In some embodiments, Figure 7 As shown, the control system further includes a shift register 3 for realizing row-by-row dynamic control through serial communication.

[0045] The shift register receives the control signal of the main control unit and switches the working state of the linear Hall chip row by row, activates the linear Hall chip of the target row, and controls the chips of other rows to remain in a dormant state; The main control unit includes a plurality of wake-up ports; the main control unit activates the linear Hall chip signal output of the target row or receives an interrupt signal through the wake-up port.

[0046] In this embodiment, in order to save the port of the main control unit, a shift register is set. Specifically, the shift register is provided with a plurality of serial communication input ports and a plurality of register output ports. The main control unit MCU includes a plurality of serial communication output ports and a plurality of wake-up ports. The plurality of serial communication output ports are connected to the plurality of serial communication input ports one by one. The plurality of wake-up ports are connected to the wake-up pins of each row of the linear Hall chips one by one. The plurality of register output ports are connected to the sleep pins of each row of the linear Hall chips one by one.

[0047] Continuing to take the 8×8 linear Hall chip matrix as an example, the multiple serial communication input ports include a data input port DS, a clock input port SHCP and a latch input port STCP, and the multiple registered output ports include 8 registered output ports Q0~Q7. Correspondingly, the multiple serial communication output ports include 3 serial communication ports GPIO_0~GPIO_2, and the multiple wake-up ports include 8 wake-up ports AWAKE`0~AWAKE`7.

[0048] The data input port DS of the shift register is used to receive the serial sleep signal from the main control unit. The clock input port SHCP is used to receive the clock signal provided by the main control unit. The latch input port STCP is used to receive the latch signal of the main control unit. The main control unit sends the sleep signal to the shift register bit by bit through the data input port DS, and shifts it into the register under the control of the clock signal. When the sleep signal is shifted, the latch input port STCP latches the sleep signal to the register output port according to the latch signal.

[0049] In this embodiment, by setting the shift register to communicate with the main control unit, only a small number of ports are needed to control multiple outputs, thereby saving port resources of the main control unit. At the same time, the shift register supports high-speed serial data transmission, effectively improving the data transmission efficiency between the main control unit and the linear Hall chip matrix.

[0050] In some embodiments, the output signal supports analog voltage output or digital signal output to meet the requirements of different data acquisition devices.

[0051] In some embodiments, the logic control signal includes but is not limited to a level signal, a level inversion signal, a pulse signal, a timing control signal, and a data carrier signal.

[0052] In some embodiments, continue to refer to Figure 7 As shown, the main control unit also includes a plurality of sampling ports, the number of which matches the linear Hall chip matrix structure, namely ADC0 to ADC7 in the figure; in the case of high noise requirements and relatively low sampling speed, the control system also includes an RC low-pass filter module 4. The RC low-pass filter module is connected between the output end of each linear Hall chip and the plurality of sampling ports, and is used to filter out high-frequency noise in the signal to improve the sampling accuracy of the sampling port of the main control unit.

[0053] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A row and column scanning control system based on a sleep and wake-up function chip, characterized in that: The system comprises: The linear Hall chip matrix is ​​composed of a plurality of linear Hall chips arranged in a matrix structure of N rows × M columns, wherein each of the linear Hall chips comprises: A sleep pin, used to receive a sleep signal to control the working state of the linear Hall chip and switch the linear Hall chip to a sleep state; A wake-up pin, used to receive a logic control signal to manage the output state of the linear Hall chip, or to output an interrupt signal in sleep mode to trigger system wake-up; Signal output pin, used to output detection signal; A main control unit, the main control unit is connected to the sleep pin and the wake-up pin of each row of the linear Hall chips; The main control unit at least comprises: M groups of acquisition input ports, corresponding to M columns of the linear Hall chip matrix respectively; The signal output pins of each column of the linear Hall chip are short-circuited with each other and correspondingly connected to a group of acquisition input ports of the main control unit; The main control unit controls the system to enter a high-speed progressive scanning mode, a high-speed interlaced scanning mode, or a medium-speed scanning mode by configuring a signal combination of the sleep pin and / or the wake-up pin, and receives the detection signal output by the linear Hall chip matrix; In the sleep mode, if any of the linear Hall chips detects a change in the external magnetic field, an interrupt signal is output to the main control unit through the wake-up pin to trigger system wake-up.

2. The row-column scanning control system according to claim 1, characterized in that: The working state of the linear Hall chip is controlled by the main control unit, and the state switching is performed through the sleep pin and the wake-up pin to manage the signal output of the chip, specifically including: Sleep mode: when the main control unit sends a sleep signal to the linear Hall chip of the target row, the linear Hall chip of the target row enters a sleep state, stops normal signal output, and its signal output pin is in a high impedance state; Working mode: When the main control unit sends a wake-up signal to the linear Hall chip of the target row, the linear Hall chip of the target row exits the sleep state and enters the working mode, starts to detect changes in the external magnetic field, and sends a detection signal through the corresponding signal output pin; The main control unit realizes row-by-row scanning by dynamically controlling the sleep pins and wake-up pins of each row of linear Hall chips, so that the linear Hall chips in the target row are in working mode, while the linear Hall chips in the remaining rows remain in sleep mode or high impedance state.

3. The row-column scanning control system according to claim 1, characterized in that: The main control unit sends a sleep signal to all the chips, and enters the sleep mode itself, retaining only the interrupt wake-up function; at the same time, all the chips switch to low power consumption mode and independently detect changes in the external magnetic field; When any of the chips detects that the change in the external magnetic field exceeds a set threshold, the chip outputs the interrupt signal to the main control unit; after receiving the interrupt signal, the main control unit switches from the sleep mode to the normal working mode.

4. The row-column scanning control system according to claim 1, characterized in that: The system can operate in different scanning modes, and the main control unit controls the working state of the linear Hall matrix, specifically including: In the high-speed progressive scanning mode, the main control unit sequentially activates the linear Hall chip of the target row to make it enter the working state for magnetic field detection, and the chips of the remaining rows remain in the dormant state; when the detection of the chip of the target row is completed, it re-enters the dormant state and activates the chip of the next target row at the same time, and this cycle is repeated to achieve efficient progressive scanning; In the high-speed interlaced row scanning mode, the main control unit simultaneously activates multiple rows of the linear Hall chips according to the preset logic, so that they enter the working state synchronously; the main control unit sequentially collects the detection signal of the current target row, and the linear Hall chip of the next target row is already in the waiting state for collection, and this cycle is carried out to realize the high-speed scanning of the interlaced rows; In the medium-speed scanning mode, the main control unit controls the linear Hall chip of the target row to keep working, and the linear Hall chips of the remaining rows to keep sleeping, and this cycle is repeated to achieve medium-speed scanning.

5. The system according to claim 4, characterized in that The high-speed progressive scanning mode specifically includes: The main control unit controls the states of all the sleep pins to put all the linear Hall chips into working state; The main control unit sequentially configures the logic control signal to the wake-up pin of the target row, so that the linear Hall chip of the target row outputs the detection signal to the main control unit through the corresponding signal output pin; After the linear Hall chip of the target row is scanned, the linear Hall chip of the next target row is activated in sequence, and this cycle is repeated to achieve high-speed row-by-row scanning and signal acquisition of the linear Hall chip matrix.

6. The system according to claim 4, characterized in that The high-speed interlaced line scanning mode specifically includes: The main control unit configures the states of the sleep pins of multiple rows so that the linear Hall chips in n adjacent rows in the linear Hall chip matrix are in working state, and the linear Hall chips in the remaining rows remain in sleep state; According to the preset scanning sequence, the main control unit sequentially configures the logic control signal to the wake-up pin of the current target row, so that the linear Hall chip of the current target row outputs the detection signal to the main control unit through the corresponding signal output pin; While the linear Hall chip of the current target row is collecting data, the linear Hall chip of the next target row is in a waiting state to collect data, so as to reduce the delay when switching rows; When the scanning of the linear Hall chips in n adjacent rows is completed, the main control unit controls the linear Hall chips in n adjacent rows of the current row to re-enter the sleep state, and activates the linear Hall chips in the next group of n adjacent rows, and repeats this cycle to achieve high-speed scanning of alternate rows.

7. The system according to claim 4, characterized in that The medium-speed scanning mode is suitable for power-sensitive scenarios, including: The main control unit controls the state of the sleep pin of the target row so that the linear Hall chip of the target row is in working state, and the linear Hall chips of the remaining rows remain in sleep state; The linear Hall chip of the target row detects the change of the external magnetic field and transmits the detection signal to the main control unit through the corresponding signal output pin; After the data collection of the linear Hall chip of the target row is completed, the main control unit selects to keep the linear Hall chip of the target row working or to put the linear Hall chip of the target row into a dormant state according to system requirements.

8. The system according to claim 1, characterized in that The main control unit includes multiple groups of ports, each group of ports includes: A sleep port, connected to the sleep pins of the linear Hall chips in each row; The wake-up port is respectively connected to the wake-up pins of the linear Hall chip in each row.

9. The system according to claim 1, characterized in that The control system also includes a shift register to achieve row-by-row dynamic control through serial communication; The shift register has a plurality of serial communication input ports and a register output port; The main control unit is provided with a plurality of serial communication output ports and a wake-up port; Each of the serial communication input ports is connected one-to-one to each of the serial communication output ports of the main control unit; each of the registered output ports is connected one-to-one to the sleep pins of each row of the linear Hall chips; and each of the wake-up ports is connected one-to-one to the wake-up pins of each row of the linear Hall chips.

10. The system according to claim 1, characterized in that The detection signal of the linear Hall chip supports analog voltage output or digital signal output to meet the requirements of different data acquisition devices.

11. The system according to claim 1, characterized in that The logic control signal includes one of a level signal, a level inversion signal, a pulse signal, a timing control signal or a data carrier signal.

12. The system according to claim 1, characterized in that The linear Hall chip matrix may adopt a dynamic N×M arrangement, where N and M are any positive integers, to adapt to different signal acquisition requirements.

13. The system according to claim 6, characterized in that The main control unit configures the sleep pin to put the linear Hall chips in n adjacent rows in the linear Hall chip matrix into working mode, where n is any positive integer greater than or equal to 2.

14. The system according to claim 3, characterized in that The main control unit controls multiple linear Hall chip matrices through clock signals to achieve synchronous signal acquisition.

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