High-precision LDO circuit with low noise and high transient enhancement capability

Abstract

The invention relates to a high-precision LDO (Low Dropout Regulator) circuit with low noise and high transient enhancement capability. The LDO circuit comprises an LDO circuit body; the reference voltage generation unit is used for providing reference voltage required by the LDO circuit body during working and comprises a band-gap reference used for generating reference voltage and an accurate low-pass filter used for carrying out anti-noise processing on the reference voltage, and when the anti-noise processing is carried out on the reference voltage, the accurate low-pass filter is used for carrying out anti-noise processing on the reference voltage; the method at least comprises voltage buffering processing and low-pass filtering processing which are carried out in sequence, and corresponding reference buffering voltage is generated after voltage buffering processing is carried out on reference voltage; when low-pass filtering processing is carried out on the generated reference buffer voltage, at least removing power supply noise and / or ground bounce interference of the reference buffer voltage so as to generate a corresponding reference voltage after low-pass filtering processing, and loading the generated reference voltage to the LDO circuit body. The circuit has relatively high anti-noise capability and transient enhancement capability, and the precision and stability of output voltage are improved.

Description

Technical Field

[0001] The invention relates to an LDO circuit, in particular to a high-precision LDO circuit with low noise and high transient enhancement capability. Background Art

[0002] Compared with DC-DC switching regulators, low-dropout linear regulators (LDO) have the characteristics of small area and low voltage ripple. They have been widely used in portable electronic devices to provide high-quality voltage sources for other chips.

[0003] As the manufacturing processes used by various high-performance chips, such as FPGA (Field Programmable Gate Array), CPU (Central Processing Unit) and GPU (Graphics Processing Unit), become more and more advanced (7nm to 3nm) and the frequencies become higher and higher, the requirements for the accuracy, transient performance and stability of the voltage source are also getting higher and higher. For example, the SERDES interface circuit integrated on the mainstream billion-gate FPGA in China has a transmission rate of 32Gbps, the operating voltage of its internal digital circuit is 0.9V, the operating voltage of the analog circuit is 1.2V, the accuracy deviation is required to be less than ±5%, and it has a strong load transient response speed and relatively high noise resistance.

[0004] For LDO circuits, one of the key technologies in design is to achieve high stability and fast transient response under conditions where the load currents vary greatly. Therefore, how to improve the noise immunity and transient enhancement capabilities of LDO circuits and improve the accuracy of power supply provided by LDO circuits are technical problems that need to be solved urgently. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a high-precision LDO circuit with low noise and high transient enhancement capability, which has high anti-noise capability and transient enhancement capability, and improves the accuracy and stability of the output voltage.

[0006] According to the technical solution provided by the present invention, a high-precision LDO circuit with low noise and high transient enhancement capability is provided, and the LDO circuit comprises:

[0007] LDO circuit body;

[0008] The reference voltage generating unit is used to provide the reference voltage required by the LDO circuit body when it is working, including a bandgap reference for generating the reference voltage and a precise low-pass filter for performing anti-noise processing on the reference voltage, wherein:

[0009] When the reference voltage is subjected to noise reduction processing, at least voltage buffering processing and low-pass filtering processing are performed in sequence.

[0010] Performing voltage buffering on the reference voltage to generate a corresponding reference buffer voltage;

[0011] When the generated reference buffer voltage is low-pass filtered, at least power supply noise and / or ground bounce interference of the reference buffer voltage is removed to generate a corresponding reference voltage after low-pass filtering, and the generated reference voltage is loaded into the LDO circuit body.

[0012] The LDO circuit body includes an error amplifier, a drive buffer, a power tube circuit and a voltage feedback circuit, wherein:

[0013] The reference voltage generated by the reference voltage generating unit is loaded onto the in-phase terminal of the error amplifier, the output terminal of the error amplifier is connected to the driving buffer, and the output terminal of the driving buffer is connected to the gate terminal of the power PMOS tube in the power tube circuit, so as to load the driving voltage VG onto the gate terminal of the power PMOS tube through the driving buffer;

[0014] The drain terminal of the power PMOS tube is connected to the voltage feedback circuit to feed back the working sampling voltage to the inverting terminal of the error amplifier through the voltage feedback circuit.

[0015] The combination of the drain end of the power PMOS tube and the voltage feedback circuit forms the circuit body output end of the LDO circuit body.

[0016] Also included is a transient response detection enhancement circuit for transient response detection and enhancement, wherein:

[0017] The transient response detection enhancement circuit is adaptively connected to the circuit body output terminal of the LDO circuit body and the driving buffer to load the output voltage VOUT of the circuit body output terminal and the driving voltage VG to the transient response detection enhancement circuit;

[0018] Based on the output voltage VOUT, the transient response detection enhancement circuit detects the transient response of the LDO circuit body, wherein:

[0019] When the transient response of the LDO circuit body is determined to change, the transient response detection enhancement circuit generates a corresponding transient response enhancement signal, and loads the transient response enhancement signal to the driving buffer, and configures the driving buffer to adjust the output driving voltage VG based on the current transient response enhancement signal, so that the output voltage VOUT of the LDO circuit body remains stable.

[0020] Based on the driving voltage VG adjusted by the driving buffer, the transient response enhancement signal generated by the transient response detection enhancement circuit is regulated so that the transient response enhancement signal generated by the transient response detection enhancement circuit remains stable after transient response enhancement.

[0021] The transient response detection enhancement circuit includes a voltage detection control circuit and a transient response enhancement signal generation circuit adaptively connected to the voltage detection control circuit, wherein:

[0022] The voltage detection and control circuit is used to simultaneously connect the output voltage VOUT and the driving voltage VG;

[0023] The transient response enhancement signal generating circuit generates a transient response enhancement signal and loads the generated transient response enhancement signal to the driving buffer;

[0024] When determining the transient response state based on the output voltage VOUT, the voltage detection and control circuit generates a voltage detection and control signal adapted to the current transient response state, and loads the voltage detection and control signal to the transient response enhancement signal generation circuit, so as to configure the transient response enhancement signal generation circuit to control the generated transient response enhancement signal in the direction of transient response change;

[0025] Based on the driving voltage VG adjusted by the driving buffer, the voltage detection and control circuit generates a voltage detection and control signal adapted to the current driving voltage VG, and loads the voltage detection and control signal to the transient response enhancement signal generation circuit, so as to configure the transient response enhancement signal generation circuit to control the generated transient response enhancement signal in the opposite direction of the driving voltage change;

[0026] When the transient response enhancement signal generated by the transient response enhancement signal generating circuit is regulated, the changing direction of the transient response is consistent with the changing direction of the driving voltage.

[0027] The voltage detection and control circuit includes a PMOS tube P25 and an NMOS tube N21, wherein:

[0028] The source terminal of the PMOS tube P25 is connected to the output voltage VOUT through the resistor R19, the gate terminal of the PMOS tube P25 is connected to the drain terminal of the PMOS tube P25, the drain terminal of the NMOS tube N21 and the gate terminal of the PMOS tube P26, and the source terminal of the NMOS tube N21 is grounded;

[0029] The gate terminal of the NMOS tube N21 is connected to the gate terminal of the NMOS tube N22, the drain terminal of the NMOS tube N22, and the drain terminal of the PMOS tube P26, and the gate terminal of the NMOS tube N21, the gate terminal of the MOS tube N22, the drain terminal of the NMOS tube N22, and the drain terminal of the PMOS tube P26 are connected to each other to form the output connection terminal of the voltage detection and control circuit;

[0030] The source terminal of the PMOS tube P26 is connected to the drain terminal of the PMOS tube P27 through the resistor R20, the gate terminal of the PMOS tube P27 is connected to the driving voltage VG, the source terminal of the PMOS tube P27 is connected to the power supply VDD, and the source terminal of the NMOS tube N22 is grounded;

[0031] The transient response enhancement signal generating circuit includes a PMOS transistor P28, a PMOS transistor P29 and an NMOS transistor N23, wherein:

[0032] The source terminal of the PMOS tube P28 is connected to the power supply VDD, the drain terminal of the PMOS tube P28 is connected to the source terminal of the PMOS tube P29, and the drain terminal of the PMOS tube P29 is connected to the drain terminal of the NMNOS tube N23 to form the output connection terminal of the transient response enhancement signal generating circuit.

[0033] The source terminal of the NMOS tube N23 is grounded, and the gate terminal of the NMOS tube N23 is connected to the output connection terminal of the voltage detection and control circuit;

[0034] The gate terminal of the PMOS transistor P28 is connected to the bias voltage VBP0 , and the gate terminal of the PMOS transistor P29 is connected to the bias voltage VBP1 .

[0035] It also includes a dynamic frequency compensation circuit for frequency compensation of the LDO circuit body, wherein:

[0036] The dynamic frequency compensation circuit includes a Miller structure frequency compensation unit and a load current compensation unit for performing dynamic frequency compensation based on the load current.

[0037] The Miller structure frequency compensation unit is adaptively connected to the output end of the circuit body and the inverting end of the error amplifier, so as to use the Miller structure frequency compensation unit to push the pole of the inverting end of the error amplifier to a low frequency;

[0038] The load current compensation unit includes a frequency compensation variable resistance unit, and the frequency compensation variable resistance unit is adaptively connected to the Miller structure frequency compensation unit, wherein:

[0039] Configuring the resistance value of the frequency compensation variable resistor unit based on the driving voltage VG so that the resistance value of the frequency compensation variable resistor is adapted to the load current;

[0040] After the resistance value of the frequency compensation variable resistor is configured by using the driving voltage VG, loop frequency compensation is performed on the LDO circuit body based on the frequency compensation variable resistor unit and the Miller structure compensation unit.

[0041] The bandgap reference comprises a bandgap operational amplifier circuit and a zero temperature drift reference voltage output unit connected in sequence, wherein:

[0042] The bandgap operational amplifier circuit adopts an operational amplifier circuit capable of gain bootstrapping;

[0043] The zero temperature drift reference voltage output unit includes a zero temperature drift reference voltage generation unit and a reference voltage adjustment unit adaptively connected to the zero temperature drift reference voltage generation unit.

[0044] The zero temperature drift reference voltage generating unit in the zero temperature drift reference voltage output unit is adaptively connected to the bandgap operational amplifier circuit, wherein:

[0045] A reference voltage difference is generated in a zero temperature drift reference voltage generation unit, and the reference voltage difference is converted into a corresponding zero temperature drift basic voltage through a bandgap operational amplifier circuit;

[0046] The reference voltage trimming unit is used to trim the zero temperature drift basic voltage to generate a reference voltage after the trimming process.

[0047] The reference voltage trimming circuit includes a plurality of current trimming units based on current trimming, wherein the current trimming unit includes a current trimming main unit and a trimming reset control signal generating unit adaptively connected to the current trimming main unit;

[0048] When current trimming is performed based on the current trimming unit, pre-trimming is performed using the current trimming main unit first, and post-trimming is performed after the pre-trimming, wherein:

[0049] During pre-adjustment, the pre-adjustment data is loaded into the current adjustment main unit, so that the current adjustment main unit generates a pre-adjustment state signal corresponding to the pre-adjustment data;

[0050] Based on the pre-trim state signal generated by the pre-trim, determining the current trimming target state signal of the current trimming main unit during post-trim, wherein the state of the current trimming target state signal is a trimming effective state or a trimming invalid state;

[0051] During post-adjustment, based on the current adjustment target state signal, the target adjustment data is loaded into the current adjustment main unit, and the current adjustment unit outputs the corresponding current adjustment target state signal, and a dual-mode adjustment state signal is formed based on the current adjustment target state signal, wherein:

[0052] When the state of the current trimming target state signal is a trimming effective state, the polycrystalline fuse in the current trimming main unit is blown by a current blowing method based on the current trimming target state signal and the trimming enable signal in an effective state, so as to lock the current trimming target state signal output by the current trimming main unit after the polycrystalline fuse is blown;

[0053] After the current trimming unit is powered on again, the trimming reset control signal generating unit is used to generate a trimming reset control signal, so that the current trimming main unit configures the generated trimming state signal as a corresponding current trimming target state signal under the trimming reset control signal.

[0054] The precise low-pass filter includes a voltage buffer device for performing a voltage buffering process and a low-pass filter for performing a low-pass filtering process, wherein:

[0055] The voltage buffer includes a PMOS tube P8 receiving a reference voltage, a source terminal of the PMOS tube P8 is connected to a source terminal of the PMOS tube P9 and a drain terminal of the PMOS tube P7, and a source terminal of the PMOS tube P7 is connected to a drain terminal of the PMOS tube P6;

[0056] The drain terminal of the PMOS tube P8 is connected to the drain terminal of the NMOS tube N6, the gate terminal of the NMOS tube N6 and the gate terminal of the NMOS tube N7, the source terminal of the NMOS tube N6 is grounded through the resistor R9, and the source terminal of the NMOS tube N7 is grounded through the resistor R10;

[0057] The drain terminal of the NMOS tube N7 is connected to the drain terminal of the PMOS tube P9 and the gate terminal of the NMOS tube N9. The source terminal of the NMOS tube N9 is grounded through the resistor R11. The drain terminal of the NMOS tube N9 is connected to the source terminal of the NMOS tube N8, the gate terminal of the PMOS tube P10 and the gate terminal of the PMOS tube P12. The drain terminal of the NMOS tube N8 is connected to the drain terminal of the PMOS tube P11. The source terminal of the PMOS tube P11 is connected to the drain terminal of the PMOS tube P10.

[0058] The drain end of the PMOS tube P12 is connected to the source end of the PMOS tube P13, the drain end of the PMOS tube P13 is connected to one end of the resistor R12, the other end of the resistor R12 is adaptively connected to the gate end of the PMOS tube P9, one end of the resistor R13 and the low-pass filter, and the other end of the resistor R13 is adaptively connected to the voltage buffer adjustment unit;

[0059] The source terminal of the PMOS transistor P6 , the source terminal of the PMOS transistor P10 , and the source terminal of the PMOS transistor P12 are all connected to the power source VDD.

[0060] The error amplifier comprises an error amplifier rail-to-rail input stage and an error amplifier high-gain output stage, wherein:

[0061] The error amplifier rail-to-rail input stage receives the reference voltage and is adaptively connected to the driving buffer through the error amplifier high-gain output stage;

[0062] The error amplifier rail-to-rail input stage includes a reference voltage receiving part and a sampling voltage receiving part, the reference voltage is loaded into the reference voltage receiving part, and the working sampling voltage is loaded into the sampling voltage receiving part, wherein:

[0063] The reference voltage receiving unit includes an NMOS tube N12, a PMOS tube P21 and an NMOS tube N14, and the reference voltage is simultaneously loaded to the gate end of the NMOS tube N12, the gate end of the PMOS tube P21 and the gate end of the NMOS tube N14;

[0064] The sampling voltage receiving unit includes an NMOS tube N13, a PMOS tube P22 and an NMOS tube N15, and the working sampling voltage is simultaneously loaded to the gate end of the NMOS tube N13, the gate end of the PMOS tube P22 and the gate end of the NMOS tube N15;

[0065] The drain terminal of the NMOS tube N12, the source terminal of the PMOS tube P21, the source terminal of the PMOS tube P22, and the drain terminal of the NMOS tube N13 are all connected to the drain terminal of the PMOS tube P20, the source terminal of the PMOS tube P20 is connected to the drain terminal of the PMOS tube P19, the source terminal of the PMOS tube P19 is connected to the power supply VDD, and the source terminal of the NMOS tube N12 and the source terminal of the NMOS tube N13 are all grounded;

[0066] The source terminals of the NMOS tube N14 and the NMOS tube N15 are both connected to the drain terminal of the NMOS tube N16, the source terminal of the NMOS tube N16 is connected to the drain terminal of the NMOS tube N17, and the source terminal of the NMOS tube N17 is grounded;

[0067] The drain terminal of the PMOS tube P21 is connected to one end of the resistor R14 in the error amplifier high gain output stage and the source terminal of the PMOS tube P23, the drain terminal of the PMOS tube P22 is connected to one end of the resistor R15 in the error amplifier high gain output stage and the source terminal of the PMOS tube P24, and the other ends of the resistors R14 and R15 are connected to the power supply VDD;

[0068] The drain terminal of the PMOS tube P23 is connected to the drain terminal of the NMOS tube N14, the drain terminal of the NMOS tube N18 in the error amplifier high gain output stage, the gate terminal of the NMOS tube N18, and the gate terminal of the NMOS tube N19 in the error amplifier high gain output stage.

[0069] The drain terminal of the NMOS tube N19 is connected to the drain terminal of the NMOS tube N15, the drain electrode of the PMOS tube P24, and the error amplification frequency compensation unit in the error amplification high gain output stage to form an error amplification output terminal of the error amplifier;

[0070] The source terminal of the NMOS tube N18 is grounded through the resistor R16, and the source terminal of the NMOS tube N19 is grounded through the resistor R17;

[0071] The gate terminal of the PMOS tube P10 is connected to the bias voltage VBP0, the gate terminal of the PMOS tube P20 is connected to the bias voltage VBP1, and the gate terminal of the PMOS tube P23 and the gate terminal of the PMOS tube P24 are both connected to the bias voltage VBP2;

[0072] The gate terminal of the NMOS tube N16 is connected to the bias voltage VBN1, and the gate terminal of the NMOS tube N16 is connected to the bias voltage VBN0.

[0073] The advantages of the present invention are as follows: when the reference voltage generating unit provides a reference voltage, a bandgap reference is used to generate the reference voltage, and an accurate low-pass filter is used to perform anti-noise processing on the reference voltage, so that a high-precision reference voltage can be generated after the anti-noise processing, thereby improving the anti-noise capability of the LDO circuit and the accuracy of the output voltage.

[0074] By using the transient response detection enhancement circuit in conjunction with the driving buffer, transient response detection of the LDO circuit load can be realized, and the transient response of the LDO circuit can be enhanced; frequency compensation can be realized by using the dynamic frequency compensation circuit and the error amplification frequency compensation unit, thereby improving the loop stability and reliability of the LDO circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Figure 1 The figure is a circuit block diagram of an embodiment of the LDO circuit of the present invention.

[0076] Figure 2 The figure is a circuit diagram of an embodiment of the bandgap reference of the present invention.

[0077] Figure 3 The figure is a circuit diagram of an embodiment of the precise low-pass filter of the present invention.

[0078] Figure 4 The figure is a circuit diagram of an embodiment of the error amplifier of the present invention.

[0079] Figure 5 The schematic diagram of a transient response detection enhancement circuit according to an embodiment of the present invention is shown in FIG.

[0080] Figure 6 The figure is a circuit diagram of an embodiment of a driving buffer of the present invention.

[0081] Figure 7 The following is a circuit diagram of an embodiment of a dynamic frequency compensation circuit of the present invention.

[0082] Figure 8 The schematic diagram of a circuit of a reference voltage trimming unit according to an embodiment of the present invention is shown in FIG.

[0083] Fig. 9 A schematic diagram of an embodiment of an equivalent small signal model of an LDO circuit of the present invention. DETAILED DESCRIPTION

[0084] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0085] In order to have a higher anti-noise capability and improve the accuracy of the output voltage, the present invention provides a high-precision LDO circuit with low noise and high transient enhancement capability. Specifically, the LDO circuit includes:

[0086] LDO circuit body;

[0087] The reference voltage generating unit is used to provide the reference voltage required by the LDO circuit body when it is working, including a bandgap reference for generating the reference voltage and a precise low-pass filter for performing anti-noise processing on the reference voltage, wherein:

[0088] When the reference voltage is subjected to noise reduction processing, at least voltage buffering processing and low-pass filtering processing are performed in sequence.

[0089] Performing voltage buffering on the reference voltage to generate a corresponding reference buffer voltage;

[0090] When the generated reference buffer voltage is low-pass filtered, at least power supply noise and / or ground bounce interference of the reference buffer voltage is removed to generate a corresponding reference voltage after low-pass filtering, and the generated reference voltage is loaded into the LDO circuit body.

[0091] It can be understood that the LDO circuit should include an LDO circuit body, which is a functional circuit that can realize the LDO circuit, that is, the LDO circuit body can provide a stable voltage. The LDO circuit body can adopt the existing commonly used LDO circuit form, which can be selected according to needs and will not be repeated here.

[0092] Noise is an important performance parameter of LDO circuits, which mainly comes from the interference of external power supply and ground wire and thermal noise and flicker noise generated by internal devices. Generally, PSRR (Power Supply Rejection Ratio) and SND (Spectral Noise Density) can be used to measure the noise state of LDO circuits.

[0093] Generally, the thermal noise and flicker noise of the LDO circuit are mainly affected by the reference voltage. In order to improve the anti-noise capability of the LDO circuit and reduce the noise of the reference voltage, the reference voltage provided by the present invention should be subjected to anti-noise processing. Specifically, when the reference voltage is provided by the reference voltage generation unit, the reference voltage should be subjected to anti-noise processing. The reference voltage generation unit may include a bandgap reference and a precise low-pass filter. Figure 1 An embodiment of a reference voltage generating unit is shown in FIG. In the figure, BG (Band Gap) is a band gap reference, and PLPF (Precision Low pass Filter) is a precision low pass filter. At this time, the band gap reference can generate a reference voltage, and the precision low pass filter can be used to perform anti-noise processing on the reference voltage, and generate a reference voltage after the anti-noise processing. Figure 1 In the figure, VBG is the base voltage and VREF is the reference voltage.

[0094] When the precise low-pass filter performs anti-noise processing on the reference voltage, at least voltage buffering processing and low-pass filtering processing are performed. Specifically, the reference voltage is subjected to voltage buffering processing, and a reference buffer voltage can be generated after the voltage buffering processing. Thereafter, the reference buffer voltage is subjected to low-pass filtering processing. Through the low-pass filtering processing, the power supply noise and / or ground bounce interference in the reference buffer voltage can be removed. As can be seen from the above description, the anti-noise capability of the LDO circuit can be improved, and the accuracy of the output voltage of the LDO circuit can be improved.

[0095] In one embodiment of the present invention, the bandgap reference comprises a bandgap operational amplifier circuit and a zero temperature drift reference voltage output unit connected in sequence, wherein:

[0096] The bandgap operational amplifier circuit adopts an operational amplifier circuit capable of gain bootstrapping;

[0097] The zero temperature drift reference voltage output unit includes a zero temperature drift reference voltage generation unit and a reference voltage adjustment unit adaptively connected to the zero temperature drift reference voltage generation unit.

[0098] The zero temperature drift reference voltage generating unit in the zero temperature drift reference voltage output unit is adaptively connected to the bandgap operational amplifier circuit, wherein:

[0099] A reference voltage difference is generated in a zero temperature drift reference voltage generation unit, and the reference voltage difference is converted into a corresponding zero temperature drift basic voltage through a bandgap operational amplifier circuit;

[0100] The reference voltage trimming unit is used to trim the zero temperature drift basic voltage to generate a reference voltage after the trimming process.

[0101] In order to provide an accurate reference voltage, the bandgap reference may include a bandgap operational amplifier circuit and a zero temperature drift reference voltage output unit. Specifically, the bandgap operational amplifier circuit may adopt a gain-bootstrapped operational amplifier circuit, and the zero temperature drift reference voltage output unit may include a zero temperature drift reference voltage generation unit and a reference voltage adjustment unit. The bandgap operational amplifier circuit cooperates with the zero temperature drift reference voltage generation unit to generate a zero temperature drift basic voltage. Thereafter, the zero temperature drift basic voltage is adjusted using the reference voltage adjustment unit to generate a reference voltage after the adjustment process. At this time, a more accurate reference voltage can be provided.

[0102] Figure 2 A circuit schematic diagram of an embodiment of a bandgap reference is provided in FIG. Figure 2 In the embodiment, the bandgap operational amplifier circuit may include a gain bootstrap unit, an operational amplifier second-stage unit, and an operational amplifier first-stage unit, the gain bootstrap unit is connected to the operational amplifier second-stage unit, the operational amplifier second-stage unit is connected to the operational amplifier first-stage unit, and the operational amplifier first-stage unit is connected to the zero temperature drift reference voltage generating unit. Figure 2 Explain the specifics of the bandgap operational amplifier circuit

[0103] Figure 2 In the embodiment, the gain bootstrap unit includes a PMOS tube P0, an NMOS tube N0, an NMOS tube N1 and a resistor R0, wherein the source terminal of the PMOS tube P0 is connected to the power supply VDD, the drain terminal of the PMOS tube P0 is connected to the drain terminal of the NMOS tube N0, the gate terminal of the NMOS tube N0, the gate terminal of the NMOS tube N1, the NMOS tube N2 and the gate terminal of the NMOS tube N2 in the second-stage unit of the operational amplifier, the drain terminal of the NMOS tube N1 is connected to the source terminal of the NMOS tube N0, and the source terminal of the NMOS tube is grounded through the resistor R0.

[0104] The second-stage unit of the operational amplifier includes a PMOS tube P1, an NMOS tube N2, an NMOS tube N3 and a resistor R1, wherein the source terminal of the PMOS tube P1 is connected to the voltage VDD, the gate terminal of the PMOS tube P1 is connected to the gate terminal of the PMOS tube P0, the drain terminal of the PMOS tube P1 and the drain terminal of the NMOS tube N2, the source terminal of the NMOS tube N2 is connected to the drain terminal of the NMOS tube N3, and the source terminal of the NMOS tube N3 is grounded through the resistor R1.

[0105] The first-stage unit of the operational amplifier includes a PMOS tube P2, a PMOS tube P3 and a PMOS tube P4, wherein a source terminal of the PMOS tube P2 is connected to a power supply VDD, a gate terminal of the PMOS tube P2 is connected to a gate terminal of the PMOS tube P1 and a gate terminal of the PMOS tube P0, a source terminal of the PMOS tube P2, a source terminal of the PMOS tube P3 and a source terminal of the PMOS tube P4 are connected, a drain terminal of the PMOS tube P3 is connected to a gate terminal of the NMOS tube N3 and a drain terminal of the NMOS tube N4 in the first-stage unit of the operational amplifier, a drain terminal of the PMOS tube P4 is connected to a gate terminal of the NMOS tube N4, a gate terminal of the NMOS tube N5 in the first-stage unit of the operational amplifier and a drain terminal of the NMOS tube N5, a source terminal of the NMOS tube N4 is grounded through a resistor R2, and a source terminal of the NMOS tube N5 is grounded through a resistor R3.

[0106] For the above-mentioned operational amplifier second-stage unit and operational amplifier first-stage unit, the output end of the operational amplifier first-stage unit is formed by connecting the drain end of the PMOS tube P3 and the drain end of the NMOS tube N4 to each other, and the output end of the operational amplifier second-stage unit is formed by connecting the gate end of the PMOS tube P1 and the drain end of the PMOS tube P1 and the drain end of the NMOS tube N2 to each other. Figure 2 In the figure, OP_O1 is the output terminal of the first stage unit of the operational amplifier, and OP_O2 is the output terminal of the second stage unit of the operational amplifier. When the bandgap operational amplifier circuit is formed by the above-mentioned gain bootstrap unit, the first stage unit of the operational amplifier, and the second stage unit of the operational amplifier, the bandgap operational amplifier circuit can have the characteristics of high gain, fast response and wide bandwidth.

[0107] Figure 2 In the embodiment, the zero temperature drift reference voltage generating unit includes a PMOS transistor P5, a resistor R4, a resistor R5, a resistor R7, a PNP transistor Q0 and a PNP transistor Q1, wherein the source terminal of the PMOS transistor P5 is connected to the power supply VDD, the gate terminal of the PMOS transistor P5 is connected to the gate terminal of the PMOS transistor P2, the drain terminal of the PMOS transistor P5 is connected to one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected to the gate terminal of the PMOS transistor P3 and one end of the resistor R7, and the other end of the resistor R5 is connected to the gate terminal of the PMOS transistor P4 and the emitter terminal of the PNP transistor Q1;

[0108] The other end of the resistor R7 is connected to the emitter terminal of the PNP transistor Q0 , and the base terminal of the PNP transistor Q0 , the base terminal of the PNP transistor Q1 , the collector terminal of the PNP transistor Q0 , and the collector terminal of the PNP transistor Q1 are all grounded.

[0109] Depend on Figure 2It can be seen that the gate end of the PMOS tube P3 and the gate end of the PMOS tube P4 form two differential input ends of the bandgap operational amplifier circuit, and the drain end of the PMOS tube P5 is connected to the resistor R4 and the resistor R5 to form a zero temperature drift basic voltage output end, which can be connected to the reference voltage adjustment unit through the zero temperature drift basic voltage output end.

[0110] Specifically, the PNP transistor Q0 and the PNP transistor Q1 should be configured with different areas. When the bandgap reference is working, the corresponding currents flowing through the PNP transistor Q0 and the PNP transistor Q1 are the same. It is assumed that the layout area of ​​the PNP transistor Q1 is N times the layout area of ​​the PNP transistor Q0. At this time, the voltages at the two differential input terminals of the bandgap operational amplifier circuit are equal, so that the voltage difference between the corresponding BE ends of the PNP transistor Q0 and the PNP transistor Q1 is equal to the voltage difference across the resistor R7. The voltage difference is called △VBE, wherein the voltage difference △VBE across the NPN transistor Q0 and the PNP transistor Q1 is VT*lnN, that is, a reference voltage difference can be generated in the zero temperature drift reference voltage generation unit through the PNP transistor Q0 and the PNP transistor, and the generated reference voltage difference is ΔVBE=VT*lnN, wherein VT is the thermal voltage, and the thermal voltage represents the positive temperature coefficient.

[0111] From the above description, it can be seen that after the two differential input terminals of the bandgap operational amplifier circuit are connected to the zero temperature drift reference voltage generating unit, since the voltages of the two differential input terminals of the bandgap operational amplifier circuit should be equal, the current flowing through the resistor R7 is: I R7 =ΔVBE / R7=(VT*lnN) / R7, and further, the voltage at the zero temperature drift basic voltage output end is: VBB=VBE_Q0+(R4+R7)*(VT*lnN) / R7, wherein VBB is the zero temperature drift basic voltage at the zero temperature drift basic voltage output end, VBE_Q0 is the negative temperature coefficient, and VT is the thermal voltage.

[0112] It should be noted that the negative temperature coefficient VBE_Q0 is different from the temperature coefficient of the thermal voltage VT. Generally, the positive temperature coefficient of the thermal voltage VT is about 0.087mV / °K, and the negative temperature coefficient VBE_Q0 is about -1.5mV / °K. After adjustment by the reference voltage adjustment circuit, the negative temperature coefficient VBE_Q0 can be modulated to be equal to the corresponding positive temperature coefficient of the thermal voltage VT. Thereafter, the voltage with the positive temperature coefficient and the voltage with the negative temperature coefficient are superimposed to obtain a voltage with zero temperature drift, thereby generating a basic voltage with zero temperature drift.

[0113] After obtaining the zero temperature drift basic voltage, the reference voltage trimming unit can be used to trim the zero temperature drift basic voltage to generate a reference voltage after the trimming process. Figure 2In the embodiment, the reference voltage trimming unit includes a resistor R6, a resistor R8 and a reference voltage trimming circuit, wherein one end of the resistor R6 is connected to the zero temperature drift basic voltage output end, the other end of the resistor R6 is connected to one end of the resistor R8, the other end of the resistor R8 is grounded through the reference voltage trimming circuit, and the resistor R6 and the resistor R8 are connected to each other to form a bandgap reference output end of the bandgap reference, and the reference voltage VBG can be output through the bandgap reference output end. Figure 2 X0 in the figure is a reference voltage trimming circuit, through which the zero temperature drift basic voltage VBB can be trimmed. The following is an example of how and how the reference voltage trimming circuit trims the zero temperature drift basic voltage VBB.

[0114] In one embodiment of the present invention, the reference voltage trimming circuit includes a plurality of current trimming units based on current trimming, wherein the current trimming unit includes a current trimming main unit and a trimming reset control signal generating unit adaptively connected to the current trimming main unit;

[0115] When current trimming is performed based on the current trimming unit, pre-trimming is performed using the current trimming main unit first, and post-trimming is performed after the pre-trimming, wherein:

[0116] During pre-adjustment, the pre-adjustment data is loaded into the current adjustment main unit, so that the current adjustment main unit generates a pre-adjustment state signal corresponding to the pre-adjustment data;

[0117] Based on the pre-trim state signal generated by the pre-trim, determining the current trimming target state signal of the current trimming main unit during post-trim, wherein the state of the current trimming target state signal is a trimming effective state or a trimming invalid state;

[0118] During post-adjustment, based on the current adjustment target state signal, the target adjustment data is loaded into the current adjustment main unit, and the current adjustment unit outputs the corresponding current adjustment target state signal, and a dual-mode adjustment state signal is formed based on the current adjustment target state signal, wherein:

[0119] When the state of the current trimming target state signal is a trimming effective state, the polycrystalline fuse in the current trimming main unit is blown by a current blowing method based on the current trimming target state signal and the trimming enable signal in an effective state, so as to lock the current trimming target state signal output by the current trimming main unit after the polycrystalline fuse is blown;

[0120] After the current trimming unit is powered on again, the trimming reset control signal generating unit is used to generate a trimming reset control signal, so that the current trimming main unit configures the generated trimming state signal as a corresponding current trimming target state signal under the trimming reset control signal.

[0121] Specifically, the current trimming unit may include a current trimming main unit and a trimming reset control signal generating unit, wherein the current trimming function can be realized by using the current trimming main unit, and the output state of the current trimming main unit can be reset after power is turned on again by using the trimming reset control signal generating unit.

[0122] Figure 8 , a circuit schematic diagram of an embodiment of a current trimming main unit is shown in FIG. In the figure, the current trimming main unit includes a DFF trigger, DFF0 is a DFF trigger, and the DFF trigger has a data terminal, a clock terminal, a set terminal, and a reset terminal. Figure 8 In the figure, D is the data terminal of the DFF trigger, CLK is the clock terminal of the DFF trigger, SEB is the reset terminal, and RSB is the reset terminal. The DFF trigger can use the existing commonly used D trigger. The data loaded to the data terminal can be output by using the clock signal CLK loaded to the clock terminal. Figure 8 In the figure, the Q terminal is the output terminal of the DFF trigger.

[0123] Specifically, the data loaded to the data terminal of the DFF trigger is generally "1" or "0". When the data loaded to the data terminal is "1", a high level can be obtained at the Q terminal of the DFF trigger under the clock signal CLK. When the data loaded to the data terminal is "0", a low level can be obtained at the Q terminal of the DFF trigger under the clock signal CLK. In addition, the reset terminal and the set terminal of the DFF trigger are both low-level valid. If the level loaded to the set terminal is a low level, the Q terminal output of the DFF trigger is set. When the level loaded to the reset terminal is a low level, the Q terminal output of the DFF trigger is reset. Generally, when the DFF trigger is set, the Q terminal of the DFF trigger is a high level. When the DFF trigger is reset, the Q terminal of the DFF trigger is a low level.

[0124] It should be noted that the method of using the reference voltage trimming circuit for trimming processing can be consistent with the prior art. For example, a number of trimming resistors connected in series should be set in the reference voltage trimming unit, and each trimming resistor corresponds to a trimming power tube. The trimming power tube can use a commonly used NOMS tube. At this time, the drain terminal and source terminal of the trimming power tube are connected to the two ends of a corresponding trimming resistor, and the gate terminal of the trimming power tube is connected to a current trimming unit. Among them, correspondingly connected to the trimming current unit specifically refers to connecting the gate terminal of the trimming power tube to the Q terminal of the DFF trigger. When trimming is performed, the Q terminal of the DFF trigger should be a high level so that the NMOS tube can be controlled to be turned on at a high level. The turned-on NMOS tube can be used to short-circuit the corresponding trimming resistor, so as to achieve the purpose of adjusting the resistance value in the reference voltage trimming unit. When the current trimming resistor is not needed to be trimmed, the Q terminal of the DFF trigger in the corresponding current trimming unit should be a low level. At this time, the NMOS tube is in a turned-off state, and the trimming resistor corresponding to the turned-off state will not be short-circuited.

[0125] Based on the above description, it can be known that when a DFF trigger is provided in the current trimming main unit, the DFF trigger can be used to implement pre-trim and post-trim. During pre-trim, the pre-trim data is loaded into the data terminal of the DFF trigger. Thereafter, under the action of the clock signal CLK, a corresponding pre-trim status signal can be obtained at the Q terminal of the DFF trigger. It can be known from the above description that the pre-trim status signal is a high level state or a low level state.

[0126] As can be seen from the above description, when the pre-adjustment state signal is at a high level, the NMOS tube can be driven to conduct, thereby realizing a short circuit of the corresponding adjustment resistor. Therefore, during pre-adjustment, the same adjustment operation can be performed on one or more current adjustment units to adjust the resistance value of the resistor in the reference voltage adjustment unit using the pre-adjustment state signal, and after measurement, it can be determined whether it matches the expected resistance value. Since only the pre-adjustment data in each current adjustment main unit needs to be adjusted to adjust the corresponding pre-adjustment state signal, the operation is simple during pre-adjustment, and the adjustment accuracy can be improved.

[0127] After pre-adjustment, the current adjustment target state signal of each current adjustment main unit can be determined, wherein the current adjustment target state signal is the level state of the Q-end output of the DFF trigger in each current adjustment main unit. As can be seen from the above description, the state of the current adjustment target state signal is an adjustment valid state or an adjustment invalid state. As can be seen from the above description, when the current adjustment target state signal is at a high level, it is an adjustment valid state, and when the current adjustment target signal is at a low level, it is an adjustment invalid state. After the current adjustment target state signal of each current adjustment main unit is determined, the corresponding target adjustment data can be loaded at the data end of the corresponding DFF trigger. For example, when the current adjustment target state signal is at a high level, the target adjustment data should be "1".

[0128] It should be noted that when the current trimming target state signal of the current trimming main unit is in the trimming effective state, the current trimming target state signal output by the current trimming main unit should be locked so as to maintain the current trimming state in subsequent work, such as in the above-described embodiment, the driving NMOS tube can be kept in the on state. In one embodiment of the present invention, based on the current trimming target state signal and the trimming enable signal in the effective state, the polycrystalline fuse in the current trimming main unit is blown by current fusing, so as to achieve the locking of the current trimming target state signal output by the current trimming main unit after the polycrystalline fuse is blown.

[0129] Figure 8 In the figure, Rfuse-poly is the polycrystalline fuse, ENB-PGM is the trimming enable signal, and the trimming enable signal is generally valid at a low level. When the polycrystalline fuse is blown by current blowing using an effective current path, a fuse blowing voltage should also be added to the second end of the polycrystalline fuse. Figure 8 In the figure, Vf is the fuse breaking voltage. Figure 8 In the embodiment, the first end of the polycrystalline fuse can be connected to the fuse blowing voltage, the second end of the polycrystalline fuse is connected to the drain end of the NMOS tube N100, the source end of the NOMS tube N100 is connected, the gate end of the NOMS tube N100 is connected to the output end of the NOR gate NOR0, the first input end of the NOR gate NOR0 receives the trimming enable signal, the second input end of the NOR gate NOR0 is connected to the output end of the inverter INV0, and the input end of the inverter INV0 is connected to the Q end of the DFF trigger. When the Q end of the DFF trigger is at a high level and the trimming enable signal is at a low level, the NMOS tube N100 can be turned on. When the NMOS tube N100 is turned on, a loop of the fuse blowing voltage-polycrystalline fuse-NMOS tube N100 to the ground can be formed. The formed loop can be used as an effective current path. Thereafter, the fuse is blown by the current flowing through the polycrystalline fuse.

[0130] It is understandable that the bandgap reference will have a power-off state. When the power is restored, the Q end of the DFF trigger should be restored to the current trimming target state signal after the trimming. For example, when the current trimming target state signal is in the trimming effective state, the Q end of the DFF trigger should be high level after the power is restored. When restoring the output state of the Q end of the DFF trigger, it should be based on the blown state of the polycrystalline fuse to avoid false recovery.

[0131] In order to reset the output of the DFF trigger, the current trimming main unit should include a reset signal generating unit. Figure 8 In the embodiment, the reset position signal generating unit includes a PMOS tube P101 and a Schmitt trigger, wherein:

[0132] The source terminal of the PMOS tube P101 is connected to the power supply VDD, the gate terminal of the PMOS tube P101 is connected to the preload control signal RE-LOAD, and is connected to one end of the NAND gate NAND0 and one end of the NAND gate NAND1, and the drain terminal of the PMOS tube P101 is connected to the drain terminal of the PMOS tube P100, the drain terminal of the NMOS tube N101, and the input terminal of the Schmitt trigger;

[0133] The output end of the Schmitt trigger is connected to the other end of the NAND gate NAND0 and the input end of the inverter INV1, and the output end of the inverter INV1 is connected to the other end of the NAND gate NAND1;

[0134] The output end of the NAND gate NAND0 is connected to the set end of the DFF flip-flop, and the output end of the NAND gate NAND1 is connected to the reset end of the DFF flip-flop.

[0135] Figure 8 In the above, SMIT-TRIGO is a Schmitt trigger, which can be in the form of an existing commonly used one, and can be used to remove burrs from the level. Figure 8 It can be seen from the reset position signal generating unit in that when the preload control signal RE-LOAD is in an invalid state of low level, the NAND gate NAND0 and the NAND gate NAND1 output a high level. At this time, the set drive signal at the set end of the DFF trigger is high level, and the reset drive signal at the reset end of the DFF trigger is also high level. From the above description, it can be seen that the DFF trigger currently has neither a set operation nor a reset operation. In specific implementation, the reset position signal may include a reset drive signal and a set drive signal. At this time, the reset drive signal is loaded to the reset end of the DFF trigger, and the set drive signal is loaded to the set end of the DFF trigger.

[0136] When the preload control signal RE-LOAD is at a high level, the PMOS tube P101 is in an off state, and the input voltage of the Schmitt trigger is only related to the voltage at the drain end of the PMOS tube P100. For example, when the voltage at the drain end of the PMOS tube P100 is at a high level, the set drive signal outputted by the NAND gate NAND0 is a low level signal, and the reset drive signal outputted by the NAND gate NAND1 is a high level. At this time, the DFF trigger is set, and the Q end of the DFF trigger is a current trimming target state signal of a trimming effective state; when the voltage at the drain end of the PMOS tube P100 is at a low level, the set drive signal outputted by the NAND gate NAND0 is a high level signal, and the reset drive signal outputted by the NAND gate NAND1 is a low level. At this time, the DFF trigger is reset, and the Q end of the DFF trigger is a current trimming target state signal of a trimming invalid state.

[0137] It can be seen from the above description that the trimming reset control signal includes a preload control signal RE-LOAD, a low level detection control signal CFG-N and a high level detection control signal CFG-P. The trimming reset control signal is generated by a trimming reset control signal generating unit. It can be understood that when the current trimming main unit is pre-trim and post-trim, the preload control signal RE-LOAD, the low level detection control signal CFG-N and the high level detection control signal CFG-P should all be in an invalid level state. When the current trimming unit is powered on again, the high level detection control signal CFG-P and the low level detection control signal CFG-N are immediately in a valid level state, and the preload control signal RE-LOAD is delayed to enter the valid level state.

[0138] When the preload control signal RE-LOAD and the low level detection control signal CFG-N are high level valid, and the high level detection control signal CFG-P is low level valid, the reset position signal generation unit also includes an NMOS tube N101, an NMOS tube N102 and a PMOS tube P100, the source end of the NMOS tube N102 is grounded, the drain end of the NMOS tube N102 is connected to the source end of the NMOS tube N101, the drain end of the NMOS tube N101 is connected to the drain end of the PMOS tube P100 and the reset position signal generation unit, and the source end of the PMOS tube P100 is connected to the second end of the polycrystalline fuse.

[0139] The gate terminal of the NMOS transistor N101 is connected to the low level detection control signal CFG-N, the gate terminal of the NMOS transistor N1022 is connected to the preload control signal RE-LOAD, and the gate terminal of the PMOS transistor P100 is connected to the high level detection control signal CFG-P.

[0140] When the high level detection control signal CFG-P is at a low level, the PMOS tube P100 is in a conducting state, and when the low level detection control signal CFG-N is at a high level, the NMOS tube N102 is in a conducting state. When the preload control signal RE-LOAD is at a low level, the NMOS tube N101 is in a shut-off state, and when the preload control signal RE-LOAD is at a high level, the NMOS tube N101 is in a conducting state.

[0141] When power is turned on again, the fuse blowing voltage is also loaded to the first end of the polycrystalline fuse at the same time. When working normally, the fuse blowing voltage needs to be removed. In the power-on again stage, the voltage value of the fuse blowing voltage can be lower than the voltage value in the polycrystalline fuse blowing stage. In addition, in the pre-adjustment stage, the fuse blowing voltage does not need to be added to the first end of the polycrystalline fuse. In the post-adjustment stage, the fuse blowing voltage is loaded to the first end of the polycrystalline fuse.

[0142] It can be understood that when the NMOS tube N101, the NMOS tube N102 and the PMOS tube P00 are all turned on and the fuse level state signal is obtained, then: when the polycrystalline fuse is not blown, the drain end of the PMOS tube P100 forms a path to the ground through the NMOS tube N101 and the NMOS tube N102, and the voltage at the drain end of the PMOS tube P100 is 0 level; when the polycrystalline fuse is in a blown state, when the drain end of the PMOS tube P100 is pulled up to the blown voltage by the blown voltage, at this time, the voltage at the drain end of the PMOS tube P100 is a high level.

[0143] In a specific implementation, a corresponding reset drive signal and a set drive signal can be generated according to the fuse level state, thereby realizing the set drive or reset drive of the DFF trigger according to the blowing state of the polycrystalline fuse, so that the output of the DFF trigger can be configured as the corresponding current trimming target state signal.

[0144] In one embodiment of the present invention, the LDO circuit body includes an error amplifier, a drive buffer, a power tube circuit and a voltage feedback circuit, wherein:

[0145] The reference voltage generated by the reference voltage generating unit is loaded onto the in-phase terminal of the error amplifier, the output terminal of the error amplifier is connected to the driving buffer, and the output terminal of the driving buffer is connected to the gate terminal of the power PMOS tube in the power tube circuit, so as to load the driving voltage VG onto the gate terminal of the power PMOS tube through the driving buffer;

[0146] The drain terminal of the power PMOS tube is connected to the voltage feedback circuit to feed back the working sampling voltage to the inverting terminal of the error amplifier through the voltage feedback circuit.

[0147] The combination of the drain end of the power PMOS tube and the voltage feedback circuit forms the circuit body output end of the LDO circuit body.

[0148] Figure 1 An embodiment of the LDO circuit body is shown in FIG. In the figure, the LDO circuit body may include an error amplifier, a driver buffer, a power tube circuit and a voltage feedback circuit. In the figure, EA (Error Amplifier) ​​is the error amplifier, DB (Driver Buf) is the driver buffer, Figure 1 The Power-MOS in the circuit is the power tube circuit. Figure 1 FIG. 2 shows an embodiment in which a power PMOS tube is used in a power tube circuit. Figure 1In the figure, P33 is the power PMOS tube. In the LDO circuit, the power PMOS tube can provide ampere-level current. Therefore, the size of the power PMOS tube is relatively large, occupying about half of the entire LDO circuit layout area. The driver buffer can load the driving voltage VG to the gate end of the power PMOS tube. It can be seen that the driving voltage VG can be used to control the conduction state of the power PMOS tube.

[0149] In order to improve the working stability of the LDO circuit, a voltage feedback circuit should be configured to form a negative feedback loop. Figure 1 The voltage feedback circuit includes a resistor R FB0 , resistor R FB1 And resistor R24, where resistor R FB0 One end is connected to the drain end of the power PMOS tube, and the resistor R FB0 The other end of the resistor R FB1 and one end of resistor R24, resistor R FB1 The other end of the resistor R24 ​​is connected to the inverting terminal of the error amplifier. Figure 1 In the figure, it is also shown that the drain end of the power PMOS tube passes through the capacitor C L An embodiment of grounding, in this case, the capacitor C L Represented as a load connected to the drain end of the power PMOS tube.

[0150] right Figure 1 The LDO circuit shown in the figure is analyzed from the perspective of the entire loop. Since the error amplifier has the characteristics of an operational amplifier, the reference voltage loaded to the in-phase terminal of the error amplifier should be equal to the working sampling voltage, VREF = VSENSE = VOUT*R FB1 / (R FB0 +R FB1 ), it can be deduced that the output voltage VOUT of the LDO circuit should be VREF*(R FB0 +R FB1 ) / R FB1 .

[0151] In one embodiment of the present invention, a transient response detection enhancement circuit for transient response detection and enhancement is also included, wherein:

[0152] The transient response detection enhancement circuit is adaptively connected to the circuit body output terminal of the LDO circuit body and the driving buffer to load the output voltage VOUT of the circuit body output terminal and the driving voltage VG to the transient response detection enhancement circuit;

[0153] Based on the output voltage VOUT, the transient response detection enhancement circuit detects the transient response of the LDO circuit body, wherein:

[0154] When the transient response of the LDO circuit body is determined to change, the transient response detection enhancement circuit generates a corresponding transient response enhancement signal, and loads the transient response enhancement signal to the driving buffer, and configures the driving buffer to adjust the output driving voltage VG based on the current transient response enhancement signal, so that the output voltage VOUT of the LDO circuit body remains stable.

[0155] Based on the driving voltage VG adjusted by the driving buffer, the transient response enhancement signal generated by the transient response detection enhancement circuit is regulated so that the transient response enhancement signal generated by the transient response detection enhancement circuit remains stable after transient response enhancement.

[0156] Specifically, the transient response of the LDO circuit mainly includes two parts: load transient response and linear transient response. The load transient response is affected by many factors, such as the quiescent current of the LDO circuit, the transient load current change time, etc. In order to enhance the transient response of the LDO circuit, a transient response detection enhancement circuit can be provided, such as Figure 1 middle, Figure 1 In the figure, TDAE (T ransient Detection And Enhancement) is a transient response detection enhancement circuit. In the figure, the transient response detection enhancement circuit is adapted to be connected to the circuit body output end of the LDO circuit body and the driving buffer to form a negative feedback closed loop with the driving buffer, and the formed loop is located in the inner circle of the loop formed by the voltage feedback circuit.

[0157] When performing transient response enhancement, the transient response change is first determined based on the output voltage VOUT of the LDO circuit body, and then the transient response detection enhancement circuit adjusts the output transient response enhancement signal to use the current transient response enhancement signal to adjust the driving voltage VG output by the driving buffer, so as to use the driving voltage VG to adjust the driving state of the power PMOS tube. When the driving state of the power PMOS changes, the transient response enhancement signal of the transient response detection enhancement circuit is further adjusted. At this time, the transient response of the transient response detection enhancement circuit is adjusted to reset the transient response enhancement signal, that is, to restore to the state before the transient response of the LDO circuit body changes, so that the transient response enhancement signal remains stable after the transient response enhancement; at the same time, the output voltage VOUT of the LDO circuit body also remains stable, thereby improving the load transient response of the LDO circuit and the stability and reliability of the operation of the LDO circuit body.

[0158] In one embodiment of the present invention, the transient response detection enhancement circuit includes a voltage detection control circuit and a transient response enhancement signal generating circuit adaptively connected to the voltage detection control circuit, wherein:

[0159] The voltage detection and control circuit is used to simultaneously connect the output voltage VOUT and the driving voltage VG;

[0160] The transient response enhancement signal generating circuit generates a transient response enhancement signal and loads the generated transient response enhancement signal to the driving buffer;

[0161] When determining the transient response state based on the output voltage VOUT, the voltage detection and control circuit generates a voltage detection and control signal adapted to the current transient response state, and loads the voltage detection and control signal to the transient response enhancement signal generation circuit, so as to configure the transient response enhancement signal generation circuit to control the generated transient response enhancement signal in the direction of transient response change;

[0162] Based on the driving voltage VG adjusted by the driving buffer, the voltage detection and control circuit generates a voltage detection and control signal adapted to the current driving voltage VG, and loads the voltage detection and control signal to the transient response enhancement signal generation circuit, so as to configure the transient response enhancement signal generation circuit to control the generated transient response enhancement signal in the opposite direction of the driving voltage change;

[0163] When the transient response enhancement signal generated by the transient response enhancement signal generating circuit is regulated, the changing direction of the transient response is consistent with the changing direction of the driving voltage.

[0164] Specifically, a voltage detection and control circuit is used to receive the output voltage VOUT and the driving voltage VG. The voltage detection and control circuit can generate a voltage detection control signal according to the output voltage VOUT and the driving voltage VG, so as to regulate the transient response enhancement signal generated by the transient response enhancement signal generating circuit according to the voltage detection control signal, thereby achieving the enhancement of transient response.

[0165] In one embodiment of the present invention, the voltage detection and control circuit includes a PMOS transistor P25 and an NMOS transistor N21, wherein:

[0166] The source terminal of the PMOS tube P25 is connected to the output voltage VOUT through the resistor R19, the gate terminal of the PMOS tube P25 is connected to the drain terminal of the PMOS tube P25, the drain terminal of the NMOS tube N21 and the gate terminal of the PMOS tube P26, and the source terminal of the NMOS tube N21 is grounded;

[0167] The gate terminal of the NMOS tube N21 is connected to the gate terminal of the NMOS tube N22, the drain terminal of the NMOS tube N22, and the drain terminal of the PMOS tube P26, and the gate terminal of the NMOS tube N21, the gate terminal of the MOS tube N22, the drain terminal of the NMOS tube N22, and the drain terminal of the PMOS tube P26 are connected to each other to form the output connection terminal of the voltage detection and control circuit;

[0168] The source terminal of the PMOS tube P26 is connected to the drain terminal of the PMOS tube P27 through the resistor R20, the gate terminal of the PMOS tube P27 is connected to the driving voltage VG, the source terminal of the PMOS tube P27 is connected to the power supply VDD, and the source terminal of the NMOS tube N22 is grounded;

[0169] The transient response enhancement signal generating circuit includes a PMOS transistor P28, a PMOS transistor P29 and an NMOS transistor N23, wherein:

[0170] The source terminal of the PMOS tube P28 is connected to the power supply VDD, the drain terminal of the PMOS tube P28 is connected to the source terminal of the PMOS tube P29, and the drain terminal of the PMOS tube P29 is connected to the drain terminal of the NMNOS tube N23 to form the output connection terminal of the transient response enhancement signal generating circuit.

[0171] The source terminal of the NMOS tube N23 is grounded, and the gate terminal of the NMOS tube N23 is connected to the output connection terminal of the voltage detection and control circuit;

[0172] The gate terminal of the PMOS transistor P28 is connected to the bias voltage VBP0 , and the gate terminal of the PMOS transistor P29 is connected to the bias voltage VBP1 .

[0173] Figure 5 , an embodiment of the transient response detection enhancement circuit is shown in FIG. 1 . Specifically, when the output voltage VOUT is monitored to be low, the current flowing through the PMOS tube P25 and the NMOS tube N21 will decrease, and then the voltage of the corresponding gate terminals of the NMOS tube N21 and the NMOS tube N22 will decrease. At this time, the voltage of the gate terminal of the NMOS tube N23 is also reduced, and the voltage of the drain terminal of the NMOS tube N23 will increase, that is, the transient response enhancement signal generated by the transient response enhancement signal generating circuit becomes larger. Figure 5 In the figure, EHO is the transient response enhancement signal, and the transient response enhancement signal is a voltage signal.

[0174] When the transient response enhancement signal becomes larger, the driving voltage VG output by the configured driving buffer is reduced, so that the power PMOS tube in the LDO circuit body provides a larger current, and the output voltage VOUT increases and returns to a normal value.

[0175] When the driving voltage VG decreases, the driving voltage VG will regulate the driving state of the PMOS tube P27. At this time, the current flowing through the NMOS tube N22 will increase, and the voltages at the corresponding gate terminals of the NMOS tubes N22 and N23 will increase, thereby resetting the output transient corresponding enhancement signal.

[0176] From the above description, it can be seen that the regulation process of output voltage VOUT->transient response enhancement signal->drive voltage VG->transient response enhancement signal EHO can be called a transient increase process, and it is an automatic opening and closing process, which will not affect the feedback coefficient of the entire LDO circuit loop, and thus will not affect the output voltage VOUT of the LDO circuit. It is just that when the load changes sharply, it is faster than the response of the error amplifier, thereby reducing the overshoot of the output voltage.

[0177] In one embodiment of the present invention, a dynamic frequency compensation circuit for frequency compensation of the LDO circuit body is also included, wherein:

[0178] The dynamic frequency compensation circuit includes a Miller structure frequency compensation unit and a load current compensation unit for performing dynamic frequency compensation based on the load current.

[0179] The Miller structure frequency compensation unit is adaptively connected to the output end of the circuit body and the inverting end of the error amplifier, so as to use the Miller structure frequency compensation unit to push the pole of the inverting end of the error amplifier to a low frequency;

[0180] The load current compensation unit includes a frequency compensation variable resistance unit, and the frequency compensation variable resistance unit is adaptively connected to the Miller structure frequency compensation unit, wherein:

[0181] Configuring the resistance value of the frequency compensation variable resistor unit based on the driving voltage VG so that the resistance value of the frequency compensation variable resistor is adapted to the load current;

[0182] After the resistance value of the frequency compensation variable resistor is configured by using the driving voltage VG, loop frequency compensation is performed on the LDO circuit body based on the frequency compensation variable resistor unit and the Miller structure compensation unit.

[0183] It should be noted that the LDO circuit is a multi-stage negative feedback closed-loop system with multiple zeros and poles. The stability problem is relatively complicated, and the output impedance of the power PMOS tube will change with the change of load, thereby affecting the loop gain and frequency response. This also makes the loop stability of the LDO circuit under full load conditions a key in the design.

[0184] In order to improve the stability of the LDO circuit, the present invention can realize frequency compensation for the LDO circuit through a dynamic frequency compensation circuit. Figure 1 The DFC (Dynamic Frequency Compensation) in the figure is a dynamic frequency compensation circuit. Specifically, according to the change of load current, the dynamic frequency compensation circuit can dynamically realize the frequency compensation of the LDO circuit loop, so that the LDO circuit can ensure stability under different load environments (light load and heavy load).

[0185] Figure 7 : is a circuit schematic diagram of an embodiment of a dynamic frequency compensation circuit. In the figure, the dynamic frequency compensation circuit includes a capacitor C4, a resistor R23, a capacitor C3, a PMOS tube P32 and a resistor R22, wherein one end of the capacitor C4 is connected to the inverting end of the error amplifier, the other end of the capacitor C4 is connected to one end of the capacitor C3, one end of the resistor R22 and the drain end of the PMOS tube P32, the other end of the resistor R22 is connected to the output end of the circuit body, the other end of the capacitor C3 is grounded, the source end of the PMOS tube P32 is connected to the power supply VDD through the resistor R23, and the gate end of the PMOS tube P32 is connected to the driving voltage VG.

[0186] The small signal model of the LDO circuit combined with the "Barkhausen criterion" is an important method for evaluating the stability of the system. The following is an evaluation of the stability of the LDO circuit combined with the small signal model. Fig. 9 For the present invention Figure 1 The small signal model of the LDO circuit in the circuit can be established by using existing commonly used technical means. Figure 1 The small signal model of the LDO circuit in the embodiment, the method and process of establishing the small signal model can be consistent with the prior art and will not be repeated here.

[0187] Depend on Fig. 9 It can be seen from the small signal model in that the LDO circuit of the present invention can be equivalent to four stages, wherein the first stage is an error amplifier, the second stage is a driving buffer, the third stage is a power PMOS tube, and the fourth stage is a voltage feedback circuit. Fig. 9 In the figure, gm1 is the transconductance of the error amplifier, gm2 is the transconductance of the driver buffer, gm3 is the transconductance of the power PMOS tube, gm4 is the transconductance of the PMOS tube P32 in the dynamic frequency compensation circuit, A FB is the feedback coefficient; Figure 1 In the LDO circuit, the feedback factor A FB Then R FB1 / (R FB0 +R FB1 ).

[0188] Depend on Fig. 9 It can be seen that the open-loop path of the small signal model of the LDO circuit of the present invention is: gm1->gm2->gm3->A FB ->SENSE; R O1 , R O2 They are the corresponding output resistances of the error amplifier and the driver buffer respectively; C VG is the gate capacitance of the power PMOS tube; R L , C L The corresponding load resistance and load capacitance at the output voltage VOUT point, R ESR is the load capacitance C LThe parasitic equivalent resistance on the capacitor C4 connected between point A and the inverting terminal of the error amplifier can be equivalent to the capacitor C4' between point A and GND, and the capacitor C4" between the inverting terminal of the error amplifier and GND, where C4'≈C4, C4">>C4. Since the transconductance gm4 does not form a feedforward path, it can be equivalent to a variable resistance R to GND. P32 , the variable resistance R P32 Used for dynamic frequency compensation.

[0189] Fig. 9 The open-loop transfer function of the small and medium signal model is as follows:

[0190] L(s)=(-g m1 *R S1 )*(-g m2 *R S1 )*(-g m3 *R S3 )*(A FB *ζ) (1)

[0191] Among them, R S1 , R S2 , R S3 are the equivalent output resistance of the first stage, the equivalent output resistance of the second stage, and the equivalent output resistance of the third stage respectively, and ζ is the effective coefficient of the fourth stage.

[0192] The above description can be Fig. 9 , then:

[0193] R S1 =R O1 ||(R18+1 / S*C1+R N20 ||1 / S*C2) (2)

[0194] R S2 = R O2 ||1 / S*C VG (3)

[0195] R S3 =R L ||(R FB0 +R FB1 )||(R ESR +1 / S*C L )||{R 23 +1 / [S*(C3+C4')||(R P32 +R 22 )]} (4)

[0196] ζ= 1 / S*R 24 *C4” (5)

[0197] Substituting formulas (2) to (5) into formula (1), we can obtain the following 6 poles and 4 zeros. Among them, the output end of the error amplifier generates 2 poles and 2 zeros. At this time, the poles and zeros can cancel each other out. The remaining 4 poles and 2 zeros are as follows:

[0198] P0≈-(1 / R L ) / C L ;

[0199] P1≈-(1 / R L ) / (C3+C4′);

[0200] P2=-(1 / R 24 ) / C4″;

[0201] P3=-(1 / R O2 ) / C VG ; / / high frequency

[0202] Z0≈-[1 / R 23 +1 / (R 22 +R P32 )] / (C3+C4′);

[0203] Z1=-(1 / R ESR ) / C L ;

[0204] Specifically, P0 is the main pole, which is composed of the microfarad load capacitance C at the output end of the LDO circuit. L and load resistance R L P1 is the secondary pole, which is also generated at the output end of the LDO circuit and changes with the load. L becomes smaller, the secondary pole P1 becomes larger; the P2 pole is formed by the output resistance R of the voltage feedback circuit 24 and equivalent capacitance C4”; the P3 pole is generated by the output resistance R O2 and the gate capacitance C of the power PMOS tube VG Since the output resistance of the driving buffer is very small, the P3 pole is a high-frequency pole and is far outside the cutoff frequency, which does not affect the stability of the loop.

[0205] Zero point Z0 is generated by R23 and the series capacitors C4 and C3, which is used for frequency compensation of the secondary pole P1. Zero point Z0 follows pole P1 for dynamic frequency compensation according to the load change. Zero point Z1 is generated by the load capacitor C L and its equivalent series resistance R ESR The zero point Z1 is used for frequency compensation of the pole P2. Through the above frequency compensation method, there is only one main pole P0 equivalently within the cut-off frequency, so the frequency response of the LDO circuit of the present invention is stable.

[0206] From the above description, it can be seen that the capacitor C4 and the resistor R23 form a Miller structure frequency compensation unit, thereby pushing the pole P2 of the inverting end of the error amplifier to a low frequency to compensate for the load capacitance and the parasitic equivalent resistance R ESR The zero point Z1 formed is used for zero-pole cancellation. The series resistor R23 forms a zero point Z0, and by connecting the PMOS tube P32 between point A and the power supply VDD, the PMOS tube P32 is used as a variable resistor. When the PMOS tube P32 is used as a variable resistor, the drive voltage VG controls the size of the variable resistor, and the drive voltage VG just determines the size of the load current. The change of the load current has an impact on the main pole P0 and the secondary pole P1 at the output voltage VOUT. In this way, the frequency compensation of the LDO circuit loop can be dynamically realized according to the change of the load current.

[0207] In one embodiment of the present invention, the precise low-pass filter comprises a voltage buffer device for performing voltage buffering processing and a low-pass filter for performing low-pass filtering processing, wherein:

[0208] The voltage buffer includes a PMOS tube P8 receiving a reference voltage, a source terminal of the PMOS tube P8 is connected to a source terminal of the PMOS tube P9 and a drain terminal of the PMOS tube P7, and a source terminal of the PMOS tube P7 is connected to a drain terminal of the PMOS tube P6;

[0209] The drain terminal of the PMOS tube P8 is connected to the drain terminal of the NMOS tube N6, the gate terminal of the NMOS tube N6 and the gate terminal of the NMOS tube N7, the source terminal of the NMOS tube N6 is grounded through the resistor R9, and the source terminal of the NMOS tube N7 is grounded through the resistor R10;

[0210] The drain terminal of the NMOS tube N7 is connected to the drain terminal of the PMOS tube P9 and the gate terminal of the NMOS tube N9. The source terminal of the NMOS tube N9 is grounded through the resistor R11. The drain terminal of the NMOS tube N9 is connected to the source terminal of the NMOS tube N8, the gate terminal of the PMOS tube P10 and the gate terminal of the PMOS tube P12. The drain terminal of the NMOS tube N8 is connected to the drain terminal of the PMOS tube P11. The source terminal of the PMOS tube P11 is connected to the drain terminal of the PMOS tube P10.

[0211] The drain end of the PMOS tube P12 is connected to the source end of the PMOS tube P13, the drain end of the PMOS tube P13 is connected to one end of the resistor R12, the other end of the resistor R12 is adaptively connected to the gate end of the PMOS tube P9, one end of the resistor R13 and the low-pass filter, and the other end of the resistor R13 is adaptively connected to the voltage buffer adjustment unit;

[0212] The source terminal of the PMOS transistor P6 , the source terminal of the PMOS transistor P10 , and the source terminal of the PMOS transistor P12 are all connected to the power source VDD.

[0213] Figure 3 An embodiment of an accurate low-pass filter is shown in Figure 3 X1 in the figure is a voltage buffer adjustment unit, which can be in the same form as the reference voltage adjustment circuit. The specific adjustment method and process can refer to the corresponding description above, which will not be repeated here.

[0214] Specifically, the voltage buffer transmits the reference voltage generated by the bandgap reference to VBG_BUF, that is, to Figure 3 The resistor R12, the resistor R13 and the gate terminal of the PMOS tube P9 are connected to each other to form a voltage buffer output node, and a reference buffer voltage can be obtained at the voltage buffer output node. As can be seen from the above description, the voltage buffer trimming unit in the voltage buffer can be used to achieve trimming, and then a zero temperature drift voltage can be obtained, thereby improving the accuracy of the reference buffer voltage through the voltage buffer trimming unit; in addition, the above voltage buffer has a high input impedance and a low output impedance, and the high input impedance can isolate the front and rear voltages, and the low output impedance can eliminate ground bounce interference.

[0215] Figure 3 An embodiment of a low-pass filter is also shown in FIG. Figure 3 In the embodiment, the low-pass filter includes a current source circuit and a filter capacitor, wherein the current source circuit includes a PMOS tube P14, a PMOS tube P15, a PMOS tube P16, a PMOS tube P17, a PMOS tube P18, an NMOS tube N10, and an NMOS tube N11, wherein the source terminal of the PMOS tube P14 is connected to the power supply VDD, the drain terminal of the PMOS tube P14 is connected to the source terminal of the PMOS tube P15, the drain terminal of the PMOS tube P15 is connected to the source terminal of the PMOS tube P16, the drain terminal of the PMOS tube P16 is connected to the drain terminal of the NMOS tube N10, the gate terminal of the NMOS tube N10, and the gate terminal of the NMOS tube N11, and the source terminal of the NMOS tube N10 and the source terminal of the NMOS tube N11 are both grounded;

[0216] The drain terminal of the NMOS tube N11 is connected to the drain terminal of the PMOS tube P17, the gate terminal of the PMOS tube P17 and the gate terminal of the PMOS tube P18. The source terminal of the PMOS tube P17 and the source terminal of the PMOS tube P18 are both connected to the voltage buffer output node. The drain terminal of the PMOS tube P18 is grounded through a filter capacitor. Figure 3 In the figure, C0 is the filter capacitor. After the drain terminal of the PMOS tube P18 is connected to the filter capacitor, the filter output terminal of the precise low-pass filter can be formed. The reference voltage can be obtained through the filter output terminal. Figure 3 The VREF in it is the reference voltage.

[0217] In specific implementation, after obtaining the reference buffer voltage, a low-pass filter formed by a current source circuit and a filter capacitor can eliminate noise from the power supply VDD and ground bounce interference from GND, thereby ensuring a high-stability and high-precision reference voltage VREF output.

[0218] In one embodiment of the present invention, the error amplifier comprises an error amplifier rail-to-rail input stage and an error amplifier high-gain output stage, wherein:

[0219] The error amplifier rail-to-rail input stage receives the reference voltage and is adaptively connected to the driving buffer through the error amplifier high-gain output stage;

[0220] The error amplifier rail-to-rail input stage includes a reference voltage receiving part and a sampling voltage receiving part, the reference voltage is loaded into the reference voltage receiving part, and the working sampling voltage is loaded into the sampling voltage receiving part, wherein:

[0221] The reference voltage receiving unit includes an NMOS tube N12, a PMOS tube P21 and an NMOS tube N14, and the reference voltage is simultaneously loaded to the gate end of the NMOS tube N12, the gate end of the PMOS tube P21 and the gate end of the NMOS tube N14;

[0222] The sampling voltage receiving unit includes an NMOS tube N13, a PMOS tube P22 and an NMOS tube N15, and the working sampling voltage is simultaneously loaded to the gate end of the NMOS tube N13, the gate end of the PMOS tube P22 and the gate end of the NMOS tube N15;

[0223] The drain terminal of the NMOS tube N12, the source terminal of the PMOS tube P21, the source terminal of the PMOS tube P22, and the drain terminal of the NMOS tube N13 are all connected to the drain terminal of the PMOS tube P20, the source terminal of the PMOS tube P20 is connected to the drain terminal of the PMOS tube P19, the source terminal of the PMOS tube P19 is connected to the power supply VDD, and the source terminal of the NMOS tube N12 and the source terminal of the NMOS tube N13 are all grounded;

[0224] The source terminals of the NMOS tube N14 and the NMOS tube N15 are both connected to the drain terminal of the NMOS tube N16, the source terminal of the NMOS tube N16 is connected to the drain terminal of the NMOS tube N17, and the source terminal of the NMOS tube N17 is grounded;

[0225] The drain terminal of the PMOS tube P21 is connected to one end of the resistor R14 in the error amplifier high gain output stage and the source terminal of the PMOS tube P23, the drain terminal of the PMOS tube P22 is connected to one end of the resistor R15 in the error amplifier high gain output stage and the source terminal of the PMOS tube P24, and the other ends of the resistors R14 and R15 are connected to the power supply VDD;

[0226] The drain terminal of the PMOS tube P23 is connected to the drain terminal of the NMOS tube N14, the drain terminal of the NMOS tube N18 in the error amplifier high gain output stage, the gate terminal of the NMOS tube N18, and the gate terminal of the NMOS tube N19 in the error amplifier high gain output stage.

[0227] The drain terminal of the NMOS tube N19 is connected to the drain terminal of the NMOS tube N15, the drain electrode of the PMOS tube P24, and the error amplification frequency compensation unit in the error amplification high gain output stage to form an error amplification output terminal of the error amplifier;

[0228] The source terminal of the NMOS tube N18 is grounded through the resistor R16, and the source terminal of the NMOS tube N19 is grounded through the resistor R17;

[0229] The gate terminal of the PMOS tube P10 is connected to the bias voltage VBP0, the gate terminal of the PMOS tube P20 is connected to the bias voltage VBP1, and the gate terminal of the PMOS tube P23 and the gate terminal of the PMOS tube P24 are both connected to the bias voltage VBP2;

[0230] The gate terminal of the NMOS tube N16 is connected to the bias voltage VBN1, and the gate terminal of the NMOS tube N16 is connected to the bias voltage VBN0.

[0231] Figure 4 An embodiment of the error amplifier is shown in the figure. In the error amplifier rail-to-rail input stage, the NMOS transistor N14 and the NMOS transistor N15 form a first differential transistor pair, and the first differential transistor pair formed can be used to process high input voltage signals. The PMOS transistor P21 and the PMOS transistor P22 form a second differential transistor pair, and the second differential transistor pair is used to process low input voltage signals, thereby realizing rail-to-rail voltage processing. The methods and processes for processing low input voltage signals and high input voltage signals are consistent with the prior art and will not be repeated here.

[0232] An error amplifier frequency compensation unit is set in the error amplifier high gain output stage. Figure 4 The FC in the figure is the error amplifier frequency compensation unit, which can be used to generate two zero points to compensate for the two poles of the error amplifier, thereby reducing the influence of the error amplifier on the phase margin in the loop of the entire LDO circuit.

[0233] Figure 4 An embodiment of the error amplification frequency compensation unit is also shown in the figure. In the figure, the error amplification frequency compensation unit includes a resistor R18, a capacitor C1, a capacitor C2 and an NMOS tube N20, wherein one end of the resistor R18 is connected to the error amplification output end, the other end of the resistor R18 is connected to the gate end of the NMOS tube N20 and one end of the capacitor C1, the other end of the capacitor C1 is connected to the drain end of the NMOS tube N20 and one end of the capacitor C2, and the other end of the capacitor C2 and the source end of the NMOS tube N20 are both grounded.

[0234] For the above-mentioned drive buffer, Figure 6 An embodiment of a drive buffer is shown in FIG. Figure 6 In the embodiment, the driving buffer includes a PMOS tube P30 and a PMOS tube P31, wherein the source terminal of the PMOS tube P30 and the source base of the PMOS tube P31 are both connected to the power supply VDD.

[0235] The gate terminal of the PMOS transistor P30 is connected to the drain terminal of the PMOS transistor P30, the drain terminal of the NMOS transistor N24, the drain terminal of the PMOS transistor P31 and one end of the resistor R21, and after connection, a driving buffer output terminal of the driving buffer is formed, so that the driving buffer output terminal can output the driving voltage VG.

[0236] The gate terminal of the NMOS tube N24 is connected to the output terminal of the transient response detection enhancement circuit, the source terminal of the NMOS tube N24 is connected to the drain terminal of the NMOS tube N25, the gate terminal of the NMOS tube N25 is connected to the error amplification output terminal of the error amplifier, and the source terminal of the NMOS tube N25 is grounded;

[0237] The gate terminal of the PMOS tube P31 is connected to the other end of the resistor R21 and the drain terminal of the NMOS tube N26, the source terminal of the NMOS tube N26 is connected to the drain terminal of the NMOS tube N27, the source terminal of the NMOS tube N27 is grounded, the gate terminal of the NMOS tube N26 receives the bias voltage VBN0, and the gate terminal of the NMOS tube N27 receives the bias voltage VBN1.

[0238] Specifically, the driving buffer can output a driving voltage VG to drive the power PMOS tube. Since the power PMOS tube has a very large gate capacitance, the driving buffer needs to have a relatively large driving capability. In specific implementation, the PMOS tube P30, the PMOS tube P31, the NMOS tube N24 and the NMOS tube N25 are designed to be larger in size, specifically to meet the driving requirements of the power PMOS tube. Figure 6 The driving buffer shown in FIG. 1 has a relatively small output resistance, and the pole formed at the output end of the driving buffer is a high-frequency pole, which does not affect the stability of the LDO circuit loop.

[0239] It should be noted that the bias voltage used in the above circuit is generally generated by a bias voltage circuit. The bias voltage generating circuit can adopt an existing commonly used form, and the specific form is based on whether it can generate the above bias voltage.

Claims

1. A high-precision LDO circuit with low noise and high transient enhancement capability, characterized in that: The LDO circuit comprises: LDO circuit body; The reference voltage generating unit is used to provide the reference voltage required by the LDO circuit body when it is working, including a bandgap reference for generating the reference voltage and a precise low-pass filter for performing anti-noise processing on the reference voltage, wherein: When the reference voltage is subjected to noise reduction processing, at least voltage buffering processing and low-pass filtering processing are performed in sequence. Performing voltage buffering on the reference voltage to generate a corresponding reference buffer voltage; When the generated reference buffer voltage is low-pass filtered, at least power supply noise and / or ground bounce interference of the reference buffer voltage is removed to generate a corresponding reference voltage after low-pass filtering, and the generated reference voltage is loaded into the LDO circuit body.

2. The high-precision LDO circuit with low noise and high transient enhancement capability according to claim 1 is characterized in that: The LDO circuit body includes an error amplifier, a drive buffer, a power tube circuit and a voltage feedback circuit, wherein: The reference voltage generated by the reference voltage generating unit is loaded onto the in-phase terminal of the error amplifier, the output terminal of the error amplifier is connected to the driving buffer, and the output terminal of the driving buffer is connected to the gate terminal of the power PMOS tube in the power tube circuit, so as to load the driving voltage VG onto the gate terminal of the power PMOS tube through the driving buffer; The drain terminal of the power PMOS tube is connected to the voltage feedback circuit to feed back the working sampling voltage to the inverting terminal of the error amplifier through the voltage feedback circuit. The combination of the drain end of the power PMOS tube and the voltage feedback circuit forms the circuit body output end of the LDO circuit body.

3. The high-precision LDO circuit with low noise and high transient enhancement capability according to claim 2 is characterized in that: Also included is a transient response detection enhancement circuit for transient response detection and enhancement, wherein: The transient response detection enhancement circuit is adaptively connected to the circuit body output terminal of the LDO circuit body and the driving buffer to load the output voltage VOUT of the circuit body output terminal and the driving voltage VG to the transient response detection enhancement circuit; Based on the output voltage VOUT, the transient response detection enhancement circuit detects the transient response of the LDO circuit body, wherein: When the transient response of the LDO circuit body is determined to change, the transient response detection enhancement circuit generates a corresponding transient response enhancement signal, and loads the transient response enhancement signal to the driving buffer, and configures the driving buffer to adjust the output driving voltage VG based on the current transient response enhancement signal, so that the output voltage VOUT of the LDO circuit body remains stable. Based on the driving voltage VG adjusted by the driving buffer, the transient response enhancement signal generated by the transient response detection enhancement circuit is regulated so that the transient response enhancement signal generated by the transient response detection enhancement circuit remains stable after transient response enhancement.

4. The high-precision LDO circuit with low noise and high transient enhancement capability according to claim 3 is characterized in that: The transient response detection enhancement circuit includes a voltage detection control circuit and a transient response enhancement signal generation circuit adaptively connected to the voltage detection control circuit, wherein: The voltage detection and control circuit is used to simultaneously connect the output voltage VOUT and the driving voltage VG; The transient response enhancement signal generating circuit generates a transient response enhancement signal and loads the generated transient response enhancement signal to the driving buffer; When determining the transient response state based on the output voltage VOUT, the voltage detection and control circuit generates a voltage detection and control signal adapted to the current transient response state, and loads the voltage detection and control signal to the transient response enhancement signal generation circuit, so as to configure the transient response enhancement signal generation circuit to control the generated transient response enhancement signal in the direction of transient response change; Based on the driving voltage VG adjusted by the driving buffer, the voltage detection and control circuit generates a voltage detection and control signal adapted to the current driving voltage VG, and loads the voltage detection and control signal to the transient response enhancement signal generation circuit, so as to configure the transient response enhancement signal generation circuit to control the generated transient response enhancement signal in the opposite direction of the driving voltage change; When the transient response enhancement signal generated by the transient response enhancement signal generating circuit is regulated, the changing direction of the transient response is consistent with the changing direction of the driving voltage.

5. The high-precision LDO circuit with low noise and high transient enhancement capability according to claim 4 is characterized in that: The voltage detection and control circuit includes a PMOS tube P25 and an NMOS tube N21, wherein: The source terminal of the PMOS tube P25 is connected to the output voltage VOUT through the resistor R19, the gate terminal of the PMOS tube P25 is connected to the drain terminal of the PMOS tube P25, the drain terminal of the NMOS tube N21 and the gate terminal of the PMOS tube P26, and the source terminal of the NMOS tube N21 is grounded; The gate terminal of the NMOS tube N21 is connected to the gate terminal of the NMOS tube N22, the drain terminal of the NMOS tube N22, and the drain terminal of the PMOS tube P26, and the gate terminal of the NMOS tube N21, the gate terminal of the MOS tube N22, the drain terminal of the NMOS tube N22, and the drain terminal of the PMOS tube P26 are connected to each other to form the output connection terminal of the voltage detection and control circuit; The source terminal of the PMOS tube P26 is connected to the drain terminal of the PMOS tube P27 through the resistor R20, the gate terminal of the PMOS tube P27 is connected to the driving voltage VG, the source terminal of the PMOS tube P27 is connected to the power supply VDD, and the source terminal of the NMOS tube N22 is grounded; The transient response enhancement signal generating circuit includes a PMOS transistor P28, a PMOS transistor P29 and an NMOS transistor N23, wherein: The source terminal of the PMOS tube P28 is connected to the power supply VDD, the drain terminal of the PMOS tube P28 is connected to the source terminal of the PMOS tube P29, and the drain terminal of the PMOS tube P29 is connected to the drain terminal of the NMNOS tube N23 to form the output connection terminal of the transient response enhancement signal generating circuit. The source terminal of the NMOS tube N23 is grounded, and the gate terminal of the NMOS tube N23 is connected to the output connection terminal of the voltage detection and control circuit; The gate terminal of the PMOS transistor P28 is connected to the bias voltage VBP0 , and the gate terminal of the PMOS transistor P29 is connected to the bias voltage VBP1 .

6. The LDO circuit with low noise, high precision and transient enhancement capability according to any one of claims 2 to 5, characterized in that: It also includes a dynamic frequency compensation circuit for frequency compensation of the LDO circuit body, wherein: The dynamic frequency compensation circuit includes a Miller structure frequency compensation unit and a load current compensation unit for performing dynamic frequency compensation based on the load current. The Miller structure frequency compensation unit is adaptively connected to the output end of the circuit body and the inverting end of the error amplifier, so as to use the Miller structure frequency compensation unit to push the pole of the inverting end of the error amplifier to a low frequency; The load current compensation unit includes a frequency compensation variable resistance unit, and the frequency compensation variable resistance unit is adaptively connected to the Miller structure frequency compensation unit, wherein: Configuring the resistance value of the frequency compensation variable resistor unit based on the driving voltage VG so that the resistance value of the frequency compensation variable resistor is adapted to the load current; After the resistance value of the frequency compensation variable resistor is configured by using the driving voltage VG, loop frequency compensation is performed on the LDO circuit body based on the frequency compensation variable resistor unit and the Miller structure compensation unit.

7. The LDO circuit with low noise, high precision and transient enhancement capability according to any one of claims 1 to 5, characterized in that: The bandgap reference comprises a bandgap operational amplifier circuit and a zero temperature drift reference voltage output unit connected in sequence, wherein: The bandgap operational amplifier circuit adopts an operational amplifier circuit capable of gain bootstrapping; The zero temperature drift reference voltage output unit includes a zero temperature drift reference voltage generation unit and a reference voltage adjustment unit adaptively connected to the zero temperature drift reference voltage generation unit. The zero temperature drift reference voltage generating unit in the zero temperature drift reference voltage output unit is adaptively connected to the bandgap operational amplifier circuit, wherein: A reference voltage difference is generated in a zero temperature drift reference voltage generation unit, and the reference voltage difference is converted into a corresponding zero temperature drift basic voltage through a bandgap operational amplifier circuit; The reference voltage trimming unit is used to trim the zero temperature drift basic voltage to generate a reference voltage after the trimming process.

8. The LDO circuit with low noise, high precision and transient enhancement capability according to claim 7 is characterized in that: The reference voltage trimming circuit includes a plurality of current trimming units based on current trimming, wherein the current trimming unit includes a current trimming main unit and a trimming reset control signal generating unit adaptively connected to the current trimming main unit; When current trimming is performed based on the current trimming unit, pre-trimming is performed using the current trimming main unit first, and post-trimming is performed after the pre-trimming, wherein: During pre-adjustment, the pre-adjustment data is loaded into the current adjustment main unit, so that the current adjustment main unit generates a pre-adjustment state signal corresponding to the pre-adjustment data; Based on the pre-trim state signal generated by the pre-trim, determining the current trimming target state signal of the current trimming main unit during post-trim, wherein the state of the current trimming target state signal is a trimming effective state or a trimming invalid state; During post-adjustment, based on the current adjustment target state signal, the target adjustment data is loaded into the current adjustment main unit, and the current adjustment unit outputs the corresponding current adjustment target state signal, and a dual-mode adjustment state signal is formed based on the current adjustment target state signal, wherein: When the state of the current trimming target state signal is a trimming effective state, the polycrystalline fuse in the current trimming main unit is blown by a current blowing method based on the current trimming target state signal and the trimming enable signal in an effective state, so as to lock the current trimming target state signal output by the current trimming main unit after the polycrystalline fuse is blown; After the current trimming unit is powered on again, the trimming reset control signal generating unit is used to generate a trimming reset control signal, so that the current trimming main unit configures the generated trimming state signal as a corresponding current trimming target state signal under the trimming reset control signal.

9. The LDO circuit with low noise, high precision and transient enhancement capability according to any one of claims 1 to 5, characterized in that: The precise low-pass filter includes a voltage buffer device for performing a voltage buffering process and a low-pass filter for performing a low-pass filtering process, wherein: The voltage buffer includes a PMOS tube P8 receiving a reference voltage, a source terminal of the PMOS tube P8 is connected to a source terminal of the PMOS tube P9 and a drain terminal of the PMOS tube P7, and a source terminal of the PMOS tube P7 is connected to a drain terminal of the PMOS tube P6; The drain terminal of the PMOS tube P8 is connected to the drain terminal of the NMOS tube N6, the gate terminal of the NMOS tube N6 and the gate terminal of the NMOS tube N7, the source terminal of the NMOS tube N6 is grounded through the resistor R9, and the source terminal of the NMOS tube N7 is grounded through the resistor R10; The drain terminal of the NMOS tube N7 is connected to the drain terminal of the PMOS tube P9 and the gate terminal of the NMOS tube N9. The source terminal of the NMOS tube N9 is grounded through the resistor R11. The drain terminal of the NMOS tube N9 is connected to the source terminal of the NMOS tube N8, the gate terminal of the PMOS tube P10 and the gate terminal of the PMOS tube P12. The drain terminal of the NMOS tube N8 is connected to the drain terminal of the PMOS tube P11. The source terminal of the PMOS tube P11 is connected to the drain terminal of the PMOS tube P10. The drain end of the PMOS tube P12 is connected to the source end of the PMOS tube P13, the drain end of the PMOS tube P13 is connected to one end of the resistor R12, the other end of the resistor R12 is adaptively connected to the gate end of the PMOS tube P9, one end of the resistor R13 and the low-pass filter, and the other end of the resistor R13 is adaptively connected to the voltage buffer adjustment unit; The source terminal of the PMOS transistor P6 , the source terminal of the PMOS transistor P10 , and the source terminal of the PMOS transistor P12 are all connected to the power source VDD.

10. The LDO circuit with low noise, high precision and transient enhancement capability according to any one of claims 2 to 5, characterized in that: The error amplifier comprises an error amplifier rail-to-rail input stage and an error amplifier high-gain output stage, wherein: The error amplifier rail-to-rail input stage receives the reference voltage and is adaptively connected to the driving buffer through the error amplifier high-gain output stage; The error amplifier rail-to-rail input stage includes a reference voltage receiving part and a sampling voltage receiving part, the reference voltage is loaded into the reference voltage receiving part, and the working sampling voltage is loaded into the sampling voltage receiving part, wherein: The reference voltage receiving unit includes an NMOS tube N12, a PMOS tube P21 and an NMOS tube N14, and the reference voltage is simultaneously loaded to the gate end of the NMOS tube N12, the gate end of the PMOS tube P21 and the gate end of the NMOS tube N14; The sampling voltage receiving unit includes an NMOS tube N13, a PMOS tube P22 and an NMOS tube N15, and the working sampling voltage is simultaneously loaded to the gate end of the NMOS tube N13, the gate end of the PMOS tube P22 and the gate end of the NMOS tube N15; The drain terminal of the NMOS tube N12, the source terminal of the PMOS tube P21, the source terminal of the PMOS tube P22, and the drain terminal of the NMOS tube N13 are all connected to the drain terminal of the PMOS tube P20, the source terminal of the PMOS tube P20 is connected to the drain terminal of the PMOS tube P19, the source terminal of the PMOS tube P19 is connected to the power supply VDD, and the source terminal of the NMOS tube N12 and the source terminal of the NMOS tube N13 are all grounded; The source terminals of the NMOS tube N14 and the NMOS tube N15 are both connected to the drain terminal of the NMOS tube N16, the source terminal of the NMOS tube N16 is connected to the drain terminal of the NMOS tube N17, and the source terminal of the NMOS tube N17 is grounded; The drain terminal of the PMOS tube P21 is connected to one end of the resistor R14 in the error amplifier high gain output stage and the source terminal of the PMOS tube P23, the drain terminal of the PMOS tube P22 is connected to one end of the resistor R15 in the error amplifier high gain output stage and the source terminal of the PMOS tube P24, and the other ends of the resistors R14 and R15 are connected to the power supply VDD; The drain terminal of the PMOS tube P23 is connected to the drain terminal of the NMOS tube N14, the drain terminal of the NMOS tube N18 in the error amplifier high gain output stage, the gate terminal of the NMOS tube N18, and the gate terminal of the NMOS tube N19 in the error amplifier high gain output stage. The drain terminal of the NMOS tube N19 is connected to the drain terminal of the NMOS tube N15, the drain electrode of the PMOS tube P24, and the error amplification frequency compensation unit in the error amplification high gain output stage to form an error amplification output terminal of the error amplifier; The source terminal of the NMOS tube N18 is grounded through the resistor R16, and the source terminal of the NMOS tube N19 is grounded through the resistor R17; The gate terminal of the PMOS tube P10 is connected to the bias voltage VBP0, the gate terminal of the PMOS tube P20 is connected to the bias voltage VBP1, and the gate terminal of the PMOS tube P23 and the gate terminal of the PMOS tube P24 are both connected to the bias voltage VBP2; The gate terminal of the NMOS tube N16 is connected to the bias voltage VBN1, and the gate terminal of the NMOS tube N16 is connected to the bias voltage VBN0.

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