A bias current source with a wide voltage range

Abstract

The present invention provides a bias current source with a wide voltage range, comprising a bias current generating module and a bias current output module. The bias current generating module generates a bias current that varies very little within a power supply voltage range of 5.5V to 52V and has a self-starting function to prevent the bias current generating module from being in a zero state. Transistors M1 to M4 form a common source and common gate structure that can reduce the impact of VDD changes on the output bias current. Capacitors C1 and C2 can reduce the impact of VDD voltage jitter on the bias current, providing strong anti-interference capabilities. The bias current output module of the present invention can provide both source and sink bias current as needed, and the bias current generating module and the bias current output module cooperate to ensure that the bias current varies little with temperature and has high precision.

Description

Technical Field

[0001] The present invention relates to the field of electrical technology, and in particular to a bias current source with a wide voltage range. Background Art

[0002] For stable operation, high-performance analog integrated circuits and mixed-analog circuits require bias current sources with minimal temperature variation, high stability, self-startup, and a wide input voltage range. Bias current sources are a crucial reference source in analog and mixed-analog integrated circuits, providing bias current to other modules within the chip. The bias current should exhibit minimal variation with changes in supply voltage and temperature.

[0003] However, the conventional resistor divider bias current source circuit is Figure 1 As shown, either the power consumption is large or the layout area is large, and the bias current varies greatly with temperature and the input power supply voltage varies greatly, and the input voltage range is small. Summary of the Invention

[0004] The present invention aims to address the problem of bias current varying significantly with temperature and input power supply voltage, and provides a bias current source with a wide voltage range, comprising a bias current generating module and a bias current output module. The bias current generating module generates a bias current that varies minimally within a power supply voltage range of 5.5V to 52V, and also has a self-starting function to prevent the bias current generating module from being in a zero state. Transistors M1 to M4 form a common source and common gate structure that can reduce the impact of VDD variations on the output bias current. Capacitors C1 and C2 can reduce the impact of VDD voltage jitter on the bias current, providing strong anti-interference capabilities. The bias current output module of the present invention can provide both source and sink bias current as needed, and the bias current generating module and the bias current output module cooperate to minimize bias current variations with temperature and achieve high precision.

[0005] The present invention provides a bias current source with a wide voltage range, comprising a bias current generating module and a bias current output module connected;

[0006] The bias current generation module outputs a positive temperature coefficient bias current to the bias current output module. The bias current output module cooperates with the bias current generation module to output the source current P27_G and the sink current C13_PLUS and reduce the influence of temperature on the output current.

[0007] The bias current generating module includes tubes M1 and M2 whose sources are respectively connected to the power supply voltage VDD, a tube M3 whose source is connected to the drain of tube M1, a tube M4 whose source is connected to the drain of tube M2, a tube M10 whose drain is connected to the drain of tube M3, resistors R1 and R2 connected in parallel with the source of tube M10, a tube Q1 whose collector is connected to the other end of resistor R1 and whose base is connected to the other end of resistor R2, a resistor R4 connected to the emitter of tube Q1, a resistor R3 whose one end is connected to the drain of tube M4, a collector connected to the other end of resistor R3, and an emitter connected to resistor R4, and a grounded The transistor Q2 is connected to the end thereof, the Zener diode Q3 having its cathode connected to the gate of the transistor M10, a resistor R6 having one end connected to the power supply voltage VDD, a transistor M11 having its drain connected to the other end of the resistor R6 and its gate connected to the cathode of the Zener diode Q3, transistors M5 and M6 having their sources connected to the source of the transistor M11 respectively, a capacitor C2 connected in parallel with the transistor M6, a resistor R8 having one end connected to the drain of the transistor M5, a transistor Q4 having its collector connected to the other end of the resistor R8, a resistor R9 having one end connected to the drain of the transistor M6, and a transistor M7 having its gate and drain both connected to the other end of the resistor R9;

[0008] The gate and drain of tube M1 are connected and then connected to the gate of tube M2. The gate and drain of tube M3 are connected and then connected to the gate of tube M4. The gate of tube M10 is the bias current source signal input terminal. The base of tube Q1 is connected to the base and collector of tube Q2. Resistor R4, the emitter of tube Q2, the emitter of tube Q4, and the source of tube M7 are connected and then grounded. The base of tube Q4 is connected between resistor R3 and the collector of tube Q2. The anode of Zener diode Q3 is grounded. The gate and drain of tube M5 are connected and then connected to the gate of tube M6. The gate of tube M6 is connected to the other end of capacitor C2 and outputs source current P27_G. The gate and drain of tube M7 are connected and outputs sink current C13_PLUS.

[0009] The tubes M1 to M6 are all PMOS tubes, the tubes M7, M10, and M11 are all NMOS tubes, and the tubes Q1, Q2, and Q4 are all three-stage tubes.

[0010] In the bias current source with a wide voltage range described in the present invention, as a preferred embodiment, the positive temperature coefficient bias current is output by the tube Q1, the tube Q2, and the resistor R4.

[0011] In the bias current source with a wide voltage range described in the present invention, as a preferred embodiment, the current passing through the resistor R2 is:

[0012] I R2 =(VDD-V TH1 -V TH3 -V BE1 ) / (R2+R4);

[0013] Among them, V TH1 is the voltage of tube M1, V TH3 is the voltage of tube M3, VBE1 is the voltage of tube Q1;

[0014] I R2 is a positive temperature coefficient current.

[0015] The bias current source with a wide voltage range described in the present invention is preferably configured such that I M3 =I R1 +I R2 ;

[0016] Among them, I M3 is the drain current of tube M3, I R1 is the current flowing through resistor R1;

[0017] And: I M3 =I M4 , I M4 is the drain current of tube M4;

[0018] I M4 =I Q2C +I Q2B +I Q4B , I Q2C is the collector current of tube Q2, I Q2B is the base current of tube Q2, I Q4B is the base current of tube Q4;

[0019] As the temperature increases, I R2 Increased I M3 , I M4 Increase, I Q2C and I Q2B As the temperature increases, it offsets part of the increase in the base current flowing through tube Q4.

[0020] The bias current source with a wide voltage range described in the present invention preferably further includes a startup circuit, which comprises a resistor R5 connected in parallel with a resistor R6 and a capacitor C1 having one end connected to the gate of the transistor M10, the cathode of the Zener diode Q3, and the gate of the transistor M11, and the other end connected to ground.

[0021] When the bias current source circuit is powered on, the voltage at the upper end of the capacitor C1 rises and causes the gate voltage of the tube M10 in the bias current generating module to rise for self-starting, thereby preventing the bias current generating module from being in a zero state.

[0022] The present invention provides a bias current source with a wide voltage range. As a preferred embodiment, capacitors C1 and C2 can reduce the effect of voltage VDD jitter on the bias current.

[0023] In the bias current source with a wide voltage range described in the present invention, as a preferred embodiment, the transistors M1, M2, M3, and M4 are cascode current mirrors and are all high-voltage PMOS transistors.

[0024] In the bias current source with a wide voltage range described in the present invention, as an optimal embodiment, the tube M11 is a high-voltage tube.

[0025] In the bias current source with a wide voltage range described in the present invention, as a preferred embodiment, the resistance values ​​of the resistors R1 and R3 are the same, and the ratio of the tube Q1 to the tube Q2 is 6:1.

[0026] In the bias current source with a wide voltage range described in the present invention, as a preferred embodiment, the transistors M5 and M6 form a current mirror.

[0027] The present invention provides a bias current source with a wide power supply range, including a bias current generating module and a bias current output module. Figure 2 As shown, the bias current generation module generates a bias current with a positive temperature coefficient, meaning that the bias current increases with rising temperature. R5 and C1 in the bias current output module form a startup circuit. When the circuit is powered on, the voltage at the top of capacitor C1 slowly rises, causing the gate voltage of M10 in the current generation module to slowly rise, preventing the bias current generation module from being in a zero state and causing the bias current to be zero. M3 and M4 in the bias current generation module are high-voltage transistors, and M1, M2, M3, and M4 are also high-voltage transistors. The MOS transistor connection method (cascode current mirror) ensures that the bias current is minimally affected by changes in the power supply voltage. When M1 and M2 are turned on, the difference between their source and drain voltages is minimal, preventing breakdown due to high power supply voltages. The bias current output module's circuit function is to output a highly accurate bias current. The voltage of Zener diode Q3 decreases with rising temperature, so the gate voltage of M11 also decreases with rising temperature, causing the source current of M11 to remain essentially unchanged with temperature. Because the bias current generator generates a current that increases with temperature, the output bias currents P27_G and C13_PLUS in the bias current output module vary very little with temperature. M11 in the bias current output module is a high-voltage transistor, allowing the module to operate normally even at high voltages.

[0028] The present invention has the following advantages:

[0029] (1) The bias current generating module of the present invention generates a bias current that varies very little within the power supply voltage range of 5.5V to 52V. It also has a self-starting function to prevent the bias current generating module from being in a zero state. The M1 to M4 transistors form a common source and common gate structure to reduce the impact of VDD changes on the output bias current. The capacitors C1 and C2 can reduce the impact of VDD voltage jitter on the bias current, and have strong anti-interference performance.

[0030] (2) The bias current output module of the present invention can provide bias current source and bias current sink as needed, and the bias current generation module and the bias current output module cooperate with each other to ensure that the bias current changes little with temperature and has high precision.

[0031] (3) The present invention provides a bias current source with a wide power supply range, high precision, strong anti-interference performance, and the ability to provide a source / sink bias current. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a traditional resistor divider bias current source circuit diagram;

[0033] Figure 2 A system diagram of a bias current source with a wide voltage range;

[0034] Figure 3 The figure is a specific circuit diagram of a bias current source with a wide voltage range. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0036] Example 1

[0037] like Figure 2 、 3 As shown, a bias current source with a wide voltage range includes a bias current generating module and a bias current output module; the bias current generating module inputs a C14_PLUS signal;

[0038] like Figure 2 As shown, the bias current generation module generates a bias current with a positive temperature coefficient, that is, the bias current increases with increasing temperature. R5 and C1 in the bias current output module form a startup circuit. When the circuit is powered on, the voltage at the top of capacitor C1 slowly rises, causing the gate voltage of M10 in the current generation module to slowly rise, preventing the bias current generation module from being in a zero state, resulting in zero bias current. M3 and M4 in the bias current output module are high-voltage transistors, and M1, M2, M3, and M4 are high-voltage MOS transistors. The connection method of the transistors can make the bias current change very little with the power supply voltage. When M1 and M2 are turned on, the voltage difference between their source and drain is very small, and they will not break down due to the high power supply voltage. The positive temperature coefficient bias current is composed of Q1, Q2, and R4 in the bias current generation module. The current formula is:

[0039]

[0040] Where, ΔV BEAs the temperature rises, the current passing through R2 is: I R2 =(VDD-V TH1 -V TH3 -V BE1 ) / (R2+R4), because V TH1 、V TH2 、V BE1 The voltage decreases as the temperature increases, so I R2 It is also a current with a positive temperature coefficient. After the action of the current mirror M1 to M4, the drain current of M4 is equal to the collector current of Q2 plus the base current of Q4. Because the collector current of Q2 is also a current with a positive temperature coefficient, that is, the current increases with the increase of temperature, the current flowing into the base of Q4 changes very little with the temperature. And because the base of Q4 is connected to the base of Q2, when the temperature rises, the V BE Decrease, Q2's V BE The collector current of Q4 remains unchanged. Similarly, the gates of M10 and M11 are connected together, so the source current of M11 changes little with temperature.

[0041] In summary, the output bias current has a small change with temperature and high precision. The M11 in the bias current output module is a high voltage tube, which can make the module still work normally under high voltage.

[0042] M5 and M6 of the bias current output module form a current mirror, which can provide source current P27_G and sink current C13_PLUS according to different current requirements.

[0043] Resistors R1:R3 are 1:1

[0044] Transistor Q1:Q2 is 6:1

[0045] In this embodiment, the current changes as follows: M3 drain current = current flowing through R1 + current flowing through R2, that is, I M3 =I R1 +I R2 , and because M3 and M4 form a current mirror structure, I M3 =I M4 , because the drain current of M4 = collector current of Q2 + base current of Q2 + base current of Q4, that is, I M4 =I Q2C +I Q2B +I Q4B , so when the temperature increases, the flow through I R2 The current increases, I M3 The current increases, so I M4 Increase, and because the collector current and base current of Q2 increase, it can be concluded from the above formula that the base current flowing through Q4 remains basically unchanged.

[0046] For example: Q at room temperature 1C =5uA, I R2 =2uA, I Q2C =5uA, I Q2B =1uA, I Q4B =1uA, when the temperature rises, Q 1C =6uA, I R2 =3uA, I Q2C =6uA, I Q2B =2uA, so I Q4B =1uA.

[0047] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. A bias current source with a wide voltage range, characterized in that: including a bias current generating module and a bias current output module connected thereto; The bias current generating module outputs a positive temperature coefficient bias current to the bias current output module, and the bias current output module cooperates with the bias current generating module to output a source current P27_G and a sink current C13_PLUS and reduce the influence of temperature on the output current; The bias current generating module includes transistors M1 and M2 whose sources are respectively connected to the power supply voltage VDD, a transistor M3 whose source is connected to the drain of the transistor M1, a transistor M4 whose source is connected to the drain of the transistor M2, a transistor M10 whose drain is connected to the drain of the transistor M3, resistors R1 and R2 connected in parallel with the source of the transistor M10, a transistor Q1 whose collector is connected to the other end of the resistor R1 and whose base is connected to the other end of the resistor R2, a resistor R4 connected to the emitter of the transistor Q1, a resistor R3 whose one end is connected to the drain of the transistor M4, a collector connected to the other end of the resistor R3 and whose emitter is connected to the resistor R4. Transistor Q2 connected to the ground terminal, Zener diode Q3 with its cathode connected to the gate of transistor M10, resistor R6 with one end connected to the power supply voltage VDD, transistor M11 with its drain connected to the other end of resistor R6 and its gate connected to the cathode of Zener diode Q3, transistors M5 and M6 with their sources connected to the source of transistor M11 respectively, capacitor C2 connected in parallel with transistor M6, resistor R8 with one end connected to the drain of transistor M5, transistor Q4 with its collector connected to the other end of resistor R8, resistor R9 with one end connected to the drain of transistor M6, and transistor M7 with its gate and drain both connected to the other end of resistor R9; The gate and drain of tube M1 are connected and then connected to the gate of tube M2. The gate and drain of tube M3 are connected and then connected to the gate of tube M4. The gate of tube M10 is the bias current source signal input terminal. The base of tube Q1 is connected to the base and collector of tube Q2. Resistor R4, the emitter of tube Q2, the emitter of tube Q4, and the source of tube M7 are connected and then grounded. The base of tube Q4 is connected between resistor R3 and the collector of tube Q2. The anode of Zener diode Q3 is grounded. The gate and drain of tube M5 are connected and then connected to the gate of tube M6. The gate of tube M6 is connected to the other end of capacitor C2 and outputs source current P27_G. The gate and drain of tube M7 are connected and outputs sink current C13_PLUS. The tubes M1 to M6 are all PMOS tubes, the tubes M7, M10, and M11 are all NMOS tubes, and the tubes Q1, Q2, and Q4 are all three-stage tubes.

2. The bias current source with a wide voltage range according to claim 1, wherein: The positive temperature coefficient bias current is output by tube Q1, tube Q2, and resistor R4.

3. The bias current source with a wide voltage range according to claim 2, wherein: The current through resistor R2 is: I R2 =(VDD-V TH1 -V TH3 -V BE1 ) / (R2+R4); Among them, V TH1 is the voltage of tube M1, V TH3 is the voltage of tube M3, V BE1 is the voltage of tube Q1; I R2 is a positive temperature coefficient current.

4. The bias current source with a wide voltage range according to claim 3, wherein: I M3 =I R1 +I R2 ; Among them, I M3 is the drain current of tube M3, I R1 is the current flowing through resistor R1; And: I M3 =I M4 , I M4 is the drain current of tube M4; I M4 =I Q2C +I Q2B +I Q4B , I Q2C is the collector current of tube Q2, I Q2B is the base current of tube Q2, I Q4B is the base current of tube Q4; As the temperature increases, I R2 Increased I M3 , I M4 Increase, I Q2C and I Q2B As the temperature increases, it offsets part of the increase in the base current flowing through tube Q4.

5. The bias current source with a wide voltage range according to claim 1, wherein: The startup circuit is composed of a resistor R5 connected in parallel with the resistor R6 and a capacitor C1 with one end connected to the gate of the tube M10, the cathode of the Zener diode Q3, and the gate of the tube M11, and the other end being grounded; When the bias current source circuit is powered on, the voltage at the upper end of the capacitor C1 rises and causes the gate voltage of the transistor M10 in the bias current generating module to rise for self-starting, thereby preventing the bias current generating module from being in a zero state.

6. The bias current source with a wide voltage range according to claim 5, wherein: Capacitors C1 and C2 can reduce the impact of voltage VDD jitter on the bias current.

7. The bias current source with a wide voltage range according to claim 1, wherein: The tubes M1, M2, M3, and M4 are common-source and common-gate current mirrors and are all high-voltage PMOS tubes.

8. The bias current source with a wide voltage range according to claim 1, wherein: Pipe M11 is a high-pressure pipe.

9. The bias current source with a wide voltage range according to claim 1, wherein: The resistance values ​​of the resistor R1 and the resistor R3 are the same.

10. The bias current source with a wide voltage range according to claim 1, wherein: The tube M5 and the tube M6 form a current mirror.

Images