Current comparison circuit for off-chip resistor identification and electronic chip

Abstract

The embodiment of the invention provides an off-chip resistor identification current comparison circuit and an electronic chip. The off-chip resistor identification current comparison circuit comprises a pin current determination module, a current mirror module and N current comparison modules, wherein the pin current determination module is configured to bias a pin voltage of a mode selection pin to a reference voltage according to the reference voltage, and obtain a pin current according to the pin voltage and an off-chip resistor; the current mirroring module is configured to mirror the pin current to each current comparison module; the current comparison module is configured to output a level signal according to the reference current and the mirrored pin current, different current comparison modules correspond to different reference resistors, and the reference current corresponding to different current comparison modules is determined based on the reference resistors and the reference voltage, so that the logic of the current comparison circuit is simplified, the area of the circuit is saved, and the reliability of the circuit is improved. And the time required for identifying the off-chip resistance value is shortened.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits and related technical fields, and in particular, to a current comparison circuit and an electronic chip suitable for off-chip resistance identification. Background Art

[0002] In the prior art, the user can connect a resistor to the mode selection pin of the chip, and the chip can select the chip's operating mode, operating frequency, etc. by identifying the resistance value of the off-chip resistor connected to the mode selection pin. In the existing chip operating mode and operating frequency selection method, a preset reference current (IMODE) is usually injected into the mode selection pin, and the voltage of the pin (VMODE = IMODE*RMODE) is sampled at the same time, and compared with the internal reference voltage (VREF). The resistance value of the off-chip resistor connected to the mode selection pin is judged based on the comparison result, and then the chip's operating mode or operating frequency, etc. are selected.

[0003] However, in the prior art solution, it is necessary to use the same voltage comparator to determine the gear position of the off-chip resistor by time-division multiplexing. Therefore, it is necessary to use a time-division multiplexing control circuit to switch the reference current and reference voltage of each gear, sample and compare, and finally store the result of each judgment and integrate it to determine the gear position of the off-chip resistor connected to the mode selection pin. In addition, in the process of injecting the reference current into the mode selection pin, the parasitic capacitor in parallel with the off-chip resistor will be shunted. If you want to get the accurate mode selection pin voltage and sample it, you must wait for enough time to make the potential on the parasitic capacitor stable, and the reference current will all flow to the off-chip resistor. Similarly, there are similar problems in switching the reference voltage of different gears inside the chip. The reference voltage in the chip is usually divided by the resistor string and transmitted to the input stage of the comparator through a low-pass filter. Due to the limited load capacity, once the reference voltage value is switched, it is also necessary to wait for the corresponding stabilization time before the comparator can compare, otherwise it may output an erroneous comparison result.

[0004] Since the existing solution adopts time-division multiplexing control logic, it is necessary to wait for the sampling signal to stabilize when making judgments for each preset gear. Therefore, when judging multi-gear resistance values, the sampling signal stabilization time required for the entire detection process is more obvious. Summary of the invention

[0005] The embodiments described in this article provide a current comparison circuit and an electronic chip for off-chip resistance identification. Compared with existing solutions, they charge the mode selection pin faster, require a shorter stabilization time, do not require time-division multiplexing timing control, and shorten the time required for the chip to identify the resistance value of the off-chip resistor.

[0006] In a first aspect, according to the content of the present disclosure, a current comparison circuit for off-chip resistor identification is provided, the current comparison circuit includes a mode selection pin, the mode selection pin is electrically connected to the off-chip resistor, and includes: a pin current determination module, a current mirror module, a reference current generation module and N current comparison modules;

[0007] The pin current determination module is configured to bias the pin voltage of the mode selection pin to the reference voltage according to the reference voltage, and obtain the pin current according to the pin voltage and the off-chip resistor;

[0008] The current mirror module is configured to mirror the pin current to each current comparison module;

[0009] The current comparison module is configured to output a level signal based on a reference current and the pin current after mirroring. Different current comparison modules correspond to different reference resistors. The reference currents corresponding to different current comparison modules are determined based on the reference resistor, the reference voltage and the mirror ratio of the current mirror module.

[0010] In some embodiments of the present disclosure, the pin current determination module includes an amplifier and a first transistor, the positive input terminal of the amplifier receives a reference voltage, the reverse input terminal of the amplifier and the second terminal of the first transistor are electrically connected to the mode selection pin, the output terminal of the amplifier is electrically connected to the control terminal of the first transistor, and the first terminal of the first transistor is electrically connected to the current mirror module.

[0011] In some embodiments of the present disclosure, the current mirror module includes N+1 second transistors, the first end of each of the second transistors is electrically connected to the power supply voltage node, the second end of the first second transistor is electrically connected to the control end of each second transistor, and the second ends of the other second transistors except the first second transistor are electrically connected to a current comparison module.

[0012] In some embodiments of the present disclosure, the current comparison module includes a buffer, an input end of the buffer receives the pin current and the reference current simultaneously, and an output end of the buffer outputs a level signal.

[0013] In some embodiments of the present disclosure, a control module is also included;

[0014] The control module is configured to determine the resistance range of the off-chip resistor according to the level signal output by each current comparison module, and to output a control signal to the reference voltage generating module when the level signal output by each current comparison module is a high level or a low level, so as to control the size of the reference voltage output by the reference voltage generating module to the pin current determination module.

[0015] In some embodiments of the present disclosure, the reference current is generated based on a reference current generating module inside the current comparison circuit, or based on a reference current generating module outside the current comparison circuit.

[0016] In some embodiments of the present disclosure, the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor.

[0017] In a second aspect, according to the content of the present disclosure, there is provided an electronic chip, comprising a current comparison circuit for off-chip resistance identification as described in any one of the first aspects.

[0018] The current comparison circuit and electronic chip for off-chip resistance identification provided by the embodiment of the present disclosure first determine the pin voltage of the mode selection pin through the feedback loop of the pin current determination module, and then determine the pin current according to the pin voltage of the mode selection pin and the off-chip resistance after the potential of the pin voltage is stabilized. Compared with the prior art in which a fixed reference current is injected into the mode selection pin, and the reference voltage is determined based on the reference current and the off-chip resistance after the potential of the pin voltage is stabilized, the charging time of the capacitor based on the fixed voltage in this solution is shorter than the charging time of the capacitor based on the fixed current. Therefore, the time for waiting for the potential of the capacitor connected in parallel with the off-chip resistance to stabilize is shorter. The length is shorter, which shortens the time required for the chip to identify the resistance value of the off-chip resistor; in addition, the current mirror module samples the pin current and then mirrors it to each current comparison module, and then different current comparison modules receive the reference current and compare the reference current with the mirrored pin current. There is no need for time-division multiplexing timing control, which greatly simplifies the logic complexity and saves the corresponding chip area. Since the current comparison module compares the reference current and the pin current, there is no need to establish a high-precision reference voltage generation module for each comparison module branch, which simplifies the logic of the current comparison circuit and reduces the overall volume of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0020] Figure 1 It is a structural schematic diagram of a current comparison circuit for off-chip resistance identification provided by an embodiment of the present disclosure;

[0021] Figure 2 It is a specific circuit structure diagram of a current comparison circuit for off-chip resistance identification provided by an embodiment of the present disclosure;

[0022] Figure 3It is a structural schematic diagram of another current comparison circuit for off-chip resistance identification provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0025] In all embodiments of the present disclosure, terms such as “first” and “second” are used only to distinguish one component (or a part of a component) from another component (or another part of a component).

[0026] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0027] Based on the problems existing in the prior art, the present disclosure provides a current comparison circuit for off-chip resistance identification. Figure 1It is a structural schematic diagram of a current comparison circuit for off-chip resistance identification provided by an embodiment of the present disclosure. The current comparison circuit for off-chip resistance identification includes a mode selection pin MODE, which is electrically connected to an off-chip resistance Rmode. The current comparison circuit for off-chip resistance identification includes: a pin current determination module 10, a current mirror module 20 and N current comparison modules 40; wherein, the pin current determination module 10 is configured to bias the pin voltage of the mode selection pin MODE to a reference voltage according to a reference voltage, and obtain the pin current according to the pin voltage and the off-chip resistance; the current mirror module 20 is configured to mirror the pin current to each current comparison module 40; the current comparison module 40 is configured to output a level signal according to the reference current and the pin current after mirroring, different current comparison modules correspond to different reference resistors, and the reference currents corresponding to different current comparison modules are determined based on the reference resistance, the reference voltage and the mirror ratio of the current mirror module.

[0028] The current comparison circuit for off-chip resistance identification provided by the embodiment of the present disclosure is provided with a pin current determination module 10. The pin current determination module 10 first biases the reference voltage to the mode selection pin MODE. After receiving the reference voltage, the mode selection pin MODE determines the pin current flowing through the mode selection pin MODE according to the off-chip resistance Rmode connected to the mode selection pin MODE and the reference voltage. Then, the pin current is mirrored to each current comparison module 40 through the current mirror module 20. The current comparison module 40 receives the reference current and the pin current mirrored by the current mirror module 20, and compares the reference current and the pin current to output a level signal. Each current comparison module 40 outputs a level signal based on the reference current and the pin current, and different current comparison modules correspond to different reference resistors. Therefore, the resistance range of the off-chip resistance electrically connected to the mode selection pin can be determined according to the level signal output by the current comparison module 40, and then the working mode or working frequency of the electronic chip can be selected.

[0029] It should be noted that, in the current comparison circuit for off-chip resistance identification provided by the embodiment of the present disclosure, the number of current comparison modules provided is not specifically limited.

[0030] As a specific example, Figure 3As shown, the current comparison circuit for off-chip resistance recognition includes four current comparison modules 40, the reference voltage is Vref, the off-chip resistance is Rmode, the pin voltage of the mode selection pin satisfies: Vmode=Vref, the pin current satisfies: Imode=Vmode / Rmode=Vref / Rmode, and through the mirror ratio of the current mirror module, it can be determined that the pin current input to the first current comparison module is Imode1=N1*Vmode / Rmode=N1*Vref / Rmode, the pin current input to the second current comparison module is Imode2=N2*Vmode / Rmode=N2*Vref / Rmode, and the pin current input to the third current comparison module is Imode1=N1*Vmode / Rmode=N1*Vref / Rmode. The pin current of the block is Imode3=N3*Vmode / Rmode=N3*Vref / Rmode, and the pin current input to the fourth current comparison module is Imode4=N4*Vmode / Rmode=N4*Vref / Rmode. N1 is the mirror ratio of the current mirror module to the branch corresponding to the first current comparison module, N2 is the mirror ratio of the current mirror module to the branch corresponding to the second current comparison module, N3 is the mirror ratio of the current mirror module to the branch corresponding to the third current comparison module, and N4 is the mirror ratio of the current mirror module to the branch corresponding to the second current comparison module. The reference current received by the first current comparison module is Iref1, the reference current received by the second current comparison module is Iref2, the reference current received by the third current comparison module is Iref3, and the reference current received by the fourth current comparison module is Iref4. The first current comparison module outputs a level signal by comparing the pin current Imode1 and the reference current Iref1, the second current comparison module outputs a level signal by comparing the pin current Imode2 and the reference current Iref2, the third current comparison module outputs a level signal by comparing the pin current Imode3 and the reference current Iref3, and the fourth current comparison module outputs a level signal by comparing the pin current Imode4 and the reference current Iref4. According to the level signals output by each comparison module, the resistance range of the off-chip resistor connected to the mode selection pin is determined.

[0031] For example, the reference resistance value corresponding to the first current comparison module is 10kΩ, the reference resistance value corresponding to the second current comparison module is 20kΩ, the reference resistance value corresponding to the third current comparison module is 30kΩ, and the reference resistance value corresponding to the fourth current comparison module is 40kΩ. If the level signal output by the first current comparison module is a high level, the level signal output by the second current comparison module is a low level, the level signal output by the third current comparison module is a low level, and the level signal output by the fourth current comparison module is a low level, it can be determined that the resistance value of the off-chip resistor connected to the mode selection pin is in the resistance value range of 10kΩ to 20kΩ.

[0032] It should be noted that in the above embodiments, the reference current corresponding to different reference currents can be determined based on the reference voltage, the reference resistor and the mirror ratio of the current mirror module. For example, the reference current Iref1 is determined based on the reference voltage Vref, the reference resistor of the first current comparison module and the mirror ratio of the current mirror module, the reference current Iref2 is determined based on the reference voltage Vref, the reference resistor of the second current comparison module and the mirror ratio of the current mirror module, the reference current Iref3 is determined based on the reference voltage Vref, the reference resistor of the third current comparison module and the mirror ratio of the current mirror module, and the reference current Iref4 is determined based on the reference voltage Vref, the reference resistor of the fourth current comparison module and the mirror ratio of the current mirror module.

[0033] In addition, in the above embodiment, if the level signals output by the four current comparison modules 40 are all low levels, indicating that the pin currents output by the pin current determination module to each current comparison module are all smaller than the minimum value of the reference current generated by the reference current generation module, at this time, the reference voltage can be increased to increase the pin current output to each current comparison module; if the level signals output by the four current comparison modules are all high levels, indicating that the pin currents output by the pin current determination module to each current comparison module are all larger than the reference current generated by the reference current generation module, at this time, the reference voltage can be reduced to reduce the pin current output to each current comparison module.

[0034] The current comparison circuit for off-chip resistance identification provided by the embodiment of the present disclosure first determines the pin voltage of the mode selection pin through the feedback loop of the pin current determination module, and then determines the pin current according to the pin voltage of the mode selection pin and the off-chip resistance after the potential of the pin voltage is stabilized. Compared with the prior art in which a fixed reference current is injected into the mode selection pin, and the reference voltage is determined based on the reference current and the off-chip resistance after the potential of the pin voltage is stabilized, the charging time of the capacitor based on the fixed voltage in this solution is shorter than the charging time of the capacitor based on the fixed current. Therefore, the time for waiting for the potential of the capacitor connected in parallel with the off-chip resistance to stabilize is shorter. The time required for the chip to identify the resistance value of the off-chip resistor is short, which shortens the time required for the chip to identify the resistance value of the off-chip resistor. In addition, the current mirror module samples the pin current and then mirrors it to each current comparison module. Then different current comparison modules receive the reference current and compare the reference current with the mirrored pin current. There is no need for time-division multiplexing timing control, which greatly simplifies the logic complexity and saves the corresponding chip area. Moreover, since the current comparison module compares the reference current and the pin current, there is no need to establish a high-precision reference voltage generation module for each comparison module branch, which simplifies the logic of the current comparison circuit and reduces the overall volume of the circuit.

[0035] Based on the above embodiments, Figure 2 is a circuit structure diagram of a current comparison circuit for off-chip resistance recognition provided by an embodiment of the present disclosure, such as Figure 2 As shown, the pin current determination module 10 includes an amplifier A and a first transistor M1, the positive input terminal of the amplifier A receives a reference voltage Vref, the reverse input terminal of the amplifier A and the second terminal of the first transistor M1 are electrically connected to the mode selection pin MODE, the output terminal of the amplifier A is electrically connected to the control terminal of the first transistor M1, and the first terminal of the first transistor M1 is electrically connected to the current mirror module 20.

[0036] Specifically, Figure 2 As shown, the pin current determination module 10 includes an amplifier A and a first transistor M1. A feedback loop is constructed based on the amplifier A and the first transistor M1 to implement the pin voltage Vmode of the mode selection pin MODE to follow the reference voltage Vref. At this time, the current flowing through the off-chip resistor Rmode is Imode=Vmode / Rmode=Vref / Rmode, and the current flowing through the first transistor is the same as the current flowing through the off-chip resistor, which is the pin current.

[0037] Based on the above embodiments, continue to refer to Figure 2The current mirror module 20 includes N+1 second transistors, the first end of each second transistor is electrically connected to the power supply voltage node, the second end of the first second transistor is electrically connected to the control end of each second transistor, and the second ends of the other second transistors except the first second transistor are electrically connected to a current comparison module 40.

[0038] Exemplary, combined Figure 2 When the current comparison module 40 includes 4, the number of the second transistors is 5, the first second transistor collects the pin current flowing through the first transistor, and mirrors the collected pin current flowing through the first transistor to the first current comparison module through the second second transistor, mirrors the collected pin current flowing through the first transistor to the second current comparison module through the third second transistor, mirrors the collected pin current flowing through the first transistor to the third current comparison module through the fourth second transistor, and mirrors the collected pin current flowing through the first transistor to the fourth current comparison module through the fifth second transistor.

[0039] It should be noted that, in the above embodiment, the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor.

[0040] In addition, the mirroring ratios of the pin current mirrored by the current mirror module to each current comparison module may be the same or different, and the embodiments of the present disclosure do not specifically limit this.

[0041] In a specific implementation, the reference current may be generated based on a reference current generating module inside the current comparison circuit, or may be generated based on a reference current generating module outside the current comparison circuit.

[0042] Figure 2 The exemplary representation is that the reference current is generated based on the reference current generating module 30 inside the current comparison circuit, such as Figure 2 As shown, the reference current generating module 30 includes a current source, a first end of the current source is electrically connected to the current comparing module, and a second end of the current source is electrically connected to the ground node.

[0043] The reference current generating module is configured to include a current source, and a reference current is generated by the current source. The reference current generated by the current source included in one reference current generating module is output to one current comparison module accordingly.

[0044] Exemplarily, the reference current generated by the current source included in the first reference current generating module is Iref1, the reference current generated by the current source included in the second reference current generating module is Iref2, the reference current generated by the current source included in the third reference current generating module is Iref3, and the reference current generated by the current source included in the fourth reference current generating module is Iref4. The reference current received by the first current comparison module is the reference current Iref1 generated by the current source included in the first reference current generating module, the reference current received by the second current comparison module is the reference current Iref2 generated by the current source included in the second reference current generating module, the reference current received by the third current comparison module is the reference current Iref3 generated by the current source included in the third reference current generating module, and the reference current received by the fourth current comparison module is the reference current Iref4 generated by the current source included in the fourth reference current generating module.

[0045] Based on the above embodiments, continue to refer to Figure 2 The current comparison module 40 includes a buffer, an input end of the buffer receives the pin current and the reference current respectively, and an output end of the buffer outputs a level signal.

[0046] like Figure 2 As shown, the current comparison module includes a buffer, which receives the pin current and the reference current respectively. When the pin current is greater than the reference current, the level signal output by the buffer is a high level, and when the pin current is less than the reference current, the level signal output by the buffer is a low level. Through the level signals output by each buffer, the resistance range of the off-chip resistor connected to the mode selection pin can be determined, thereby determining the working module or working frequency of the electronic chip.

[0047] Based on the above embodiments, Figure 3 is a structural schematic diagram of another current comparison circuit for off-chip resistance identification provided by an embodiment of the present disclosure, such as Figure 3 As shown, the current comparison circuit for off-chip resistance identification also includes: a control module; the control module is configured to determine the resistance range of the off-chip resistance according to the level signal output by each current comparison module, and when the level signal output by each current comparison module is a high level or a low level, output a control signal to the reference voltage generating module to control the size of the reference voltage output by the reference voltage generating module to the pin current determination module.

[0048] Specifically, the current comparison circuit for off-chip resistor identification provided in the embodiment of the present disclosure also includes a control module 50. The control module 50 obtains the level signal output by each current comparison module, and then determines the resistance range of the off-chip resistor connected to the mode selection pin according to the level signal output by each current comparison module.

[0049] In a specific implementation, the reference voltage may be generated based on a reference voltage generating module 60 inside the current comparison circuit, or may be generated based on a reference voltage generating module outside the current comparison circuit, and the embodiments of the present disclosure do not specifically limit this.

[0050] In one implementation, the reference voltage generating module 60 includes M resistors connected in series.

[0051] For example, if the reference resistance value corresponding to the reference current Iref1 is 10kΩ, the reference resistance value corresponding to the reference current Iref2 is 20kΩ, the reference resistance value corresponding to the reference current Iref3 is 30kΩ, and the reference resistance value corresponding to the reference current Iref4 is 40kΩ, if the level signal output by the first current comparison module is a high level, the level signal output by the second current comparison module is a low level, the level signal output by the third current comparison module is a low level, and the level signal output by the fourth current comparison module is a low level, it can be determined that the resistance value of the off-chip resistor connected to the mode selection pin is in the resistance range of 10kΩ to 20kΩ.

[0052] In addition, in the above embodiment, if the level signals output by the four current comparison modules are all low levels, indicating that the pin current output by the pin current determination module to each current comparison module is less than the minimum value of the reference current generated by the reference current generation module, at this time, the control module increases the pin current output to each current comparison module by controlling the reference voltage output by the reference voltage generation module to the pin current determination module; if the level signals output by the four current comparison modules are all high levels, indicating that the pin current output by the pin current determination module to each current comparison module is greater than the reference current generated by the reference current generation module, at this time, the control module reduces the pin current output to each current comparison module by controlling the reference voltage output by the reference voltage generation module to the pin current determination module.

[0053] It should be noted that Figure 3 The example shows that the reference current is generated based on the reference current generating module 30 inside the current comparison circuit. The reference current can also be generated based on the reference current generating module outside the current comparison circuit. The embodiments of the present disclosure do not specifically limit this.

[0054] The embodiment of the present disclosure further provides an electronic chip, which includes the current comparison circuit for off-chip resistance identification provided by the embodiment of the present disclosure.

[0055] The embodiments of the present disclosure also provide an electronic device. The electronic device includes an electronic chip according to the embodiments of the present disclosure. The electronic device is, for example, a smart terminal device, such as a tablet computer, a smart phone, etc.

[0056] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0057] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial number of each step / process mentioned above does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. In addition, the serial numbers of the embodiments of the present application mentioned above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0058] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0059] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A current comparison circuit for off-chip resistor identification, the current comparison circuit comprising a mode selection pin, the mode selection pin being electrically connected to the off-chip resistor, characterized in that: include: Pin current determination module, current mirror module and N current comparison modules; The pin current determination module is configured to bias the pin voltage of the mode selection pin to the reference voltage according to the reference voltage, and obtain the pin current according to the pin voltage and the off-chip resistor; The current mirror module is configured to mirror the pin current to each current comparison module; The current comparison module is configured to output a level signal based on a reference current and the pin current after mirroring. Different current comparison modules correspond to different reference resistors. The reference currents corresponding to different current comparison modules are determined based on the reference resistor, the reference voltage and the mirror ratio of the current mirror module.

2. The circuit according to claim 1, characterized in that The pin current determination module includes an amplifier and a first transistor, the positive input terminal of the amplifier receives a reference voltage, the reverse input terminal of the amplifier and the second terminal of the first transistor are electrically connected to the mode selection pin, the output terminal of the amplifier is electrically connected to the control terminal of the first transistor, and the first terminal of the first transistor is electrically connected to the current mirror module.

3. The circuit according to claim 2, characterized in that The current mirror module includes N+1 second transistors, the first end of each of the second transistors is electrically connected to the power supply voltage node, the second end of the first second transistor is electrically connected to the control end of each second transistor, and the second ends of the other second transistors except the first second transistor are electrically connected to a current comparison module.

4. The circuit according to claim 1, characterized in that The current comparison module includes a buffer, an input end of the buffer receives the pin current and the reference current simultaneously, and an output end of the buffer outputs a level signal.

5. The circuit according to claim 1, characterized in that Also includes a control module; The control module is configured to determine the resistance range of the off-chip resistor according to the level signal output by each current comparison module, and to output a control signal to the reference voltage generating module when the level signal output by each current comparison module is a high level or a low level, so as to control the size of the reference voltage output by the reference voltage generating module to the pin current determination module.

6. The circuit according to claim 1, characterized in that The reference current is generated based on a reference current generating module inside the current comparison circuit, or based on a reference current generating module outside the current comparison circuit.

7. The circuit according to claim 3, characterized in that The first transistor is an NMOS transistor, and the second transistor is a PMOS transistor.

8. An electronic chip, characterized in that: The invention comprises the current comparison circuit as described in any one of claims 1 to 7.

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