A storage device control method, chip, storage medium and solid state hard disk

Abstract

A control method, chip, storage medium and solid state hard disk for a storage device, wherein the method is applied to a storage device provided with Nand Flash, and the method comprises: writing user data from a host and the logical address of the user data into a data page of the Nand Flash, and caching a mapping relationship between the logical address and the physical address of the user data; writing the mapping relationship between the cached logical address and the physical address into a mapping page of the Nand Flash according to a preset rule; when power is turned on again after power failure is detected, the mapping relationship between the logical address and the physical address in the cache lost due to power failure is restored according to the mapping relationship between the logical address and the physical address written in the mapping page of the Nand Flash and the logical address recorded in the data page, so as to ensure that the data stored in the storage device can still be normally accessed by the host when the storage device is powered on again after power failure.

Description

Technical Field

[0001] This article relates to storage control technology, in particular to a control method, chip, storage medium and solid-state hard disk of a storage device. Background Art

[0002] Nand Flash is the mainstream storage medium currently used in storage devices. It supports non-volatile storage technology and can keep data from being lost when there is no power. The host accesses the storage device through the logical address, and the Nand Flash in the storage device stores data with the physical address. Therefore, the storage device using Nand Flash will store an address mapping table to record the mapping relationship between the logical address and the physical address of the user data.

[0003] After the user data from the host is written into the Nand Flash of the storage device, the DRAM or SDRAM of the storage device temporarily stores the address mapping relationship of the user data. Since the data in the DRAM or SDRAM will be lost after power failure, it is necessary to regularly write the address mapping relationship stored in the DRAM or SDRAM into the Nand Flash to maintain the persistence of the address mapping relationship. If the storage device loses power before the address mapping relationship temporarily stored in the DRAM or SDRAM is written into the Nand Flash, the address mapping relationship will be lost, and the host will not be able to access the corresponding data. Summary of the invention

[0004] The embodiments of the present application provide a control method, chip, storage medium and solid-state hard disk of a storage device, which can ensure that the data stored in the storage device can still be normally accessed by the host when the storage device is powered on again after power failure.

[0005] The control method of a storage device provided in an embodiment of the present application is applied to a storage device provided with Nand Flash, and the method includes: Write the user data from the host and the logical address of the user data into the data page of Nand Flash, and cache the mapping relationship between the logical address and the physical address of the user data; According to the preset rules, the mapping relationship between the cached logical address and the physical address is written into the mapping page of Nand Flash; When power is turned on again after power failure is detected, the mapping relationship between the logical address and the physical address in the cache that was lost due to power failure is restored according to the mapping relationship between the logical address and the physical address written in the mapping page of the Nand Flash and the logical address recorded in the data page.

[0006] As an exemplary embodiment, writing the user data from the host and the logical address of the user data into the data page of the Nand Flash includes: The user data from the host is written into the data area of ​​the data page, and the logical address of the user data is written into the free area for storing metadata in the same data page, wherein the size of the data area is 16KB and the size of the free area is 2KB.

[0007] As an exemplary embodiment, writing the user data from the host into the data area of ​​the data page, and writing the logical address of the user data into a free area for storing metadata in the same data page includes: For each data page: The user data from the host is written into the data area of ​​the data page in units of 4KB data blocks, with a total of 4 data blocks; The four logical addresses corresponding to the four data blocks are sequentially written into a free area for storing metadata in the same data page, where the size of each logical address is 4 bytes, for a total of 16 bytes.

[0008] As an exemplary embodiment, writing the mapping relationship between the cached logical address and the physical address into the mapping page of NandFlash includes: The mapping relationship between the logical address and the physical address of the cached user data is written into the data area of ​​the mapping page according to the order in which the user data is written into the data page, and the size of the data area is 16KB.

[0009] As an exemplary embodiment, writing the mapping relationship between the cached logical address and the physical address into the mapping page of the Nand Flash according to a preset rule includes: When the total user data size of the multiple data pages written into the Nand Flash satisfies 16 MB, the mapping relationship between the logical address and the physical address of each user data in the multiple data pages cached is written into the mapping page of the Nand Flash.

[0010] As an exemplary embodiment, the method of restoring the mapping relationship between the logical address and the physical address lost due to power failure in the cache according to the mapping relationship between the logical address and the physical address written in the mapping page of the Nand Flash and the logical address recorded in the data page includes: Determine the starting physical address in the mapping relationship that needs to be restored according to the mapping relationship between the logical address and the physical address written in the mapping page of Nand Flash; The data page corresponding to the starting physical address is determined, and the mapping relationship between the physical address and the logical address of the user data is read and cached starting from the data page until there is no more logical address to read.

[0011] As an exemplary embodiment, the determining the starting physical address in the mapping relationship to be restored according to the mapping relationship between the logical address and the physical address written in the mapping page of the Nand Flash includes: Determine, according to the mapping relationship between the logical address and the physical address written in the mapping page of the Nand Flash, the physical address corresponding to the user data last written into the data page among the user data corresponding to the written mapping relationship; The next physical address of the physical address corresponding to the user data last written into the data page is used as the starting physical address in the mapping relationship that needs to be restored.

[0012] An embodiment of the present application provides a non-volatile computer-readable storage medium, which stores one or more program instructions, and the one or more program instructions can be executed by one or more processors to implement the method described in any of the previous embodiments.

[0013] The control chip provided in the embodiment of the present application comprises: a memory configured to store computer program instructions executable on the processor; A processor is configured to execute the computer program instructions to implement the method as described in any of the previous embodiments.

[0014] The solid-state hard disk provided in the embodiment of the present application comprises: The control chip as described in the previous embodiment, and Nand Flash that communicates with the control chip.

[0015] The technical solution recorded in the embodiment of the present application can restore the address mapping relationship in the cache that is lost due to power failure when the storage device is powered on again after power failure, thereby ensuring that the cache mapping relationship can be written to Nand Flash for non-volatile storage, and further ensuring that the host has normal access to the stored data when the storage device is powered on again after power failure.

[0016] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0018] Figure 1 A flow chart of a control method of a storage device provided for the implementation of this application; Figure 2 An example diagram of the structure of a data page in Nand Flash provided in an embodiment of the present application; Figure 3 An example diagram of writing user data and logical addresses into a data page provided by an embodiment of the present application; Figure 4 An example diagram of writing user data into a data page provided in an embodiment of the present application; Figure 5 A control chip module diagram provided in an embodiment of the present application; Figure 6 A block diagram of a solid-state hard disk provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0020] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0021] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0022] The present application embodiment provides a control method for a storage device, the method being applied to a storage device provided with NandFlash, such as Figure 1 As shown, the control method comprises the following steps: Step S101: After receiving user data from the host, write the user data and the logical address of the user data into the data page of the Nand Flash, and cache the mapping relationship between the logical address and the physical address of the user data; The storage structure of Nand Flash consists of multiple blocks, each of which contains multiple pages. Block is the basic unit of Nand Flash erase operation, and page is the basic unit of Nand Flash read and write operation. Step S102 writes the mapping relationship between the cached logical address and the physical address into the mapping page of NandFlash according to the preset rule; The data page in Nand Flash is used to store user data, and the mapping page is used to store the mapping relationship between the logical address and the physical address. The data page and the mapping page have the same structure. Storing the user data and the mapping relationship in different areas of Nand Flash can reduce the interference of frequent updates of the mapping relationship on the user data and improve the access performance of the user data. Step S103: When power is turned on again after power failure is detected, the mapping relationship between the logical address and the physical address in the cache that was lost due to power failure is restored according to the mapping relationship between the logical address and the physical address written in the mapping page of the Nand Flash and the logical address recorded in the data page.

[0023] Exemplarily, the storage device, such as a solid-state drive (SSD), can determine whether power is off or on by detecting the power status in real time. If it is detected that the power supply voltage drops below a preset voltage threshold, it can be determined that a power off has occurred; if it is detected that the power supply voltage rises above the voltage threshold, it can be determined that a power on has occurred.

[0024] The method recorded in the embodiment of the present application can restore the address mapping relationship in the cache that is lost due to power failure when the storage device is powered on again after power failure, thereby ensuring that the cache mapping relationship can be written to Nand Flash for non-volatile storage, and further ensuring that the host has normal access to the stored data when the storage device is powered on again after power failure.

[0025] In an exemplary embodiment, writing the user data from the host and the logical address of the user data into the data page of the Nand Flash includes: Writing user data from the host into a data area of ​​a data page, and writing a logical address of the user data into a free area for storing metadata in the same data page, wherein the size of the data area is 16KB, and the size of the free area is 2KB; Figure 2 An example of a structure of a data page in a Nand Flash is provided, wherein the data area is used to store user data, and the free area is used to store metadata, and the metadata includes: a logical address of the user data.

[0026] In an exemplary embodiment, writing the user data from the host into the data area of ​​the data page, and writing the logical address of the user data into the free area for storing metadata in the same data page, comprises: For each data page: The user data from the host is written into the data area of ​​the data page in units of 4KB data blocks, with a total of 4 data blocks; the 4 logical addresses corresponding to the 4 data blocks are sequentially written into the free area for storing metadata in the same data page, with the size of each logical address being 4Bytes, for a total of 16Bytes. Figure 3 An example of writing user data and logical addresses into a data page is given. Each grid in the figure represents a user data, and there are 4 user data in total (data1-data4 in the figure); each user data corresponds to a logical address, corresponding to the gray bar in the figure, so the 4 user data have 4 logical addresses in total.

[0027] The minimum unit of host operation data is a 4KB data block. In this embodiment, 4 data blocks are written in one data page, totaling 16KB, which can fill the data area of ​​one data page. That is, the storage space of the page can be fully utilized without generating additional data management overhead due to insufficient written data, thereby ensuring the performance of the storage device.

[0028] In an exemplary embodiment, writing the mapping relationship between the cached logical address and the physical address into the mapping page of NandFlash includes: The mapping relationship between the cached logical address and the physical address is written into the data area of ​​the mapping page according to the sequence of writing the user data into the data page, and the size of the data area is 16KB.

[0029] The address mapping relationship is written into the mapping page in a preset order to facilitate subsequent analysis of the mapping relationship stored in the mapping page.

[0030] In an exemplary embodiment, writing the mapping relationship between the cached logical address and the physical address into the mapping page of the Nand Flash according to a preset rule includes: When the total user data size of the multiple data pages written into the Nand Flash is 16 MB, the mapping relationship between the logical address and the physical address of each user data in the multiple cached data pages is written into the mapping page of the Nand Flash.

[0031] Each 4KB user data block corresponds to a mapping relationship, and the size of the mapping relationship is 4Byte; for 16MB user data, the number of corresponding user data blocks is 16MB / 4KB = 4K, and the size of the corresponding mapping relationship is 4Byte*4K=16KB, which can just fill up the data area of ​​a page. Since the smallest unit of writing data is a page, if a page is not fully written this time, the page data written this time must be moved out for the next write, and then the data must be merged and written in again. This operation will increase the actual write amount. This embodiment can ensure that a full page is written, which can reduce the occurrence of write amplification, improve write efficiency, and extend the service life of the storage device.

[0032] In an exemplary embodiment, the method of restoring the mapping relationship between the logical address and the physical address in the cache that is lost due to power failure according to the mapping relationship between the logical address and the physical address written in the mapping page of the Nand Flash and the logical address recorded in the data page includes: Determine the starting physical address in the mapping relationship that needs to be restored according to the mapping relationship between the logical address and the physical address written in the mapping page of Nand Flash; Determine the data page corresponding to the starting physical address, and start reading and caching the physical address and logical address of the user data from the data page until no logical address can be read; wherein, no logical address can be read, which may be reading a data page without user data written in it, or reading a data page without four user data blocks being written in it.

[0033] In an exemplary embodiment, the step of determining the starting physical address in the mapping relationship to be restored according to the mapping relationship between the logical address and the physical address written in the mapping page of the Nand Flash includes: Determine, according to the mapping relationship between the logical address and the physical address written in the mapping page of the Nand Flash, the physical address corresponding to the user data last written into the data page in the user data corresponding to the written mapping relationship; illustratively, in the case where the mapping relationship between the logical address and the physical address is written into the mapping page in the order in which the user data is written into the data page, the physical address in the mapping relationship last recorded in the mapping page is the physical address corresponding to the user data last written into the data page in the user data corresponding to the mapping relationship written into the Nand Flash; The next physical address of the physical address corresponding to the user data last written into the data page is used as the starting physical address in the mapping relationship that needs to be restored.

[0034] The technical solution described in the above-mentioned embodiment of the present application is illustrated below with a specific application example.

[0035] Receive user data from the host; Write user data in 4KB blocks into the data area of ​​a data page of Nand Flash, write the logical address corresponding to each data block into the free area of ​​the data page, and cache the mapping relationship between the logical address and the physical address of each data block; Continue to receive user data and write the user data into the next data page; After 1024 data pages are written, that is, the total user data written reaches 16MB, the mapping relationship corresponding to the cached 16MB user data is written into a mapping page of Nand Flash. For the convenience of subsequent description, this mapping page is recorded as mapping page n; Continue to receive user data and write the received user data into the next data page of Nand Flash. Figure 4 A schematic diagram of writing user data into a data page is shown, in which 16MB corresponds to 1024 data pages; When the total user data to be written reaches 16MB, the mapping relationship corresponding to the cached 16MB user data is written into the next mapping page of Nand Flash, which is recorded as mapping page (n+1). Continue to receive user data and write the received user data into the next data page of Nand Flash; After detecting that a power outage has occurred and then powering on again, the system log can be used to locate and determine that the block has incomplete records. The mapping records corresponding to all previous 16MB of user data are loaded, that is, the mapping records recorded in mapping page n and mapping page (n+1) are loaded. The physical address of the user data last written to the data page among all previous 16MB of user data is found based on the loaded mapping records. Starting from the physical address next to the physical address of the user data last written into the data page, the logical address and the physical address of the user data recorded in the data page are read in sequence. If the first data page to be read records 4 user data blocks, the logical address and the physical address of the 4 user data blocks are cached, and then the second data page is read until there is no logical address to be read; After receiving the user data, the received user data is continued to be written into the data page of Nand Flash, and the address mapping relationship of the user data written into the cache is; When the total user data to be written into the data page reaches 16 MB, the mapping relationship corresponding to the cached 16 MB user data is written into the next mapping page of the Nand Flash, which is recorded as mapping page (n+2).

[0036] After performing the above operations, when the storage device is powered on again after power failure, the address mapping relationship in the cache that is lost due to power failure can be restored to ensure normal access of the host to the stored data.

[0037] An embodiment of the present application also provides a non-volatile computer-readable storage medium, which stores one or more program instructions, and the one or more program instructions can be executed by one or more processors to implement the control method of the storage device as described in any of the previous embodiments.

[0038] The present application also provides a control chip. Figure 5 As shown, the chip includes: A memory 501 configured to store computer program instructions executable on a processor; The processor 502 is configured to execute the computer program instructions to implement the control method of the storage device as described in any of the previous embodiments.

[0039] The present application also provides a solid state hard disk. Figure 6 As shown, the solid state hard disk includes: The control chip 601 as described in the previous embodiment, and Nand Flash 602 communicating with the control chip 601 .

[0040] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A method for controlling a storage device, applied to a storage device provided with Nand Flash, the method comprising: Write the user data from the host and the logical address of the user data into the data page of Nand Flash, and cache the mapping relationship between the logical address and the physical address of the user data; According to the preset rules, the mapping relationship between the cached logical address and the physical address is written into the mapping page of Nand Flash; When power is turned on again after power failure is detected, the mapping relationship between the logical address and the physical address in the cache that was lost due to power failure is restored according to the mapping relationship between the logical address and the physical address written in the mapping page of the Nand Flash and the logical address recorded in the data page.

2. The method according to claim 1, characterized in that Writing the user data from the host and the logical address of the user data into the data page of the Nand Flash includes: The user data from the host is written into the data area of ​​the data page, and the logical address of the user data is written into the free area for storing metadata in the same data page, wherein the size of the data area is 16KB and the size of the free area is 2KB.

3. The method according to claim 2, characterized in that The step of writing the user data from the host into the data area of ​​the data page and writing the logical address of the user data into a free area for storing metadata in the same data page comprises: For each data page: The user data from the host is written into the data area of ​​the data page in units of 4KB data blocks, with a total of 4 data blocks; The four logical addresses corresponding to the four data blocks are sequentially written into a free area for storing metadata in the same data page, where the size of each logical address is 4 bytes, for a total of 16 bytes.

4. The method according to claim 1, characterized in that: The step of writing the mapping relationship between the cached logical address and the physical address into the mapping page of the Nand Flash includes: The mapping relationship between the logical address and the physical address of the cached user data is written into the data area of ​​the mapping page according to the order in which the user data is written into the data page, and the size of the data area is 16KB.

5. The method according to claim 1, characterized in that: The step of writing the mapping relationship between the cached logical address and the physical address into the mapping page of the Nand Flash according to the preset rule includes: When the total user data size of the multiple data pages written into the Nand Flash satisfies 16 MB, the mapping relationship between the logical address and the physical address of each user data in the multiple data pages cached is written into the mapping page of the Nand Flash.

6. The method according to claim 1, characterized in that The method of restoring the mapping relationship between the logical address and the physical address lost due to power failure in the cache according to the mapping relationship between the logical address and the physical address written in the mapping page of the Nand Flash and the logical address recorded in the data page includes: Determine the starting physical address in the mapping relationship that needs to be restored according to the mapping relationship between the logical address and the physical address written in the mapping page of Nand Flash; The data page corresponding to the starting physical address is determined, and the mapping relationship between the physical address and the logical address of the user data is read and cached starting from the data page until there is no more logical address to read.

7. The method according to claim 6, characterized in that The step of determining the starting physical address in the mapping relationship to be restored according to the mapping relationship between the logical address and the physical address written in the mapping page of the Nand Flash includes: Determine, according to the mapping relationship between the logical address and the physical address written in the mapping page of the Nand Flash, the physical address corresponding to the user data last written into the data page among the user data corresponding to the written mapping relationship; The next physical address of the physical address corresponding to the user data last written into the data page is used as the starting physical address in the mapping relationship that needs to be restored.

8. A non-transitory computer-readable storage medium storing one or more program instructions, wherein the one or more program instructions can be executed by one or more processors to implement the method according to any one of claims 1 to 7.

9. A control chip, characterized in that: The chip comprises: a memory configured to store computer program instructions executable on the processor; A processor, configured to execute the computer program instructions to implement the method according to any one of claims 1 to 7.

10. A solid state hard disk, characterized in that: The solid state drive comprises: The control chip as claimed in claim 9, and Nand Flash that communicates with the control chip.

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